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Merge branch 'for-33' of git://repo.or.cz/linux-kbuild
[linux-2.6-block.git] / drivers / spi / spi_mpc8xxx.c
CommitLineData
ccf06998 1/*
575c5807 2 * MPC8xxx SPI controller driver.
ccf06998
KG		 3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
4c1fba44
AV		 8 * CPM SPI and QE buffer descriptors mode support:
9 * Copyright (c) 2009 MontaVista Software, Inc.
10 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
11 *
ccf06998
KG		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
fd8a11e1 21#include <linux/bug.h>
35b4b3c0
AV		 22#include <linux/errno.h>
23#include <linux/err.h>
9effb959 24#include <linux/io.h>
ccf06998
KG		 25#include <linux/completion.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/irq.h>
29#include <linux/device.h>
30#include <linux/spi/spi.h>
31#include <linux/spi/spi_bitbang.h>
32#include <linux/platform_device.h>
33#include <linux/fsl_devices.h>
4c1fba44
AV		 34#include <linux/dma-mapping.h>
35#include <linux/mm.h>
36#include <linux/mutex.h>
35b4b3c0
AV		 37#include <linux/of.h>
38#include <linux/of_platform.h>
39#include <linux/gpio.h>
40#include <linux/of_gpio.h>
41#include <linux/of_spi.h>
ccf06998 42
35b4b3c0 43#include <sysdev/fsl_soc.h>
4c1fba44
AV		 44#include <asm/cpm.h>
45#include <asm/qe.h>
ccf06998 46#include <asm/irq.h>
ccf06998 47
4c1fba44
AV		 48/* CPM1 and CPM2 are mutually exclusive. */
49#ifdef CONFIG_CPM1
50#include <asm/cpm1.h>
51#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
52#else
53#include <asm/cpm2.h>
54#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
55#endif
56
ccf06998 57/* SPI Controller registers */
575c5807 58struct mpc8xxx_spi_reg {
ccf06998
KG		 59 u8 res1[0x20];
60 __be32 mode;
61 __be32 event;
62 __be32 mask;
63 __be32 command;
64 __be32 transmit;
65 __be32 receive;
66};
67
4c1fba44
AV		 68/* SPI Parameter RAM */
69struct spi_pram {
70 __be16 rbase; /* Rx Buffer descriptor base address */
71 __be16 tbase; /* Tx Buffer descriptor base address */
72 u8 rfcr; /* Rx function code */
73 u8 tfcr; /* Tx function code */
74 __be16 mrblr; /* Max receive buffer length */
75 __be32 rstate; /* Internal */
76 __be32 rdp; /* Internal */
77 __be16 rbptr; /* Internal */
78 __be16 rbc; /* Internal */
79 __be32 rxtmp; /* Internal */
80 __be32 tstate; /* Internal */
81 __be32 tdp; /* Internal */
82 __be16 tbptr; /* Internal */
83 __be16 tbc; /* Internal */
84 __be32 txtmp; /* Internal */
85 __be32 res; /* Tx temp. */
86 __be16 rpbase; /* Relocation pointer (CPM1 only) */
87 __be16 res1; /* Reserved */
88};
89
ccf06998 90/* SPI Controller mode register definitions */
2a485d7a 91#define SPMODE_LOOP (1 << 30)
ccf06998
KG		 92#define SPMODE_CI_INACTIVEHIGH (1 << 29)
93#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
94#define SPMODE_DIV16 (1 << 27)
95#define SPMODE_REV (1 << 26)
96#define SPMODE_MS (1 << 25)
97#define SPMODE_ENABLE (1 << 24)
98#define SPMODE_LEN(x) ((x) << 20)
99#define SPMODE_PM(x) ((x) << 16)
f29ba280 100#define SPMODE_OP (1 << 14)
c9bfcb31 101#define SPMODE_CG(x) ((x) << 7)
ccf06998
KG		 102
103/*
104 * Default for SPI Mode:
105 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
106 */
107#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
108 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
109
110/* SPIE register values */
111#define SPIE_NE 0x00000200 /* Not empty */
112#define SPIE_NF 0x00000100 /* Not full */
113
114/* SPIM register values */
115#define SPIM_NE 0x00000200 /* Not empty */
116#define SPIM_NF 0x00000100 /* Not full */
117
4c1fba44
AV		 118#define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
119#define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
120
121/* SPCOM register values */
122#define SPCOM_STR (1 << 23) /* Start transmit */
123
124#define SPI_PRAM_SIZE 0x100
125#define SPI_MRBLR ((unsigned int)PAGE_SIZE)
126
ccf06998 127/* SPI Controller driver's private data. */
575c5807 128struct mpc8xxx_spi {
4c1fba44 129 struct device *dev;
575c5807 130 struct mpc8xxx_spi_reg __iomem *base;
ccf06998
KG		 131
132 /* rx & tx bufs from the spi_transfer */
133 const void *tx;
134 void *rx;
135
4c1fba44
AV		 136 int subblock;
137 struct spi_pram __iomem *pram;
138 struct cpm_buf_desc __iomem *tx_bd;
139 struct cpm_buf_desc __iomem *rx_bd;
140
141 struct spi_transfer *xfer_in_progress;
142
143 /* dma addresses for CPM transfers */
144 dma_addr_t tx_dma;
145 dma_addr_t rx_dma;
146 bool map_tx_dma;
147 bool map_rx_dma;
148
149 dma_addr_t dma_dummy_tx;
150 dma_addr_t dma_dummy_rx;
151
ccf06998 152 /* functions to deal with different sized buffers */
575c5807
AV		 153 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
154 u32(*get_tx) (struct mpc8xxx_spi *);
ccf06998
KG		 155
156 unsigned int count;
35b4b3c0 157 unsigned int irq;
ccf06998
KG		 158
159 unsigned nsecs; /* (clock cycle time)/2 */
160
e24a4d1e 161 u32 spibrg; /* SPIBRG input clock */
f29ba280
JT		 162 u32 rx_shift; /* RX data reg shift when in qe mode */
163 u32 tx_shift; /* TX data reg shift when in qe mode */
164
87ec0e98 165 unsigned int flags;
f29ba280 166
c9bfcb31
JT		 167 struct workqueue_struct *workqueue;
168 struct work_struct work;
169
170 struct list_head queue;
171 spinlock_t lock;
172
173 struct completion done;
174};
175
4c1fba44
AV		 176static void *mpc8xxx_dummy_rx;
177static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
178static int mpc8xxx_dummy_rx_refcnt;
179
575c5807 180struct spi_mpc8xxx_cs {
c9bfcb31 181 /* functions to deal with different sized buffers */
575c5807
AV		 182 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
183 u32 (*get_tx) (struct mpc8xxx_spi *);
c9bfcb31
JT		 184 u32 rx_shift; /* RX data reg shift when in qe mode */
185 u32 tx_shift; /* TX data reg shift when in qe mode */
186 u32 hw_mode; /* Holds HW mode register settings */
ccf06998
KG		 187};
188
575c5807 189static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
ccf06998
KG		 190{
191 out_be32(reg, val);
192}
193
575c5807 194static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
ccf06998
KG		 195{
196 return in_be32(reg);
197}
198
199#define MPC83XX_SPI_RX_BUF(type) \
34c8a20c 200static \
575c5807 201void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
ccf06998 202{ \
575c5807
AV		 203 type *rx = mpc8xxx_spi->rx; \
204 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
205 mpc8xxx_spi->rx = rx; \
ccf06998
KG		 206}
207
208#define MPC83XX_SPI_TX_BUF(type) \
34c8a20c 209static \
575c5807 210u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
ccf06998
KG		 211{ \
212 u32 data; \
575c5807 213 const type *tx = mpc8xxx_spi->tx; \
4b1badf5
DB		 214 if (!tx) \
215 return 0; \
575c5807
AV		 216 data = *tx++ << mpc8xxx_spi->tx_shift; \
217 mpc8xxx_spi->tx = tx; \
ccf06998
KG		 218 return data; \
219}
220
221MPC83XX_SPI_RX_BUF(u8)
222MPC83XX_SPI_RX_BUF(u16)
223MPC83XX_SPI_RX_BUF(u32)
224MPC83XX_SPI_TX_BUF(u8)
225MPC83XX_SPI_TX_BUF(u16)
226MPC83XX_SPI_TX_BUF(u32)
227
a35c1710
AV		 228static void mpc8xxx_spi_change_mode(struct spi_device *spi)
229{
230 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
231 struct spi_mpc8xxx_cs *cs = spi->controller_state;
232 __be32 __iomem *mode = &mspi->base->mode;
233 unsigned long flags;
234
235 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
236 return;
237
238 /* Turn off IRQs locally to minimize time that SPI is disabled. */
239 local_irq_save(flags);
240
241 /* Turn off SPI unit prior changing mode */
242 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
243 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
244
4c1fba44
AV		 245 /* When in CPM mode, we need to reinit tx and rx. */
246 if (mspi->flags & SPI_CPM_MODE) {
247 if (mspi->flags & SPI_QE) {
248 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
249 QE_CR_PROTOCOL_UNSPECIFIED, 0);
250 } else {
251 cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
252 if (mspi->flags & SPI_CPM1) {
253 out_be16(&mspi->pram->rbptr,
254 in_be16(&mspi->pram->rbase));
255 out_be16(&mspi->pram->tbptr,
256 in_be16(&mspi->pram->tbase));
257 }
258 }
259 }
260
a35c1710
AV		 261 local_irq_restore(flags);
262}
263
575c5807 264static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
ccf06998 265{
575c5807 266 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
364fdbc0
AV		 267 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
268 bool pol = spi->mode & SPI_CS_HIGH;
575c5807 269 struct spi_mpc8xxx_cs *cs = spi->controller_state;
ccf06998 270
ccf06998 271 if (value == BITBANG_CS_INACTIVE) {
364fdbc0
AV		 272 if (pdata->cs_control)
273 pdata->cs_control(spi, !pol);
ccf06998
KG		 274 }
275
276 if (value == BITBANG_CS_ACTIVE) {
575c5807
AV		 277 mpc8xxx_spi->rx_shift = cs->rx_shift;
278 mpc8xxx_spi->tx_shift = cs->tx_shift;
279 mpc8xxx_spi->get_rx = cs->get_rx;
280 mpc8xxx_spi->get_tx = cs->get_tx;
c9bfcb31 281
a35c1710
AV		 282 mpc8xxx_spi_change_mode(spi);
283
364fdbc0
AV		 284 if (pdata->cs_control)
285 pdata->cs_control(spi, pol);
ccf06998
KG		 286 }
287}
288
289static
575c5807 290int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
ccf06998 291{
575c5807 292 struct mpc8xxx_spi *mpc8xxx_spi;
c9bfcb31 293 u8 bits_per_word, pm;
ccf06998 294 u32 hz;
575c5807 295 struct spi_mpc8xxx_cs *cs = spi->controller_state;
ccf06998 296
575c5807 297 mpc8xxx_spi = spi_master_get_devdata(spi->master);
ccf06998
KG		 298
299 if (t) {
300 bits_per_word = t->bits_per_word;
301 hz = t->speed_hz;
302 } else {
303 bits_per_word = 0;
304 hz = 0;
305 }
306
307 /* spi_transfer level calls that work per-word */
308 if (!bits_per_word)
309 bits_per_word = spi->bits_per_word;
310
311 /* Make sure its a bit width we support [4..16, 32] */
312 if ((bits_per_word < 4)
313 || ((bits_per_word > 16) && (bits_per_word != 32)))
314 return -EINVAL;
315
c9bfcb31
JT		 316 if (!hz)
317 hz = spi->max_speed_hz;
318
319 cs->rx_shift = 0;
320 cs->tx_shift = 0;
ccf06998 321 if (bits_per_word <= 8) {
575c5807
AV		 322 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
323 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
87ec0e98 324 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
c9bfcb31
JT		 325 cs->rx_shift = 16;
326 cs->tx_shift = 24;
f29ba280 327 }
ccf06998 328 } else if (bits_per_word <= 16) {
575c5807
AV		 329 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
330 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
87ec0e98 331 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
c9bfcb31
JT		 332 cs->rx_shift = 16;
333 cs->tx_shift = 16;
f29ba280 334 }
ccf06998 335 } else if (bits_per_word <= 32) {
575c5807
AV		 336 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
337 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
ccf06998
KG		 338 } else
339 return -EINVAL;
340
87ec0e98
AV		 341 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
342 spi->mode & SPI_LSB_FIRST) {
c9bfcb31 343 cs->tx_shift = 0;
35cc0b97 344 if (bits_per_word <= 8)
c9bfcb31 345 cs->rx_shift = 8;
35cc0b97 346 else
c9bfcb31 347 cs->rx_shift = 0;
35cc0b97
AV		 348 }
349
575c5807
AV		 350 mpc8xxx_spi->rx_shift = cs->rx_shift;
351 mpc8xxx_spi->tx_shift = cs->tx_shift;
352 mpc8xxx_spi->get_rx = cs->get_rx;
353 mpc8xxx_spi->get_tx = cs->get_tx;
ccf06998
KG		 354
355 if (bits_per_word == 32)
356 bits_per_word = 0;
357 else
358 bits_per_word = bits_per_word - 1;
359
32421daa 360 /* mask out bits we are going to set */
c9bfcb31
JT		 361 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
362 | SPMODE_PM(0xF));
363
364 cs->hw_mode |= SPMODE_LEN(bits_per_word);
365
575c5807 366 if ((mpc8xxx_spi->spibrg / hz) > 64) {
53604dbe 367 cs->hw_mode |= SPMODE_DIV16;
575c5807 368 pm = mpc8xxx_spi->spibrg / (hz * 64);
fd8a11e1
AV		 369
370 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
371 "Will use %d Hz instead.\n", dev_name(&spi->dev),
575c5807 372 hz, mpc8xxx_spi->spibrg / 1024);
fd8a11e1 373 if (pm > 16)
53604dbe 374 pm = 16;
a61f5345 375 } else
575c5807 376 pm = mpc8xxx_spi->spibrg / (hz * 4);
a61f5345
CG		 377 if (pm)
378 pm--;
379
380 cs->hw_mode |= SPMODE_PM(pm);
a35c1710
AV		 381
382 mpc8xxx_spi_change_mode(spi);
c9bfcb31
JT		 383 return 0;
384}
ccf06998 385
4c1fba44 386static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
c9bfcb31 387{
4c1fba44
AV		 388 struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
389 struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
390 unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
391 unsigned int xfer_ofs;
ccf06998 392
4c1fba44
AV		 393 xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
394
395 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
396 out_be16(&rx_bd->cbd_datlen, 0);
397 out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
398
399 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
400 out_be16(&tx_bd->cbd_datlen, xfer_len);
401 out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
402 BD_SC_LAST);
403
404 /* start transfer */
405 mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR);
406}
407
408static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
409 struct spi_transfer *t, bool is_dma_mapped)
410{
411 struct device *dev = mspi->dev;
412
413 if (is_dma_mapped) {
414 mspi->map_tx_dma = 0;
415 mspi->map_rx_dma = 0;
416 } else {
417 mspi->map_tx_dma = 1;
418 mspi->map_rx_dma = 1;
419 }
420
421 if (!t->tx_buf) {
422 mspi->tx_dma = mspi->dma_dummy_tx;
423 mspi->map_tx_dma = 0;
424 }
425
426 if (!t->rx_buf) {
427 mspi->rx_dma = mspi->dma_dummy_rx;
428 mspi->map_rx_dma = 0;
429 }
430
431 if (mspi->map_tx_dma) {
432 void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
433
434 mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
435 DMA_TO_DEVICE);
436 if (dma_mapping_error(dev, mspi->tx_dma)) {
437 dev_err(dev, "unable to map tx dma\n");
438 return -ENOMEM;
439 }
440 } else {
441 mspi->tx_dma = t->tx_dma;
442 }
443
444 if (mspi->map_rx_dma) {
445 mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
446 DMA_FROM_DEVICE);
447 if (dma_mapping_error(dev, mspi->rx_dma)) {
448 dev_err(dev, "unable to map rx dma\n");
449 goto err_rx_dma;
450 }
451 } else {
452 mspi->rx_dma = t->rx_dma;
453 }
454
455 /* enable rx ints */
456 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB);
457
458 mspi->xfer_in_progress = t;
459 mspi->count = t->len;
460
461 /* start CPM transfers */
462 mpc8xxx_spi_cpm_bufs_start(mspi);
463
464 return 0;
465
466err_rx_dma:
467 if (mspi->map_tx_dma)
468 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
469 return -ENOMEM;
470}
471
472static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
473{
474 struct device *dev = mspi->dev;
475 struct spi_transfer *t = mspi->xfer_in_progress;
476
477 if (mspi->map_tx_dma)
478 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
479 if (mspi->map_tx_dma)
480 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
481 mspi->xfer_in_progress = NULL;
482}
483
484static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
485 struct spi_transfer *t, unsigned int len)
486{
487 u32 word;
488
489 mspi->count = len;
490
491 /* enable rx ints */
492 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
493
494 /* transmit word */
495 word = mspi->get_tx(mspi);
496 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
497
498 return 0;
499}
500
501static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
502 bool is_dma_mapped)
503{
504 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
505 unsigned int len = t->len;
506 u8 bits_per_word;
507 int ret;
c9bfcb31 508
c9bfcb31
JT		 509 bits_per_word = spi->bits_per_word;
510 if (t->bits_per_word)
511 bits_per_word = t->bits_per_word;
4c1fba44 512
aa77d96b
PK		 513 if (bits_per_word > 8) {
514 /* invalid length? */
515 if (len & 1)
516 return -EINVAL;
c9bfcb31 517 len /= 2;
aa77d96b
PK		 518 }
519 if (bits_per_word > 16) {
520 /* invalid length? */
521 if (len & 1)
522 return -EINVAL;
c9bfcb31 523 len /= 2;
aa77d96b 524 }
aa77d96b 525
4c1fba44
AV		 526 mpc8xxx_spi->tx = t->tx_buf;
527 mpc8xxx_spi->rx = t->rx_buf;
c9bfcb31 528
4c1fba44 529 INIT_COMPLETION(mpc8xxx_spi->done);
c9bfcb31 530
4c1fba44
AV		 531 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
532 ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
533 else
534 ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);
535 if (ret)
536 return ret;
c9bfcb31 537
575c5807 538 wait_for_completion(&mpc8xxx_spi->done);
c9bfcb31
JT		 539
540 /* disable rx ints */
575c5807 541 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
c9bfcb31 542
4c1fba44
AV		 543 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
544 mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi);
545
575c5807 546 return mpc8xxx_spi->count;
c9bfcb31
JT		 547}
548
575c5807 549static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
c9bfcb31 550{
b9b9af11
AV		 551 struct spi_device *spi = m->spi;
552 struct spi_transfer *t;
553 unsigned int cs_change;
554 const int nsecs = 50;
555 int status;
556
557 cs_change = 1;
558 status = 0;
559 list_for_each_entry(t, &m->transfers, transfer_list) {
560 if (t->bits_per_word || t->speed_hz) {
561 /* Don't allow changes if CS is active */
562 status = -EINVAL;
563
564 if (cs_change)
575c5807 565 status = mpc8xxx_spi_setup_transfer(spi, t);
b9b9af11 566 if (status < 0)
c9bfcb31 567 break;
b9b9af11 568 }
c9bfcb31 569
b9b9af11 570 if (cs_change) {
575c5807 571 mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
b9b9af11
AV		 572 ndelay(nsecs);
573 }
574 cs_change = t->cs_change;
575 if (t->len)
4c1fba44 576 status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
b9b9af11
AV		 577 if (status) {
578 status = -EMSGSIZE;
579 break;
c9bfcb31 580 }
b9b9af11 581 m->actual_length += t->len;
c9bfcb31 582
b9b9af11
AV		 583 if (t->delay_usecs)
584 udelay(t->delay_usecs);
c9bfcb31 585
b9b9af11 586 if (cs_change) {
c9bfcb31 587 ndelay(nsecs);
575c5807 588 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
b9b9af11 589 ndelay(nsecs);
c9bfcb31 590 }
b9b9af11
AV		 591 }
592
593 m->status = status;
594 m->complete(m->context);
595
596 if (status || !cs_change) {
597 ndelay(nsecs);
575c5807 598 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
b9b9af11
AV		 599 }
600
575c5807 601 mpc8xxx_spi_setup_transfer(spi, NULL);
b9b9af11
AV		 602}
603
575c5807 604static void mpc8xxx_spi_work(struct work_struct *work)
b9b9af11 605{
575c5807 606 struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
b9b9af11
AV		 607 work);
608
575c5807
AV		 609 spin_lock_irq(&mpc8xxx_spi->lock);
610 while (!list_empty(&mpc8xxx_spi->queue)) {
611 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
b9b9af11
AV		 612 struct spi_message, queue);
613
614 list_del_init(&m->queue);
575c5807 615 spin_unlock_irq(&mpc8xxx_spi->lock);
c9bfcb31 616
575c5807 617 mpc8xxx_spi_do_one_msg(m);
c9bfcb31 618
575c5807 619 spin_lock_irq(&mpc8xxx_spi->lock);
c9bfcb31 620 }
575c5807 621 spin_unlock_irq(&mpc8xxx_spi->lock);
ccf06998
KG		 622}
623
575c5807 624static int mpc8xxx_spi_setup(struct spi_device *spi)
ccf06998 625{
575c5807 626 struct mpc8xxx_spi *mpc8xxx_spi;
ccf06998 627 int retval;
c9bfcb31 628 u32 hw_mode;
575c5807 629 struct spi_mpc8xxx_cs *cs = spi->controller_state;
ccf06998
KG		 630
631 if (!spi->max_speed_hz)
632 return -EINVAL;
633
c9bfcb31
JT		 634 if (!cs) {
635 cs = kzalloc(sizeof *cs, GFP_KERNEL);
636 if (!cs)
637 return -ENOMEM;
638 spi->controller_state = cs;
639 }
575c5807 640 mpc8xxx_spi = spi_master_get_devdata(spi->master);
ccf06998 641
c9bfcb31 642 hw_mode = cs->hw_mode; /* Save orginal settings */
575c5807 643 cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
c9bfcb31
JT		 644 /* mask out bits we are going to set */
645 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
646 | SPMODE_REV | SPMODE_LOOP);
647
648 if (spi->mode & SPI_CPHA)
649 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
650 if (spi->mode & SPI_CPOL)
651 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
652 if (!(spi->mode & SPI_LSB_FIRST))
653 cs->hw_mode |= SPMODE_REV;
654 if (spi->mode & SPI_LOOP)
655 cs->hw_mode |= SPMODE_LOOP;
656
575c5807 657 retval = mpc8xxx_spi_setup_transfer(spi, NULL);
c9bfcb31
JT		 658 if (retval < 0) {
659 cs->hw_mode = hw_mode; /* Restore settings */
ccf06998 660 return retval;
c9bfcb31 661 }
ccf06998
KG		 662 return 0;
663}
664
4c1fba44 665static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
ccf06998 666{
4c1fba44 667 u16 len;
ccf06998 668
4c1fba44
AV		 669 dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
670 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
ccf06998 671
4c1fba44
AV		 672 len = in_be16(&mspi->rx_bd->cbd_datlen);
673 if (len > mspi->count) {
674 WARN_ON(1);
675 len = mspi->count;
676 }
ccf06998 677
4c1fba44
AV		 678 /* Clear the events */
679 mpc8xxx_spi_write_reg(&mspi->base->event, events);
ccf06998 680
4c1fba44
AV		 681 mspi->count -= len;
682 if (mspi->count)
683 mpc8xxx_spi_cpm_bufs_start(mspi);
684 else
685 complete(&mspi->done);
686}
687
688static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
689{
690 /* We need handle RX first */
691 if (events & SPIE_NE) {
692 u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);
693
694 if (mspi->rx)
695 mspi->get_rx(rx_data, mspi);
ccf06998
KG		 696 }
697
4c1fba44 698 if ((events & SPIE_NF) == 0)
ccf06998 699 /* spin until TX is done */
4c1fba44
AV		 700 while (((events =
701 mpc8xxx_spi_read_reg(&mspi->base->event)) &
ccf06998 702 SPIE_NF) == 0)
9effb959 703 cpu_relax();
ccf06998 704
4c1fba44
AV		 705 /* Clear the events */
706 mpc8xxx_spi_write_reg(&mspi->base->event, events);
707
708 mspi->count -= 1;
709 if (mspi->count) {
710 u32 word = mspi->get_tx(mspi);
711
712 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
ccf06998 713 } else {
4c1fba44 714 complete(&mspi->done);
ccf06998 715 }
4c1fba44 716}
ccf06998 717
4c1fba44
AV		 718static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
719{
720 struct mpc8xxx_spi *mspi = context_data;
721 irqreturn_t ret = IRQ_NONE;
722 u32 events;
723
724 /* Get interrupt events(tx/rx) */
725 events = mpc8xxx_spi_read_reg(&mspi->base->event);
726 if (events)
727 ret = IRQ_HANDLED;
728
729 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
730
731 if (mspi->flags & SPI_CPM_MODE)
732 mpc8xxx_spi_cpm_irq(mspi, events);
733 else
734 mpc8xxx_spi_cpu_irq(mspi, events);
ccf06998
KG		 735
736 return ret;
737}
4c1fba44 738
575c5807 739static int mpc8xxx_spi_transfer(struct spi_device *spi,
c9bfcb31
JT		 740 struct spi_message *m)
741{
575c5807 742 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
c9bfcb31
JT		 743 unsigned long flags;
744
745 m->actual_length = 0;
746 m->status = -EINPROGRESS;
747
575c5807
AV		 748 spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
749 list_add_tail(&m->queue, &mpc8xxx_spi->queue);
750 queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
751 spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
c9bfcb31
JT		 752
753 return 0;
754}
755
756
575c5807 757static void mpc8xxx_spi_cleanup(struct spi_device *spi)
c9bfcb31
JT		 758{
759 kfree(spi->controller_state);
760}
ccf06998 761
4c1fba44
AV		 762static void *mpc8xxx_spi_alloc_dummy_rx(void)
763{
764 mutex_lock(&mpc8xxx_dummy_rx_lock);
765
766 if (!mpc8xxx_dummy_rx)
767 mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
768 if (mpc8xxx_dummy_rx)
769 mpc8xxx_dummy_rx_refcnt++;
770
771 mutex_unlock(&mpc8xxx_dummy_rx_lock);
772
773 return mpc8xxx_dummy_rx;
774}
775
776static void mpc8xxx_spi_free_dummy_rx(void)
777{
778 mutex_lock(&mpc8xxx_dummy_rx_lock);
779
780 switch (mpc8xxx_dummy_rx_refcnt) {
781 case 0:
782 WARN_ON(1);
783 break;
784 case 1:
785 kfree(mpc8xxx_dummy_rx);
786 mpc8xxx_dummy_rx = NULL;
787 /* fall through */
788 default:
789 mpc8xxx_dummy_rx_refcnt--;
790 break;
791 }
792
793 mutex_unlock(&mpc8xxx_dummy_rx_lock);
794}
795
796static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
797{
798 struct device *dev = mspi->dev;
799 struct device_node *np = dev_archdata_get_node(&dev->archdata);
800 const u32 *iprop;
801 int size;
802 unsigned long spi_base_ofs;
803 unsigned long pram_ofs = -ENOMEM;
804
805 /* Can't use of_address_to_resource(), QE muram isn't at 0. */
806 iprop = of_get_property(np, "reg", &size);
807
808 /* QE with a fixed pram location? */
809 if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
810 return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
811
812 /* QE but with a dynamic pram location? */
813 if (mspi->flags & SPI_QE) {
814 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
815 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
816 QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
817 return pram_ofs;
818 }
819
820 /* CPM1 and CPM2 pram must be at a fixed addr. */
821 if (!iprop || size != sizeof(*iprop) * 4)
822 return -ENOMEM;
823
824 spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2);
825 if (IS_ERR_VALUE(spi_base_ofs))
826 return -ENOMEM;
827
828 if (mspi->flags & SPI_CPM2) {
829 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
830 if (!IS_ERR_VALUE(pram_ofs)) {
831 u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs);
832
833 out_be16(spi_base, pram_ofs);
834 }
835 } else {
836 struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs);
837 u16 rpbase = in_be16(&pram->rpbase);
838
839 /* Microcode relocation patch applied? */
840 if (rpbase)
841 pram_ofs = rpbase;
842 else
843 return spi_base_ofs;
844 }
845
846 cpm_muram_free(spi_base_ofs);
847 return pram_ofs;
848}
849
850static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
851{
852 struct device *dev = mspi->dev;
853 struct device_node *np = dev_archdata_get_node(&dev->archdata);
854 const u32 *iprop;
855 int size;
856 unsigned long pram_ofs;
857 unsigned long bds_ofs;
858
859 if (!(mspi->flags & SPI_CPM_MODE))
860 return 0;
861
862 if (!mpc8xxx_spi_alloc_dummy_rx())
863 return -ENOMEM;
864
865 if (mspi->flags & SPI_QE) {
866 iprop = of_get_property(np, "cell-index", &size);
867 if (iprop && size == sizeof(*iprop))
868 mspi->subblock = *iprop;
869
870 switch (mspi->subblock) {
871 default:
872 dev_warn(dev, "cell-index unspecified, assuming SPI1");
873 /* fall through */
874 case 0:
875 mspi->subblock = QE_CR_SUBBLOCK_SPI1;
876 break;
877 case 1:
878 mspi->subblock = QE_CR_SUBBLOCK_SPI2;
879 break;
880 }
881 }
882
883 pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi);
884 if (IS_ERR_VALUE(pram_ofs)) {
885 dev_err(dev, "can't allocate spi parameter ram\n");
886 goto err_pram;
887 }
888
889 bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
890 sizeof(*mspi->rx_bd), 8);
891 if (IS_ERR_VALUE(bds_ofs)) {
892 dev_err(dev, "can't allocate bds\n");
893 goto err_bds;
894 }
895
896 mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
897 DMA_TO_DEVICE);
898 if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
899 dev_err(dev, "unable to map dummy tx buffer\n");
900 goto err_dummy_tx;
901 }
902
903 mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR,
904 DMA_FROM_DEVICE);
905 if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
906 dev_err(dev, "unable to map dummy rx buffer\n");
907 goto err_dummy_rx;
908 }
909
910 mspi->pram = cpm_muram_addr(pram_ofs);
911
912 mspi->tx_bd = cpm_muram_addr(bds_ofs);
913 mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
914
915 /* Initialize parameter ram. */
916 out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
917 out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
918 out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
919 out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
920 out_be16(&mspi->pram->mrblr, SPI_MRBLR);
921 out_be32(&mspi->pram->rstate, 0);
922 out_be32(&mspi->pram->rdp, 0);
923 out_be16(&mspi->pram->rbptr, 0);
924 out_be16(&mspi->pram->rbc, 0);
925 out_be32(&mspi->pram->rxtmp, 0);
926 out_be32(&mspi->pram->tstate, 0);
927 out_be32(&mspi->pram->tdp, 0);
928 out_be16(&mspi->pram->tbptr, 0);
929 out_be16(&mspi->pram->tbc, 0);
930 out_be32(&mspi->pram->txtmp, 0);
931
932 return 0;
933
934err_dummy_rx:
935 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
936err_dummy_tx:
937 cpm_muram_free(bds_ofs);
938err_bds:
939 cpm_muram_free(pram_ofs);
940err_pram:
941 mpc8xxx_spi_free_dummy_rx();
942 return -ENOMEM;
943}
944
945static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
946{
947 struct device *dev = mspi->dev;
948
949 dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
950 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
951 cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
952 cpm_muram_free(cpm_muram_offset(mspi->pram));
953 mpc8xxx_spi_free_dummy_rx();
954}
955
87ec0e98
AV		 956static const char *mpc8xxx_spi_strmode(unsigned int flags)
957{
4c1fba44 958 if (flags & SPI_QE_CPU_MODE) {
87ec0e98 959 return "QE CPU";
4c1fba44
AV		 960 } else if (flags & SPI_CPM_MODE) {
961 if (flags & SPI_QE)
962 return "QE";
963 else if (flags & SPI_CPM2)
964 return "CPM2";
965 else
966 return "CPM1";
967 }
87ec0e98
AV		 968 return "CPU";
969}
970
35b4b3c0 971static struct spi_master * __devinit
575c5807 972mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
ccf06998 973{
35b4b3c0 974 struct fsl_spi_platform_data *pdata = dev->platform_data;
ccf06998 975 struct spi_master *master;
575c5807 976 struct mpc8xxx_spi *mpc8xxx_spi;
ccf06998
KG		 977 u32 regval;
978 int ret = 0;
979
575c5807 980 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
ccf06998
KG		 981 if (master == NULL) {
982 ret = -ENOMEM;
983 goto err;
984 }
985
35b4b3c0 986 dev_set_drvdata(dev, master);
ccf06998 987
e7db06b5
DB		 988 /* the spi->mode bits understood by this driver: */
989 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
990 | SPI_LSB_FIRST | SPI_LOOP;
991
575c5807
AV		 992 master->setup = mpc8xxx_spi_setup;
993 master->transfer = mpc8xxx_spi_transfer;
994 master->cleanup = mpc8xxx_spi_cleanup;
995
996 mpc8xxx_spi = spi_master_get_devdata(master);
4c1fba44 997 mpc8xxx_spi->dev = dev;
575c5807
AV		 998 mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
999 mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
87ec0e98 1000 mpc8xxx_spi->flags = pdata->flags;
575c5807
AV		 1001 mpc8xxx_spi->spibrg = pdata->sysclk;
1002
4c1fba44
AV		 1003 ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi);
1004 if (ret)
1005 goto err_cpm_init;
1006
575c5807
AV		 1007 mpc8xxx_spi->rx_shift = 0;
1008 mpc8xxx_spi->tx_shift = 0;
87ec0e98 1009 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
575c5807
AV		 1010 mpc8xxx_spi->rx_shift = 16;
1011 mpc8xxx_spi->tx_shift = 24;
f29ba280
JT		 1012 }
1013
575c5807 1014 init_completion(&mpc8xxx_spi->done);
ccf06998 1015
575c5807
AV		 1016 mpc8xxx_spi->base = ioremap(mem->start, mem->end - mem->start + 1);
1017 if (mpc8xxx_spi->base == NULL) {
ccf06998 1018 ret = -ENOMEM;
4c1fba44 1019 goto err_ioremap;
ccf06998
KG		 1020 }
1021
575c5807 1022 mpc8xxx_spi->irq = irq;
ccf06998
KG		 1023
1024 /* Register for SPI Interrupt */
575c5807
AV		 1025 ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
1026 0, "mpc8xxx_spi", mpc8xxx_spi);
ccf06998
KG		 1027
1028 if (ret != 0)
1029 goto unmap_io;
1030
1031 master->bus_num = pdata->bus_num;
1032 master->num_chipselect = pdata->max_chipselect;
1033
1034 /* SPI controller initializations */
575c5807
AV		 1035 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
1036 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
1037 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
1038 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
ccf06998
KG		 1039
1040 /* Enable SPI interface */
1041 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
87ec0e98 1042 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
f29ba280
JT		 1043 regval |= SPMODE_OP;
1044
575c5807
AV		 1045 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
1046 spin_lock_init(&mpc8xxx_spi->lock);
1047 init_completion(&mpc8xxx_spi->done);
1048 INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
1049 INIT_LIST_HEAD(&mpc8xxx_spi->queue);
ccf06998 1050
575c5807 1051 mpc8xxx_spi->workqueue = create_singlethread_workqueue(
6c7377ab 1052 dev_name(master->dev.parent));
575c5807 1053 if (mpc8xxx_spi->workqueue == NULL) {
c9bfcb31 1054 ret = -EBUSY;
ccf06998 1055 goto free_irq;
c9bfcb31
JT		 1056 }
1057
1058 ret = spi_register_master(master);
1059 if (ret < 0)
1060 goto unreg_master;
ccf06998 1061
87ec0e98
AV		 1062 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
1063 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
ccf06998 1064
35b4b3c0 1065 return master;
ccf06998 1066
c9bfcb31 1067unreg_master:
575c5807 1068 destroy_workqueue(mpc8xxx_spi->workqueue);
ccf06998 1069free_irq:
575c5807 1070 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
ccf06998 1071unmap_io:
575c5807 1072 iounmap(mpc8xxx_spi->base);
4c1fba44
AV		 1073err_ioremap:
1074 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1075err_cpm_init:
ccf06998 1076 spi_master_put(master);
ccf06998 1077err:
35b4b3c0 1078 return ERR_PTR(ret);
ccf06998
KG		 1079}
1080
575c5807 1081static int __devexit mpc8xxx_spi_remove(struct device *dev)
ccf06998 1082{
575c5807 1083 struct mpc8xxx_spi *mpc8xxx_spi;
ccf06998
KG		 1084 struct spi_master *master;
1085
35b4b3c0 1086 master = dev_get_drvdata(dev);
575c5807 1087 mpc8xxx_spi = spi_master_get_devdata(master);
ccf06998 1088
575c5807
AV		 1089 flush_workqueue(mpc8xxx_spi->workqueue);
1090 destroy_workqueue(mpc8xxx_spi->workqueue);
c9bfcb31
JT		 1091 spi_unregister_master(master);
1092
575c5807
AV		 1093 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1094 iounmap(mpc8xxx_spi->base);
4c1fba44 1095 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
ccf06998
KG		 1096
1097 return 0;
1098}
1099
575c5807 1100struct mpc8xxx_spi_probe_info {
35b4b3c0
AV		 1101 struct fsl_spi_platform_data pdata;
1102 int *gpios;
1103 bool *alow_flags;
1104};
1105
575c5807 1106static struct mpc8xxx_spi_probe_info *
35b4b3c0
AV		 1107to_of_pinfo(struct fsl_spi_platform_data *pdata)
1108{
575c5807 1109 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
35b4b3c0
AV		 1110}
1111
575c5807 1112static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
35b4b3c0
AV		 1113{
1114 struct device *dev = spi->dev.parent;
575c5807 1115 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
35b4b3c0
AV		 1116 u16 cs = spi->chip_select;
1117 int gpio = pinfo->gpios[cs];
1118 bool alow = pinfo->alow_flags[cs];
1119
1120 gpio_set_value(gpio, on ^ alow);
1121}
1122
575c5807 1123static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
35b4b3c0
AV		 1124{
1125 struct device_node *np = dev_archdata_get_node(&dev->archdata);
1126 struct fsl_spi_platform_data *pdata = dev->platform_data;
575c5807 1127 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
35b4b3c0
AV		 1128 unsigned int ngpios;
1129 int i = 0;
1130 int ret;
1131
1132 ngpios = of_gpio_count(np);
1133 if (!ngpios) {
1134 /*
1135 * SPI w/o chip-select line. One SPI device is still permitted
1136 * though.
1137 */
1138 pdata->max_chipselect = 1;
1139 return 0;
1140 }
1141
02141546 1142 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
35b4b3c0
AV		 1143 if (!pinfo->gpios)
1144 return -ENOMEM;
02141546 1145 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
35b4b3c0 1146
02141546 1147 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
35b4b3c0
AV		 1148 GFP_KERNEL);
1149 if (!pinfo->alow_flags) {
1150 ret = -ENOMEM;
1151 goto err_alloc_flags;
1152 }
1153
1154 for (; i < ngpios; i++) {
1155 int gpio;
1156 enum of_gpio_flags flags;
1157
1158 gpio = of_get_gpio_flags(np, i, &flags);
1159 if (!gpio_is_valid(gpio)) {
1160 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
783058fd 1161 ret = gpio;
35b4b3c0
AV		 1162 goto err_loop;
1163 }
1164
1165 ret = gpio_request(gpio, dev_name(dev));
1166 if (ret) {
1167 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
1168 goto err_loop;
1169 }
1170
1171 pinfo->gpios[i] = gpio;
1172 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
1173
1174 ret = gpio_direction_output(pinfo->gpios[i],
1175 pinfo->alow_flags[i]);
1176 if (ret) {
1177 dev_err(dev, "can't set output direction for gpio "
1178 "#%d: %d\n", i, ret);
1179 goto err_loop;
1180 }
1181 }
1182
1183 pdata->max_chipselect = ngpios;
575c5807 1184 pdata->cs_control = mpc8xxx_spi_cs_control;
35b4b3c0
AV		 1185
1186 return 0;
1187
1188err_loop:
1189 while (i >= 0) {
1190 if (gpio_is_valid(pinfo->gpios[i]))
1191 gpio_free(pinfo->gpios[i]);
1192 i--;
1193 }
1194
1195 kfree(pinfo->alow_flags);
1196 pinfo->alow_flags = NULL;
1197err_alloc_flags:
1198 kfree(pinfo->gpios);
1199 pinfo->gpios = NULL;
1200 return ret;
1201}
1202
575c5807 1203static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
35b4b3c0
AV		 1204{
1205 struct fsl_spi_platform_data *pdata = dev->platform_data;
575c5807 1206 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
35b4b3c0
AV		 1207 int i;
1208
1209 if (!pinfo->gpios)
1210 return 0;
1211
1212 for (i = 0; i < pdata->max_chipselect; i++) {
1213 if (gpio_is_valid(pinfo->gpios[i]))
1214 gpio_free(pinfo->gpios[i]);
1215 }
1216
1217 kfree(pinfo->gpios);
1218 kfree(pinfo->alow_flags);
1219 return 0;
1220}
1221
575c5807 1222static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
35b4b3c0
AV		 1223 const struct of_device_id *ofid)
1224{
1225 struct device *dev = &ofdev->dev;
1226 struct device_node *np = ofdev->node;
575c5807 1227 struct mpc8xxx_spi_probe_info *pinfo;
35b4b3c0
AV		 1228 struct fsl_spi_platform_data *pdata;
1229 struct spi_master *master;
1230 struct resource mem;
1231 struct resource irq;
1232 const void *prop;
1233 int ret = -ENOMEM;
1234
1235 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
1236 if (!pinfo)
1237 return -ENOMEM;
1238
1239 pdata = &pinfo->pdata;
1240 dev->platform_data = pdata;
1241
1242 /* Allocate bus num dynamically. */
1243 pdata->bus_num = -1;
1244
1245 /* SPI controller is either clocked from QE or SoC clock. */
1246 pdata->sysclk = get_brgfreq();
1247 if (pdata->sysclk == -1) {
1248 pdata->sysclk = fsl_get_sys_freq();
1249 if (pdata->sysclk == -1) {
1250 ret = -ENODEV;
1251 goto err_clk;
1252 }
1253 }
1254
1255 prop = of_get_property(np, "mode", NULL);
1256 if (prop && !strcmp(prop, "cpu-qe"))
87ec0e98 1257 pdata->flags = SPI_QE_CPU_MODE;
4c1fba44
AV		 1258 else if (prop && !strcmp(prop, "qe"))
1259 pdata->flags = SPI_CPM_MODE | SPI_QE;
1260 else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
1261 pdata->flags = SPI_CPM_MODE | SPI_CPM2;
1262 else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
1263 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
35b4b3c0 1264
575c5807 1265 ret = of_mpc8xxx_spi_get_chipselects(dev);
35b4b3c0
AV		 1266 if (ret)
1267 goto err;
1268
1269 ret = of_address_to_resource(np, 0, &mem);
1270 if (ret)
1271 goto err;
1272
1273 ret = of_irq_to_resource(np, 0, &irq);
1274 if (!ret) {
1275 ret = -EINVAL;
1276 goto err;
1277 }
1278
575c5807 1279 master = mpc8xxx_spi_probe(dev, &mem, irq.start);
35b4b3c0
AV		 1280 if (IS_ERR(master)) {
1281 ret = PTR_ERR(master);
1282 goto err;
1283 }
1284
1285 of_register_spi_devices(master, np);
1286
1287 return 0;
1288
1289err:
575c5807 1290 of_mpc8xxx_spi_free_chipselects(dev);
35b4b3c0
AV		 1291err_clk:
1292 kfree(pinfo);
1293 return ret;
1294}
1295
575c5807 1296static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev)
35b4b3c0
AV		 1297{
1298 int ret;
1299
575c5807 1300 ret = mpc8xxx_spi_remove(&ofdev->dev);
35b4b3c0
AV		 1301 if (ret)
1302 return ret;
575c5807 1303 of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
35b4b3c0
AV		 1304 return 0;
1305}
1306
575c5807 1307static const struct of_device_id of_mpc8xxx_spi_match[] = {
35b4b3c0
AV		 1308 { .compatible = "fsl,spi" },
1309 {},
1310};
575c5807 1311MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
35b4b3c0 1312
575c5807
AV		 1313static struct of_platform_driver of_mpc8xxx_spi_driver = {
1314 .name = "mpc8xxx_spi",
1315 .match_table = of_mpc8xxx_spi_match,
1316 .probe = of_mpc8xxx_spi_probe,
1317 .remove = __devexit_p(of_mpc8xxx_spi_remove),
35b4b3c0
AV		 1318};
1319
1320#ifdef CONFIG_MPC832x_RDB
1321/*
1322 * XXX XXX XXX
1323 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1324 * only. The driver should go away soon, since newer MPC8323E-RDB's device
1325 * tree can work with OpenFirmware driver. But for now we support old trees
1326 * as well.
1327 */
575c5807 1328static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
35b4b3c0
AV		 1329{
1330 struct resource *mem;
1331 unsigned int irq;
1332 struct spi_master *master;
1333
1334 if (!pdev->dev.platform_data)
1335 return -EINVAL;
1336
1337 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1338 if (!mem)
1339 return -EINVAL;
1340
1341 irq = platform_get_irq(pdev, 0);
1342 if (!irq)
1343 return -EINVAL;
1344
575c5807 1345 master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
35b4b3c0
AV		 1346 if (IS_ERR(master))
1347 return PTR_ERR(master);
1348 return 0;
1349}
1350
575c5807 1351static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
35b4b3c0 1352{
575c5807 1353 return mpc8xxx_spi_remove(&pdev->dev);
35b4b3c0
AV		 1354}
1355
575c5807
AV		 1356MODULE_ALIAS("platform:mpc8xxx_spi");
1357static struct platform_driver mpc8xxx_spi_driver = {
1358 .probe = plat_mpc8xxx_spi_probe,
b3a08945 1359 .remove = __devexit_p(plat_mpc8xxx_spi_remove),
ccf06998 1360 .driver = {
575c5807 1361 .name = "mpc8xxx_spi",
7e38c3c4 1362 .owner = THIS_MODULE,
ccf06998
KG		 1363 },
1364};
1365
35b4b3c0
AV		 1366static bool legacy_driver_failed;
1367
1368static void __init legacy_driver_register(void)
1369{
575c5807 1370 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
35b4b3c0
AV		 1371}
1372
1373static void __exit legacy_driver_unregister(void)
1374{
1375 if (legacy_driver_failed)
1376 return;
575c5807 1377 platform_driver_unregister(&mpc8xxx_spi_driver);
35b4b3c0
AV		 1378}
1379#else
1380static void __init legacy_driver_register(void) {}
1381static void __exit legacy_driver_unregister(void) {}
1382#endif /* CONFIG_MPC832x_RDB */
1383
575c5807 1384static int __init mpc8xxx_spi_init(void)
ccf06998 1385{
35b4b3c0 1386 legacy_driver_register();
575c5807 1387 return of_register_platform_driver(&of_mpc8xxx_spi_driver);
ccf06998
KG		 1388}
1389
575c5807 1390static void __exit mpc8xxx_spi_exit(void)
ccf06998 1391{
575c5807 1392 of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
35b4b3c0 1393 legacy_driver_unregister();
ccf06998
KG		 1394}
1395
575c5807
AV		 1396module_init(mpc8xxx_spi_init);
1397module_exit(mpc8xxx_spi_exit);
ccf06998
KG		 1398
1399MODULE_AUTHOR("Kumar Gala");
575c5807 1400MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
ccf06998 1401MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)