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scsi: qla2xxx: Enable type checking for the SRB free and done callback functions
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
585def9b
QT		 17#include <linux/refcount.h>
18
1da177e4
LT		 19#include <scsi/scsi_tcq.h>
20#include <scsi/scsicam.h>
21#include <scsi/scsi_transport.h>
22#include <scsi/scsi_transport_fc.h>
23
2d70c103
NB		 24#include "qla_target.h"
25
1da177e4
LT		 26/*
27 * Driver version
28 */
29char qla2x00_version_str[40];
30
6a03b4cd
HZ		 31static int apidev_major;
32
1da177e4
LT		 33/*
34 * SRB allocation cache
35 */
d7459527 36struct kmem_cache *srb_cachep;
1da177e4 37
a9083016
GM		 38/*
39 * CT6 CTX allocation cache
40 */
41static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 42/*
43 * error level for logging
44 */
3f006ac3 45uint ql_errlev = 0x8001;
a9083016 46
fa492630 47static int ql2xenableclass2;
2d70c103
NB		 48module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
49MODULE_PARM_DESC(ql2xenableclass2,
50 "Specify if Class 2 operations are supported from the very "
51 "beginning. Default is 0 - class 2 not supported.");
52
8ae6d9c7 53
1da177e4 54int ql2xlogintimeout = 20;
f2019cb1 55module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 56MODULE_PARM_DESC(ql2xlogintimeout,
57 "Login timeout value in seconds.");
58
a7b61842 59int qlport_down_retry;
f2019cb1 60module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 61MODULE_PARM_DESC(qlport_down_retry,
900d9f98 62 "Maximum number of command retries to a port that returns "
1da177e4
LT		 63 "a PORT-DOWN status.");
64
1da177e4
LT		 65int ql2xplogiabsentdevice;
66module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
67MODULE_PARM_DESC(ql2xplogiabsentdevice,
68 "Option to enable PLOGI to devices that are not present after "
900d9f98 69 "a Fabric scan. This is needed for several broken switches. "
0d52e642 70 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
1da177e4 71
c1c7178c 72int ql2xloginretrycount;
f2019cb1 73module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 74MODULE_PARM_DESC(ql2xloginretrycount,
75 "Specify an alternate value for the NVRAM login retry count.");
76
a7a167bf 77int ql2xallocfwdump = 1;
f2019cb1 78module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 79MODULE_PARM_DESC(ql2xallocfwdump,
80 "Option to enable allocation of memory for a firmware dump "
81 "during HBA initialization. Memory allocation requirements "
82 "vary by ISP type. Default is 1 - allocate memory.");
83
11010fec 84int ql2xextended_error_logging;
27d94035 85module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 86module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 87MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 88 "Option to enable extended error logging,\n"
89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 100 "\t\t0x1e400000 - Preferred value for capturing essential "
101 "debug information (equivalent to old "
102 "ql2xextended_error_logging=1).\n"
3ce8866c 103 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 104
a9083016 105int ql2xshiftctondsd = 6;
f2019cb1 106module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 107MODULE_PARM_DESC(ql2xshiftctondsd,
108 "Set to control shifting of command type processing "
109 "based on total number of SG elements.");
110
58e2753c 111int ql2xfdmienable = 1;
de187df8 112module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 113module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 114MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 115 "Enables FDMI registrations. "
116 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 117
d213a4b7 118#define MAX_Q_DEPTH 64
50280c01 119static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 120module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
121MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 122 "Maximum queue depth to set for each LUN. "
d213a4b7 123 "Default is 64.");
df7baa50 124
e84067d7
DG		 125#if (IS_ENABLED(CONFIG_NVME_FC))
126int ql2xenabledif;
127#else
9e522cd8 128int ql2xenabledif = 2;
e84067d7 129#endif
9e522cd8 130module_param(ql2xenabledif, int, S_IRUGO);
bad75002 131MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 132 " Enable T10-CRC-DIF:\n"
133 " Default is 2.\n"
134 " 0 -- No DIF Support\n"
135 " 1 -- Enable DIF for all types\n"
136 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 137
e84067d7
DG		 138#if (IS_ENABLED(CONFIG_NVME_FC))
139int ql2xnvmeenable = 1;
140#else
141int ql2xnvmeenable;
142#endif
143module_param(ql2xnvmeenable, int, 0644);
144MODULE_PARM_DESC(ql2xnvmeenable,
145 "Enables NVME support. "
146 "0 - no NVMe. Default is Y");
147
8cb2049c 148int ql2xenablehba_err_chk = 2;
bad75002
AE		 149module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
150MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 151 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 152 " Default is 2.\n"
8cb2049c
AE		 153 " 0 -- Error isolation disabled\n"
154 " 1 -- Error isolation enabled only for DIX Type 0\n"
155 " 2 -- Error isolation enabled for all Types\n");
bad75002 156
58e2753c 157int ql2xiidmaenable = 1;
f2019cb1 158module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 159MODULE_PARM_DESC(ql2xiidmaenable,
160 "Enables iIDMA settings "
161 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
162
d7459527
MH		 163int ql2xmqsupport = 1;
164module_param(ql2xmqsupport, int, S_IRUGO);
165MODULE_PARM_DESC(ql2xmqsupport,
166 "Enable on demand multiple queue pairs support "
167 "Default is 1 for supported. "
168 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 169
170int ql2xfwloadbin;
86e45bf6 171module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 172module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 173MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 174 "Option to specify location from which to load ISP firmware:.\n"
175 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 176 " interface.\n"
177 " 1 -- load firmware from flash.\n"
178 " 0 -- use default semantics.\n");
179
ae97c91e 180int ql2xetsenable;
f2019cb1 181module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 182MODULE_PARM_DESC(ql2xetsenable,
183 "Enables firmware ETS burst."
184 "Default is 0 - skip ETS enablement.");
185
6907869d 186int ql2xdbwr = 1;
86e45bf6 187module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 188MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 189 "Option to specify scheme for request queue posting.\n"
190 " 0 -- Regular doorbell.\n"
191 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 192
f4c496c1 193int ql2xtargetreset = 1;
f2019cb1 194module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 195MODULE_PARM_DESC(ql2xtargetreset,
196 "Enable target reset."
197 "Default is 1 - use hw defaults.");
198
4da26e16 199int ql2xgffidenable;
f2019cb1 200module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 201MODULE_PARM_DESC(ql2xgffidenable,
202 "Enables GFF_ID checks of port type. "
203 "Default is 0 - Do not use GFF_ID information.");
a9083016 204
043dc1d7 205int ql2xasynctmfenable = 1;
f2019cb1 206module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 207MODULE_PARM_DESC(ql2xasynctmfenable,
208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
84e13c45 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 210
211int ql2xdontresethba;
86e45bf6 212module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 213MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 214 "Option to specify reset behaviour.\n"
215 " 0 (Default) -- Reset on failure.\n"
216 " 1 -- Do not reset on failure.\n");
ed0de87c 217
1abf635d
HR		 218uint64_t ql2xmaxlun = MAX_LUNS;
219module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 220MODULE_PARM_DESC(ql2xmaxlun,
221 "Defines the maximum LU number to register with the SCSI "
222 "midlayer. Default is 65535.");
223
08de2844
GM		 224int ql2xmdcapmask = 0x1F;
225module_param(ql2xmdcapmask, int, S_IRUGO);
226MODULE_PARM_DESC(ql2xmdcapmask,
227 "Set the Minidump driver capture mask level. "
6e96fa7b 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 229
3aadff35 230int ql2xmdenable = 1;
08de2844
GM		 231module_param(ql2xmdenable, int, S_IRUGO);
232MODULE_PARM_DESC(ql2xmdenable,
233 "Enable/disable MiniDump. "
3aadff35
GM		 234 "0 - MiniDump disabled. "
235 "1 (Default) - MiniDump enabled.");
08de2844 236
c1c7178c 237int ql2xexlogins;
b0d6cabd
HM		 238module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
239MODULE_PARM_DESC(ql2xexlogins,
240 "Number of extended Logins. "
241 "0 (Default)- Disabled.");
242
99e1b683
QT		 243int ql2xexchoffld = 1024;
244module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 245MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 246 "Number of target exchanges.");
247
248int ql2xiniexchg = 1024;
249module_param(ql2xiniexchg, uint, 0644);
250MODULE_PARM_DESC(ql2xiniexchg,
251 "Number of initiator exchanges.");
2f56a7f1 252
c1c7178c 253int ql2xfwholdabts;
f198cafa
HM		 254module_param(ql2xfwholdabts, int, S_IRUGO);
255MODULE_PARM_DESC(ql2xfwholdabts,
256 "Allow FW to hold status IOCB until ABTS rsp received. "
257 "0 (Default) Do not set fw option. "
258 "1 - Set fw option to hold ABTS.");
259
41dc529a
QT		 260int ql2xmvasynctoatio = 1;
261module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
262MODULE_PARM_DESC(ql2xmvasynctoatio,
263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
264 "0 (Default). Do not move IOCBs"
265 "1 - Move IOCBs.");
266
e4e3a2ce
QT		 267int ql2xautodetectsfp = 1;
268module_param(ql2xautodetectsfp, int, 0444);
269MODULE_PARM_DESC(ql2xautodetectsfp,
270 "Detect SFP range and set appropriate distance.\n"
271 "1 (Default): Enable\n");
272
e7240af5
HM		 273int ql2xenablemsix = 1;
274module_param(ql2xenablemsix, int, 0444);
275MODULE_PARM_DESC(ql2xenablemsix,
276 "Set to enable MSI or MSI-X interrupt mechanism.\n"
277 " Default is 1, enable MSI-X interrupt mechanism.\n"
278 " 0 -- enable traditional pin-based mechanism.\n"
279 " 1 -- enable MSI-X interrupt mechanism.\n"
280 " 2 -- enable MSI interrupt mechanism.\n");
281
9ecf0b0d
QT		 282int qla2xuseresexchforels;
283module_param(qla2xuseresexchforels, int, 0444);
284MODULE_PARM_DESC(qla2xuseresexchforels,
285 "Reserve 1/2 of emergency exchanges for ELS.\n"
286 " 0 (default): disabled");
287
b3ede8ea 288static int ql2xprotmask;
7855d2ba
MP		 289module_param(ql2xprotmask, int, 0644);
290MODULE_PARM_DESC(ql2xprotmask,
291 "Override DIF/DIX protection capabilities mask\n"
292 "Default is 0 which sets protection mask based on "
293 "capabilities reported by HBA firmware.\n");
294
b3ede8ea 295static int ql2xprotguard;
7855d2ba
MP		 296module_param(ql2xprotguard, int, 0644);
297MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
298 " 0 -- Let HBA firmware decide\n"
299 " 1 -- Force T10 CRC\n"
300 " 2 -- Force IP checksum\n");
301
50b81275
GM		 302int ql2xdifbundlinginternalbuffers;
303module_param(ql2xdifbundlinginternalbuffers, int, 0644);
304MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
305 "Force using internal buffers for DIF information\n"
306 "0 (Default). Based on check.\n"
307 "1 Force using internal buffers\n");
308
1a2fbf18 309static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 310static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 311static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 312static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 313
45235022 314
1da177e4 315static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 316struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 317
1da177e4
LT		 318/* TODO Convert to inlines
319 *
320 * Timer routines
321 */
1da177e4 322
2c3dfe3f 323__inline__ void
8e5f4ba0 324qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 325{
8e5f4ba0 326 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 327 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 328 add_timer(&vha->timer);
329 vha->timer_active = 1;
1da177e4
LT		 330}
331
332static inline void
e315cd28 333qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 334{
a9083016 335 /* Currently used for 82XX only. */
7c3df132
SK		 336 if (vha->device_flags & DFLG_DEV_FAILED) {
337 ql_dbg(ql_dbg_timer, vha, 0x600d,
338 "Device in a failed state, returning.\n");
a9083016 339 return;
7c3df132 340 }
a9083016 341
e315cd28 342 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 343}
344
a824ebb3 345static __inline__ void
e315cd28 346qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 347{
e315cd28
AC		 348 del_timer_sync(&vha->timer);
349 vha->timer_active = 0;
1da177e4
LT		 350}
351
1da177e4
LT		 352static int qla2x00_do_dpc(void *data);
353
354static void qla2x00_rst_aen(scsi_qla_host_t *);
355
73208dfd
AC		 356static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
357 struct req_que **, struct rsp_que **);
e30d1756 358static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 359static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 360int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
361 struct qla_qpair *qpair);
1da177e4 362
1da177e4 363/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 364static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
365 struct rsp_que *rsp)
366{
367 struct qla_hw_data *ha = vha->hw;
bd432bb5 368
8abfa9e2
QT		 369 rsp->qpair = ha->base_qpair;
370 rsp->req = req;
0691094f 371 ha->base_qpair->hw = ha;
8abfa9e2
QT		 372 ha->base_qpair->req = req;
373 ha->base_qpair->rsp = rsp;
374 ha->base_qpair->vha = vha;
375 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
376 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
377 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
6a629468 378 ha->base_qpair->srb_mempool = ha->srb_mempool;
8abfa9e2
QT		 379 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
380 ha->base_qpair->enable_class_2 = ql2xenableclass2;
381 /* init qpair to this cpu. Will adjust at run time. */
86531887 382 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 383 ha->base_qpair->pdev = ha->pdev;
384
ecc89f25 385 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
8abfa9e2
QT		 386 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
387}
388
9a347ff4
CD		 389static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
390 struct rsp_que *rsp)
73208dfd 391{
7c3df132 392 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
bd432bb5 393
6396bb22 394 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 395 GFP_KERNEL);
396 if (!ha->req_q_map) {
7c3df132
SK		 397 ql_log(ql_log_fatal, vha, 0x003b,
398 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 399 goto fail_req_map;
400 }
401
6396bb22 402 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 403 GFP_KERNEL);
404 if (!ha->rsp_q_map) {
7c3df132
SK		 405 ql_log(ql_log_fatal, vha, 0x003c,
406 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 407 goto fail_rsp_map;
408 }
d7459527 409
e326d22a
QT		 410 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
411 if (ha->base_qpair == NULL) {
412 ql_log(ql_log_warn, vha, 0x00e0,
413 "Failed to allocate base queue pair memory.\n");
414 goto fail_base_qpair;
415 }
416
8abfa9e2 417 qla_init_base_qpair(vha, req, rsp);
e326d22a 418
c38d1baf 419 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 420 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
421 GFP_KERNEL);
422 if (!ha->queue_pair_map) {
423 ql_log(ql_log_fatal, vha, 0x0180,
424 "Unable to allocate memory for queue pair ptrs.\n");
425 goto fail_qpair_map;
426 }
d7459527
MH		 427 }
428
9a347ff4
CD		 429 /*
430 * Make sure we record at least the request and response queue zero in
431 * case we need to free them if part of the probe fails.
432 */
433 ha->rsp_q_map[0] = rsp;
434 ha->req_q_map[0] = req;
73208dfd
AC		 435 set_bit(0, ha->rsp_qid_map);
436 set_bit(0, ha->req_qid_map);
6a2cf8d3 437 return 0;
73208dfd 438
d7459527 439fail_qpair_map:
82de802a
QT		 440 kfree(ha->base_qpair);
441 ha->base_qpair = NULL;
442fail_base_qpair:
d7459527
MH		 443 kfree(ha->rsp_q_map);
444 ha->rsp_q_map = NULL;
73208dfd
AC		 445fail_rsp_map:
446 kfree(ha->req_q_map);
447 ha->req_q_map = NULL;
448fail_req_map:
449 return -ENOMEM;
450}
451
2afa19a9 452static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 453{
8ae6d9c7
GM		 454 if (IS_QLAFX00(ha)) {
455 if (req && req->ring_fx00)
456 dma_free_coherent(&ha->pdev->dev,
457 (req->length_fx00 + 1) * sizeof(request_t),
458 req->ring_fx00, req->dma_fx00);
459 } else if (req && req->ring)
73208dfd
AC		 460 dma_free_coherent(&ha->pdev->dev,
461 (req->length + 1) * sizeof(request_t),
462 req->ring, req->dma);
463
6d634067 464 if (req)
8d93f550 465 kfree(req->outstanding_cmds);
6d634067
BK		 466
467 kfree(req);
73208dfd
AC		 468}
469
2afa19a9
AC		 470static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
471{
8ae6d9c7 472 if (IS_QLAFX00(ha)) {
3f6c9be2 473 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 474 dma_free_coherent(&ha->pdev->dev,
475 (rsp->length_fx00 + 1) * sizeof(request_t),
476 rsp->ring_fx00, rsp->dma_fx00);
477 } else if (rsp && rsp->ring) {
2afa19a9
AC		 478 dma_free_coherent(&ha->pdev->dev,
479 (rsp->length + 1) * sizeof(response_t),
480 rsp->ring, rsp->dma);
8ae6d9c7 481 }
6d634067 482 kfree(rsp);
2afa19a9
AC		 483}
484
73208dfd
AC		 485static void qla2x00_free_queues(struct qla_hw_data *ha)
486{
487 struct req_que *req;
488 struct rsp_que *rsp;
489 int cnt;
093df737 490 unsigned long flags;
73208dfd 491
82de802a
QT		 492 if (ha->queue_pair_map) {
493 kfree(ha->queue_pair_map);
494 ha->queue_pair_map = NULL;
495 }
496 if (ha->base_qpair) {
497 kfree(ha->base_qpair);
498 ha->base_qpair = NULL;
499 }
500
093df737 501 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 502 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 503 if (!test_bit(cnt, ha->req_qid_map))
504 continue;
505
73208dfd 506 req = ha->req_q_map[cnt];
093df737
QT		 507 clear_bit(cnt, ha->req_qid_map);
508 ha->req_q_map[cnt] = NULL;
509
510 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 511 qla2x00_free_req_que(ha, req);
093df737 512 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 513 }
093df737
QT		 514 spin_unlock_irqrestore(&ha->hardware_lock, flags);
515
73208dfd
AC		 516 kfree(ha->req_q_map);
517 ha->req_q_map = NULL;
2afa19a9 518
093df737
QT		 519
520 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 521 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 522 if (!test_bit(cnt, ha->rsp_qid_map))
523 continue;
524
2afa19a9 525 rsp = ha->rsp_q_map[cnt];
c3c42394 526 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 527 ha->rsp_q_map[cnt] = NULL;
528 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 529 qla2x00_free_rsp_que(ha, rsp);
093df737 530 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 531 }
093df737
QT		 532 spin_unlock_irqrestore(&ha->hardware_lock, flags);
533
2afa19a9
AC		 534 kfree(ha->rsp_q_map);
535 ha->rsp_q_map = NULL;
73208dfd
AC		 536}
537
1da177e4 538static char *
dc6d6d34 539qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
1da177e4 540{
e315cd28 541 struct qla_hw_data *ha = vha->hw;
dc6d6d34 542 static const char *const pci_bus_modes[] = {
1da177e4
LT		 543 "33", "66", "100", "133",
544 };
545 uint16_t pci_bus;
546
1da177e4
LT		 547 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
548 if (pci_bus) {
dc6d6d34
BVA		 549 snprintf(str, str_len, "PCI-X (%s MHz)",
550 pci_bus_modes[pci_bus]);
1da177e4
LT		 551 } else {
552 pci_bus = (ha->pci_attr & BIT_8) >> 8;
dc6d6d34 553 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
1da177e4 554 }
1da177e4 555
dc6d6d34 556 return str;
1da177e4
LT		 557}
558
fca29703 559static char *
dc6d6d34 560qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
fca29703 561{
dc6d6d34
BVA		 562 static const char *const pci_bus_modes[] = {
563 "33", "66", "100", "133",
564 };
e315cd28 565 struct qla_hw_data *ha = vha->hw;
fca29703 566 uint32_t pci_bus;
fca29703 567
62a276f8 568 if (pci_is_pcie(ha->pdev)) {
62a276f8 569 uint32_t lstat, lspeed, lwidth;
dc6d6d34 570 const char *speed_str;
fca29703 571
62a276f8
BH		 572 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
573 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
574 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703 575
49300af7
SK		 576 switch (lspeed) {
577 case 1:
dc6d6d34 578 speed_str = "2.5GT/s";
49300af7
SK		 579 break;
580 case 2:
dc6d6d34 581 speed_str = "5.0GT/s";
49300af7
SK		 582 break;
583 case 3:
dc6d6d34 584 speed_str = "8.0GT/s";
49300af7
SK		 585 break;
586 default:
dc6d6d34 587 speed_str = "<unknown>";
49300af7
SK		 588 break;
589 }
dc6d6d34 590 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
fca29703
AV		 591
592 return str;
593 }
594
fca29703 595 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
dc6d6d34
BVA		 596 if (pci_bus == 0 || pci_bus == 8)
597 snprintf(str, str_len, "PCI (%s MHz)",
598 pci_bus_modes[pci_bus >> 3]);
599 else
600 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
601 pci_bus & 4 ? 2 : 1,
602 pci_bus_modes[pci_bus & 3]);
fca29703
AV		 603
604 return str;
605}
606
e5f82ab8 607static char *
df57caba 608qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 609{
610 char un_str[10];
e315cd28 611 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 612
df57caba
HM		 613 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
614 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 615
616 if (ha->fw_attributes & BIT_9) {
617 strcat(str, "FLX");
618 return (str);
619 }
620
621 switch (ha->fw_attributes & 0xFF) {
622 case 0x7:
623 strcat(str, "EF");
624 break;
625 case 0x17:
626 strcat(str, "TP");
627 break;
628 case 0x37:
629 strcat(str, "IP");
630 break;
631 case 0x77:
632 strcat(str, "VI");
633 break;
634 default:
635 sprintf(un_str, "(%x)", ha->fw_attributes);
636 strcat(str, un_str);
637 break;
638 }
639 if (ha->fw_attributes & 0x100)
640 strcat(str, "X");
641
642 return (str);
643}
644
e5f82ab8 645static char *
df57caba 646qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 647{
e315cd28 648 struct qla_hw_data *ha = vha->hw;
f0883ac6 649
df57caba 650 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 651 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 652 return str;
fca29703
AV		 653}
654
6c18a43e 655void qla2x00_sp_free_dma(srb_t *sp)
fca29703 656{
25ff6af1 657 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 658 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 659 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 660
9ba56b95
GM		 661 if (sp->flags & SRB_DMA_VALID) {
662 scsi_dma_unmap(cmd);
663 sp->flags &= ~SRB_DMA_VALID;
7c3df132 664 }
fca29703 665
9ba56b95
GM		 666 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
667 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
668 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
669 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
670 }
671
d5ff0eed 672 if (!ctx)
711a08d7 673 return;
d5ff0eed 674
9ba56b95
GM		 675 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
676 /* List assured to be having elements */
d5ff0eed 677 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 678 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
679 }
680
681 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 682 struct crc_context *ctx0 = ctx;
683
684 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 685 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
686 }
687
688 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 689 struct ct6_dsd *ctx1 = ctx;
fca29703 690
9ba56b95 691 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 692 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 693 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
694 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
695 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
696 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95 697 }
9ba56b95
GM		 698}
699
6c18a43e 700void qla2x00_sp_compl(srb_t *sp, int res)
9ba56b95 701{
9ba56b95 702 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 703 struct completion *comp = sp->comp;
9ba56b95 704
db4bf822 705 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0))
9ba56b95 706 return;
219d27d7
BVA		 707
708 atomic_dec(&sp->ref_count);
9ba56b95 709
f3caa990 710 sp->free(sp);
740e2935 711 cmd->result = res;
711a08d7 712 CMD_SP(cmd) = NULL;
9ba56b95 713 cmd->scsi_done(cmd);
219d27d7
BVA		 714 if (comp)
715 complete(comp);
711a08d7 716 qla2x00_rel_sp(sp);
fca29703
AV		 717}
718
6c18a43e 719void qla2xxx_qpair_sp_free_dma(srb_t *sp)
d7459527 720{
d7459527
MH		 721 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
722 struct qla_hw_data *ha = sp->fcport->vha->hw;
723 void *ctx = GET_CMD_CTX_SP(sp);
724
725 if (sp->flags & SRB_DMA_VALID) {
726 scsi_dma_unmap(cmd);
727 sp->flags &= ~SRB_DMA_VALID;
728 }
729
730 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
731 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
732 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
733 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
734 }
735
d5ff0eed 736 if (!ctx)
711a08d7 737 return;
d5ff0eed 738
d7459527
MH		 739 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
740 /* List assured to be having elements */
d5ff0eed 741 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 742 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
743 }
744
50b81275 745 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
d8f945bf 746 struct crc_context *difctx = ctx;
50b81275
GM		 747 struct dsd_dma *dif_dsd, *nxt_dsd;
748
749 list_for_each_entry_safe(dif_dsd, nxt_dsd,
750 &difctx->ldif_dma_hndl_list, list) {
751 list_del(&dif_dsd->list);
752 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
753 dif_dsd->dsd_list_dma);
754 kfree(dif_dsd);
755 difctx->no_dif_bundl--;
756 }
757
758 list_for_each_entry_safe(dif_dsd, nxt_dsd,
759 &difctx->ldif_dsd_list, list) {
760 list_del(&dif_dsd->list);
761 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
762 dif_dsd->dsd_list_dma);
763 kfree(dif_dsd);
764 difctx->no_ldif_dsd--;
765 }
766
767 if (difctx->no_ldif_dsd) {
768 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
769 "%s: difctx->no_ldif_dsd=%x\n",
770 __func__, difctx->no_ldif_dsd);
771 }
772
773 if (difctx->no_dif_bundl) {
774 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
775 "%s: difctx->no_dif_bundl=%x\n",
776 __func__, difctx->no_dif_bundl);
777 }
778 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
d7459527 779 }
d8f945bf
BVA		 780
781 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
782 struct ct6_dsd *ctx1 = ctx;
783
784 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
785 ctx1->fcp_cmnd_dma);
786 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
787 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
788 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
789 mempool_free(ctx1, ha->ctx_mempool);
790 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
791 }
792
793 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
794 struct crc_context *ctx0 = ctx;
795
796 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
797 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
798 }
d7459527
MH		 799}
800
6c18a43e 801void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
d7459527 802{
d7459527 803 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 804 struct completion *comp = sp->comp;
d7459527 805
db4bf822 806 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0))
d7459527 807 return;
219d27d7
BVA		 808
809 atomic_dec(&sp->ref_count);
d7459527 810
f3caa990 811 sp->free(sp);
711a08d7
GM		 812 cmd->result = res;
813 CMD_SP(cmd) = NULL;
d7459527 814 cmd->scsi_done(cmd);
219d27d7
BVA		 815 if (comp)
816 complete(comp);
711a08d7 817 qla2xxx_rel_qpair_sp(sp->qpair, sp);
d7459527
MH		 818}
819
1da177e4 820static int
f5e3e40b 821qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 822{
134ae078 823 scsi_qla_host_t *vha = shost_priv(host);
fca29703 824 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 825 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 826 struct qla_hw_data *ha = vha->hw;
827 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 828 srb_t *sp;
829 int rval;
830
2dbb02fd
BVA		 831 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
832 WARN_ON_ONCE(!rport)) {
04dfaa53
MFO		 833 cmd->result = DID_NO_CONNECT << 16;
834 goto qc24_fail_command;
835 }
836
5601236b 837 if (ha->mqenable) {
6d58ef05
BVA		 838 uint32_t tag;
839 uint16_t hwq;
840 struct qla_qpair *qpair = NULL;
841
f664a3cc
JA		 842 tag = blk_mq_unique_tag(cmd->request);
843 hwq = blk_mq_unique_tag_to_hwq(tag);
844 qpair = ha->queue_pair_map[hwq];
5601236b
MH		 845
846 if (qpair)
847 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 848 }
849
85880801 850 if (ha->flags.eeh_busy) {
7c3df132 851 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 852 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 853 "PCI Channel IO permanent failure, exiting "
854 "cmd=%p.\n", cmd);
b9b12f73 855 cmd->result = DID_NO_CONNECT << 16;
7c3df132 856 } else {
5f28d2d7 857 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 858 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 859 cmd->result = DID_REQUEUE << 16;
7c3df132 860 }
14e660e6
SJ		 861 goto qc24_fail_command;
862 }
863
19a7b4ae
JSEC		 864 rval = fc_remote_port_chkready(rport);
865 if (rval) {
866 cmd->result = rval;
5f28d2d7 867 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 868 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
869 cmd, rval);
fca29703
AV		 870 goto qc24_fail_command;
871 }
872
bad75002
AE		 873 if (!vha->flags.difdix_supported &&
874 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 875 ql_dbg(ql_dbg_io, vha, 0x3004,
876 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
877 cmd);
bad75002
AE		 878 cmd->result = DID_NO_CONNECT << 16;
879 goto qc24_fail_command;
880 }
aa651be8
CD		 881
882 if (!fcport) {
883 cmd->result = DID_NO_CONNECT << 16;
884 goto qc24_fail_command;
885 }
886
fca29703
AV		 887 if (atomic_read(&fcport->state) != FCS_ONLINE) {
888 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 889 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 890 ql_dbg(ql_dbg_io, vha, 0x3005,
891 "Returning DNC, fcport_state=%d loop_state=%d.\n",
892 atomic_read(&fcport->state),
893 atomic_read(&base_vha->loop_state));
fca29703
AV		 894 cmd->result = DID_NO_CONNECT << 16;
895 goto qc24_fail_command;
896 }
7b594131 897 goto qc24_target_busy;
fca29703
AV		 898 }
899
e05fe292
CD		 900 /*
901 * Return target busy if we've received a non-zero retry_delay_timer
902 * in a FCP_RSP.
903 */
975f7d46
BP		 904 if (fcport->retry_delay_timestamp == 0) {
905 /* retry delay not set */
906 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 907 fcport->retry_delay_timestamp = 0;
908 else
909 goto qc24_target_busy;
910
b00ee7d7 911 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 912 if (!sp)
f5e3e40b 913 goto qc24_host_busy;
fca29703 914
9ba56b95
GM		 915 sp->u.scmd.cmd = cmd;
916 sp->type = SRB_SCSI_CMD;
917 atomic_set(&sp->ref_count, 1);
918 CMD_SP(cmd) = (void *)sp;
919 sp->free = qla2x00_sp_free_dma;
920 sp->done = qla2x00_sp_compl;
921
e315cd28 922 rval = ha->isp_ops->start_scsi(sp);
7c3df132 923 if (rval != QLA_SUCCESS) {
53016ed3 924 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 925 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 926 goto qc24_host_busy_free_sp;
7c3df132 927 }
fca29703 928
fca29703
AV		 929 return 0;
930
931qc24_host_busy_free_sp:
f3caa990 932 sp->free(sp);
fca29703 933
f5e3e40b 934qc24_host_busy:
fca29703
AV		 935 return SCSI_MLQUEUE_HOST_BUSY;
936
7b594131
MC		 937qc24_target_busy:
938 return SCSI_MLQUEUE_TARGET_BUSY;
939
fca29703 940qc24_fail_command:
f5e3e40b 941 cmd->scsi_done(cmd);
fca29703
AV		 942
943 return 0;
944}
945
d7459527
MH		 946/* For MQ supported I/O */
947int
948qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
949 struct qla_qpair *qpair)
950{
951 scsi_qla_host_t *vha = shost_priv(host);
952 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
953 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
954 struct qla_hw_data *ha = vha->hw;
955 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
956 srb_t *sp;
957 int rval;
958
2dbb02fd 959 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE;
d7459527
MH		 960 if (rval) {
961 cmd->result = rval;
962 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
963 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
964 cmd, rval);
965 goto qc24_fail_command;
966 }
967
968 if (!fcport) {
969 cmd->result = DID_NO_CONNECT << 16;
970 goto qc24_fail_command;
971 }
972
973 if (atomic_read(&fcport->state) != FCS_ONLINE) {
974 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
975 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
976 ql_dbg(ql_dbg_io, vha, 0x3077,
977 "Returning DNC, fcport_state=%d loop_state=%d.\n",
978 atomic_read(&fcport->state),
979 atomic_read(&base_vha->loop_state));
980 cmd->result = DID_NO_CONNECT << 16;
981 goto qc24_fail_command;
982 }
983 goto qc24_target_busy;
984 }
985
986 /*
987 * Return target busy if we've received a non-zero retry_delay_timer
988 * in a FCP_RSP.
989 */
990 if (fcport->retry_delay_timestamp == 0) {
991 /* retry delay not set */
992 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
993 fcport->retry_delay_timestamp = 0;
994 else
995 goto qc24_target_busy;
996
6a629468 997 sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC);
d7459527
MH		 998 if (!sp)
999 goto qc24_host_busy;
1000
1001 sp->u.scmd.cmd = cmd;
1002 sp->type = SRB_SCSI_CMD;
1003 atomic_set(&sp->ref_count, 1);
1004 CMD_SP(cmd) = (void *)sp;
1005 sp->free = qla2xxx_qpair_sp_free_dma;
1006 sp->done = qla2xxx_qpair_sp_compl;
1007 sp->qpair = qpair;
1008
1009 rval = ha->isp_ops->start_scsi_mq(sp);
1010 if (rval != QLA_SUCCESS) {
1011 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1012 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1013 if (rval == QLA_INTERFACE_ERROR)
1014 goto qc24_fail_command;
1015 goto qc24_host_busy_free_sp;
1016 }
1017
1018 return 0;
1019
1020qc24_host_busy_free_sp:
f3caa990 1021 sp->free(sp);
d7459527
MH		 1022
1023qc24_host_busy:
1024 return SCSI_MLQUEUE_HOST_BUSY;
1025
1026qc24_target_busy:
1027 return SCSI_MLQUEUE_TARGET_BUSY;
1028
1029qc24_fail_command:
1030 cmd->scsi_done(cmd);
1031
1032 return 0;
1033}
1034
1da177e4
LT		 1035/*
1036 * qla2x00_eh_wait_on_command
1037 * Waits for the command to be returned by the Firmware for some
1038 * max time.
1039 *
1040 * Input:
1da177e4 1041 * cmd = Scsi Command to wait on.
1da177e4
LT		 1042 *
1043 * Return:
fcef0893
BVA		 1044 * Completed in time : QLA_SUCCESS
1045 * Did not complete in time : QLA_FUNCTION_FAILED
1da177e4
LT		 1046 */
1047static int
e315cd28 1048qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1049{
fe74c71f 1050#define ABORT_POLLING_PERIOD 1000
478c3b03 1051#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1052 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1053 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1054 struct qla_hw_data *ha = vha->hw;
f4f051eb 1055 int ret = QLA_SUCCESS;
1da177e4 1056
85880801 1057 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1058 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1059 "Return:eh_wait.\n");
85880801
AV		 1060 return ret;
1061 }
1062
d970432c 1063 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1064 msleep(ABORT_POLLING_PERIOD);
f4f051eb 1065 }
1066 if (CMD_SP(cmd))
1067 ret = QLA_FUNCTION_FAILED;
1da177e4 1068
f4f051eb 1069 return ret;
1da177e4
LT		 1070}
1071
1072/*
1073 * qla2x00_wait_for_hba_online
fa2a1ce5 1074 * Wait till the HBA is online after going through
1da177e4
LT		 1075 * <= MAX_RETRIES_OF_ISP_ABORT or
1076 * finally HBA is disabled ie marked offline
1077 *
1078 * Input:
1079 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1080 *
1081 * Note:
1da177e4
LT		 1082 * Does context switching-Release SPIN_LOCK
1083 * (if any) before calling this routine.
1084 *
1085 * Return:
1086 * Success (Adapter is online) : 0
1087 * Failed (Adapter is offline/disabled) : 1
1088 */
854165f4 1089int
e315cd28 1090qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1091{
fca29703
AV		 1092 int return_status;
1093 unsigned long wait_online;
e315cd28
AC		 1094 struct qla_hw_data *ha = vha->hw;
1095 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1096
fa2a1ce5 1097 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1098 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1099 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1100 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1101 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1102
1103 msleep(1000);
1104 }
e315cd28 1105 if (base_vha->flags.online)
fa2a1ce5 1106 return_status = QLA_SUCCESS;
1da177e4
LT		 1107 else
1108 return_status = QLA_FUNCTION_FAILED;
1109
1da177e4
LT		 1110 return (return_status);
1111}
1112
726b8548
QT		 1113static inline int test_fcport_count(scsi_qla_host_t *vha)
1114{
1115 struct qla_hw_data *ha = vha->hw;
1116 unsigned long flags;
1117 int res;
1118
1119 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1120 ql_dbg(ql_dbg_init, vha, 0x00ec,
1121 "tgt %p, fcport_count=%d\n",
1122 vha, vha->fcport_count);
726b8548
QT		 1123 res = (vha->fcport_count == 0);
1124 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1125
1126 return res;
1127}
1128
1129/*
1130 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1131 * it has dependency on UNLOADING flag to stop device discovery
1132 */
efa93f48 1133void
726b8548
QT		 1134qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1135{
1136 qla2x00_mark_all_devices_lost(vha, 0);
1137
b85e0957 1138 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1139}
1140
86fbee86 1141/*
638a1a01
SC		 1142 * qla2x00_wait_for_hba_ready
1143 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1144 *
1145 * Input:
1146 * ha - pointer to host adapter structure
1147 *
1148 * Note:
1149 * Does context switching-Release SPIN_LOCK
1150 * (if any) before calling this routine.
1151 *
86fbee86 1152 */
638a1a01
SC		 1153static void
1154qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1155{
86fbee86 1156 struct qla_hw_data *ha = vha->hw;
783e0dc4 1157 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1158
1d483901
DC		 1159 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1160 ha->flags.mbox_busy) ||
1161 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1162 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1163 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1164 break;
86fbee86 1165 msleep(1000);
783e0dc4 1166 }
86fbee86
LC		 1167}
1168
2533cf67
LC		 1169int
1170qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1171{
1172 int return_status;
1173 unsigned long wait_reset;
1174 struct qla_hw_data *ha = vha->hw;
1175 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1176
1177 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1178 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1179 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1180 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1181 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1182
1183 msleep(1000);
1184
1185 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1186 ha->flags.chip_reset_done)
1187 break;
1188 }
1189 if (ha->flags.chip_reset_done)
1190 return_status = QLA_SUCCESS;
1191 else
1192 return_status = QLA_FUNCTION_FAILED;
1193
1194 return return_status;
1195}
1196
585def9b 1197static int
083a469d
GM		 1198sp_get(struct srb *sp)
1199{
845bbb09 1200 if (!refcount_inc_not_zero((refcount_t *)&sp->ref_count))
585def9b
QT		 1201 /* kref get fail */
1202 return ENXIO;
1203 else
1204 return 0;
083a469d
GM		 1205}
1206
a465537a
SC		 1207#define ISP_REG_DISCONNECT 0xffffffffU
1208/**************************************************************************
1209* qla2x00_isp_reg_stat
1210*
1211* Description:
1212* Read the host status register of ISP before aborting the command.
1213*
1214* Input:
1215* ha = pointer to host adapter structure.
1216*
1217*
1218* Returns:
1219* Either true or false.
1220*
1221* Note: Return true if there is register disconnect.
1222**************************************************************************/
1223static inline
1224uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1225{
1226 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1227 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1228
bf6061b1
SC		 1229 if (IS_P3P_TYPE(ha))
1230 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1231 else
1232 return ((RD_REG_DWORD(&reg->host_status)) ==
1233 ISP_REG_DISCONNECT);
a465537a
SC		 1234}
1235
1da177e4
LT		 1236/**************************************************************************
1237* qla2xxx_eh_abort
1238*
1239* Description:
1240* The abort function will abort the specified command.
1241*
1242* Input:
1243* cmd = Linux SCSI command packet to be aborted.
1244*
1245* Returns:
1246* Either SUCCESS or FAILED.
1247*
1248* Note:
2ea00202 1249* Only return FAILED if command not returned by firmware.
1da177e4 1250**************************************************************************/
e5f82ab8 1251static int
1da177e4
LT		 1252qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1253{
e315cd28 1254 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
8dd9593c 1255 DECLARE_COMPLETION_ONSTACK(comp);
f4f051eb 1256 srb_t *sp;
4e98d3b8 1257 int ret;
9cb78c16
HR		 1258 unsigned int id;
1259 uint64_t lun;
18e144d3 1260 unsigned long flags;
219d27d7 1261 int rval;
e315cd28 1262 struct qla_hw_data *ha = vha->hw;
585def9b 1263 struct qla_qpair *qpair;
1da177e4 1264
a465537a
SC		 1265 if (qla2x00_isp_reg_stat(ha)) {
1266 ql_log(ql_log_info, vha, 0x8042,
1267 "PCI/Register disconnect, exiting.\n");
1268 return FAILED;
1269 }
1da177e4 1270
4e98d3b8
AV		 1271 ret = fc_block_scsi_eh(cmd);
1272 if (ret != 0)
1273 return ret;
4e98d3b8 1274
170babc3 1275 sp = (srb_t *) CMD_SP(cmd);
585def9b
QT		 1276 if (!sp)
1277 return SUCCESS;
1278
1279 qpair = sp->qpair;
1280 if (!qpair)
1281 return SUCCESS;
1282
7f4374e6
QT		 1283 if (sp->fcport && sp->fcport->deleted)
1284 return SUCCESS;
1285
585def9b 1286 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
219d27d7 1287 if (sp->type != SRB_SCSI_CMD || GET_CMD_SP(sp) != cmd) {
585def9b
QT		 1288 /* there's a chance an interrupt could clear
1289 the ptr as part of done & free */
1290 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1291 return SUCCESS;
1292 }
1da177e4 1293
8dd9593c 1294 /* Get a reference to the sp and drop the lock. */
585def9b
QT		 1295 if (sp_get(sp)){
1296 /* ref_count is already 0 */
1297 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1298 return SUCCESS;
1299 }
585def9b
QT		 1300 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1301
1302 id = cmd->device->id;
1303 lun = cmd->device->lun;
1da177e4 1304
7c3df132 1305 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1306 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1307 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1308
f934c9d0 1309 rval = ha->isp_ops->abort_command(sp);
219d27d7
BVA		 1310 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1311 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
f934c9d0 1312
219d27d7
BVA		 1313 switch (rval) {
1314 case QLA_SUCCESS:
711a08d7 1315 /*
219d27d7
BVA		 1316 * The command has been aborted. That means that the firmware
1317 * won't report a completion.
711a08d7 1318 */
219d27d7
BVA		 1319 sp->done(sp, DID_ABORT << 16);
1320 ret = SUCCESS;
1321 break;
8dd9593c
BVA		 1322 case QLA_FUNCTION_PARAMETER_ERROR: {
1323 /* Wait for the command completion. */
1324 uint32_t ratov = ha->r_a_tov/10;
1325 uint32_t ratov_j = msecs_to_jiffies(4 * ratov * 1000);
1326
1327 WARN_ON_ONCE(sp->comp);
1328 sp->comp = &comp;
1329 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1330 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1331 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1332 __func__, ha->r_a_tov);
1333 ret = FAILED;
1334 } else {
1335 ret = SUCCESS;
1336 }
1337 break;
1338 }
219d27d7
BVA		 1339 default:
1340 /*
1341 * Either abort failed or abort and completion raced. Let
1342 * the SCSI core retry the abort in the former case.
1343 */
1344 ret = FAILED;
1345 break;
1da177e4 1346 }
219d27d7 1347
8dd9593c
BVA		 1348 sp->comp = NULL;
1349 atomic_dec(&sp->ref_count);
7c3df132 1350 ql_log(ql_log_info, vha, 0x801c,
219d27d7
BVA		 1351 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1352 vha->host_no, id, lun, ret);
1da177e4 1353
f4f051eb 1354 return ret;
1355}
1da177e4 1356
fcef0893
BVA		 1357/*
1358 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1359 */
4d78c973 1360int
e315cd28 1361qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1362 uint64_t l, enum nexus_wait_type type)
f4f051eb 1363{
17d98630 1364 int cnt, match, status;
18e144d3 1365 unsigned long flags;
e315cd28 1366 struct qla_hw_data *ha = vha->hw;
73208dfd 1367 struct req_que *req;
4d78c973 1368 srb_t *sp;
9ba56b95 1369 struct scsi_cmnd *cmd;
1da177e4 1370
523ec773 1371 status = QLA_SUCCESS;
17d98630 1372
e315cd28 1373 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1374 req = vha->req;
17d98630 1375 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1376 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1377 sp = req->outstanding_cmds[cnt];
1378 if (!sp)
523ec773 1379 continue;
9ba56b95 1380 if (sp->type != SRB_SCSI_CMD)
cf53b069 1381 continue;
25ff6af1 1382 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1383 continue;
1384 match = 0;
9ba56b95 1385 cmd = GET_CMD_SP(sp);
17d98630
AC		 1386 switch (type) {
1387 case WAIT_HOST:
1388 match = 1;
1389 break;
1390 case WAIT_TARGET:
9ba56b95 1391 match = cmd->device->id == t;
17d98630
AC		 1392 break;
1393 case WAIT_LUN:
9ba56b95
GM		 1394 match = (cmd->device->id == t &&
1395 cmd->device->lun == l);
17d98630 1396 break;
73208dfd 1397 }
17d98630
AC		 1398 if (!match)
1399 continue;
1400
1401 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1402 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1403 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1404 }
e315cd28 1405 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1406
1407 return status;
1da177e4
LT		 1408}
1409
523ec773
AV		 1410static char *reset_errors[] = {
1411 "HBA not online",
1412 "HBA not ready",
1413 "Task management failed",
1414 "Waiting for command completions",
1415};
1da177e4 1416
e5f82ab8 1417static int
523ec773 1418__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1419 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1420{
e315cd28 1421 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1422 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1423 int err;
1da177e4 1424
7c3df132 1425 if (!fcport) {
523ec773 1426 return FAILED;
7c3df132 1427 }
1da177e4 1428
4e98d3b8
AV		 1429 err = fc_block_scsi_eh(cmd);
1430 if (err != 0)
1431 return err;
1432
7f4374e6
QT		 1433 if (fcport->deleted)
1434 return SUCCESS;
1435
7c3df132 1436 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1437 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1438 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1439
523ec773 1440 err = 0;
7c3df132
SK		 1441 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1442 ql_log(ql_log_warn, vha, 0x800a,
1443 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1444 goto eh_reset_failed;
7c3df132 1445 }
523ec773 1446 err = 2;
ac444b4f 1447 if (do_reset(fcport, cmd->device->lun, 1)
7c3df132
SK		 1448 != QLA_SUCCESS) {
1449 ql_log(ql_log_warn, vha, 0x800c,
1450 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1451 goto eh_reset_failed;
7c3df132 1452 }
523ec773 1453 err = 3;
e315cd28 1454 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1455 cmd->device->lun, type) != QLA_SUCCESS) {
1456 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1457 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1458 goto eh_reset_failed;
7c3df132 1459 }
523ec773 1460
7c3df132 1461 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1462 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1463 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1464
1465 return SUCCESS;
1466
4d78c973 1467eh_reset_failed:
7c3df132 1468 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1469 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1470 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1471 cmd);
523ec773
AV		 1472 return FAILED;
1473}
1da177e4 1474
523ec773
AV		 1475static int
1476qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1477{
e315cd28
AC		 1478 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1479 struct qla_hw_data *ha = vha->hw;
1da177e4 1480
a465537a
SC		 1481 if (qla2x00_isp_reg_stat(ha)) {
1482 ql_log(ql_log_info, vha, 0x803e,
1483 "PCI/Register disconnect, exiting.\n");
1484 return FAILED;
1485 }
1486
523ec773
AV		 1487 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1488 ha->isp_ops->lun_reset);
1da177e4
LT		 1489}
1490
1da177e4 1491static int
523ec773 1492qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1493{
e315cd28
AC		 1494 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1495 struct qla_hw_data *ha = vha->hw;
1da177e4 1496
a465537a
SC		 1497 if (qla2x00_isp_reg_stat(ha)) {
1498 ql_log(ql_log_info, vha, 0x803f,
1499 "PCI/Register disconnect, exiting.\n");
1500 return FAILED;
1501 }
1502
523ec773
AV		 1503 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1504 ha->isp_ops->target_reset);
1da177e4
LT		 1505}
1506
1da177e4
LT		 1507/**************************************************************************
1508* qla2xxx_eh_bus_reset
1509*
1510* Description:
1511* The bus reset function will reset the bus and abort any executing
1512* commands.
1513*
1514* Input:
1515* cmd = Linux SCSI command packet of the command that cause the
1516* bus reset.
1517*
1518* Returns:
1519* SUCCESS/FAILURE (defined as macro in scsi.h).
1520*
1521**************************************************************************/
e5f82ab8 1522static int
1da177e4
LT		 1523qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1524{
e315cd28 1525 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1526 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1527 int ret = FAILED;
9cb78c16
HR		 1528 unsigned int id;
1529 uint64_t lun;
a465537a
SC		 1530 struct qla_hw_data *ha = vha->hw;
1531
1532 if (qla2x00_isp_reg_stat(ha)) {
1533 ql_log(ql_log_info, vha, 0x8040,
1534 "PCI/Register disconnect, exiting.\n");
1535 return FAILED;
1536 }
f4f051eb 1537
f4f051eb 1538 id = cmd->device->id;
1539 lun = cmd->device->lun;
1da177e4 1540
7c3df132 1541 if (!fcport) {
f4f051eb 1542 return ret;
7c3df132 1543 }
1da177e4 1544
4e98d3b8
AV		 1545 ret = fc_block_scsi_eh(cmd);
1546 if (ret != 0)
1547 return ret;
1548 ret = FAILED;
1549
7f4374e6
QT		 1550 if (qla2x00_chip_is_down(vha))
1551 return ret;
1552
7c3df132 1553 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1554 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1555
e315cd28 1556 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1557 ql_log(ql_log_fatal, vha, 0x8013,
1558 "Wait for hba online failed board disabled.\n");
f4f051eb 1559 goto eh_bus_reset_done;
1da177e4
LT		 1560 }
1561
ad537689
SK		 1562 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1563 ret = SUCCESS;
1564
f4f051eb 1565 if (ret == FAILED)
1566 goto eh_bus_reset_done;
1da177e4 1567
9a41a62b 1568 /* Flush outstanding commands. */
4d78c973 1569 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1570 QLA_SUCCESS) {
1571 ql_log(ql_log_warn, vha, 0x8014,
1572 "Wait for pending commands failed.\n");
9a41a62b 1573 ret = FAILED;
7c3df132 1574 }
1da177e4 1575
f4f051eb 1576eh_bus_reset_done:
7c3df132 1577 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1578 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1579 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1580
f4f051eb 1581 return ret;
1da177e4
LT		 1582}
1583
1584/**************************************************************************
1585* qla2xxx_eh_host_reset
1586*
1587* Description:
1588* The reset function will reset the Adapter.
1589*
1590* Input:
1591* cmd = Linux SCSI command packet of the command that cause the
1592* adapter reset.
1593*
1594* Returns:
1595* Either SUCCESS or FAILED.
1596*
1597* Note:
1598**************************************************************************/
e5f82ab8 1599static int
1da177e4
LT		 1600qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1601{
e315cd28 1602 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1603 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1604 int ret = FAILED;
9cb78c16
HR		 1605 unsigned int id;
1606 uint64_t lun;
e315cd28 1607 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1608
a465537a
SC		 1609 if (qla2x00_isp_reg_stat(ha)) {
1610 ql_log(ql_log_info, vha, 0x8041,
1611 "PCI/Register disconnect, exiting.\n");
1612 schedule_work(&ha->board_disable);
1613 return SUCCESS;
1614 }
1615
f4f051eb 1616 id = cmd->device->id;
1617 lun = cmd->device->lun;
f4f051eb 1618
7c3df132 1619 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1620 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1621
63ee7072
CD		 1622 /*
1623 * No point in issuing another reset if one is active. Also do not
1624 * attempt a reset if we are updating flash.
1625 */
1626 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1627 goto eh_host_reset_lock;
1da177e4 1628
e315cd28
AC		 1629 if (vha != base_vha) {
1630 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1631 goto eh_host_reset_lock;
e315cd28 1632 } else {
7ec0effd 1633 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1634 if (!qla82xx_fcoe_ctx_reset(vha)) {
1635 /* Ctx reset success */
1636 ret = SUCCESS;
1637 goto eh_host_reset_lock;
1638 }
1639 /* fall thru if ctx reset failed */
1640 }
68ca949c
AC		 1641 if (ha->wq)
1642 flush_workqueue(ha->wq);
1643
e315cd28 1644 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1645 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1646 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1647 /* failed. schedule dpc to try */
1648 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1649
7c3df132
SK		 1650 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1651 ql_log(ql_log_warn, vha, 0x802a,
1652 "wait for hba online failed.\n");
e315cd28 1653 goto eh_host_reset_lock;
7c3df132 1654 }
e315cd28
AC		 1655 }
1656 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1657 }
1da177e4 1658
e315cd28 1659 /* Waiting for command to be returned to OS.*/
4d78c973 1660 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1661 QLA_SUCCESS)
f4f051eb 1662 ret = SUCCESS;
1da177e4 1663
f4f051eb 1664eh_host_reset_lock:
cfb0919c 1665 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1666 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1667 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1668
f4f051eb 1669 return ret;
1670}
1da177e4
LT		 1671
1672/*
1673* qla2x00_loop_reset
1674* Issue loop reset.
1675*
1676* Input:
1677* ha = adapter block pointer.
1678*
1679* Returns:
1680* 0 = success
1681*/
a4722cf2 1682int
e315cd28 1683qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1684{
0c8c39af 1685 int ret;
bdf79621 1686 struct fc_port *fcport;
e315cd28 1687 struct qla_hw_data *ha = vha->hw;
1da177e4 1688
5854771e
AB		 1689 if (IS_QLAFX00(ha)) {
1690 return qlafx00_loop_reset(vha);
1691 }
1692
f4c496c1 1693 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1694 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1695 if (fcport->port_type != FCT_TARGET)
1696 continue;
1697
1698 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1699 if (ret != QLA_SUCCESS) {
7c3df132 1700 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1701 "Bus Reset failed: Reset=%d "
7c3df132 1702 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1703 }
1704 }
1705 }
1706
8ae6d9c7 1707
6246b8a1 1708 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1709 atomic_set(&vha->loop_state, LOOP_DOWN);
1710 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1711 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1712 ret = qla2x00_full_login_lip(vha);
0c8c39af 1713 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1714 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1715 "full_login_lip=%d.\n", ret);
749af3d5 1716 }
0c8c39af
AV		 1717 }
1718
0d6e61bc 1719 if (ha->flags.enable_lip_reset) {
e315cd28 1720 ret = qla2x00_lip_reset(vha);
ad537689 1721 if (ret != QLA_SUCCESS)
7c3df132
SK		 1722 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1723 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1724 }
1725
1da177e4 1726 /* Issue marker command only when we are going to start the I/O */
e315cd28 1727 vha->marker_needed = 1;
1da177e4 1728
0c8c39af 1729 return QLA_SUCCESS;
1da177e4
LT		 1730}
1731
c4e521b6
BVA		 1732static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1733 unsigned long *flags)
1734 __releases(qp->qp_lock_ptr)
1735 __acquires(qp->qp_lock_ptr)
1736{
219d27d7 1737 DECLARE_COMPLETION_ONSTACK(comp);
c4e521b6
BVA		 1738 scsi_qla_host_t *vha = qp->vha;
1739 struct qla_hw_data *ha = vha->hw;
219d27d7 1740 int rval;
c4e521b6 1741
219d27d7
BVA		 1742 if (sp_get(sp))
1743 return;
1744
1745 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1746 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1747 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1748 !qla2x00_isp_reg_stat(ha))) {
1749 sp->comp = &comp;
219d27d7 1750 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
5589b08e 1751 rval = ha->isp_ops->abort_command(sp);
219d27d7
BVA		 1752
1753 switch (rval) {
1754 case QLA_SUCCESS:
1755 sp->done(sp, res);
1756 break;
1757 case QLA_FUNCTION_PARAMETER_ERROR:
1758 wait_for_completion(&comp);
1759 break;
c4e521b6 1760 }
219d27d7
BVA		 1761
1762 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1763 sp->comp = NULL;
c4e521b6 1764 }
d2d2b5a5
BVA		 1765
1766 atomic_dec(&sp->ref_count);
c4e521b6
BVA		 1767}
1768
bbead493
QT		 1769static void
1770__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1771{
eb023220 1772 int cnt;
df4bf0bb
AV		 1773 unsigned long flags;
1774 srb_t *sp;
bbead493 1775 scsi_qla_host_t *vha = qp->vha;
e315cd28 1776 struct qla_hw_data *ha = vha->hw;
73208dfd 1777 struct req_que *req;
c5419e26
QT		 1778 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1779 struct qla_tgt_cmd *cmd;
c0cb4496 1780
6a2cf8d3
BK		 1781 if (!ha->req_q_map)
1782 return;
bbead493
QT		 1783 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1784 req = qp->req;
1785 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1786 sp = req->outstanding_cmds[cnt];
1787 if (sp) {
1788 req->outstanding_cmds[cnt] = NULL;
6b0431d6
QT		 1789 switch (sp->cmd_type) {
1790 case TYPE_SRB:
c4e521b6 1791 qla2x00_abort_srb(qp, sp, res, &flags);
585def9b
QT		 1792 break;
1793 case TYPE_TGT_CMD:
bbead493
QT		 1794 if (!vha->hw->tgt.tgt_ops || !tgt ||
1795 qla_ini_mode_enabled(vha)) {
585def9b
QT		 1796 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1797 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1798 vha->dpc_flags);
bbead493 1799 continue;
c733ab35 1800 }
bbead493 1801 cmd = (struct qla_tgt_cmd *)sp;
aefed3e5 1802 cmd->aborted = 1;
585def9b
QT		 1803 break;
1804 case TYPE_TGT_TMCMD:
aefed3e5 1805 /* Skip task management functions. */
585def9b
QT		 1806 break;
1807 default:
1808 break;
73208dfd 1809 }
df4bf0bb
AV		 1810 }
1811 }
bbead493
QT		 1812 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1813}
1814
1815void
1816qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1817{
1818 int que;
1819 struct qla_hw_data *ha = vha->hw;
1820
26a77799
AV		 1821 /* Continue only if initialization complete. */
1822 if (!ha->base_qpair)
1823 return;
bbead493
QT		 1824 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1825
26a77799
AV		 1826 if (!ha->queue_pair_map)
1827 return;
bbead493
QT		 1828 for (que = 0; que < ha->max_qpairs; que++) {
1829 if (!ha->queue_pair_map[que])
1830 continue;
1831
1832 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1833 }
df4bf0bb
AV		 1834}
1835
f4f051eb 1836static int
1837qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1838{
bdf79621 1839 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1840
19a7b4ae 1841 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1842 return -ENXIO;
bdf79621 1843
19a7b4ae 1844 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1845
f4f051eb 1846 return 0;
1847}
1da177e4 1848
f4f051eb 1849static int
1850qla2xxx_slave_configure(struct scsi_device *sdev)
1851{
e315cd28 1852 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1853 struct req_que *req = vha->req;
8482e118 1854
9e522cd8
AE		 1855 if (IS_T10_PI_CAPABLE(vha->hw))
1856 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1857
db5ed4df 1858 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1859 return 0;
1860}
1da177e4 1861
f4f051eb 1862static void
1863qla2xxx_slave_destroy(struct scsi_device *sdev)
1864{
1865 sdev->hostdata = NULL;
1da177e4
LT		 1866}
1867
1868/**
1869 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1870 * @ha: HA context
1871 *
1872 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1873 * supported addressing method.
1874 */
1875static void
53303c42 1876qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1877{
7524f9b9 1878 /* Assume a 32bit DMA mask. */
1da177e4 1879 ha->flags.enable_64bit_addressing = 0;
1da177e4 1880
6a35528a 1881 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1882 /* Any upper-dword bits set? */
1883 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1884 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1885 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1886 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1887 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1888 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1889 return;
1da177e4 1890 }
1da177e4 1891 }
7524f9b9 1892
284901a9
YH		 1893 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1894 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1895}
1896
fd34f556 1897static void
e315cd28 1898qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1899{
1900 unsigned long flags = 0;
1901 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1902
1903 spin_lock_irqsave(&ha->hardware_lock, flags);
1904 ha->interrupts_on = 1;
1905 /* enable risc and host interrupts */
1906 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1907 RD_REG_WORD(&reg->ictrl);
1908 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1909
1910}
1911
1912static void
e315cd28 1913qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1914{
1915 unsigned long flags = 0;
1916 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1917
1918 spin_lock_irqsave(&ha->hardware_lock, flags);
1919 ha->interrupts_on = 0;
1920 /* disable risc and host interrupts */
1921 WRT_REG_WORD(&reg->ictrl, 0);
1922 RD_REG_WORD(&reg->ictrl);
1923 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1924}
1925
1926static void
e315cd28 1927qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1928{
1929 unsigned long flags = 0;
1930 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1931
1932 spin_lock_irqsave(&ha->hardware_lock, flags);
1933 ha->interrupts_on = 1;
1934 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1935 RD_REG_DWORD(&reg->ictrl);
1936 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1937}
1938
1939static void
e315cd28 1940qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1941{
1942 unsigned long flags = 0;
1943 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1944
124f85e6
AV		 1945 if (IS_NOPOLLING_TYPE(ha))
1946 return;
fd34f556
AV		 1947 spin_lock_irqsave(&ha->hardware_lock, flags);
1948 ha->interrupts_on = 0;
1949 WRT_REG_DWORD(&reg->ictrl, 0);
1950 RD_REG_DWORD(&reg->ictrl);
1951 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1952}
1953
706f457d
GM		 1954static int
1955qla2x00_iospace_config(struct qla_hw_data *ha)
1956{
1957 resource_size_t pio;
1958 uint16_t msix;
706f457d 1959
706f457d
GM		 1960 if (pci_request_selected_regions(ha->pdev, ha->bars,
1961 QLA2XXX_DRIVER_NAME)) {
1962 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1963 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1964 pci_name(ha->pdev));
1965 goto iospace_error_exit;
1966 }
1967 if (!(ha->bars & 1))
1968 goto skip_pio;
1969
1970 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1971 pio = pci_resource_start(ha->pdev, 0);
1972 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1973 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1974 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1975 "Invalid pci I/O region size (%s).\n",
1976 pci_name(ha->pdev));
1977 pio = 0;
1978 }
1979 } else {
1980 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1981 "Region #0 no a PIO resource (%s).\n",
1982 pci_name(ha->pdev));
1983 pio = 0;
1984 }
1985 ha->pio_address = pio;
1986 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1987 "PIO address=%llu.\n",
1988 (unsigned long long)ha->pio_address);
1989
1990skip_pio:
1991 /* Use MMIO operations for all accesses. */
1992 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1993 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1994 "Region #1 not an MMIO resource (%s), aborting.\n",
1995 pci_name(ha->pdev));
1996 goto iospace_error_exit;
1997 }
1998 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1999 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2000 "Invalid PCI mem region size (%s), aborting.\n",
2001 pci_name(ha->pdev));
2002 goto iospace_error_exit;
2003 }
2004
2005 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2006 if (!ha->iobase) {
2007 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2008 "Cannot remap MMIO (%s), aborting.\n",
2009 pci_name(ha->pdev));
2010 goto iospace_error_exit;
2011 }
2012
2013 /* Determine queue resources */
2014 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2015 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 2016 if (!ql2xmqsupport || !ql2xnvmeenable ||
2017 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 2018 goto mqiobase_exit;
2019
2020 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2021 pci_resource_len(ha->pdev, 3));
2022 if (ha->mqiobase) {
2023 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2024 "MQIO Base=%p.\n", ha->mqiobase);
2025 /* Read MSIX vector size of the board */
2026 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2027 ha->msix_count = msix + 1;
706f457d 2028 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2029 /* MB interrupt uses 1 vector */
2030 ha->max_req_queues = ha->msix_count - 1;
2031 ha->max_rsp_queues = ha->max_req_queues;
2032 /* Queue pairs is the max value minus the base queue pair */
2033 ha->max_qpairs = ha->max_rsp_queues - 1;
2034 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2035 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2036
706f457d 2037 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2038 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2039 } else
2040 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2041 "BAR 3 not enabled.\n");
2042
2043mqiobase_exit:
706f457d 2044 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2045 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2046 return (0);
2047
2048iospace_error_exit:
2049 return (-ENOMEM);
2050}
2051
2052
6246b8a1
GM		 2053static int
2054qla83xx_iospace_config(struct qla_hw_data *ha)
2055{
2056 uint16_t msix;
6246b8a1
GM		 2057
2058 if (pci_request_selected_regions(ha->pdev, ha->bars,
2059 QLA2XXX_DRIVER_NAME)) {
2060 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2061 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2062 pci_name(ha->pdev));
2063
2064 goto iospace_error_exit;
2065 }
2066
2067 /* Use MMIO operations for all accesses. */
2068 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2069 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2070 "Invalid pci I/O region size (%s).\n",
2071 pci_name(ha->pdev));
2072 goto iospace_error_exit;
2073 }
2074 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2075 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2076 "Invalid PCI mem region size (%s), aborting\n",
2077 pci_name(ha->pdev));
2078 goto iospace_error_exit;
2079 }
2080
2081 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2082 if (!ha->iobase) {
2083 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2084 "Cannot remap MMIO (%s), aborting.\n",
2085 pci_name(ha->pdev));
2086 goto iospace_error_exit;
2087 }
2088
2089 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2090 /* 83XX 26XX always use MQ type access for queues
2091 * - mbar 2, a.k.a region 4 */
2092 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2093 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2094 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2095 pci_resource_len(ha->pdev, 4));
2096
2097 if (!ha->mqiobase) {
2098 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2099 "BAR2/region4 not enabled\n");
2100 goto mqiobase_exit;
2101 }
2102
2103 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2104 pci_resource_len(ha->pdev, 2));
2105 if (ha->msixbase) {
2106 /* Read MSIX vector size of the board */
2107 pci_read_config_word(ha->pdev,
2108 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2109 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2110 /*
2111 * By default, driver uses at least two msix vectors
2112 * (default & rspq)
2113 */
c38d1baf 2114 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2115 /* MB interrupt uses 1 vector */
2116 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2117
2118 /* ATIOQ needs 1 vector. That's 1 less QPair */
2119 if (QLA_TGT_MODE_ENABLED())
2120 ha->max_req_queues--;
2121
d0d2c68b
MH		 2122 ha->max_rsp_queues = ha->max_req_queues;
2123
d7459527
MH		 2124 /* Queue pairs is the max value minus
2125 * the base queue pair */
2126 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2127 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2128 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2129 }
2130 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2131 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2132 } else
2133 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2134 "BAR 1 not enabled.\n");
2135
2136mqiobase_exit:
6246b8a1 2137 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2138 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2139 return 0;
2140
2141iospace_error_exit:
2142 return -ENOMEM;
2143}
2144
fd34f556
AV		 2145static struct isp_operations qla2100_isp_ops = {
2146 .pci_config = qla2100_pci_config,
2147 .reset_chip = qla2x00_reset_chip,
2148 .chip_diag = qla2x00_chip_diag,
2149 .config_rings = qla2x00_config_rings,
2150 .reset_adapter = qla2x00_reset_adapter,
2151 .nvram_config = qla2x00_nvram_config,
2152 .update_fw_options = qla2x00_update_fw_options,
2153 .load_risc = qla2x00_load_risc,
2154 .pci_info_str = qla2x00_pci_info_str,
2155 .fw_version_str = qla2x00_fw_version_str,
2156 .intr_handler = qla2100_intr_handler,
2157 .enable_intrs = qla2x00_enable_intrs,
2158 .disable_intrs = qla2x00_disable_intrs,
2159 .abort_command = qla2x00_abort_command,
523ec773
AV		 2160 .target_reset = qla2x00_abort_target,
2161 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2162 .fabric_login = qla2x00_login_fabric,
2163 .fabric_logout = qla2x00_fabric_logout,
2164 .calc_req_entries = qla2x00_calc_iocbs_32,
2165 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2166 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2167 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2168 .read_nvram = qla2x00_read_nvram_data,
2169 .write_nvram = qla2x00_write_nvram_data,
2170 .fw_dump = qla2100_fw_dump,
2171 .beacon_on = NULL,
2172 .beacon_off = NULL,
2173 .beacon_blink = NULL,
2174 .read_optrom = qla2x00_read_optrom_data,
2175 .write_optrom = qla2x00_write_optrom_data,
2176 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2177 .start_scsi = qla2x00_start_scsi,
d7459527 2178 .start_scsi_mq = NULL,
a9083016 2179 .abort_isp = qla2x00_abort_isp,
706f457d 2180 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2181 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2182};
2183
2184static struct isp_operations qla2300_isp_ops = {
2185 .pci_config = qla2300_pci_config,
2186 .reset_chip = qla2x00_reset_chip,
2187 .chip_diag = qla2x00_chip_diag,
2188 .config_rings = qla2x00_config_rings,
2189 .reset_adapter = qla2x00_reset_adapter,
2190 .nvram_config = qla2x00_nvram_config,
2191 .update_fw_options = qla2x00_update_fw_options,
2192 .load_risc = qla2x00_load_risc,
2193 .pci_info_str = qla2x00_pci_info_str,
2194 .fw_version_str = qla2x00_fw_version_str,
2195 .intr_handler = qla2300_intr_handler,
2196 .enable_intrs = qla2x00_enable_intrs,
2197 .disable_intrs = qla2x00_disable_intrs,
2198 .abort_command = qla2x00_abort_command,
523ec773
AV		 2199 .target_reset = qla2x00_abort_target,
2200 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2201 .fabric_login = qla2x00_login_fabric,
2202 .fabric_logout = qla2x00_fabric_logout,
2203 .calc_req_entries = qla2x00_calc_iocbs_32,
2204 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2205 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2206 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2207 .read_nvram = qla2x00_read_nvram_data,
2208 .write_nvram = qla2x00_write_nvram_data,
2209 .fw_dump = qla2300_fw_dump,
2210 .beacon_on = qla2x00_beacon_on,
2211 .beacon_off = qla2x00_beacon_off,
2212 .beacon_blink = qla2x00_beacon_blink,
2213 .read_optrom = qla2x00_read_optrom_data,
2214 .write_optrom = qla2x00_write_optrom_data,
2215 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2216 .start_scsi = qla2x00_start_scsi,
d7459527 2217 .start_scsi_mq = NULL,
a9083016 2218 .abort_isp = qla2x00_abort_isp,
7ec0effd 2219 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2220 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2221};
2222
2223static struct isp_operations qla24xx_isp_ops = {
2224 .pci_config = qla24xx_pci_config,
2225 .reset_chip = qla24xx_reset_chip,
2226 .chip_diag = qla24xx_chip_diag,
2227 .config_rings = qla24xx_config_rings,
2228 .reset_adapter = qla24xx_reset_adapter,
2229 .nvram_config = qla24xx_nvram_config,
2230 .update_fw_options = qla24xx_update_fw_options,
2231 .load_risc = qla24xx_load_risc,
2232 .pci_info_str = qla24xx_pci_info_str,
2233 .fw_version_str = qla24xx_fw_version_str,
2234 .intr_handler = qla24xx_intr_handler,
2235 .enable_intrs = qla24xx_enable_intrs,
2236 .disable_intrs = qla24xx_disable_intrs,
2237 .abort_command = qla24xx_abort_command,
523ec773
AV		 2238 .target_reset = qla24xx_abort_target,
2239 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2240 .fabric_login = qla24xx_login_fabric,
2241 .fabric_logout = qla24xx_fabric_logout,
2242 .calc_req_entries = NULL,
2243 .build_iocbs = NULL,
2244 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2245 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2246 .read_nvram = qla24xx_read_nvram_data,
2247 .write_nvram = qla24xx_write_nvram_data,
2248 .fw_dump = qla24xx_fw_dump,
2249 .beacon_on = qla24xx_beacon_on,
2250 .beacon_off = qla24xx_beacon_off,
2251 .beacon_blink = qla24xx_beacon_blink,
2252 .read_optrom = qla24xx_read_optrom_data,
2253 .write_optrom = qla24xx_write_optrom_data,
2254 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2255 .start_scsi = qla24xx_start_scsi,
d7459527 2256 .start_scsi_mq = NULL,
a9083016 2257 .abort_isp = qla2x00_abort_isp,
7ec0effd 2258 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2259 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2260};
2261
c3a2f0df
AV		 2262static struct isp_operations qla25xx_isp_ops = {
2263 .pci_config = qla25xx_pci_config,
2264 .reset_chip = qla24xx_reset_chip,
2265 .chip_diag = qla24xx_chip_diag,
2266 .config_rings = qla24xx_config_rings,
2267 .reset_adapter = qla24xx_reset_adapter,
2268 .nvram_config = qla24xx_nvram_config,
2269 .update_fw_options = qla24xx_update_fw_options,
2270 .load_risc = qla24xx_load_risc,
2271 .pci_info_str = qla24xx_pci_info_str,
2272 .fw_version_str = qla24xx_fw_version_str,
2273 .intr_handler = qla24xx_intr_handler,
2274 .enable_intrs = qla24xx_enable_intrs,
2275 .disable_intrs = qla24xx_disable_intrs,
2276 .abort_command = qla24xx_abort_command,
523ec773
AV		 2277 .target_reset = qla24xx_abort_target,
2278 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2279 .fabric_login = qla24xx_login_fabric,
2280 .fabric_logout = qla24xx_fabric_logout,
2281 .calc_req_entries = NULL,
2282 .build_iocbs = NULL,
2283 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2284 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2285 .read_nvram = qla25xx_read_nvram_data,
2286 .write_nvram = qla25xx_write_nvram_data,
2287 .fw_dump = qla25xx_fw_dump,
2288 .beacon_on = qla24xx_beacon_on,
2289 .beacon_off = qla24xx_beacon_off,
2290 .beacon_blink = qla24xx_beacon_blink,
338c9161 2291 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2292 .write_optrom = qla24xx_write_optrom_data,
2293 .get_flash_version = qla24xx_get_flash_version,
bad75002 2294 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2295 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2296 .abort_isp = qla2x00_abort_isp,
7ec0effd 2297 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2298 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2299};
2300
3a03eb79
AV		 2301static struct isp_operations qla81xx_isp_ops = {
2302 .pci_config = qla25xx_pci_config,
2303 .reset_chip = qla24xx_reset_chip,
2304 .chip_diag = qla24xx_chip_diag,
2305 .config_rings = qla24xx_config_rings,
2306 .reset_adapter = qla24xx_reset_adapter,
2307 .nvram_config = qla81xx_nvram_config,
2308 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2309 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2310 .pci_info_str = qla24xx_pci_info_str,
2311 .fw_version_str = qla24xx_fw_version_str,
2312 .intr_handler = qla24xx_intr_handler,
2313 .enable_intrs = qla24xx_enable_intrs,
2314 .disable_intrs = qla24xx_disable_intrs,
2315 .abort_command = qla24xx_abort_command,
2316 .target_reset = qla24xx_abort_target,
2317 .lun_reset = qla24xx_lun_reset,
2318 .fabric_login = qla24xx_login_fabric,
2319 .fabric_logout = qla24xx_fabric_logout,
2320 .calc_req_entries = NULL,
2321 .build_iocbs = NULL,
2322 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2323 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2324 .read_nvram = NULL,
2325 .write_nvram = NULL,
3a03eb79
AV		 2326 .fw_dump = qla81xx_fw_dump,
2327 .beacon_on = qla24xx_beacon_on,
2328 .beacon_off = qla24xx_beacon_off,
6246b8a1 2329 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2330 .read_optrom = qla25xx_read_optrom_data,
2331 .write_optrom = qla24xx_write_optrom_data,
2332 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2333 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2334 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2335 .abort_isp = qla2x00_abort_isp,
7ec0effd 2336 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2337 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2338};
2339
2340static struct isp_operations qla82xx_isp_ops = {
2341 .pci_config = qla82xx_pci_config,
2342 .reset_chip = qla82xx_reset_chip,
2343 .chip_diag = qla24xx_chip_diag,
2344 .config_rings = qla82xx_config_rings,
2345 .reset_adapter = qla24xx_reset_adapter,
2346 .nvram_config = qla81xx_nvram_config,
2347 .update_fw_options = qla24xx_update_fw_options,
2348 .load_risc = qla82xx_load_risc,
9d55ca66 2349 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2350 .fw_version_str = qla24xx_fw_version_str,
2351 .intr_handler = qla82xx_intr_handler,
2352 .enable_intrs = qla82xx_enable_intrs,
2353 .disable_intrs = qla82xx_disable_intrs,
2354 .abort_command = qla24xx_abort_command,
2355 .target_reset = qla24xx_abort_target,
2356 .lun_reset = qla24xx_lun_reset,
2357 .fabric_login = qla24xx_login_fabric,
2358 .fabric_logout = qla24xx_fabric_logout,
2359 .calc_req_entries = NULL,
2360 .build_iocbs = NULL,
2361 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2362 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2363 .read_nvram = qla24xx_read_nvram_data,
2364 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2365 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2366 .beacon_on = qla82xx_beacon_on,
2367 .beacon_off = qla82xx_beacon_off,
2368 .beacon_blink = NULL,
a9083016
GM		 2369 .read_optrom = qla82xx_read_optrom_data,
2370 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2371 .get_flash_version = qla82xx_get_flash_version,
a9083016 2372 .start_scsi = qla82xx_start_scsi,
d7459527 2373 .start_scsi_mq = NULL,
a9083016 2374 .abort_isp = qla82xx_abort_isp,
706f457d 2375 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2376 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2377};
2378
7ec0effd
AD		 2379static struct isp_operations qla8044_isp_ops = {
2380 .pci_config = qla82xx_pci_config,
2381 .reset_chip = qla82xx_reset_chip,
2382 .chip_diag = qla24xx_chip_diag,
2383 .config_rings = qla82xx_config_rings,
2384 .reset_adapter = qla24xx_reset_adapter,
2385 .nvram_config = qla81xx_nvram_config,
2386 .update_fw_options = qla24xx_update_fw_options,
2387 .load_risc = qla82xx_load_risc,
2388 .pci_info_str = qla24xx_pci_info_str,
2389 .fw_version_str = qla24xx_fw_version_str,
2390 .intr_handler = qla8044_intr_handler,
2391 .enable_intrs = qla82xx_enable_intrs,
2392 .disable_intrs = qla82xx_disable_intrs,
2393 .abort_command = qla24xx_abort_command,
2394 .target_reset = qla24xx_abort_target,
2395 .lun_reset = qla24xx_lun_reset,
2396 .fabric_login = qla24xx_login_fabric,
2397 .fabric_logout = qla24xx_fabric_logout,
2398 .calc_req_entries = NULL,
2399 .build_iocbs = NULL,
2400 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2401 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2402 .read_nvram = NULL,
2403 .write_nvram = NULL,
a1b23c5a 2404 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2405 .beacon_on = qla82xx_beacon_on,
2406 .beacon_off = qla82xx_beacon_off,
2407 .beacon_blink = NULL,
888e639d 2408 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2409 .write_optrom = qla8044_write_optrom_data,
2410 .get_flash_version = qla82xx_get_flash_version,
2411 .start_scsi = qla82xx_start_scsi,
d7459527 2412 .start_scsi_mq = NULL,
7ec0effd
AD		 2413 .abort_isp = qla8044_abort_isp,
2414 .iospace_config = qla82xx_iospace_config,
2415 .initialize_adapter = qla2x00_initialize_adapter,
2416};
2417
6246b8a1
GM		 2418static struct isp_operations qla83xx_isp_ops = {
2419 .pci_config = qla25xx_pci_config,
2420 .reset_chip = qla24xx_reset_chip,
2421 .chip_diag = qla24xx_chip_diag,
2422 .config_rings = qla24xx_config_rings,
2423 .reset_adapter = qla24xx_reset_adapter,
2424 .nvram_config = qla81xx_nvram_config,
2425 .update_fw_options = qla81xx_update_fw_options,
2426 .load_risc = qla81xx_load_risc,
2427 .pci_info_str = qla24xx_pci_info_str,
2428 .fw_version_str = qla24xx_fw_version_str,
2429 .intr_handler = qla24xx_intr_handler,
2430 .enable_intrs = qla24xx_enable_intrs,
2431 .disable_intrs = qla24xx_disable_intrs,
2432 .abort_command = qla24xx_abort_command,
2433 .target_reset = qla24xx_abort_target,
2434 .lun_reset = qla24xx_lun_reset,
2435 .fabric_login = qla24xx_login_fabric,
2436 .fabric_logout = qla24xx_fabric_logout,
2437 .calc_req_entries = NULL,
2438 .build_iocbs = NULL,
2439 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2440 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2441 .read_nvram = NULL,
2442 .write_nvram = NULL,
2443 .fw_dump = qla83xx_fw_dump,
2444 .beacon_on = qla24xx_beacon_on,
2445 .beacon_off = qla24xx_beacon_off,
2446 .beacon_blink = qla83xx_beacon_blink,
2447 .read_optrom = qla25xx_read_optrom_data,
2448 .write_optrom = qla24xx_write_optrom_data,
2449 .get_flash_version = qla24xx_get_flash_version,
2450 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2451 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2452 .abort_isp = qla2x00_abort_isp,
2453 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2454 .initialize_adapter = qla2x00_initialize_adapter,
2455};
2456
2457static struct isp_operations qlafx00_isp_ops = {
2458 .pci_config = qlafx00_pci_config,
2459 .reset_chip = qlafx00_soft_reset,
2460 .chip_diag = qlafx00_chip_diag,
2461 .config_rings = qlafx00_config_rings,
2462 .reset_adapter = qlafx00_soft_reset,
2463 .nvram_config = NULL,
2464 .update_fw_options = NULL,
2465 .load_risc = NULL,
2466 .pci_info_str = qlafx00_pci_info_str,
2467 .fw_version_str = qlafx00_fw_version_str,
2468 .intr_handler = qlafx00_intr_handler,
2469 .enable_intrs = qlafx00_enable_intrs,
2470 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2471 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2472 .target_reset = qlafx00_abort_target,
2473 .lun_reset = qlafx00_lun_reset,
2474 .fabric_login = NULL,
2475 .fabric_logout = NULL,
2476 .calc_req_entries = NULL,
2477 .build_iocbs = NULL,
2478 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2479 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2480 .read_nvram = qla24xx_read_nvram_data,
2481 .write_nvram = qla24xx_write_nvram_data,
2482 .fw_dump = NULL,
2483 .beacon_on = qla24xx_beacon_on,
2484 .beacon_off = qla24xx_beacon_off,
2485 .beacon_blink = NULL,
2486 .read_optrom = qla24xx_read_optrom_data,
2487 .write_optrom = qla24xx_write_optrom_data,
2488 .get_flash_version = qla24xx_get_flash_version,
2489 .start_scsi = qlafx00_start_scsi,
d7459527 2490 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2491 .abort_isp = qlafx00_abort_isp,
2492 .iospace_config = qlafx00_iospace_config,
2493 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2494};
2495
f73cb695
CD		 2496static struct isp_operations qla27xx_isp_ops = {
2497 .pci_config = qla25xx_pci_config,
2498 .reset_chip = qla24xx_reset_chip,
2499 .chip_diag = qla24xx_chip_diag,
2500 .config_rings = qla24xx_config_rings,
2501 .reset_adapter = qla24xx_reset_adapter,
2502 .nvram_config = qla81xx_nvram_config,
a36f1443 2503 .update_fw_options = qla24xx_update_fw_options,
f73cb695
CD		 2504 .load_risc = qla81xx_load_risc,
2505 .pci_info_str = qla24xx_pci_info_str,
2506 .fw_version_str = qla24xx_fw_version_str,
2507 .intr_handler = qla24xx_intr_handler,
2508 .enable_intrs = qla24xx_enable_intrs,
2509 .disable_intrs = qla24xx_disable_intrs,
2510 .abort_command = qla24xx_abort_command,
2511 .target_reset = qla24xx_abort_target,
2512 .lun_reset = qla24xx_lun_reset,
2513 .fabric_login = qla24xx_login_fabric,
2514 .fabric_logout = qla24xx_fabric_logout,
2515 .calc_req_entries = NULL,
2516 .build_iocbs = NULL,
2517 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2518 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2519 .read_nvram = NULL,
2520 .write_nvram = NULL,
2521 .fw_dump = qla27xx_fwdump,
2522 .beacon_on = qla24xx_beacon_on,
2523 .beacon_off = qla24xx_beacon_off,
2524 .beacon_blink = qla83xx_beacon_blink,
2525 .read_optrom = qla25xx_read_optrom_data,
2526 .write_optrom = qla24xx_write_optrom_data,
2527 .get_flash_version = qla24xx_get_flash_version,
2528 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2529 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2530 .abort_isp = qla2x00_abort_isp,
2531 .iospace_config = qla83xx_iospace_config,
2532 .initialize_adapter = qla2x00_initialize_adapter,
2533};
2534
ea5b6382 2535static inline void
e315cd28 2536qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2537{
2538 ha->device_type = DT_EXTENDED_IDS;
2539 switch (ha->pdev->device) {
2540 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2541 ha->isp_type |= DT_ISP2100;
ea5b6382 2542 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2543 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2544 break;
2545 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2546 ha->isp_type |= DT_ISP2200;
ea5b6382 2547 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2548 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2549 break;
2550 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2551 ha->isp_type |= DT_ISP2300;
4a59f71d 2552 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2553 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2554 break;
2555 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2556 ha->isp_type |= DT_ISP2312;
4a59f71d 2557 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2558 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2559 break;
2560 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2561 ha->isp_type |= DT_ISP2322;
4a59f71d 2562 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2563 if (ha->pdev->subsystem_vendor == 0x1028 &&
2564 ha->pdev->subsystem_device == 0x0170)
2565 ha->device_type |= DT_OEM_001;
441d1072 2566 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2567 break;
2568 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2569 ha->isp_type |= DT_ISP6312;
441d1072 2570 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2571 break;
2572 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2573 ha->isp_type |= DT_ISP6322;
441d1072 2574 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2575 break;
2576 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2577 ha->isp_type |= DT_ISP2422;
4a59f71d 2578 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2579 ha->device_type |= DT_FWI2;
c76f2c01 2580 ha->device_type |= DT_IIDMA;
441d1072 2581 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2582 break;
2583 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2584 ha->isp_type |= DT_ISP2432;
4a59f71d 2585 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2586 ha->device_type |= DT_FWI2;
c76f2c01 2587 ha->device_type |= DT_IIDMA;
441d1072 2588 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2589 break;
4d4df193 2590 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2591 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2592 ha->device_type |= DT_ZIO_SUPPORTED;
2593 ha->device_type |= DT_FWI2;
2594 ha->device_type |= DT_IIDMA;
2595 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2596 break;
044cc6c8 2597 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2598 ha->isp_type |= DT_ISP5422;
e428924c 2599 ha->device_type |= DT_FWI2;
441d1072 2600 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2601 break;
044cc6c8 2602 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2603 ha->isp_type |= DT_ISP5432;
e428924c 2604 ha->device_type |= DT_FWI2;
441d1072 2605 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2606 break;
c3a2f0df 2607 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2608 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2609 ha->device_type |= DT_ZIO_SUPPORTED;
2610 ha->device_type |= DT_FWI2;
2611 ha->device_type |= DT_IIDMA;
441d1072 2612 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2613 break;
3a03eb79 2614 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2615 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2616 ha->device_type |= DT_ZIO_SUPPORTED;
2617 ha->device_type |= DT_FWI2;
2618 ha->device_type |= DT_IIDMA;
2619 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2620 break;
a9083016 2621 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2622 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2623 ha->device_type |= DT_ZIO_SUPPORTED;
2624 ha->device_type |= DT_FWI2;
2625 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2626 /* Initialize 82XX ISP flags */
2627 qla82xx_init_flags(ha);
2628 break;
7ec0effd 2629 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2630 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2631 ha->device_type |= DT_ZIO_SUPPORTED;
2632 ha->device_type |= DT_FWI2;
2633 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2634 /* Initialize 82XX ISP flags */
2635 qla82xx_init_flags(ha);
2636 break;
6246b8a1 2637 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2638 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2639 ha->device_type |= DT_ZIO_SUPPORTED;
2640 ha->device_type |= DT_FWI2;
2641 ha->device_type |= DT_IIDMA;
2642 ha->device_type |= DT_T10_PI;
2643 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2644 break;
2645 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2646 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2647 ha->device_type |= DT_ZIO_SUPPORTED;
2648 ha->device_type |= DT_FWI2;
2649 ha->device_type |= DT_IIDMA;
2650 ha->device_type |= DT_T10_PI;
2651 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2652 break;
8ae6d9c7 2653 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2654 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2655 break;
f73cb695 2656 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2657 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2658 ha->device_type |= DT_ZIO_SUPPORTED;
2659 ha->device_type |= DT_FWI2;
2660 ha->device_type |= DT_IIDMA;
8ce3f570 2661 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2662 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2663 break;
2c5bbbb2 2664 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2665 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2666 ha->device_type |= DT_ZIO_SUPPORTED;
2667 ha->device_type |= DT_FWI2;
2668 ha->device_type |= DT_IIDMA;
8ce3f570 2669 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2670 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2671 break;
2b48992f 2672 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2673 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2674 ha->device_type |= DT_ZIO_SUPPORTED;
2675 ha->device_type |= DT_FWI2;
2676 ha->device_type |= DT_IIDMA;
8ce3f570 2677 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2678 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2679 break;
ecc89f25
JC		 2680 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2681 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2682 ha->isp_type |= DT_ISP2081;
2683 ha->device_type |= DT_ZIO_SUPPORTED;
2684 ha->device_type |= DT_FWI2;
2685 ha->device_type |= DT_IIDMA;
2686 ha->device_type |= DT_T10_PI;
2687 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2688 break;
2689 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2690 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2691 ha->isp_type |= DT_ISP2281;
2692 ha->device_type |= DT_ZIO_SUPPORTED;
2693 ha->device_type |= DT_FWI2;
2694 ha->device_type |= DT_IIDMA;
2695 ha->device_type |= DT_T10_PI;
2696 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2697 break;
ea5b6382 2698 }
e5b68a61 2699
a9083016 2700 if (IS_QLA82XX(ha))
43a9c38b 2701 ha->port_no = ha->portnum & 1;
f73cb695 2702 else {
a9083016
GM		 2703 /* Get adapter physical port no from interrupt pin register. */
2704 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
ecc89f25
JC		 2705 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2706 IS_QLA27XX(ha) || IS_QLA28XX(ha))
f73cb695
CD		 2707 ha->port_no--;
2708 else
2709 ha->port_no = !(ha->port_no & 1);
2710 }
a9083016 2711
7c3df132 2712 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2713 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2714 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2715}
2716
1e99e33a
AV		 2717static void
2718qla2xxx_scan_start(struct Scsi_Host *shost)
2719{
e315cd28 2720 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2721
cbc8eb67
AV		 2722 if (vha->hw->flags.running_gold_fw)
2723 return;
2724
e315cd28
AC		 2725 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2726 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2727 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2728 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2729}
2730
2731static int
2732qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2733{
e315cd28 2734 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2735
a5dd506e
BK		 2736 if (test_bit(UNLOADING, &vha->dpc_flags))
2737 return 1;
e315cd28 2738 if (!vha->host)
1e99e33a 2739 return 1;
e315cd28 2740 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2741 return 1;
2742
e315cd28 2743 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2744}
2745
ec7193e2
QT		 2746static void qla2x00_iocb_work_fn(struct work_struct *work)
2747{
2748 struct scsi_qla_host *vha = container_of(work,
2749 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2750 struct qla_hw_data *ha = vha->hw;
2751 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
0aca7784 2752 int i = 2;
9b3e0f4d
QT		 2753 unsigned long flags;
2754
2755 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2756 return;
ec7193e2 2757
9b3e0f4d 2758 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2759 qla2x00_do_work(vha);
9b3e0f4d 2760 i--;
ec7193e2 2761 }
9b3e0f4d
QT		 2762
2763 spin_lock_irqsave(&vha->work_lock, flags);
2764 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2765 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2766}
2767
1da177e4
LT		 2768/*
2769 * PCI driver interface
2770 */
6f039790 2771static int
7ee61397 2772qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2773{
a1541d5a 2774 int ret = -ENODEV;
1da177e4 2775 struct Scsi_Host *host;
e315cd28
AC		 2776 scsi_qla_host_t *base_vha = NULL;
2777 struct qla_hw_data *ha;
29856e28 2778 char pci_info[30];
7d613ac6 2779 char fw_str[30], wq_name[30];
5433383e 2780 struct scsi_host_template *sht;
642ef983 2781 int bars, mem_only = 0;
e315cd28 2782 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2783 struct req_que *req = NULL;
2784 struct rsp_que *rsp = NULL;
5601236b 2785 int i;
d7459527 2786
285d0321 2787 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2788 sht = &qla2xxx_driver_template;
5433383e 2789 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2790 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2791 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2792 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2793 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2794 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2795 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2796 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2797 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2798 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2799 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2800 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2801 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f 2802 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
ecc89f25
JC		 2803 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2804 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2805 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2806 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2807 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
285d0321 2808 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2809 mem_only = 1;
7c3df132
SK		 2810 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2811 "Mem only adapter.\n");
285d0321 2812 }
7c3df132
SK		 2813 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2814 "Bars=%d.\n", bars);
285d0321 2815
09483916
BH		 2816 if (mem_only) {
2817 if (pci_enable_device_mem(pdev))
ddff7ed4 2818 return ret;
09483916
BH		 2819 } else {
2820 if (pci_enable_device(pdev))
ddff7ed4 2821 return ret;
09483916 2822 }
285d0321 2823
0927678f
JB		 2824 /* This may fail but that's ok */
2825 pci_enable_pcie_error_reporting(pdev);
285d0321 2826
5da05a26
GM		 2827 /* Turn off T10-DIF when FC-NVMe is enabled */
2828 if (ql2xnvmeenable)
2829 ql2xenabledif = 0;
2830
e315cd28
AC		 2831 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2832 if (!ha) {
7c3df132
SK		 2833 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2834 "Unable to allocate memory for ha.\n");
ddff7ed4 2835 goto disable_device;
1da177e4 2836 }
7c3df132
SK		 2837 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2838 "Memory allocated for ha=%p.\n", ha);
e315cd28 2839 ha->pdev = pdev;
33e79977
QT		 2840 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2841 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2842 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2843 spin_lock_init(&ha->tgt.atio_lock);
2844
deeae7a6 2845 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2846
2847 /* Clear our data area */
285d0321 2848 ha->bars = bars;
09483916 2849 ha->mem_only = mem_only;
df4bf0bb 2850 spin_lock_init(&ha->hardware_lock);
339aa70e 2851 spin_lock_init(&ha->vport_slock);
a9b6f722 2852 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2853 mutex_init(&ha->optrom_mutex);
1da177e4 2854
ea5b6382 2855 /* Set ISP-type information. */
2856 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2857
2858 /* Set EEH reset type to fundamental if required by hba */
95676112 2859 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
ecc89f25 2860 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
ca79cf66 2861 pdev->needs_freset = 1;
ca79cf66 2862
cba1e47f
CD		 2863 ha->prev_topology = 0;
2864 ha->init_cb_size = sizeof(init_cb_t);
2865 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2866 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2867 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2868 atomic_set(&ha->num_pend_mbx_stage1, 0);
2869 atomic_set(&ha->num_pend_mbx_stage2, 0);
2870 atomic_set(&ha->num_pend_mbx_stage3, 0);
8b4673ba
QT		 2871 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2872 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
cba1e47f 2873
abbd8870 2874 /* Assign ISP specific operations. */
1da177e4 2875 if (IS_QLA2100(ha)) {
642ef983 2876 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2877 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2878 req_length = REQUEST_ENTRY_CNT_2100;
2879 rsp_length = RESPONSE_ENTRY_CNT_2100;
2880 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2881 ha->gid_list_info_size = 4;
3a03eb79
AV		 2882 ha->flash_conf_off = ~0;
2883 ha->flash_data_off = ~0;
2884 ha->nvram_conf_off = ~0;
2885 ha->nvram_data_off = ~0;
fd34f556 2886 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2887 } else if (IS_QLA2200(ha)) {
642ef983 2888 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2889 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2890 req_length = REQUEST_ENTRY_CNT_2200;
2891 rsp_length = RESPONSE_ENTRY_CNT_2100;
2892 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2893 ha->gid_list_info_size = 4;
3a03eb79
AV		 2894 ha->flash_conf_off = ~0;
2895 ha->flash_data_off = ~0;
2896 ha->nvram_conf_off = ~0;
2897 ha->nvram_data_off = ~0;
fd34f556 2898 ha->isp_ops = &qla2100_isp_ops;
fca29703 2899 } else if (IS_QLA23XX(ha)) {
642ef983 2900 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2901 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2902 req_length = REQUEST_ENTRY_CNT_2200;
2903 rsp_length = RESPONSE_ENTRY_CNT_2300;
2904 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2905 ha->gid_list_info_size = 6;
854165f4 2906 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2907 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2908 ha->flash_conf_off = ~0;
2909 ha->flash_data_off = ~0;
2910 ha->nvram_conf_off = ~0;
2911 ha->nvram_data_off = ~0;
fd34f556 2912 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2913 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2914 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2915 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2916 req_length = REQUEST_ENTRY_CNT_24XX;
2917 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2918 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2919 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2920 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2921 ha->gid_list_info_size = 8;
854165f4 2922 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2923 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2924 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2925 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2926 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2927 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2928 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2929 } else if (IS_QLA25XX(ha)) {
642ef983 2930 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2931 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2932 req_length = REQUEST_ENTRY_CNT_24XX;
2933 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2934 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2935 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2936 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2937 ha->gid_list_info_size = 8;
2938 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2939 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2940 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2941 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2942 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2943 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2944 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2945 } else if (IS_QLA81XX(ha)) {
642ef983 2946 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2947 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2948 req_length = REQUEST_ENTRY_CNT_24XX;
2949 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2950 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2951 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2952 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2953 ha->gid_list_info_size = 8;
2954 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2955 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2956 ha->isp_ops = &qla81xx_isp_ops;
2957 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2958 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2959 ha->nvram_conf_off = ~0;
2960 ha->nvram_data_off = ~0;
a9083016 2961 } else if (IS_QLA82XX(ha)) {
642ef983 2962 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2963 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2964 req_length = REQUEST_ENTRY_CNT_82XX;
2965 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2966 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2967 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2968 ha->gid_list_info_size = 8;
2969 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2970 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2971 ha->isp_ops = &qla82xx_isp_ops;
2972 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2973 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2974 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2975 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2976 } else if (IS_QLA8044(ha)) {
2977 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2978 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2979 req_length = REQUEST_ENTRY_CNT_82XX;
2980 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2981 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2982 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2983 ha->gid_list_info_size = 8;
2984 ha->optrom_size = OPTROM_SIZE_83XX;
2985 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2986 ha->isp_ops = &qla8044_isp_ops;
2987 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2988 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2989 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2990 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2991 } else if (IS_QLA83XX(ha)) {
7d613ac6 2992 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2993 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2994 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2995 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2996 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2997 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2998 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2999 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3000 ha->gid_list_info_size = 8;
3001 ha->optrom_size = OPTROM_SIZE_83XX;
3002 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3003 ha->isp_ops = &qla83xx_isp_ops;
3004 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3005 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3006 ha->nvram_conf_off = ~0;
3007 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 3008 } else if (IS_QLAFX00(ha)) {
3009 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3010 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3011 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3012 req_length = REQUEST_ENTRY_CNT_FX00;
3013 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 3014 ha->isp_ops = &qlafx00_isp_ops;
3015 ha->port_down_retry_count = 30; /* default value */
3016 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3017 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 3018 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 3019 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 3020 ha->mr.host_info_resend = false;
3021 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 3022 } else if (IS_QLA27XX(ha)) {
3023 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3024 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3025 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 3026 req_length = REQUEST_ENTRY_CNT_83XX;
3027 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 3028 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 3029 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3030 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3031 ha->gid_list_info_size = 8;
3032 ha->optrom_size = OPTROM_SIZE_83XX;
3033 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3034 ha->isp_ops = &qla27xx_isp_ops;
3035 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3036 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3037 ha->nvram_conf_off = ~0;
3038 ha->nvram_data_off = ~0;
ecc89f25
JC		 3039 } else if (IS_QLA28XX(ha)) {
3040 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3041 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3042 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3043 req_length = REQUEST_ENTRY_CNT_24XX;
3044 rsp_length = RESPONSE_ENTRY_CNT_2300;
3045 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3046 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3047 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3048 ha->gid_list_info_size = 8;
3049 ha->optrom_size = OPTROM_SIZE_28XX;
3050 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3051 ha->isp_ops = &qla27xx_isp_ops;
3052 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3053 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3054 ha->nvram_conf_off = ~0;
3055 ha->nvram_data_off = ~0;
1da177e4 3056 }
6246b8a1 3057
7c3df132
SK		 3058 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3059 "mbx_count=%d, req_length=%d, "
3060 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 3061 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3062 "max_fibre_devices=%d.\n",
7c3df132
SK		 3063 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3064 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 3065 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 3066 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3067 "isp_ops=%p, flash_conf_off=%d, "
3068 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3069 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3070 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3071
3072 /* Configure PCI I/O space */
3073 ret = ha->isp_ops->iospace_config(ha);
3074 if (ret)
0a63ad12 3075 goto iospace_config_failed;
706f457d
GM		 3076
3077 ql_log_pci(ql_log_info, pdev, 0x001d,
3078 "Found an ISP%04X irq %d iobase 0x%p.\n",
3079 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3080 mutex_init(&ha->vport_lock);
d7459527 3081 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3082 init_completion(&ha->mbx_cmd_comp);
3083 complete(&ha->mbx_cmd_comp);
3084 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3085 init_completion(&ha->dcbx_comp);
f356bef1 3086 init_completion(&ha->lb_portup_comp);
1da177e4 3087
2c3dfe3f 3088 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3089
53303c42 3090 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3091 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3092 "64 Bit addressing is %s.\n",
3093 ha->flags.enable_64bit_addressing ? "enable" :
3094 "disable");
73208dfd 3095 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3096 if (ret) {
7c3df132
SK		 3097 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3098 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3099
e315cd28
AC		 3100 goto probe_hw_failed;
3101 }
3102
73208dfd 3103 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3104 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3105 req->max_q_depth = ql2xmaxqdepth;
3106
e315cd28
AC		 3107
3108 base_vha = qla2x00_create_host(sht, ha);
3109 if (!base_vha) {
a1541d5a 3110 ret = -ENOMEM;
e315cd28 3111 goto probe_hw_failed;
1da177e4
LT		 3112 }
3113
e315cd28 3114 pci_set_drvdata(pdev, base_vha);
6b383979 3115 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3116
e315cd28 3117 host = base_vha->host;
2afa19a9 3118 base_vha->req = req;
73208dfd 3119 if (IS_QLA2XXX_MIDTYPE(ha))
f6602f3b
QT		 3120 base_vha->mgmt_svr_loop_id =
3121 qla2x00_reserve_mgmt_server_loop_id(base_vha);
73208dfd 3122 else
e315cd28
AC		 3123 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3124 base_vha->vp_idx;
58548cb5 3125
8ae6d9c7
GM		 3126 /* Setup fcport template structure. */
3127 ha->mr.fcport.vha = base_vha;
3128 ha->mr.fcport.port_type = FCT_UNKNOWN;
3129 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3130 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3131 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3132 ha->mr.fcport.scan_state = 1;
3133
58548cb5
GM		 3134 /* Set the SG table size based on ISP type */
3135 if (!IS_FWI2_CAPABLE(ha)) {
3136 if (IS_QLA2100(ha))
3137 host->sg_tablesize = 32;
3138 } else {
3139 if (!IS_QLA82XX(ha))
3140 host->sg_tablesize = QLA_SG_ALL;
3141 }
642ef983 3142 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3143 host->cmd_per_lun = 3;
3144 host->unique_id = host->host_no;
e02587d7 3145 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3146 host->max_cmd_len = 32;
3147 else
3148 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3149 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3150 /* Older HBAs support only 16-bit LUNs */
3151 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3152 ql2xmaxlun > 0xffff)
3153 host->max_lun = 0xffff;
3154 else
3155 host->max_lun = ql2xmaxlun;
e315cd28 3156 host->transportt = qla2xxx_transport_template;
9a069e19 3157 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3158
7c3df132
SK		 3159 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3160 "max_id=%d this_id=%d "
3161 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3162 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3163 host->this_id, host->cmd_per_lun, host->unique_id,
3164 host->max_cmd_len, host->max_channel, host->max_lun,
3165 host->transportt, sht->vendor_id);
3166
1010f21e
HM		 3167 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3168
d7459527
MH		 3169 /* Set up the irqs */
3170 ret = qla2x00_request_irqs(ha, rsp);
3171 if (ret)
6a2cf8d3 3172 goto probe_failed;
d7459527 3173
9a347ff4 3174 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3175 ret = qla2x00_alloc_queues(ha, req, rsp);
3176 if (ret) {
9a347ff4
CD		 3177 ql_log(ql_log_fatal, base_vha, 0x003d,
3178 "Failed to allocate memory for queue pointers..."
3179 "aborting.\n");
26a77799 3180 ret = -ENODEV;
6a2cf8d3 3181 goto probe_failed;
9a347ff4
CD		 3182 }
3183
f664a3cc 3184 if (ha->mqenable) {
5601236b
MH		 3185 /* number of hardware queues supported by blk/scsi-mq*/
3186 host->nr_hw_queues = ha->max_qpairs;
3187
3188 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3189 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3190 } else {
3191 if (ql2xnvmeenable) {
3192 host->nr_hw_queues = ha->max_qpairs;
3193 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3194 "FC-NVMe support is enabled, HW queues=%d\n",
3195 host->nr_hw_queues);
3196 } else {
3197 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3198 "blk/scsi-mq disabled.\n");
3199 }
3200 }
5601236b 3201
2d70c103 3202 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3203
90a86fc0
JC		 3204 pci_save_state(pdev);
3205
9a347ff4 3206 /* Assign back pointers */
2afa19a9
AC		 3207 rsp->req = req;
3208 req->rsp = rsp;
9a347ff4 3209
8ae6d9c7
GM		 3210 if (IS_QLAFX00(ha)) {
3211 ha->rsp_q_map[0] = rsp;
3212 ha->req_q_map[0] = req;
3213 set_bit(0, ha->req_qid_map);
3214 set_bit(0, ha->rsp_qid_map);
3215 }
3216
08029990
AV		 3217 /* FWI2-capable only. */
3218 req->req_q_in = &ha->iobase->isp24.req_q_in;
3219 req->req_q_out = &ha->iobase->isp24.req_q_out;
3220 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3221 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
ecc89f25
JC		 3222 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3223 IS_QLA28XX(ha)) {
08029990
AV		 3224 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3225 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3226 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3227 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3228 }
3229
8ae6d9c7
GM		 3230 if (IS_QLAFX00(ha)) {
3231 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3232 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3233 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3234 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3235 }
3236
7ec0effd 3237 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3238 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3239 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3240 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3241 }
3242
7c3df132
SK		 3243 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3244 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3245 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3246 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3247 "req->req_q_in=%p req->req_q_out=%p "
3248 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3249 req->req_q_in, req->req_q_out,
3250 rsp->rsp_q_in, rsp->rsp_q_out);
3251 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3252 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3253 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3254 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3255 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3256 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3257
d48cc67c 3258 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3259
8ae6d9c7 3260 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3261 ql_log(ql_log_fatal, base_vha, 0x00d6,
3262 "Failed to initialize adapter - Adapter flags %x.\n",
3263 base_vha->device_flags);
1da177e4 3264
a9083016
GM		 3265 if (IS_QLA82XX(ha)) {
3266 qla82xx_idc_lock(ha);
3267 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3268 QLA8XXX_DEV_FAILED);
a9083016 3269 qla82xx_idc_unlock(ha);
7c3df132
SK		 3270 ql_log(ql_log_fatal, base_vha, 0x00d7,
3271 "HW State: FAILED.\n");
7ec0effd
AD		 3272 } else if (IS_QLA8044(ha)) {
3273 qla8044_idc_lock(ha);
3274 qla8044_wr_direct(base_vha,
3275 QLA8044_CRB_DEV_STATE_INDEX,
3276 QLA8XXX_DEV_FAILED);
3277 qla8044_idc_unlock(ha);
3278 ql_log(ql_log_fatal, base_vha, 0x0150,
3279 "HW State: FAILED.\n");
a9083016
GM		 3280 }
3281
a1541d5a 3282 ret = -ENODEV;
1da177e4
LT		 3283 goto probe_failed;
3284 }
3285
3b1bef64
CD		 3286 if (IS_QLAFX00(ha))
3287 host->can_queue = QLAFX00_MAX_CANQUEUE;
3288 else
3289 host->can_queue = req->num_outstanding_cmds - 10;
3290
3291 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3292 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3293 host->can_queue, base_vha->req,
3294 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3295
e326d22a 3296 if (ha->mqenable) {
e326d22a 3297 bool startit = false;
e326d22a 3298
f664a3cc 3299 if (QLA_TGT_MODE_ENABLED())
e326d22a 3300 startit = false;
e326d22a 3301
f664a3cc 3302 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
e326d22a 3303 startit = true;
e326d22a 3304
f664a3cc
JA		 3305 /* Create start of day qpairs for Block MQ */
3306 for (i = 0; i < ha->max_qpairs; i++)
3307 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b 3308 }
68ca949c 3309
cbc8eb67
AV		 3310 if (ha->flags.running_gold_fw)
3311 goto skip_dpc;
3312
1da177e4
LT		 3313 /*
3314 * Startup the kernel thread for this host adapter
3315 */
39a11240 3316 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3317 "%s_dpc", base_vha->host_str);
39a11240 3318 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3319 ql_log(ql_log_fatal, base_vha, 0x00ed,
3320 "Failed to start DPC thread.\n");
39a11240 3321 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3322 ha->dpc_thread = NULL;
1da177e4
LT		 3323 goto probe_failed;
3324 }
7c3df132
SK		 3325 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3326 "DPC thread started successfully.\n");
1da177e4 3327
2d70c103
NB		 3328 /*
3329 * If we're not coming up in initiator mode, we might sit for
3330 * a while without waking up the dpc thread, which leads to a
3331 * stuck process warning. So just kick the dpc once here and
3332 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3333 */
3334 qla2xxx_wake_dpc(base_vha);
3335
f3ddac19
CD		 3336 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3337
81178772
SK		 3338 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3339 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3340 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3341 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3342
3343 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3344 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3345 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3346 INIT_WORK(&ha->idc_state_handler,
3347 qla83xx_idc_state_handler_work);
3348 INIT_WORK(&ha->nic_core_unrecoverable,
3349 qla83xx_nic_core_unrecoverable_work);
3350 }
3351
cbc8eb67 3352skip_dpc:
e315cd28
AC		 3353 list_add_tail(&base_vha->list, &ha->vp_list);
3354 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3355
3356 /* Initialized the timer */
8e5f4ba0 3357 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3358 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3359 "Started qla2x00_timer with "
3360 "interval=%d.\n", WATCH_INTERVAL);
3361 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3362 "Detected hba at address=%p.\n",
3363 ha);
d19044c3 3364
e02587d7 3365 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3366 if (ha->fw_attributes & BIT_4) {
9e522cd8 3367 int prot = 0, guard;
bd432bb5 3368
bad75002 3369 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3370 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3371 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3372 if (ql2xenabledif == 1)
3373 prot = SHOST_DIX_TYPE0_PROTECTION;
7855d2ba
MP		 3374 if (ql2xprotmask)
3375 scsi_host_set_prot(host, ql2xprotmask);
3376 else
3377 scsi_host_set_prot(host,
3378 prot | SHOST_DIF_TYPE1_PROTECTION
3379 | SHOST_DIF_TYPE2_PROTECTION
3380 | SHOST_DIF_TYPE3_PROTECTION
3381 | SHOST_DIX_TYPE1_PROTECTION
3382 | SHOST_DIX_TYPE2_PROTECTION
3383 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3384
3385 guard = SHOST_DIX_GUARD_CRC;
3386
3387 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3388 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3389 guard |= SHOST_DIX_GUARD_IP;
3390
7855d2ba
MP		 3391 if (ql2xprotguard)
3392 scsi_host_set_guard(host, ql2xprotguard);
3393 else
3394 scsi_host_set_guard(host, guard);
bad75002
AE		 3395 } else
3396 base_vha->flags.difdix_supported = 0;
3397 }
3398
a9083016
GM		 3399 ha->isp_ops->enable_intrs(ha);
3400
1fe19ee4
AB		 3401 if (IS_QLAFX00(ha)) {
3402 ret = qlafx00_fx_disc(base_vha,
3403 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3404 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3405 QLA_SG_ALL : 128;
3406 }
3407
a1541d5a
AV		 3408 ret = scsi_add_host(host, &pdev->dev);
3409 if (ret)
3410 goto probe_failed;
3411
1486400f
MR		 3412 base_vha->flags.init_done = 1;
3413 base_vha->flags.online = 1;
edaa5c74 3414 ha->prev_minidump_failed = 0;
1486400f 3415
7c3df132
SK		 3416 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3417 "Init done and hba is online.\n");
3418
726b8548
QT		 3419 if (qla_ini_mode_enabled(base_vha) ||
3420 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3421 scsi_scan_host(host);
3422 else
3423 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3424 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3425
e315cd28 3426 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3427
8ae6d9c7 3428 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3429 ret = qlafx00_fx_disc(base_vha,
3430 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3431
3432 /* Register system information */
3433 ret = qlafx00_fx_disc(base_vha,
3434 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3435 }
3436
e315cd28 3437 qla2x00_init_host_attr(base_vha);
a1541d5a 3438
e315cd28 3439 qla2x00_dfs_setup(base_vha);
df613b96 3440
03eb912a
AB		 3441 ql_log(ql_log_info, base_vha, 0x00fb,
3442 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3443 ql_log(ql_log_info, base_vha, 0x00fc,
3444 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
dc6d6d34
BVA		 3445 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3446 sizeof(pci_info)),
7c3df132
SK		 3447 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3448 base_vha->host_no,
df57caba 3449 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3450
2d70c103
NB		 3451 qlt_add_target(ha, base_vha);
3452
6b383979 3453 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3454
3455 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3456 return -ENODEV;
3457
e4e3a2ce
QT		 3458 if (ha->flags.detected_lr_sfp) {
3459 ql_log(ql_log_info, base_vha, 0xffff,
3460 "Reset chip to pick up LR SFP setting\n");
3461 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3462 qla2xxx_wake_dpc(base_vha);
3463 }
3464
1da177e4
LT		 3465 return 0;
3466
3467probe_failed:
b9978769
AV		 3468 if (base_vha->timer_active)
3469 qla2x00_stop_timer(base_vha);
3470 base_vha->flags.online = 0;
3471 if (ha->dpc_thread) {
3472 struct task_struct *t = ha->dpc_thread;
3473
3474 ha->dpc_thread = NULL;
3475 kthread_stop(t);
3476 }
3477
e315cd28 3478 qla2x00_free_device(base_vha);
e315cd28 3479 scsi_host_put(base_vha->host);
6d634067
BK		 3480 /*
3481 * Need to NULL out local req/rsp after
3482 * qla2x00_free_device => qla2x00_free_queues frees
3483 * what these are pointing to. Or else we'll
3484 * fall over below in qla2x00_free_req/rsp_que.
3485 */
3486 req = NULL;
3487 rsp = NULL;
1da177e4 3488
e315cd28 3489probe_hw_failed:
d64d6c56 3490 qla2x00_mem_free(ha);
3491 qla2x00_free_req_que(ha, req);
3492 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3493 qla2x00_clear_drv_active(ha);
3494
0a63ad12 3495iospace_config_failed:
7ec0effd 3496 if (IS_P3P_TYPE(ha)) {
0a63ad12 3497 if (!ha->nx_pcibase)
f73cb695 3498 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3499 if (!ql2xdbwr)
f73cb695 3500 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3501 } else {
3502 if (ha->iobase)
3503 iounmap(ha->iobase);
8ae6d9c7
GM		 3504 if (ha->cregbase)
3505 iounmap(ha->cregbase);
a9083016 3506 }
e315cd28
AC		 3507 pci_release_selected_regions(ha->pdev, ha->bars);
3508 kfree(ha);
1da177e4 3509
ddff7ed4 3510disable_device:
e315cd28 3511 pci_disable_device(pdev);
a1541d5a 3512 return ret;
1da177e4 3513}
1da177e4 3514
e30d1756
MI		 3515static void
3516qla2x00_shutdown(struct pci_dev *pdev)
3517{
3518 scsi_qla_host_t *vha;
3519 struct qla_hw_data *ha;
3520
3521 vha = pci_get_drvdata(pdev);
3522 ha = vha->hw;
3523
efdb5760
SC		 3524 ql_log(ql_log_info, vha, 0xfffa,
3525 "Adapter shutdown\n");
3526
3527 /*
3528 * Prevent future board_disable and wait
3529 * until any pending board_disable has completed.
3530 */
3531 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3532 cancel_work_sync(&ha->board_disable);
3533
3534 if (!atomic_read(&pdev->enable_cnt))
3535 return;
3536
42479343
AB		 3537 /* Notify ISPFX00 firmware */
3538 if (IS_QLAFX00(ha))
3539 qlafx00_driver_shutdown(vha, 20);
3540
e30d1756
MI		 3541 /* Turn-off FCE trace */
3542 if (ha->flags.fce_enabled) {
3543 qla2x00_disable_fce_trace(vha, NULL, NULL);
3544 ha->flags.fce_enabled = 0;
3545 }
3546
3547 /* Turn-off EFT trace */
3548 if (ha->eft)
3549 qla2x00_disable_eft_trace(vha);
3550
ecc89f25
JC		 3551 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3552 IS_QLA28XX(ha)) {
3407fc37
QT		 3553 if (ha->flags.fw_started)
3554 qla2x00_abort_isp_cleanup(vha);
3555 } else {
3556 /* Stop currently executing firmware. */
3557 qla2x00_try_to_stop_firmware(vha);
3558 }
e30d1756
MI		 3559
3560 /* Turn adapter off line */
3561 vha->flags.online = 0;
3562
3563 /* turn-off interrupts on the card */
3564 if (ha->interrupts_on) {
3565 vha->flags.init_done = 0;
3566 ha->isp_ops->disable_intrs(ha);
3567 }
3568
3569 qla2x00_free_irqs(vha);
3570
3571 qla2x00_free_fw_dump(ha);
61d41f61 3572
61d41f61 3573 pci_disable_device(pdev);
efdb5760
SC		 3574 ql_log(ql_log_info, vha, 0xfffe,
3575 "Adapter shutdown successfully.\n");
e30d1756
MI		 3576}
3577
fe1b806f 3578/* Deletes all the virtual ports for a given ha */
4c993f76 3579static void
fe1b806f 3580qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3581{
fe1b806f 3582 scsi_qla_host_t *vha;
feafb7b1 3583 unsigned long flags;
e315cd28 3584
43ebf16d
AE		 3585 mutex_lock(&ha->vport_lock);
3586 while (ha->cur_vport_count) {
43ebf16d 3587 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3588
43ebf16d
AE		 3589 BUG_ON(base_vha->list.next == &ha->vp_list);
3590 /* This assumes first entry in ha->vp_list is always base vha */
3591 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3592 scsi_host_get(vha->host);
feafb7b1 3593
43ebf16d
AE		 3594 spin_unlock_irqrestore(&ha->vport_slock, flags);
3595 mutex_unlock(&ha->vport_lock);
3596
5e6803b4
HM		 3597 qla_nvme_delete(vha);
3598
43ebf16d
AE		 3599 fc_vport_terminate(vha->fc_vport);
3600 scsi_host_put(vha->host);
feafb7b1 3601
43ebf16d 3602 mutex_lock(&ha->vport_lock);
e315cd28 3603 }
43ebf16d 3604 mutex_unlock(&ha->vport_lock);
fe1b806f 3605}
1da177e4 3606
fe1b806f
CD		 3607/* Stops all deferred work threads */
3608static void
3609qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3610{
7d613ac6
SV		 3611 /* Cancel all work and destroy DPC workqueues */
3612 if (ha->dpc_lp_wq) {
3613 cancel_work_sync(&ha->idc_aen);
3614 destroy_workqueue(ha->dpc_lp_wq);
3615 ha->dpc_lp_wq = NULL;
3616 }
3617
3618 if (ha->dpc_hp_wq) {
3619 cancel_work_sync(&ha->nic_core_reset);
3620 cancel_work_sync(&ha->idc_state_handler);
3621 cancel_work_sync(&ha->nic_core_unrecoverable);
3622 destroy_workqueue(ha->dpc_hp_wq);
3623 ha->dpc_hp_wq = NULL;
3624 }
3625
b9978769
AV		 3626 /* Kill the kernel thread for this host */
3627 if (ha->dpc_thread) {
3628 struct task_struct *t = ha->dpc_thread;
3629
3630 /*
3631 * qla2xxx_wake_dpc checks for ->dpc_thread
3632 * so we need to zero it out.
3633 */
3634 ha->dpc_thread = NULL;
3635 kthread_stop(t);
3636 }
fe1b806f 3637}
1da177e4 3638
fe1b806f
CD		 3639static void
3640qla2x00_unmap_iobases(struct qla_hw_data *ha)
3641{
a9083016 3642 if (IS_QLA82XX(ha)) {
b963752f 3643
f73cb695 3644 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3645 if (!ql2xdbwr)
f73cb695 3646 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3647 } else {
3648 if (ha->iobase)
3649 iounmap(ha->iobase);
1da177e4 3650
8ae6d9c7
GM		 3651 if (ha->cregbase)
3652 iounmap(ha->cregbase);
3653
a9083016
GM		 3654 if (ha->mqiobase)
3655 iounmap(ha->mqiobase);
6246b8a1 3656
ecc89f25
JC		 3657 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3658 ha->msixbase)
6246b8a1 3659 iounmap(ha->msixbase);
a9083016 3660 }
fe1b806f
CD		 3661}
3662
3663static void
db7157d4 3664qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3665{
fe1b806f
CD		 3666 if (IS_QLA8044(ha)) {
3667 qla8044_idc_lock(ha);
c41afc9a 3668 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3669 qla8044_idc_unlock(ha);
3670 } else if (IS_QLA82XX(ha)) {
3671 qla82xx_idc_lock(ha);
3672 qla82xx_clear_drv_active(ha);
3673 qla82xx_idc_unlock(ha);
3674 }
3675}
3676
3677static void
3678qla2x00_remove_one(struct pci_dev *pdev)
3679{
3680 scsi_qla_host_t *base_vha;
3681 struct qla_hw_data *ha;
3682
beb9e315
JL		 3683 base_vha = pci_get_drvdata(pdev);
3684 ha = base_vha->hw;
45235022
QT		 3685 ql_log(ql_log_info, base_vha, 0xb079,
3686 "Removing driver\n");
beb9e315
JL		 3687
3688 /* Indicate device removal to prevent future board_disable and wait
3689 * until any pending board_disable has completed. */
3690 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3691 cancel_work_sync(&ha->board_disable);
3692
fe1b806f 3693 /*
beb9e315
JL		 3694 * If the PCI device is disabled then there was a PCI-disconnect and
3695 * qla2x00_disable_board_on_pci_error has taken care of most of the
3696 * resources.
fe1b806f 3697 */
beb9e315 3698 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3699 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3700 base_vha->gnl.l, base_vha->gnl.ldma);
3701
beb9e315
JL		 3702 scsi_host_put(base_vha->host);
3703 kfree(ha);
3704 pci_set_drvdata(pdev, NULL);
fe1b806f 3705 return;
beb9e315 3706 }
638a1a01
SC		 3707 qla2x00_wait_for_hba_ready(base_vha);
3708
ecc89f25
JC		 3709 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3710 IS_QLA28XX(ha)) {
45235022
QT		 3711 if (ha->flags.fw_started)
3712 qla2x00_abort_isp_cleanup(base_vha);
3713 } else if (!IS_QLAFX00(ha)) {
3714 if (IS_QLA8031(ha)) {
3715 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3716 "Clearing fcoe driver presence.\n");
3717 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3718 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3719 "Error while clearing DRV-Presence.\n");
3720 }
3721
3722 qla2x00_try_to_stop_firmware(base_vha);
3723 }
3724
2ce87cc5
QT		 3725 qla2x00_wait_for_sess_deletion(base_vha);
3726
726b8548
QT		 3727 /*
3728 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3729 * where it was set first.
3730 */
3731 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3732 return;
3733
fe1b806f 3734 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3735
3736 qla_nvme_delete(base_vha);
3737
726b8548
QT		 3738 dma_free_coherent(&ha->pdev->dev,
3739 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3740
a4239945
QT		 3741 vfree(base_vha->scan.l);
3742
fe1b806f
CD		 3743 if (IS_QLAFX00(ha))
3744 qlafx00_driver_shutdown(base_vha, 20);
3745
3746 qla2x00_delete_all_vps(ha, base_vha);
3747
fe1b806f
CD		 3748 qla2x00_dfs_remove(base_vha);
3749
3750 qla84xx_put_chip(base_vha);
3751
3752 /* Disable timer */
3753 if (base_vha->timer_active)
3754 qla2x00_stop_timer(base_vha);
3755
3756 base_vha->flags.online = 0;
3757
b0d6cabd
HM		 3758 /* free DMA memory */
3759 if (ha->exlogin_buf)
3760 qla2x00_free_exlogin_buffer(ha);
3761
2f56a7f1
HM		 3762 /* free DMA memory */
3763 if (ha->exchoffld_buf)
3764 qla2x00_free_exchoffld_buffer(ha);
3765
fe1b806f
CD		 3766 qla2x00_destroy_deferred_work(ha);
3767
3768 qlt_remove_target(ha, base_vha);
3769
3770 qla2x00_free_sysfs_attr(base_vha, true);
3771
3772 fc_remove_host(base_vha->host);
482c9dc7 3773 qlt_remove_target_resources(ha);
fe1b806f
CD		 3774
3775 scsi_remove_host(base_vha->host);
3776
3777 qla2x00_free_device(base_vha);
3778
db7157d4 3779 qla2x00_clear_drv_active(ha);
fe1b806f 3780
d2749ffa
AE		 3781 scsi_host_put(base_vha->host);
3782
fe1b806f 3783 qla2x00_unmap_iobases(ha);
73208dfd 3784
e315cd28
AC		 3785 pci_release_selected_regions(ha->pdev, ha->bars);
3786 kfree(ha);
1da177e4 3787
90a86fc0
JC		 3788 pci_disable_pcie_error_reporting(pdev);
3789
665db93b 3790 pci_disable_device(pdev);
1da177e4 3791}
1da177e4
LT		 3792
3793static void
e315cd28 3794qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3795{
e315cd28 3796 struct qla_hw_data *ha = vha->hw;
1da177e4 3797
85880801
AV		 3798 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3799
3800 /* Disable timer */
3801 if (vha->timer_active)
3802 qla2x00_stop_timer(vha);
3803
2afa19a9 3804 qla25xx_delete_queues(vha);
85880801
AV		 3805 vha->flags.online = 0;
3806
f6ef3b18 3807 /* turn-off interrupts on the card */
a9083016
GM		 3808 if (ha->interrupts_on) {
3809 vha->flags.init_done = 0;
fd34f556 3810 ha->isp_ops->disable_intrs(ha);
a9083016 3811 }
f6ef3b18 3812
093df737
QT		 3813 qla2x00_free_fcports(vha);
3814
e315cd28 3815 qla2x00_free_irqs(vha);
1da177e4 3816
093df737
QT		 3817 /* Flush the work queue and remove it */
3818 if (ha->wq) {
3819 flush_workqueue(ha->wq);
3820 destroy_workqueue(ha->wq);
3821 ha->wq = NULL;
3822 }
3823
8867048b 3824
e315cd28 3825 qla2x00_mem_free(ha);
73208dfd 3826
08de2844
GM		 3827 qla82xx_md_free(vha);
3828
73208dfd 3829 qla2x00_free_queues(ha);
1da177e4
LT		 3830}
3831
8867048b
CD		 3832void qla2x00_free_fcports(struct scsi_qla_host *vha)
3833{
3834 fc_port_t *fcport, *tfcport;
3835
ffbc6476
QT		 3836 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3837 qla2x00_free_fcport(fcport);
8867048b
CD		 3838}
3839
d97994dc 3840static inline void
e315cd28 3841qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3842 int defer)
3843{
d97994dc 3844 struct fc_rport *rport;
67becc00 3845 scsi_qla_host_t *base_vha;
044d78e1 3846 unsigned long flags;
d97994dc 3847
3848 if (!fcport->rport)
3849 return;
3850
3851 rport = fcport->rport;
3852 if (defer) {
67becc00 3853 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3854 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3855 fcport->drport = rport;
044d78e1 3856 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3857 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3858 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3859 qla2xxx_wake_dpc(base_vha);
2d70c103 3860 } else {
df673274 3861 int now;
bd432bb5 3862
726b8548 3863 if (rport) {
83548fe2
QT		 3864 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3865 "%s %8phN. rport %p roles %x\n",
3866 __func__, fcport->port_name, rport,
3867 rport->roles);
d20ed91b 3868 fc_remote_port_delete(rport);
726b8548 3869 }
df673274 3870 qlt_do_generation_tick(vha, &now);
2d70c103 3871 }
d97994dc 3872}
3873
1da177e4
LT		 3874/*
3875 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3876 *
3877 * Input: ha = adapter block pointer. fcport = port structure pointer.
3878 *
3879 * Return: None.
3880 *
3881 * Context:
3882 */
e315cd28 3883void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3884 int do_login, int defer)
1da177e4 3885{
8ae6d9c7
GM		 3886 if (IS_QLAFX00(vha->hw)) {
3887 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3888 qla2x00_schedule_rport_del(vha, fcport, defer);
3889 return;
3890 }
3891
2c3dfe3f 3892 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3893 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3894 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3895 qla2x00_schedule_rport_del(vha, fcport, defer);
3896 }
fa2a1ce5 3897 /*
1da177e4
LT		 3898 * We may need to retry the login, so don't change the state of the
3899 * port but do the retries.
3900 */
3901 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3902 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3903
3904 if (!do_login)
3905 return;
3906
a1d0285e 3907 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3908}
3909
3910/*
3911 * qla2x00_mark_all_devices_lost
3912 * Updates fcport state when device goes offline.
3913 *
3914 * Input:
3915 * ha = adapter block pointer.
3916 * fcport = port structure pointer.
3917 *
3918 * Return:
3919 * None.
3920 *
3921 * Context:
3922 */
3923void
e315cd28 3924qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3925{
3926 fc_port_t *fcport;
3927
83548fe2
QT		 3928 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3929 "Mark all dev lost\n");
726b8548 3930
e315cd28 3931 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3932 fcport->scan_state = 0;
d8630bb9 3933 qlt_schedule_sess_for_deletion(fcport);
726b8548 3934
c6d39e23 3935 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3936 continue;
0d6e61bc 3937
1da177e4
LT		 3938 /*
3939 * No point in marking the device as lost, if the device is
3940 * already DEAD.
3941 */
3942 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3943 continue;
e315cd28 3944 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3945 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3946 if (defer)
3947 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3948 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3949 qla2x00_schedule_rport_del(vha, fcport, defer);
3950 }
1da177e4
LT		 3951 }
3952}
3953
0e145a59
BVA		 3954static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
3955{
3956 int i;
3957
3958 if (IS_FWI2_CAPABLE(ha))
3959 return;
3960
3961 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
3962 set_bit(i, ha->loop_id_map);
3963 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
3964 set_bit(BROADCAST, ha->loop_id_map);
3965}
3966
1da177e4
LT		 3967/*
3968* qla2x00_mem_alloc
3969* Allocates adapter memory.
3970*
3971* Returns:
3972* 0 = success.
e8711085 3973* !0 = failure.
1da177e4 3974*/
e8711085 3975static int
73208dfd
AC		 3976qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3977 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3978{
3979 char name[16];
1da177e4 3980
e8711085 3981 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3982 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3983 if (!ha->init_cb)
e315cd28 3984 goto fail;
e8711085 3985
2d70c103
NB		 3986 if (qlt_mem_alloc(ha) < 0)
3987 goto fail_free_init_cb;
3988
642ef983
CD		 3989 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3990 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3991 if (!ha->gid_list)
2d70c103 3992 goto fail_free_tgt_mem;
1da177e4 3993
e8711085
AV		 3994 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3995 if (!ha->srb_mempool)
e315cd28 3996 goto fail_free_gid_list;
e8711085 3997
7ec0effd 3998 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3999 /* Allocate cache for CT6 Ctx. */
4000 if (!ctx_cachep) {
4001 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4002 sizeof(struct ct6_dsd), 0,
4003 SLAB_HWCACHE_ALIGN, NULL);
4004 if (!ctx_cachep)
fc1ffd6c 4005 goto fail_free_srb_mempool;
a9083016
GM		 4006 }
4007 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4008 ctx_cachep);
4009 if (!ha->ctx_mempool)
4010 goto fail_free_srb_mempool;
7c3df132
SK		 4011 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4012 "ctx_cachep=%p ctx_mempool=%p.\n",
4013 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 4014 }
4015
e8711085
AV		 4016 /* Get memory for cached NVRAM */
4017 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4018 if (!ha->nvram)
a9083016 4019 goto fail_free_ctx_mempool;
e8711085 4020
e315cd28
AC		 4021 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4022 ha->pdev->device);
4023 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4024 DMA_POOL_SIZE, 8, 0);
4025 if (!ha->s_dma_pool)
4026 goto fail_free_nvram;
4027
7c3df132
SK		 4028 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4029 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4030 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4031
7ec0effd 4032 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 4033 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4034 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4035 if (!ha->dl_dma_pool) {
7c3df132
SK		 4036 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4037 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 4038 goto fail_s_dma_pool;
4039 }
4040
4041 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4042 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4043 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 4044 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4045 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 4046 goto fail_dl_dma_pool;
4047 }
50b81275
GM		 4048
4049 if (ql2xenabledif) {
4050 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4051 struct dsd_dma *dsd, *nxt;
4052 uint i;
4053 /* Creata a DMA pool of buffers for DIF bundling */
4054 ha->dif_bundl_pool = dma_pool_create(name,
4055 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4056 if (!ha->dif_bundl_pool) {
4057 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4058 "%s: failed create dif_bundl_pool\n",
4059 __func__);
4060 goto fail_dif_bundl_dma_pool;
4061 }
4062
4063 INIT_LIST_HEAD(&ha->pool.good.head);
4064 INIT_LIST_HEAD(&ha->pool.unusable.head);
4065 ha->pool.good.count = 0;
4066 ha->pool.unusable.count = 0;
4067 for (i = 0; i < 128; i++) {
4068 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4069 if (!dsd) {
4070 ql_dbg_pci(ql_dbg_init, ha->pdev,
4071 0xe0ee, "%s: failed alloc dsd\n",
4072 __func__);
4073 return 1;
4074 }
4075 ha->dif_bundle_kallocs++;
4076
4077 dsd->dsd_addr = dma_pool_alloc(
4078 ha->dif_bundl_pool, GFP_ATOMIC,
4079 &dsd->dsd_list_dma);
4080 if (!dsd->dsd_addr) {
4081 ql_dbg_pci(ql_dbg_init, ha->pdev,
4082 0xe0ee,
4083 "%s: failed alloc ->dsd_addr\n",
4084 __func__);
4085 kfree(dsd);
4086 ha->dif_bundle_kallocs--;
4087 continue;
4088 }
4089 ha->dif_bundle_dma_allocs++;
4090
4091 /*
4092 * if DMA buffer crosses 4G boundary,
4093 * put it on bad list
4094 */
4095 if (MSD(dsd->dsd_list_dma) ^
4096 MSD(dsd->dsd_list_dma + bufsize)) {
4097 list_add_tail(&dsd->list,
4098 &ha->pool.unusable.head);
4099 ha->pool.unusable.count++;
4100 } else {
4101 list_add_tail(&dsd->list,
4102 &ha->pool.good.head);
4103 ha->pool.good.count++;
4104 }
4105 }
4106
4107 /* return the good ones back to the pool */
4108 list_for_each_entry_safe(dsd, nxt,
4109 &ha->pool.good.head, list) {
4110 list_del(&dsd->list);
4111 dma_pool_free(ha->dif_bundl_pool,
4112 dsd->dsd_addr, dsd->dsd_list_dma);
4113 ha->dif_bundle_dma_allocs--;
4114 kfree(dsd);
4115 ha->dif_bundle_kallocs--;
4116 }
4117
4118 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4119 "%s: dif dma pool (good=%u unusable=%u)\n",
4120 __func__, ha->pool.good.count,
4121 ha->pool.unusable.count);
4122 }
4123
7c3df132 4124 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
50b81275
GM		 4125 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4126 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4127 ha->dif_bundl_pool);
a9083016
GM		 4128 }
4129
e8711085
AV		 4130 /* Allocate memory for SNS commands */
4131 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 4132 /* Get consistent memory allocated for SNS commands */
e8711085 4133 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4134 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 4135 if (!ha->sns_cmd)
e315cd28 4136 goto fail_dma_pool;
7c3df132 4137 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 4138 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 4139 } else {
e315cd28 4140 /* Get consistent memory allocated for MS IOCB */
e8711085 4141 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 4142 &ha->ms_iocb_dma);
e8711085 4143 if (!ha->ms_iocb)
e315cd28
AC		 4144 goto fail_dma_pool;
4145 /* Get consistent memory allocated for CT SNS commands */
e8711085 4146 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4147 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 4148 if (!ha->ct_sns)
4149 goto fail_free_ms_iocb;
7c3df132
SK		 4150 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4151 "ms_iocb=%p ct_sns=%p.\n",
4152 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 4153 }
4154
e315cd28 4155 /* Allocate memory for request ring */
73208dfd
AC		 4156 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4157 if (!*req) {
7c3df132
SK		 4158 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4159 "Failed to allocate memory for req.\n");
e315cd28
AC		 4160 goto fail_req;
4161 }
73208dfd
AC		 4162 (*req)->length = req_len;
4163 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4164 ((*req)->length + 1) * sizeof(request_t),
4165 &(*req)->dma, GFP_KERNEL);
4166 if (!(*req)->ring) {
7c3df132
SK		 4167 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4168 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4169 goto fail_req_ring;
4170 }
4171 /* Allocate memory for response ring */
73208dfd
AC		 4172 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4173 if (!*rsp) {
7c3df132
SK		 4174 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4175 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4176 goto fail_rsp;
4177 }
73208dfd
AC		 4178 (*rsp)->hw = ha;
4179 (*rsp)->length = rsp_len;
4180 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4181 ((*rsp)->length + 1) * sizeof(response_t),
4182 &(*rsp)->dma, GFP_KERNEL);
4183 if (!(*rsp)->ring) {
7c3df132
SK		 4184 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4185 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4186 goto fail_rsp_ring;
4187 }
73208dfd
AC		 4188 (*req)->rsp = *rsp;
4189 (*rsp)->req = *req;
7c3df132
SK		 4190 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4191 "req=%p req->length=%d req->ring=%p rsp=%p "
4192 "rsp->length=%d rsp->ring=%p.\n",
4193 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4194 (*rsp)->ring);
73208dfd
AC		 4195 /* Allocate memory for NVRAM data for vports */
4196 if (ha->nvram_npiv_size) {
6396bb22
KC		 4197 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4198 sizeof(struct qla_npiv_entry),
4199 GFP_KERNEL);
73208dfd 4200 if (!ha->npiv_info) {
7c3df132
SK		 4201 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4202 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4203 goto fail_npiv_info;
4204 }
4205 } else
4206 ha->npiv_info = NULL;
e8711085 4207
b64b0e8f 4208 /* Get consistent memory allocated for EX-INIT-CB. */
ecc89f25
JC		 4209 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4210 IS_QLA28XX(ha)) {
b64b0e8f
AV		 4211 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4212 &ha->ex_init_cb_dma);
4213 if (!ha->ex_init_cb)
4214 goto fail_ex_init_cb;
7c3df132
SK		 4215 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4216 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4217 }
4218
a9083016
GM		 4219 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4220
5ff1d584
AV		 4221 /* Get consistent memory allocated for Async Port-Database. */
4222 if (!IS_FWI2_CAPABLE(ha)) {
4223 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4224 &ha->async_pd_dma);
4225 if (!ha->async_pd)
4226 goto fail_async_pd;
7c3df132
SK		 4227 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4228 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4229 }
4230
e315cd28 4231 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4232
4233 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4234 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4235 sizeof(long),
4236 GFP_KERNEL);
5f16b331 4237 if (!ha->loop_id_map)
fc1ffd6c 4238 goto fail_loop_id_map;
5f16b331
CD		 4239 else {
4240 qla2x00_set_reserved_loop_ids(ha);
4241 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4242 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4243 }
4244
e4e3a2ce
QT		 4245 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4246 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4247 if (!ha->sfp_data) {
4248 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4249 "Unable to allocate memory for SFP read-data.\n");
4250 goto fail_sfp_data;
4251 }
4252
3f006ac3
MH		 4253 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4254 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4255 GFP_KERNEL);
4256 if (!ha->flt) {
4257 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4258 "Unable to allocate memory for FLT.\n");
4259 goto fail_flt_buffer;
4260 }
4261
b2a72ec3 4262 return 0;
e315cd28 4263
3f006ac3
MH		 4264fail_flt_buffer:
4265 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4266 ha->sfp_data, ha->sfp_data_dma);
e4e3a2ce
QT		 4267fail_sfp_data:
4268 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4269fail_loop_id_map:
4270 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4271fail_async_pd:
4272 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4273fail_ex_init_cb:
4274 kfree(ha->npiv_info);
73208dfd
AC		 4275fail_npiv_info:
4276 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4277 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4278 (*rsp)->ring = NULL;
4279 (*rsp)->dma = 0;
e315cd28 4280fail_rsp_ring:
73208dfd 4281 kfree(*rsp);
6d634067 4282 *rsp = NULL;
e315cd28 4283fail_rsp:
73208dfd
AC		 4284 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4285 sizeof(request_t), (*req)->ring, (*req)->dma);
4286 (*req)->ring = NULL;
4287 (*req)->dma = 0;
e315cd28 4288fail_req_ring:
73208dfd 4289 kfree(*req);
6d634067 4290 *req = NULL;
e315cd28
AC		 4291fail_req:
4292 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4293 ha->ct_sns, ha->ct_sns_dma);
4294 ha->ct_sns = NULL;
4295 ha->ct_sns_dma = 0;
e8711085
AV		 4296fail_free_ms_iocb:
4297 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4298 ha->ms_iocb = NULL;
4299 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4300
4301 if (ha->sns_cmd)
4302 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4303 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4304fail_dma_pool:
50b81275
GM		 4305 if (ql2xenabledif) {
4306 struct dsd_dma *dsd, *nxt;
4307
4308 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4309 list) {
4310 list_del(&dsd->list);
4311 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4312 dsd->dsd_list_dma);
4313 ha->dif_bundle_dma_allocs--;
4314 kfree(dsd);
4315 ha->dif_bundle_kallocs--;
4316 ha->pool.unusable.count--;
4317 }
4318 dma_pool_destroy(ha->dif_bundl_pool);
4319 ha->dif_bundl_pool = NULL;
4320 }
4321
4322fail_dif_bundl_dma_pool:
bad75002 4323 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4324 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4325 ha->fcp_cmnd_dma_pool = NULL;
4326 }
4327fail_dl_dma_pool:
bad75002 4328 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4329 dma_pool_destroy(ha->dl_dma_pool);
4330 ha->dl_dma_pool = NULL;
4331 }
4332fail_s_dma_pool:
e315cd28
AC		 4333 dma_pool_destroy(ha->s_dma_pool);
4334 ha->s_dma_pool = NULL;
e8711085
AV		 4335fail_free_nvram:
4336 kfree(ha->nvram);
4337 ha->nvram = NULL;
a9083016 4338fail_free_ctx_mempool:
75c1d48a 4339 mempool_destroy(ha->ctx_mempool);
a9083016 4340 ha->ctx_mempool = NULL;
e8711085 4341fail_free_srb_mempool:
75c1d48a 4342 mempool_destroy(ha->srb_mempool);
e8711085 4343 ha->srb_mempool = NULL;
e8711085 4344fail_free_gid_list:
642ef983
CD		 4345 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4346 ha->gid_list,
e315cd28 4347 ha->gid_list_dma);
e8711085
AV		 4348 ha->gid_list = NULL;
4349 ha->gid_list_dma = 0;
2d70c103
NB		 4350fail_free_tgt_mem:
4351 qlt_mem_free(ha);
e315cd28
AC		 4352fail_free_init_cb:
4353 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4354 ha->init_cb_dma);
4355 ha->init_cb = NULL;
4356 ha->init_cb_dma = 0;
e8711085 4357fail:
7c3df132
SK		 4358 ql_log(ql_log_fatal, NULL, 0x0030,
4359 "Memory allocation failure.\n");
e8711085 4360 return -ENOMEM;
1da177e4
LT		 4361}
4362
b0d6cabd
HM		 4363int
4364qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4365{
4366 int rval;
4367 uint16_t size, max_cnt, temp;
4368 struct qla_hw_data *ha = vha->hw;
4369
4370 /* Return if we don't need to alloacate any extended logins */
4371 if (!ql2xexlogins)
4372 return QLA_SUCCESS;
4373
99e1b683
QT		 4374 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4375 return QLA_SUCCESS;
4376
b0d6cabd
HM		 4377 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4378 max_cnt = 0;
4379 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4380 if (rval != QLA_SUCCESS) {
4381 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4382 "Failed to get exlogin status.\n");
4383 return rval;
4384 }
4385
4386 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4387 temp *= size;
4388
4389 if (temp != ha->exlogin_size) {
4390 qla2x00_free_exlogin_buffer(ha);
4391 ha->exlogin_size = temp;
4392
4393 ql_log(ql_log_info, vha, 0xd024,
4394 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4395 max_cnt, size, temp);
4396
4397 ql_log(ql_log_info, vha, 0xd025,
4398 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4399
4400 /* Get consistent memory for extended logins */
4401 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4402 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4403 if (!ha->exlogin_buf) {
4404 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4405 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4406 return -ENOMEM;
4407 }
b0d6cabd
HM		 4408 }
4409
4410 /* Now configure the dma buffer */
4411 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4412 if (rval) {
83548fe2 4413 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4414 "Setup extended login buffer ****FAILED****.\n");
4415 qla2x00_free_exlogin_buffer(ha);
4416 }
4417
4418 return rval;
4419}
4420
4421/*
4422* qla2x00_free_exlogin_buffer
4423*
4424* Input:
4425* ha = adapter block pointer
4426*/
4427void
4428qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4429{
4430 if (ha->exlogin_buf) {
4431 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4432 ha->exlogin_buf, ha->exlogin_buf_dma);
4433 ha->exlogin_buf = NULL;
4434 ha->exlogin_size = 0;
4435 }
4436}
4437
99e1b683
QT		 4438static void
4439qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4440{
4441 u32 temp;
0645cb83 4442 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
99e1b683
QT		 4443 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4444
d1e3635a
QT		 4445 if (max_cnt > vha->hw->max_exchg)
4446 max_cnt = vha->hw->max_exchg;
4447
99e1b683 4448 if (qla_ini_mode_enabled(vha)) {
0645cb83
QT		 4449 if (vha->ql2xiniexchg > max_cnt)
4450 vha->ql2xiniexchg = max_cnt;
4451
4452 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4453 *ret_cnt = vha->ql2xiniexchg;
99e1b683 4454
99e1b683 4455 } else if (qla_tgt_mode_enabled(vha)) {
0645cb83
QT		 4456 if (vha->ql2xexchoffld > max_cnt) {
4457 vha->ql2xexchoffld = max_cnt;
4458 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4459 }
99e1b683 4460
0645cb83
QT		 4461 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4462 *ret_cnt = vha->ql2xexchoffld;
99e1b683 4463 } else if (qla_dual_mode_enabled(vha)) {
0645cb83 4464 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
99e1b683 4465 if (temp > max_cnt) {
0645cb83
QT		 4466 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4467 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
99e1b683 4468 temp = max_cnt;
0645cb83 4469 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
99e1b683
QT		 4470 }
4471
4472 if (temp > FW_DEF_EXCHANGES_CNT)
4473 *ret_cnt = temp;
4474 }
4475}
4476
2f56a7f1
HM		 4477int
4478qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4479{
4480 int rval;
d1e3635a
QT		 4481 u16 size, max_cnt;
4482 u32 actual_cnt, totsz;
2f56a7f1
HM		 4483 struct qla_hw_data *ha = vha->hw;
4484
99e1b683
QT		 4485 if (!ha->flags.exchoffld_enabled)
4486 return QLA_SUCCESS;
4487
4488 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4489 return QLA_SUCCESS;
4490
2f56a7f1
HM		 4491 max_cnt = 0;
4492 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4493 if (rval != QLA_SUCCESS) {
4494 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4495 "Failed to get exlogin status.\n");
4496 return rval;
4497 }
4498
d1e3635a
QT		 4499 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4500 ql_log(ql_log_info, vha, 0xd014,
4501 "Actual exchange offload count: %d.\n", actual_cnt);
4502
4503 totsz = actual_cnt * size;
2f56a7f1 4504
d1e3635a 4505 if (totsz != ha->exchoffld_size) {
99e1b683 4506 qla2x00_free_exchoffld_buffer(ha);
0645cb83
QT		 4507 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4508 ha->exchoffld_size = 0;
4509 ha->flags.exchoffld_enabled = 0;
4510 return QLA_SUCCESS;
4511 }
4512
d1e3635a 4513 ha->exchoffld_size = totsz;
99e1b683
QT		 4514
4515 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4516 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4517 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4518
4519 ql_log(ql_log_info, vha, 0xd017,
4520 "Exchange Buffers requested size = 0x%x\n",
4521 ha->exchoffld_size);
4522
4523 /* Get consistent memory for extended logins */
4524 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4525 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4526 if (!ha->exchoffld_buf) {
4527 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4528 "Failed to allocate memory for Exchange Offload.\n");
4529
4530 if (ha->max_exchg >
4531 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4532 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4533 } else if (ha->max_exchg >
4534 (FW_DEF_EXCHANGES_CNT + 512)) {
4535 ha->max_exchg -= 512;
4536 } else {
4537 ha->flags.exchoffld_enabled = 0;
4538 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4539 "Disabling Exchange offload due to lack of memory\n");
4540 }
4541 ha->exchoffld_size = 0;
4542
99e1b683
QT		 4543 return -ENOMEM;
4544 }
0645cb83
QT		 4545 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4546 /* pathological case */
4547 qla2x00_free_exchoffld_buffer(ha);
4548 ha->exchoffld_size = 0;
4549 ha->flags.exchoffld_enabled = 0;
4550 ql_log(ql_log_info, vha, 0xd016,
4551 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4552 ha->exchoffld_size, actual_cnt, size, totsz);
4553 return 0;
2f56a7f1
HM		 4554 }
4555
4556 /* Now configure the dma buffer */
99e1b683 4557 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4558 if (rval) {
4559 ql_log(ql_log_fatal, vha, 0xd02e,
4560 "Setup exchange offload buffer ****FAILED****.\n");
4561 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4562 } else {
4563 /* re-adjust number of target exchange */
4564 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4565
4566 if (qla_ini_mode_enabled(vha))
4567 icb->exchange_count = 0;
4568 else
0645cb83 4569 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
2f56a7f1
HM		 4570 }
4571
4572 return rval;
4573}
4574
4575/*
4576* qla2x00_free_exchoffld_buffer
4577*
4578* Input:
4579* ha = adapter block pointer
4580*/
4581void
4582qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4583{
4584 if (ha->exchoffld_buf) {
4585 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4586 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4587 ha->exchoffld_buf = NULL;
4588 ha->exchoffld_size = 0;
4589 }
4590}
4591
1da177e4 4592/*
e30d1756
MI		 4593* qla2x00_free_fw_dump
4594* Frees fw dump stuff.
1da177e4
LT		 4595*
4596* Input:
7ec0effd 4597* ha = adapter block pointer
1da177e4 4598*/
a824ebb3 4599static void
e30d1756 4600qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4601{
a28d9e4e
JC		 4602 struct fwdt *fwdt = ha->fwdt;
4603 uint j;
4604
df613b96 4605 if (ha->fce)
f73cb695
CD		 4606 dma_free_coherent(&ha->pdev->dev,
4607 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4608
f73cb695
CD		 4609 if (ha->eft)
4610 dma_free_coherent(&ha->pdev->dev,
4611 EFT_SIZE, ha->eft, ha->eft_dma);
4612
4613 if (ha->fw_dump)
a7a167bf 4614 vfree(ha->fw_dump);
f73cb695 4615
e30d1756
MI		 4616 ha->fce = NULL;
4617 ha->fce_dma = 0;
4618 ha->eft = NULL;
4619 ha->eft_dma = 0;
e30d1756 4620 ha->fw_dumped = 0;
61f098dd 4621 ha->fw_dump_cap_flags = 0;
e30d1756 4622 ha->fw_dump_reading = 0;
f73cb695
CD		 4623 ha->fw_dump = NULL;
4624 ha->fw_dump_len = 0;
a28d9e4e
JC		 4625
4626 for (j = 0; j < 2; j++, fwdt++) {
4627 if (fwdt->template)
4628 vfree(fwdt->template);
4629 fwdt->template = NULL;
4630 fwdt->length = 0;
4631 }
e30d1756
MI		 4632}
4633
4634/*
4635* qla2x00_mem_free
4636* Frees all adapter allocated memory.
4637*
4638* Input:
4639* ha = adapter block pointer.
4640*/
4641static void
4642qla2x00_mem_free(struct qla_hw_data *ha)
4643{
4644 qla2x00_free_fw_dump(ha);
4645
81178772
SK		 4646 if (ha->mctp_dump)
4647 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4648 ha->mctp_dump_dma);
5365bf99 4649 ha->mctp_dump = NULL;
81178772 4650
75c1d48a 4651 mempool_destroy(ha->srb_mempool);
5365bf99 4652 ha->srb_mempool = NULL;
a7a167bf 4653
11bbc1d8
AV		 4654 if (ha->dcbx_tlv)
4655 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4656 ha->dcbx_tlv, ha->dcbx_tlv_dma);
5365bf99 4657 ha->dcbx_tlv = NULL;
11bbc1d8 4658
ce0423f4
AV		 4659 if (ha->xgmac_data)
4660 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4661 ha->xgmac_data, ha->xgmac_data_dma);
5365bf99 4662 ha->xgmac_data = NULL;
ce0423f4 4663
1da177e4
LT		 4664 if (ha->sns_cmd)
4665 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4666 ha->sns_cmd, ha->sns_cmd_dma);
5365bf99
BVA		 4667 ha->sns_cmd = NULL;
4668 ha->sns_cmd_dma = 0;
1da177e4
LT		 4669
4670 if (ha->ct_sns)
4671 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4672 ha->ct_sns, ha->ct_sns_dma);
5365bf99
BVA		 4673 ha->ct_sns = NULL;
4674 ha->ct_sns_dma = 0;
1da177e4 4675
88729e53 4676 if (ha->sfp_data)
e4e3a2ce
QT		 4677 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4678 ha->sfp_data_dma);
5365bf99 4679 ha->sfp_data = NULL;
88729e53 4680
3f006ac3
MH		 4681 if (ha->flt)
4682 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4683 ha->flt, ha->flt_dma);
dc035d4e
BVA		 4684 ha->flt = NULL;
4685 ha->flt_dma = 0;
3f006ac3 4686
1da177e4
LT		 4687 if (ha->ms_iocb)
4688 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
5365bf99
BVA		 4689 ha->ms_iocb = NULL;
4690 ha->ms_iocb_dma = 0;
1da177e4 4691
b64b0e8f 4692 if (ha->ex_init_cb)
a9083016
GM		 4693 dma_pool_free(ha->s_dma_pool,
4694 ha->ex_init_cb, ha->ex_init_cb_dma);
5365bf99
BVA		 4695 ha->ex_init_cb = NULL;
4696 ha->ex_init_cb_dma = 0;
b64b0e8f 4697
5ff1d584
AV		 4698 if (ha->async_pd)
4699 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5365bf99
BVA		 4700 ha->async_pd = NULL;
4701 ha->async_pd_dma = 0;
5ff1d584 4702
75c1d48a 4703 dma_pool_destroy(ha->s_dma_pool);
5365bf99 4704 ha->s_dma_pool = NULL;
1da177e4 4705
1da177e4 4706 if (ha->gid_list)
642ef983
CD		 4707 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4708 ha->gid_list, ha->gid_list_dma);
5365bf99
BVA		 4709 ha->gid_list = NULL;
4710 ha->gid_list_dma = 0;
1da177e4 4711
a9083016
GM		 4712 if (IS_QLA82XX(ha)) {
4713 if (!list_empty(&ha->gbl_dsd_list)) {
4714 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4715
4716 /* clean up allocated prev pool */
4717 list_for_each_entry_safe(dsd_ptr,
4718 tdsd_ptr, &ha->gbl_dsd_list, list) {
4719 dma_pool_free(ha->dl_dma_pool,
4720 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4721 list_del(&dsd_ptr->list);
4722 kfree(dsd_ptr);
4723 }
4724 }
4725 }
4726
75c1d48a 4727 dma_pool_destroy(ha->dl_dma_pool);
5365bf99 4728 ha->dl_dma_pool = NULL;
a9083016 4729
75c1d48a 4730 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
5365bf99 4731 ha->fcp_cmnd_dma_pool = NULL;
a9083016 4732
75c1d48a 4733 mempool_destroy(ha->ctx_mempool);
5365bf99 4734 ha->ctx_mempool = NULL;
a9083016 4735
26a77799 4736 if (ql2xenabledif && ha->dif_bundl_pool) {
50b81275
GM		 4737 struct dsd_dma *dsd, *nxt;
4738
4739 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4740 list) {
4741 list_del(&dsd->list);
4742 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4743 dsd->dsd_list_dma);
4744 ha->dif_bundle_dma_allocs--;
4745 kfree(dsd);
4746 ha->dif_bundle_kallocs--;
4747 ha->pool.unusable.count--;
4748 }
4749 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4750 list_del(&dsd->list);
4751 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4752 dsd->dsd_list_dma);
4753 ha->dif_bundle_dma_allocs--;
4754 kfree(dsd);
4755 ha->dif_bundle_kallocs--;
4756 }
4757 }
4758
0b3b6fe2 4759 dma_pool_destroy(ha->dif_bundl_pool);
dc035d4e 4760 ha->dif_bundl_pool = NULL;
50b81275 4761
2d70c103
NB		 4762 qlt_mem_free(ha);
4763
e315cd28
AC		 4764 if (ha->init_cb)
4765 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4766 ha->init_cb, ha->init_cb_dma);
5365bf99
BVA		 4767 ha->init_cb = NULL;
4768 ha->init_cb_dma = 0;
6a2cf8d3 4769
6d634067 4770 vfree(ha->optrom_buffer);
5365bf99 4771 ha->optrom_buffer = NULL;
6d634067 4772 kfree(ha->nvram);
5365bf99 4773 ha->nvram = NULL;
6d634067 4774 kfree(ha->npiv_info);
5365bf99 4775 ha->npiv_info = NULL;
6d634067 4776 kfree(ha->swl);
5365bf99 4777 ha->swl = NULL;
6d634067 4778 kfree(ha->loop_id_map);
6a2cf8d3 4779 ha->loop_id_map = NULL;
e315cd28 4780}
1da177e4 4781
e315cd28
AC		 4782struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4783 struct qla_hw_data *ha)
4784{
4785 struct Scsi_Host *host;
4786 struct scsi_qla_host *vha = NULL;
854165f4 4787
e315cd28 4788 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4789 if (!host) {
7c3df132
SK		 4790 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4791 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4792 return NULL;
e315cd28
AC		 4793 }
4794
4795 /* Clear our data area */
4796 vha = shost_priv(host);
4797 memset(vha, 0, sizeof(scsi_qla_host_t));
4798
4799 vha->host = host;
4800 vha->host_no = host->host_no;
4801 vha->hw = ha;
4802
0645cb83
QT		 4803 vha->qlini_mode = ql2x_ini_mode;
4804 vha->ql2xexchoffld = ql2xexchoffld;
4805 vha->ql2xiniexchg = ql2xiniexchg;
4806
e315cd28
AC		 4807 INIT_LIST_HEAD(&vha->vp_fcports);
4808 INIT_LIST_HEAD(&vha->work_list);
4809 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4810 INIT_LIST_HEAD(&vha->qla_cmd_list);
4811 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4812 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4813 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4814 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4815 INIT_LIST_HEAD(&vha->gnl.fcports);
2d73ac61 4816 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4817 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4818
f999f4c1 4819 spin_lock_init(&vha->work_lock);
8b2f5ff3 4820 spin_lock_init(&vha->cmd_list_lock);
726b8548 4821 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4822 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4823
2fdbc65e
BVA		 4824 vha->gnl.size = sizeof(struct get_name_list_extended) *
4825 (ha->max_loop_id + 1);
41dc529a
QT		 4826 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4827 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4828 if (!vha->gnl.l) {
83548fe2 4829 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a 4830 "Alloc failed for name list.\n");
26a77799 4831 scsi_host_put(vha->host);
41dc529a
QT		 4832 return NULL;
4833 }
f999f4c1 4834
a4239945
QT		 4835 /* todo: what about ext login? */
4836 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4837 vha->scan.l = vmalloc(vha->scan.size);
4838 if (!vha->scan.l) {
4839 ql_log(ql_log_fatal, vha, 0xd04a,
4840 "Alloc failed for scan database.\n");
4841 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4842 vha->gnl.l, vha->gnl.ldma);
26a77799 4843 scsi_host_put(vha->host);
a4239945
QT		 4844 return NULL;
4845 }
f352eeb7 4846 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4847
e315cd28 4848 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4849 ql_dbg(ql_dbg_init, vha, 0x0041,
4850 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4851 vha->host, vha->hw, vha,
4852 dev_name(&(ha->pdev->dev)));
4853
e315cd28 4854 return vha;
1da177e4
LT		 4855}
4856
726b8548 4857struct qla_work_evt *
f999f4c1 4858qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4859{
4860 struct qla_work_evt *e;
feafb7b1
AE		 4861 uint8_t bail;
4862
4863 QLA_VHA_MARK_BUSY(vha, bail);
4864 if (bail)
4865 return NULL;
0971de7f 4866
f999f4c1 4867 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4868 if (!e) {
4869 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4870 return NULL;
feafb7b1 4871 }
0971de7f
AV		 4872
4873 INIT_LIST_HEAD(&e->list);
4874 e->type = type;
4875 e->flags = QLA_EVT_FLAG_FREE;
4876 return e;
4877}
4878
726b8548 4879int
f999f4c1 4880qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4881{
f999f4c1 4882 unsigned long flags;
9b3e0f4d 4883 bool q = false;
0971de7f 4884
f999f4c1 4885 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4886 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4887
4888 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4889 q = true;
4890
f999f4c1 4891 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4892
9b3e0f4d
QT		 4893 if (q)
4894 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4895
0971de7f
AV		 4896 return QLA_SUCCESS;
4897}
4898
4899int
e315cd28 4900qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4901 u32 data)
4902{
4903 struct qla_work_evt *e;
4904
f999f4c1 4905 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4906 if (!e)
4907 return QLA_FUNCTION_FAILED;
4908
4909 e->u.aen.code = code;
4910 e->u.aen.data = data;
f999f4c1 4911 return qla2x00_post_work(vha, e);
0971de7f
AV		 4912}
4913
8a659571
AV		 4914int
4915qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4916{
4917 struct qla_work_evt *e;
4918
f999f4c1 4919 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4920 if (!e)
4921 return QLA_FUNCTION_FAILED;
4922
4923 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4924 return qla2x00_post_work(vha, e);
8a659571
AV		 4925}
4926
ac280b67
AV		 4927#define qla2x00_post_async_work(name, type) \
4928int qla2x00_post_async_##name##_work( \
4929 struct scsi_qla_host *vha, \
4930 fc_port_t *fcport, uint16_t *data) \
4931{ \
4932 struct qla_work_evt *e; \
4933 \
4934 e = qla2x00_alloc_work(vha, type); \
4935 if (!e) \
4936 return QLA_FUNCTION_FAILED; \
4937 \
4938 e->u.logio.fcport = fcport; \
4939 if (data) { \
4940 e->u.logio.data[0] = data[0]; \
4941 e->u.logio.data[1] = data[1]; \
4942 } \
6d674927 4943 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4944 return qla2x00_post_work(vha, e); \
4945}
4946
4947qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4948qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4949qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584 4950qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
11aea16a
QT		 4951qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4952qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4953
3420d36c
AV		 4954int
4955qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4956{
4957 struct qla_work_evt *e;
4958
4959 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4960 if (!e)
4961 return QLA_FUNCTION_FAILED;
4962
4963 e->u.uevent.code = code;
4964 return qla2x00_post_work(vha, e);
4965}
4966
4967static void
4968qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4969{
4970 char event_string[40];
4971 char *envp[] = { event_string, NULL };
4972
4973 switch (code) {
4974 case QLA_UEVENT_CODE_FW_DUMP:
4975 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4976 vha->host_no);
4977 break;
4978 default:
4979 /* do nothing */
4980 break;
4981 }
4982 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4983}
4984
8ae6d9c7
GM		 4985int
4986qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4987 uint32_t *data, int cnt)
4988{
4989 struct qla_work_evt *e;
4990
4991 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4992 if (!e)
4993 return QLA_FUNCTION_FAILED;
4994
4995 e->u.aenfx.evtcode = evtcode;
4996 e->u.aenfx.count = cnt;
4997 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4998 return qla2x00_post_work(vha, e);
4999}
5000
cd4ed6b4 5001void qla24xx_sched_upd_fcport(fc_port_t *fcport)
726b8548 5002{
cd4ed6b4 5003 unsigned long flags;
726b8548 5004
cd4ed6b4
QT		 5005 if (IS_SW_RESV_ADDR(fcport->d_id))
5006 return;
726b8548 5007
cd4ed6b4
QT		 5008 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5009 if (fcport->disc_state == DSC_UPD_FCPORT) {
5010 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5011 return;
5012 }
5013 fcport->jiffies_at_registration = jiffies;
5014 fcport->sec_since_registration = 0;
5015 fcport->next_disc_state = DSC_DELETED;
5016 fcport->disc_state = DSC_UPD_FCPORT;
5017 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5018
5019 queue_work(system_unbound_wq, &fcport->reg_work);
726b8548
QT		 5020}
5021
5022static
5023void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5024{
5025 unsigned long flags;
b5d15312 5026 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 5027 struct qlt_plogi_ack_t *pla =
5028 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 5029 uint8_t free_fcport = 0;
726b8548 5030
9cd883f0
QT		 5031 ql_dbg(ql_dbg_disc, vha, 0xffff,
5032 "%s %d %8phC enter\n",
5033 __func__, __LINE__, e->u.new_sess.port_name);
5034
726b8548
QT		 5035 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5036 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5037 if (fcport) {
5038 fcport->d_id = e->u.new_sess.id;
5039 if (pla) {
5040 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 5041 memcpy(fcport->node_name,
5042 pla->iocb.u.isp24.u.plogi.node_name,
5043 WWN_SIZE);
726b8548
QT		 5044 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5045 /* we took an extra ref_count to prevent PLOGI ACK when
5046 * fcport/sess has not been created.
5047 */
5048 pla->ref_count--;
5049 }
5050 } else {
b5d15312 5051 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 5052 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5053 if (fcport) {
5054 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 5055 fcport->flags |= FCF_FABRIC_DEVICE;
5056 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
c64a87f9 5057 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP)
a4239945 5058 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548 5059
c64a87f9 5060 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) {
2b5b9647
DT		 5061 fcport->fc4_type = FC4_TYPE_OTHER;
5062 fcport->fc4f_nvme = FC4_TYPE_NVME;
5063 }
33b28357 5064
726b8548
QT		 5065 memcpy(fcport->port_name, e->u.new_sess.port_name,
5066 WWN_SIZE);
b5d15312
QT		 5067 } else {
5068 ql_dbg(ql_dbg_disc, vha, 0xffff,
5069 "%s %8phC mem alloc fail.\n",
5070 __func__, e->u.new_sess.port_name);
5071
1df627b4
BVA		 5072 if (pla) {
5073 list_del(&pla->list);
b5d15312 5074 kmem_cache_free(qla_tgt_plogi_cachep, pla);
1df627b4 5075 }
b5d15312
QT		 5076 return;
5077 }
5078
5079 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 5080 /* search again to make sure no one else got ahead */
b5d15312
QT		 5081 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5082 e->u.new_sess.port_name, 1);
5083 if (tfcp) {
5084 /* should rarily happen */
5085 ql_dbg(ql_dbg_disc, vha, 0xffff,
5086 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5087 __func__, tfcp->port_name, tfcp->disc_state,
5088 tfcp->fw_login_state);
5089
5090 free_fcport = 1;
5091 } else {
726b8548
QT		 5092 list_add_tail(&fcport->list, &vha->vp_fcports);
5093
19759033
QT		 5094 }
5095 if (pla) {
5096 qlt_plogi_ack_link(vha, pla, fcport,
5097 QLT_PLOGI_LINK_SAME_WWN);
5098 pla->ref_count--;
726b8548
QT		 5099 }
5100 }
5101 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5102
5103 if (fcport) {
a4239945
QT		 5104 fcport->id_changed = 1;
5105 fcport->scan_state = QLA_FCPORT_FOUND;
8b5292bc 5106 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
a4239945
QT		 5107 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5108
5ef696aa 5109 if (pla) {
9cd883f0
QT		 5110 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5111 u16 wd3_lo;
5112
5113 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5114 fcport->local = 0;
5115 fcport->loop_id =
5116 le16_to_cpu(
5117 pla->iocb.u.isp24.nport_handle);
5118 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5119 wd3_lo =
5120 le16_to_cpu(
5121 pla->iocb.u.isp24.u.prli.wd3_lo);
5122
5123 if (wd3_lo & BIT_7)
5124 fcport->conf_compl_supported = 1;
5125
5126 if ((wd3_lo & BIT_4) == 0)
5127 fcport->port_type = FCT_INITIATOR;
5128 else
5129 fcport->port_type = FCT_TARGET;
5130 }
726b8548 5131 qlt_plogi_ack_unref(vha, pla);
5ef696aa 5132 } else {
1c6cacf4
HR		 5133 fc_port_t *dfcp = NULL;
5134
5ef696aa
QT		 5135 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5136 tfcp = qla2x00_find_fcport_by_nportid(vha,
5137 &e->u.new_sess.id, 1);
5138 if (tfcp && (tfcp != fcport)) {
5139 /*
5140 * We have a conflict fcport with same NportID.
5141 */
5142 ql_dbg(ql_dbg_disc, vha, 0xffff,
5143 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5144 __func__, tfcp->port_name, tfcp->disc_state,
5145 tfcp->fw_login_state);
5146
5147 switch (tfcp->disc_state) {
5148 case DSC_DELETED:
5149 break;
5150 case DSC_DELETE_PEND:
5151 fcport->login_pause = 1;
5152 tfcp->conflict = fcport;
5153 break;
5154 default:
5155 fcport->login_pause = 1;
5156 tfcp->conflict = fcport;
1c6cacf4 5157 dfcp = tfcp;
5ef696aa
QT		 5158 break;
5159 }
5160 }
5161 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 5162 if (dfcp)
5163 qlt_schedule_sess_for_deletion(tfcp);
a4239945 5164
a4239945 5165
8777e431
QT		 5166 if (N2N_TOPO(vha->hw))
5167 fcport->flags &= ~FCF_FABRIC_DEVICE;
5168
5169 if (N2N_TOPO(vha->hw)) {
5170 if (vha->flags.nvme_enabled) {
5171 fcport->fc4f_nvme = 1;
5172 fcport->n2n_flag = 1;
5173 }
5174 fcport->fw_login_state = 0;
5175 /*
5176 * wait link init done before sending login
5177 */
5178 } else {
5179 qla24xx_fcport_handle_login(vha, fcport);
5180 }
5ef696aa 5181 }
726b8548 5182 }
b5d15312
QT		 5183
5184 if (free_fcport) {
5185 qla2x00_free_fcport(fcport);
1df627b4
BVA		 5186 if (pla) {
5187 list_del(&pla->list);
b5d15312 5188 kmem_cache_free(qla_tgt_plogi_cachep, pla);
1df627b4 5189 }
b5d15312 5190 }
726b8548
QT		 5191}
5192
e374f9f5
QT		 5193static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5194{
5195 struct srb *sp = e->u.iosb.sp;
5196 int rval;
5197
5198 rval = qla2x00_start_sp(sp);
5199 if (rval != QLA_SUCCESS) {
5200 ql_dbg(ql_dbg_disc, vha, 0x2043,
5201 "%s: %s: Re-issue IOCB failed (%d).\n",
5202 __func__, sp->name, rval);
5203 qla24xx_sp_unmap(vha, sp);
5204 }
5205}
5206
ac280b67 5207void
e315cd28 5208qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 5209{
f999f4c1
AV		 5210 struct qla_work_evt *e, *tmp;
5211 unsigned long flags;
5212 LIST_HEAD(work);
80676d05 5213 int rc;
0971de7f 5214
f999f4c1
AV		 5215 spin_lock_irqsave(&vha->work_lock, flags);
5216 list_splice_init(&vha->work_list, &work);
5217 spin_unlock_irqrestore(&vha->work_lock, flags);
5218
5219 list_for_each_entry_safe(e, tmp, &work, list) {
80676d05 5220 rc = QLA_SUCCESS;
0971de7f
AV		 5221 switch (e->type) {
5222 case QLA_EVT_AEN:
e315cd28 5223 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 5224 e->u.aen.code, e->u.aen.data);
5225 break;
8a659571
AV		 5226 case QLA_EVT_IDC_ACK:
5227 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5228 break;
ac280b67
AV		 5229 case QLA_EVT_ASYNC_LOGIN:
5230 qla2x00_async_login(vha, e->u.logio.fcport,
5231 e->u.logio.data);
5232 break;
ac280b67 5233 case QLA_EVT_ASYNC_LOGOUT:
80676d05 5234 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
ac280b67
AV		 5235 break;
5236 case QLA_EVT_ASYNC_LOGOUT_DONE:
5237 qla2x00_async_logout_done(vha, e->u.logio.fcport,
5238 e->u.logio.data);
5239 break;
5ff1d584
AV		 5240 case QLA_EVT_ASYNC_ADISC:
5241 qla2x00_async_adisc(vha, e->u.logio.fcport,
5242 e->u.logio.data);
5243 break;
3420d36c
AV		 5244 case QLA_EVT_UEVENT:
5245 qla2x00_uevent_emit(vha, e->u.uevent.code);
5246 break;
8ae6d9c7
GM		 5247 case QLA_EVT_AENFX:
5248 qlafx00_process_aen(vha, e);
5249 break;
726b8548
QT		 5250 case QLA_EVT_GPNID:
5251 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5252 break;
e374f9f5
QT		 5253 case QLA_EVT_UNMAP:
5254 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5255 break;
9b3e0f4d
QT		 5256 case QLA_EVT_RELOGIN:
5257 qla2x00_relogin(vha);
5258 break;
726b8548
QT		 5259 case QLA_EVT_NEW_SESS:
5260 qla24xx_create_new_sess(vha, e);
5261 break;
5262 case QLA_EVT_GPDB:
5263 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5264 e->u.fcport.opt);
5265 break;
a5d42f4c
DG		 5266 case QLA_EVT_PRLI:
5267 qla24xx_async_prli(vha, e->u.fcport.fcport);
5268 break;
726b8548
QT		 5269 case QLA_EVT_GPSC:
5270 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5271 break;
726b8548
QT		 5272 case QLA_EVT_GNL:
5273 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5274 break;
5275 case QLA_EVT_NACK:
5276 qla24xx_do_nack_work(vha, e);
5277 break;
11aea16a 5278 case QLA_EVT_ASYNC_PRLO:
80676d05 5279 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
11aea16a
QT		 5280 break;
5281 case QLA_EVT_ASYNC_PRLO_DONE:
5282 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5283 e->u.logio.data);
5284 break;
a4239945 5285 case QLA_EVT_GPNFT:
33b28357
QT		 5286 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5287 e->u.gpnft.sp);
a4239945
QT		 5288 break;
5289 case QLA_EVT_GPNFT_DONE:
5290 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5291 break;
5292 case QLA_EVT_GNNFT_DONE:
5293 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5294 break;
5295 case QLA_EVT_GNNID:
5296 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5297 break;
5298 case QLA_EVT_GFPNID:
5299 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5300 break;
e374f9f5
QT		 5301 case QLA_EVT_SP_RETRY:
5302 qla_sp_retry(vha, e);
cc28e0ac
QT		 5303 break;
5304 case QLA_EVT_IIDMA:
5305 qla_do_iidma_work(vha, e->u.fcport.fcport);
5306 break;
8777e431
QT		 5307 case QLA_EVT_ELS_PLOGI:
5308 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5309 e->u.fcport.fcport, false);
5310 break;
0971de7f 5311 }
80676d05
QT		 5312
5313 if (rc == EAGAIN) {
5314 /* put 'work' at head of 'vha->work_list' */
5315 spin_lock_irqsave(&vha->work_lock, flags);
5316 list_splice(&work, &vha->work_list);
5317 spin_unlock_irqrestore(&vha->work_lock, flags);
5318 break;
5319 }
5320 list_del_init(&e->list);
0971de7f
AV		 5321 if (e->flags & QLA_EVT_FLAG_FREE)
5322 kfree(e);
feafb7b1
AE		 5323
5324 /* For each work completed decrement vha ref count */
5325 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5326 }
e315cd28 5327}
f999f4c1 5328
9b3e0f4d
QT		 5329int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5330{
5331 struct qla_work_evt *e;
5332
5333 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5334
5335 if (!e) {
5336 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5337 return QLA_FUNCTION_FAILED;
5338 }
5339
5340 return qla2x00_post_work(vha, e);
5341}
5342
e315cd28
AC		 5343/* Relogins all the fcports of a vport
5344 * Context: dpc thread
5345 */
5346void qla2x00_relogin(struct scsi_qla_host *vha)
5347{
5348 fc_port_t *fcport;
23dd98a6 5349 int status, relogin_needed = 0;
726b8548 5350 struct event_arg ea;
e315cd28
AC		 5351
5352 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5353 /*
5354 * If the port is not ONLINE then try to login
5355 * to it if we haven't run out of retries.
5356 */
5ff1d584 5357 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5358 fcport->login_retry) {
5359 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5360 fcport->disc_state == DSC_LOGIN_COMPLETE)
5361 continue;
e315cd28 5362
23dd98a6
QT		 5363 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5364 fcport->disc_state == DSC_DELETE_PEND) {
5365 relogin_needed = 1;
5366 } else {
5367 if (vha->hw->current_topology != ISP_CFG_NL) {
5368 memset(&ea, 0, sizeof(ea));
5369 ea.event = FCME_RELOGIN;
5370 ea.fcport = fcport;
5371 qla2x00_fcport_event_handler(vha, &ea);
5372 } else if (vha->hw->current_topology ==
5373 ISP_CFG_NL) {
5374 fcport->login_retry--;
5375 status =
5376 qla2x00_local_device_login(vha,
5377 fcport);
5378 if (status == QLA_SUCCESS) {
5379 fcport->old_loop_id =
5380 fcport->loop_id;
5381 ql_dbg(ql_dbg_disc, vha, 0x2003,
5382 "Port login OK: logged in ID 0x%x.\n",
5383 fcport->loop_id);
5384 qla2x00_update_fcport
5385 (vha, fcport);
5386 } else if (status == 1) {
5387 set_bit(RELOGIN_NEEDED,
5388 &vha->dpc_flags);
5389 /* retry the login again */
5390 ql_dbg(ql_dbg_disc, vha, 0x2007,
5391 "Retrying %d login again loop_id 0x%x.\n",
5392 fcport->login_retry,
5393 fcport->loop_id);
5394 } else {
5395 fcport->login_retry = 0;
5396 }
e315cd28 5397
23dd98a6
QT		 5398 if (fcport->login_retry == 0 &&
5399 status != QLA_SUCCESS)
5400 qla2x00_clear_loop_id(fcport);
5401 }
e315cd28 5402 }
e315cd28
AC		 5403 }
5404 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5405 break;
0971de7f 5406 }
9b3e0f4d 5407
23dd98a6
QT		 5408 if (relogin_needed)
5409 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5410
9b3e0f4d
QT		 5411 ql_dbg(ql_dbg_disc, vha, 0x400e,
5412 "Relogin end.\n");
0971de7f
AV		 5413}
5414
7d613ac6
SV		 5415/* Schedule work on any of the dpc-workqueues */
5416void
5417qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5418{
5419 struct qla_hw_data *ha = base_vha->hw;
5420
5421 switch (work_code) {
5422 case MBA_IDC_AEN: /* 0x8200 */
5423 if (ha->dpc_lp_wq)
5424 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5425 break;
5426
5427 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5428 if (!ha->flags.nic_core_reset_hdlr_active) {
5429 if (ha->dpc_hp_wq)
5430 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5431 } else
5432 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5433 "NIC Core reset is already active. Skip "
5434 "scheduling it again.\n");
5435 break;
5436 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5437 if (ha->dpc_hp_wq)
5438 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5439 break;
5440 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5441 if (ha->dpc_hp_wq)
5442 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5443 break;
5444 default:
5445 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5446 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5447 }
5448
5449 return;
5450}
5451
5452/* Work: Perform NIC Core Unrecoverable state handling */
5453void
5454qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5455{
5456 struct qla_hw_data *ha =
2ad1b67c 5457 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5458 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5459 uint32_t dev_state = 0;
5460
5461 qla83xx_idc_lock(base_vha, 0);
5462 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5463 qla83xx_reset_ownership(base_vha);
5464 if (ha->flags.nic_core_reset_owner) {
5465 ha->flags.nic_core_reset_owner = 0;
5466 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5467 QLA8XXX_DEV_FAILED);
5468 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5469 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5470 }
5471 qla83xx_idc_unlock(base_vha, 0);
5472}
5473
5474/* Work: Execute IDC state handler */
5475void
5476qla83xx_idc_state_handler_work(struct work_struct *work)
5477{
5478 struct qla_hw_data *ha =
2ad1b67c 5479 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5480 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5481 uint32_t dev_state = 0;
5482
5483 qla83xx_idc_lock(base_vha, 0);
5484 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5485 if (dev_state == QLA8XXX_DEV_FAILED ||
5486 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5487 qla83xx_idc_state_handler(base_vha);
5488 qla83xx_idc_unlock(base_vha, 0);
5489}
5490
fa492630 5491static int
7d613ac6
SV		 5492qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5493{
5494 int rval = QLA_SUCCESS;
5495 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5496 uint32_t heart_beat_counter1, heart_beat_counter2;
5497
5498 do {
5499 if (time_after(jiffies, heart_beat_wait)) {
5500 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5501 "Nic Core f/w is not alive.\n");
5502 rval = QLA_FUNCTION_FAILED;
5503 break;
5504 }
5505
5506 qla83xx_idc_lock(base_vha, 0);
5507 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5508 &heart_beat_counter1);
5509 qla83xx_idc_unlock(base_vha, 0);
5510 msleep(100);
5511 qla83xx_idc_lock(base_vha, 0);
5512 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5513 &heart_beat_counter2);
5514 qla83xx_idc_unlock(base_vha, 0);
5515 } while (heart_beat_counter1 == heart_beat_counter2);
5516
5517 return rval;
5518}
5519
5520/* Work: Perform NIC Core Reset handling */
5521void
5522qla83xx_nic_core_reset_work(struct work_struct *work)
5523{
5524 struct qla_hw_data *ha =
5525 container_of(work, struct qla_hw_data, nic_core_reset);
5526 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5527 uint32_t dev_state = 0;
5528
81178772
SK		 5529 if (IS_QLA2031(ha)) {
5530 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5531 ql_log(ql_log_warn, base_vha, 0xb081,
5532 "Failed to dump mctp\n");
5533 return;
5534 }
5535
7d613ac6
SV		 5536 if (!ha->flags.nic_core_reset_hdlr_active) {
5537 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5538 qla83xx_idc_lock(base_vha, 0);
5539 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5540 &dev_state);
5541 qla83xx_idc_unlock(base_vha, 0);
5542 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5543 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5544 "Nic Core f/w is alive.\n");
5545 return;
5546 }
5547 }
5548
5549 ha->flags.nic_core_reset_hdlr_active = 1;
5550 if (qla83xx_nic_core_reset(base_vha)) {
5551 /* NIC Core reset failed. */
5552 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5553 "NIC Core reset failed.\n");
5554 }
5555 ha->flags.nic_core_reset_hdlr_active = 0;
5556 }
5557}
5558
5559/* Work: Handle 8200 IDC aens */
5560void
5561qla83xx_service_idc_aen(struct work_struct *work)
5562{
5563 struct qla_hw_data *ha =
5564 container_of(work, struct qla_hw_data, idc_aen);
5565 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5566 uint32_t dev_state, idc_control;
5567
5568 qla83xx_idc_lock(base_vha, 0);
5569 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5570 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5571 qla83xx_idc_unlock(base_vha, 0);
5572 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5573 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5574 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5575 "Application requested NIC Core Reset.\n");
5576 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5577 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5578 QLA_SUCCESS) {
5579 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5580 "Other protocol driver requested NIC Core Reset.\n");
5581 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5582 }
5583 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5584 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5585 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5586 }
5587}
5588
5589static void
5590qla83xx_wait_logic(void)
5591{
5592 int i;
5593
5594 /* Yield CPU */
5595 if (!in_interrupt()) {
5596 /*
5597 * Wait about 200ms before retrying again.
5598 * This controls the number of retries for single
5599 * lock operation.
5600 */
5601 msleep(100);
5602 schedule();
5603 } else {
5604 for (i = 0; i < 20; i++)
5605 cpu_relax(); /* This a nop instr on i386 */
5606 }
5607}
5608
fa492630 5609static int
7d613ac6
SV		 5610qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5611{
5612 int rval;
5613 uint32_t data;
5614 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5615 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5616 struct qla_hw_data *ha = base_vha->hw;
bd432bb5 5617
6c315553
SK		 5618 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5619 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5620
5621 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5622 if (rval)
5623 return rval;
5624
5625 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5626 return QLA_SUCCESS;
5627 } else {
5628 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5629 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5630 data);
5631 if (rval)
5632 return rval;
5633
5634 msleep(200);
5635
5636 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5637 &data);
5638 if (rval)
5639 return rval;
5640
5641 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5642 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5643 ~(idc_lck_rcvry_stage_mask));
5644 rval = qla83xx_wr_reg(base_vha,
5645 QLA83XX_IDC_LOCK_RECOVERY, data);
5646 if (rval)
5647 return rval;
5648
5649 /* Forcefully perform IDC UnLock */
5650 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5651 &data);
5652 if (rval)
5653 return rval;
5654 /* Clear lock-id by setting 0xff */
5655 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5656 0xff);
5657 if (rval)
5658 return rval;
5659 /* Clear lock-recovery by setting 0x0 */
5660 rval = qla83xx_wr_reg(base_vha,
5661 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5662 if (rval)
5663 return rval;
5664 } else
5665 return QLA_SUCCESS;
5666 }
5667
5668 return rval;
5669}
5670
fa492630 5671static int
7d613ac6
SV		 5672qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5673{
5674 int rval = QLA_SUCCESS;
5675 uint32_t o_drv_lockid, n_drv_lockid;
5676 unsigned long lock_recovery_timeout;
5677
5678 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5679retry_lockid:
5680 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5681 if (rval)
5682 goto exit;
5683
5684 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5685 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5686 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5687 return QLA_SUCCESS;
5688 else
5689 return QLA_FUNCTION_FAILED;
5690 }
5691
5692 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5693 if (rval)
5694 goto exit;
5695
5696 if (o_drv_lockid == n_drv_lockid) {
5697 qla83xx_wait_logic();
5698 goto retry_lockid;
5699 } else
5700 return QLA_SUCCESS;
5701
5702exit:
5703 return rval;
5704}
5705
5706void
5707qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5708{
7d613ac6 5709 uint32_t data;
6c315553 5710 uint32_t lock_owner;
7d613ac6
SV		 5711 struct qla_hw_data *ha = base_vha->hw;
5712
5713 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5714retry_lock:
5715 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5716 == QLA_SUCCESS) {
5717 if (data) {
5718 /* Setting lock-id to our function-number */
5719 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5720 ha->portnum);
5721 } else {
6c315553
SK		 5722 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5723 &lock_owner);
7d613ac6 5724 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5725 "Failed to acquire IDC lock, acquired by %d, "
5726 "retrying...\n", lock_owner);
7d613ac6
SV		 5727
5728 /* Retry/Perform IDC-Lock recovery */
5729 if (qla83xx_idc_lock_recovery(base_vha)
5730 == QLA_SUCCESS) {
5731 qla83xx_wait_logic();
5732 goto retry_lock;
5733 } else
5734 ql_log(ql_log_warn, base_vha, 0xb075,
5735 "IDC Lock recovery FAILED.\n");
5736 }
5737
5738 }
5739
5740 return;
7d613ac6
SV		 5741}
5742
5743void
5744qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5745{
5897cb2f
BVA		 5746#if 0
5747 uint16_t options = (requester_id << 15) | BIT_7;
5748#endif
5749 uint16_t retry;
7d613ac6
SV		 5750 uint32_t data;
5751 struct qla_hw_data *ha = base_vha->hw;
5752
5753 /* IDC-unlock implementation using driver-unlock/lock-id
5754 * remote registers
5755 */
5756 retry = 0;
5757retry_unlock:
5758 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5759 == QLA_SUCCESS) {
5760 if (data == ha->portnum) {
5761 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5762 /* Clearing lock-id by setting 0xff */
5763 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5764 } else if (retry < 10) {
5765 /* SV: XXX: IDC unlock retrying needed here? */
5766
5767 /* Retry for IDC-unlock */
5768 qla83xx_wait_logic();
5769 retry++;
5770 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5771 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5772 goto retry_unlock;
5773 }
5774 } else if (retry < 10) {
5775 /* Retry for IDC-unlock */
5776 qla83xx_wait_logic();
5777 retry++;
5778 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5779 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5780 goto retry_unlock;
5781 }
5782
5783 return;
5784
5897cb2f 5785#if 0
7d613ac6
SV		 5786 /* XXX: IDC-unlock implementation using access-control mbx */
5787 retry = 0;
5788retry_unlock2:
5789 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5790 if (retry < 10) {
5791 /* Retry for IDC-unlock */
5792 qla83xx_wait_logic();
5793 retry++;
5794 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5795 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5796 goto retry_unlock2;
5797 }
5798 }
5799
5800 return;
5897cb2f 5801#endif
7d613ac6
SV		 5802}
5803
5804int
5805__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5806{
5807 int rval = QLA_SUCCESS;
5808 struct qla_hw_data *ha = vha->hw;
5809 uint32_t drv_presence;
5810
5811 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5812 if (rval == QLA_SUCCESS) {
5813 drv_presence |= (1 << ha->portnum);
5814 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5815 drv_presence);
5816 }
5817
5818 return rval;
5819}
5820
5821int
5822qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5823{
5824 int rval = QLA_SUCCESS;
5825
5826 qla83xx_idc_lock(vha, 0);
5827 rval = __qla83xx_set_drv_presence(vha);
5828 qla83xx_idc_unlock(vha, 0);
5829
5830 return rval;
5831}
5832
5833int
5834__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5835{
5836 int rval = QLA_SUCCESS;
5837 struct qla_hw_data *ha = vha->hw;
5838 uint32_t drv_presence;
5839
5840 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5841 if (rval == QLA_SUCCESS) {
5842 drv_presence &= ~(1 << ha->portnum);
5843 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5844 drv_presence);
5845 }
5846
5847 return rval;
5848}
5849
5850int
5851qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5852{
5853 int rval = QLA_SUCCESS;
5854
5855 qla83xx_idc_lock(vha, 0);
5856 rval = __qla83xx_clear_drv_presence(vha);
5857 qla83xx_idc_unlock(vha, 0);
5858
5859 return rval;
5860}
5861
fa492630 5862static void
7d613ac6
SV		 5863qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5864{
5865 struct qla_hw_data *ha = vha->hw;
5866 uint32_t drv_ack, drv_presence;
5867 unsigned long ack_timeout;
5868
5869 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5870 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5871 while (1) {
5872 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5873 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5874 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5875 break;
5876
5877 if (time_after_eq(jiffies, ack_timeout)) {
5878 ql_log(ql_log_warn, vha, 0xb067,
5879 "RESET ACK TIMEOUT! drv_presence=0x%x "
5880 "drv_ack=0x%x\n", drv_presence, drv_ack);
5881 /*
5882 * The function(s) which did not ack in time are forced
5883 * to withdraw any further participation in the IDC
5884 * reset.
5885 */
5886 if (drv_ack != drv_presence)
5887 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5888 drv_ack);
5889 break;
5890 }
5891
5892 qla83xx_idc_unlock(vha, 0);
5893 msleep(1000);
5894 qla83xx_idc_lock(vha, 0);
5895 }
5896
5897 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5898 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5899}
5900
fa492630 5901static int
7d613ac6
SV		 5902qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5903{
5904 int rval = QLA_SUCCESS;
5905 uint32_t idc_control;
5906
5907 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5908 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5909
5910 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5911 __qla83xx_get_idc_control(vha, &idc_control);
5912 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5913 __qla83xx_set_idc_control(vha, 0);
5914
5915 qla83xx_idc_unlock(vha, 0);
5916 rval = qla83xx_restart_nic_firmware(vha);
5917 qla83xx_idc_lock(vha, 0);
5918
5919 if (rval != QLA_SUCCESS) {
5920 ql_log(ql_log_fatal, vha, 0xb06a,
5921 "Failed to restart NIC f/w.\n");
5922 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5923 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5924 } else {
5925 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5926 "Success in restarting nic f/w.\n");
5927 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5928 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5929 }
5930
5931 return rval;
5932}
5933
5934/* Assumes idc_lock always held on entry */
5935int
5936qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5937{
5938 struct qla_hw_data *ha = base_vha->hw;
5939 int rval = QLA_SUCCESS;
5940 unsigned long dev_init_timeout;
5941 uint32_t dev_state;
5942
5943 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5944 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5945
5946 while (1) {
5947
5948 if (time_after_eq(jiffies, dev_init_timeout)) {
5949 ql_log(ql_log_warn, base_vha, 0xb06e,
5950 "Initialization TIMEOUT!\n");
5951 /* Init timeout. Disable further NIC Core
5952 * communication.
5953 */
5954 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5955 QLA8XXX_DEV_FAILED);
5956 ql_log(ql_log_info, base_vha, 0xb06f,
5957 "HW State: FAILED.\n");
5958 }
5959
5960 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5961 switch (dev_state) {
5962 case QLA8XXX_DEV_READY:
5963 if (ha->flags.nic_core_reset_owner)
5964 qla83xx_idc_audit(base_vha,
5965 IDC_AUDIT_COMPLETION);
5966 ha->flags.nic_core_reset_owner = 0;
5967 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5968 "Reset_owner reset by 0x%x.\n",
5969 ha->portnum);
5970 goto exit;
5971 case QLA8XXX_DEV_COLD:
5972 if (ha->flags.nic_core_reset_owner)
5973 rval = qla83xx_device_bootstrap(base_vha);
5974 else {
5975 /* Wait for AEN to change device-state */
5976 qla83xx_idc_unlock(base_vha, 0);
5977 msleep(1000);
5978 qla83xx_idc_lock(base_vha, 0);
5979 }
5980 break;
5981 case QLA8XXX_DEV_INITIALIZING:
5982 /* Wait for AEN to change device-state */
5983 qla83xx_idc_unlock(base_vha, 0);
5984 msleep(1000);
5985 qla83xx_idc_lock(base_vha, 0);
5986 break;
5987 case QLA8XXX_DEV_NEED_RESET:
5988 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5989 qla83xx_need_reset_handler(base_vha);
5990 else {
5991 /* Wait for AEN to change device-state */
5992 qla83xx_idc_unlock(base_vha, 0);
5993 msleep(1000);
5994 qla83xx_idc_lock(base_vha, 0);
5995 }
5996 /* reset timeout value after need reset handler */
5997 dev_init_timeout = jiffies +
5998 (ha->fcoe_dev_init_timeout * HZ);
5999 break;
6000 case QLA8XXX_DEV_NEED_QUIESCENT:
6001 /* XXX: DEBUG for now */
6002 qla83xx_idc_unlock(base_vha, 0);
6003 msleep(1000);
6004 qla83xx_idc_lock(base_vha, 0);
6005 break;
6006 case QLA8XXX_DEV_QUIESCENT:
6007 /* XXX: DEBUG for now */
6008 if (ha->flags.quiesce_owner)
6009 goto exit;
6010
6011 qla83xx_idc_unlock(base_vha, 0);
6012 msleep(1000);
6013 qla83xx_idc_lock(base_vha, 0);
6014 dev_init_timeout = jiffies +
6015 (ha->fcoe_dev_init_timeout * HZ);
6016 break;
6017 case QLA8XXX_DEV_FAILED:
6018 if (ha->flags.nic_core_reset_owner)
6019 qla83xx_idc_audit(base_vha,
6020 IDC_AUDIT_COMPLETION);
6021 ha->flags.nic_core_reset_owner = 0;
6022 __qla83xx_clear_drv_presence(base_vha);
6023 qla83xx_idc_unlock(base_vha, 0);
6024 qla8xxx_dev_failed_handler(base_vha);
6025 rval = QLA_FUNCTION_FAILED;
6026 qla83xx_idc_lock(base_vha, 0);
6027 goto exit;
6028 case QLA8XXX_BAD_VALUE:
6029 qla83xx_idc_unlock(base_vha, 0);
6030 msleep(1000);
6031 qla83xx_idc_lock(base_vha, 0);
6032 break;
6033 default:
6034 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 6035 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 6036 qla83xx_idc_unlock(base_vha, 0);
6037 qla8xxx_dev_failed_handler(base_vha);
6038 rval = QLA_FUNCTION_FAILED;
6039 qla83xx_idc_lock(base_vha, 0);
6040 goto exit;
6041 }
6042 }
6043
6044exit:
6045 return rval;
6046}
6047
f3ddac19
CD		 6048void
6049qla2x00_disable_board_on_pci_error(struct work_struct *work)
6050{
6051 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6052 board_disable);
6053 struct pci_dev *pdev = ha->pdev;
6054 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6055
726b8548
QT		 6056 /*
6057 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 6058 * where it was set first.
6059 */
6060 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6061 return;
6062
f3ddac19
CD		 6063 ql_log(ql_log_warn, base_vha, 0x015b,
6064 "Disabling adapter.\n");
6065
efdb5760
SC		 6066 if (!atomic_read(&pdev->enable_cnt)) {
6067 ql_log(ql_log_info, base_vha, 0xfffc,
6068 "PCI device disabled, no action req for PCI error=%lx\n",
6069 base_vha->pci_flags);
6070 return;
6071 }
6072
726b8548
QT		 6073 qla2x00_wait_for_sess_deletion(base_vha);
6074
f3ddac19
CD		 6075 set_bit(UNLOADING, &base_vha->dpc_flags);
6076
6077 qla2x00_delete_all_vps(ha, base_vha);
6078
6079 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6080
6081 qla2x00_dfs_remove(base_vha);
6082
6083 qla84xx_put_chip(base_vha);
6084
6085 if (base_vha->timer_active)
6086 qla2x00_stop_timer(base_vha);
6087
6088 base_vha->flags.online = 0;
6089
6090 qla2x00_destroy_deferred_work(ha);
6091
6092 /*
6093 * Do not try to stop beacon blink as it will issue a mailbox
6094 * command.
6095 */
6096 qla2x00_free_sysfs_attr(base_vha, false);
6097
6098 fc_remove_host(base_vha->host);
6099
6100 scsi_remove_host(base_vha->host);
6101
6102 base_vha->flags.init_done = 0;
6103 qla25xx_delete_queues(base_vha);
f3ddac19 6104 qla2x00_free_fcports(base_vha);
093df737 6105 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 6106 qla2x00_mem_free(ha);
6107 qla82xx_md_free(base_vha);
6108 qla2x00_free_queues(ha);
6109
f3ddac19
CD		 6110 qla2x00_unmap_iobases(ha);
6111
6112 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 6113 pci_disable_pcie_error_reporting(pdev);
6114 pci_disable_device(pdev);
f3ddac19 6115
beb9e315
JL		 6116 /*
6117 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6118 */
f3ddac19
CD		 6119}
6120
1da177e4
LT		 6121/**************************************************************************
6122* qla2x00_do_dpc
6123* This kernel thread is a task that is schedule by the interrupt handler
6124* to perform the background processing for interrupts.
6125*
6126* Notes:
6127* This task always run in the context of a kernel thread. It
6128* is kick-off by the driver's detect code and starts up
6129* up one per adapter. It immediately goes to sleep and waits for
6130* some fibre event. When either the interrupt handler or
6131* the timer routine detects a event it will one of the task
6132* bits then wake us up.
6133**************************************************************************/
6134static int
6135qla2x00_do_dpc(void *data)
6136{
e315cd28
AC		 6137 scsi_qla_host_t *base_vha;
6138 struct qla_hw_data *ha;
d7459527
MH		 6139 uint32_t online;
6140 struct qla_qpair *qpair;
1da177e4 6141
e315cd28
AC		 6142 ha = (struct qla_hw_data *)data;
6143 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 6144
8698a745 6145 set_user_nice(current, MIN_NICE);
1da177e4 6146
563585ec 6147 set_current_state(TASK_INTERRUPTIBLE);
39a11240 6148 while (!kthread_should_stop()) {
7c3df132
SK		 6149 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6150 "DPC handler sleeping.\n");
1da177e4 6151
39a11240 6152 schedule();
1da177e4 6153
c142caf0
AV		 6154 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6155 goto end_loop;
1da177e4 6156
85880801 6157 if (ha->flags.eeh_busy) {
7c3df132
SK		 6158 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6159 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 6160 goto end_loop;
85880801
AV		 6161 }
6162
1da177e4
LT		 6163 ha->dpc_active = 1;
6164
5f28d2d7
SK		 6165 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6166 "DPC handler waking up, dpc_flags=0x%lx.\n",
6167 base_vha->dpc_flags);
1da177e4 6168
a29b3dd7
JC		 6169 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6170 break;
6171
7ec0effd
AD		 6172 if (IS_P3P_TYPE(ha)) {
6173 if (IS_QLA8044(ha)) {
6174 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6175 &base_vha->dpc_flags)) {
6176 qla8044_idc_lock(ha);
6177 qla8044_wr_direct(base_vha,
6178 QLA8044_CRB_DEV_STATE_INDEX,
6179 QLA8XXX_DEV_FAILED);
6180 qla8044_idc_unlock(ha);
6181 ql_log(ql_log_info, base_vha, 0x4004,
6182 "HW State: FAILED.\n");
6183 qla8044_device_state_handler(base_vha);
6184 continue;
6185 }
6186
6187 } else {
6188 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6189 &base_vha->dpc_flags)) {
6190 qla82xx_idc_lock(ha);
6191 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6192 QLA8XXX_DEV_FAILED);
6193 qla82xx_idc_unlock(ha);
6194 ql_log(ql_log_info, base_vha, 0x0151,
6195 "HW State: FAILED.\n");
6196 qla82xx_device_state_handler(base_vha);
6197 continue;
6198 }
a9083016
GM		 6199 }
6200
6201 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6202 &base_vha->dpc_flags)) {
6203
7c3df132
SK		 6204 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6205 "FCoE context reset scheduled.\n");
a9083016
GM		 6206 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6207 &base_vha->dpc_flags))) {
6208 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6209 /* FCoE-ctx reset failed.
6210 * Escalate to chip-reset
6211 */
6212 set_bit(ISP_ABORT_NEEDED,
6213 &base_vha->dpc_flags);
6214 }
6215 clear_bit(ABORT_ISP_ACTIVE,
6216 &base_vha->dpc_flags);
6217 }
6218
7c3df132
SK		 6219 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6220 "FCoE context reset end.\n");
a9083016 6221 }
8ae6d9c7
GM		 6222 } else if (IS_QLAFX00(ha)) {
6223 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6224 &base_vha->dpc_flags)) {
6225 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6226 "Firmware Reset Recovery\n");
6227 if (qlafx00_reset_initialize(base_vha)) {
6228 /* Failed. Abort isp later. */
6229 if (!test_bit(UNLOADING,
f92f82d6 6230 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 6231 set_bit(ISP_UNRECOVERABLE,
6232 &base_vha->dpc_flags);
6233 ql_dbg(ql_dbg_dpc, base_vha,
6234 0x4021,
6235 "Reset Recovery Failed\n");
f92f82d6 6236 }
8ae6d9c7
GM		 6237 }
6238 }
6239
6240 if (test_and_clear_bit(FX00_TARGET_SCAN,
6241 &base_vha->dpc_flags)) {
6242 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6243 "ISPFx00 Target Scan scheduled\n");
6244 if (qlafx00_rescan_isp(base_vha)) {
6245 if (!test_bit(UNLOADING,
6246 &base_vha->dpc_flags))
6247 set_bit(ISP_UNRECOVERABLE,
6248 &base_vha->dpc_flags);
6249 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6250 "ISPFx00 Target Scan Failed\n");
6251 }
6252 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6253 "ISPFx00 Target Scan End\n");
6254 }
e8f5e95d
AB		 6255 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6256 &base_vha->dpc_flags)) {
6257 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6258 "ISPFx00 Host Info resend scheduled\n");
6259 qlafx00_fx_disc(base_vha,
6260 &base_vha->hw->mr.fcport,
6261 FXDISC_REG_HOST_INFO);
6262 }
a9083016
GM		 6263 }
6264
e4e3a2ce
QT		 6265 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6266 &base_vha->dpc_flags) &&
6267 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6268 qla24xx_detect_sfp(base_vha);
6269
6270 if (ha->flags.detected_lr_sfp !=
6271 ha->flags.using_lr_setting)
6272 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6273 }
6274
b08abbd9
QT		 6275 if (test_and_clear_bit
6276 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6277 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
93eca613
QT		 6278 bool do_reset = true;
6279
0645cb83 6280 switch (base_vha->qlini_mode) {
93eca613
QT		 6281 case QLA2XXX_INI_MODE_ENABLED:
6282 break;
6283 case QLA2XXX_INI_MODE_DISABLED:
0645cb83
QT		 6284 if (!qla_tgt_mode_enabled(base_vha) &&
6285 !ha->flags.fw_started)
93eca613
QT		 6286 do_reset = false;
6287 break;
6288 case QLA2XXX_INI_MODE_DUAL:
0645cb83
QT		 6289 if (!qla_dual_mode_enabled(base_vha) &&
6290 !ha->flags.fw_started)
93eca613
QT		 6291 do_reset = false;
6292 break;
6293 default:
6294 break;
6295 }
1da177e4 6296
93eca613 6297 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6298 &base_vha->dpc_flags))) {
93eca613
QT		 6299 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6300 "ISP abort scheduled.\n");
a9083016 6301 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6302 /* failed. retry later */
6303 set_bit(ISP_ABORT_NEEDED,
e315cd28 6304 &base_vha->dpc_flags);
99363ef8 6305 }
e315cd28
AC		 6306 clear_bit(ABORT_ISP_ACTIVE,
6307 &base_vha->dpc_flags);
93eca613
QT		 6308 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6309 "ISP abort end.\n");
99363ef8 6310 }
1da177e4
LT		 6311 }
6312
a394aac8
DJ		 6313 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6314 &base_vha->dpc_flags)) {
e315cd28 6315 qla2x00_update_fcports(base_vha);
c9c5ced9 6316 }
d97994dc 6317
8ae6d9c7
GM		 6318 if (IS_QLAFX00(ha))
6319 goto loop_resync_check;
6320
579d12b5 6321 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6322 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6323 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6324 if (IS_P3P_TYPE(ha)) {
6325 if (IS_QLA82XX(ha))
6326 qla82xx_device_state_handler(base_vha);
6327 if (IS_QLA8044(ha))
6328 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6329 clear_bit(ISP_QUIESCE_NEEDED,
6330 &base_vha->dpc_flags);
6331 if (!ha->flags.quiesce_owner) {
6332 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6333 if (IS_QLA82XX(ha)) {
6334 qla82xx_idc_lock(ha);
6335 qla82xx_clear_qsnt_ready(
6336 base_vha);
6337 qla82xx_idc_unlock(ha);
6338 } else if (IS_QLA8044(ha)) {
6339 qla8044_idc_lock(ha);
6340 qla8044_clear_qsnt_ready(
6341 base_vha);
6342 qla8044_idc_unlock(ha);
6343 }
8fcd6b8b
CD		 6344 }
6345 } else {
6346 clear_bit(ISP_QUIESCE_NEEDED,
6347 &base_vha->dpc_flags);
6348 qla2x00_quiesce_io(base_vha);
579d12b5 6349 }
7c3df132
SK		 6350 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6351 "Quiescence mode end.\n");
579d12b5
SK		 6352 }
6353
e315cd28 6354 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6355 &base_vha->dpc_flags) &&
e315cd28 6356 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6357
7c3df132
SK		 6358 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6359 "Reset marker scheduled.\n");
e315cd28
AC		 6360 qla2x00_rst_aen(base_vha);
6361 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6362 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6363 "Reset marker end.\n");
1da177e4
LT		 6364 }
6365
6366 /* Retry each device up to login retry count */
4005a995 6367 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6368 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6369 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6370
4005a995
QT		 6371 if (!base_vha->relogin_jif ||
6372 time_after_eq(jiffies, base_vha->relogin_jif)) {
6373 base_vha->relogin_jif = jiffies + HZ;
6374 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6375
9b3e0f4d 6376 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6377 "Relogin scheduled.\n");
9b3e0f4d 6378 qla24xx_post_relogin_work(base_vha);
4005a995 6379 }
1da177e4 6380 }
8ae6d9c7 6381loop_resync_check:
e315cd28 6382 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6383 &base_vha->dpc_flags)) {
1da177e4 6384
7c3df132
SK		 6385 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6386 "Loop resync scheduled.\n");
1da177e4
LT		 6387
6388 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6389 &base_vha->dpc_flags))) {
1da177e4 6390
52c82823 6391 qla2x00_loop_resync(base_vha);
1da177e4 6392
e315cd28
AC		 6393 clear_bit(LOOP_RESYNC_ACTIVE,
6394 &base_vha->dpc_flags);
1da177e4
LT		 6395 }
6396
7c3df132
SK		 6397 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6398 "Loop resync end.\n");
1da177e4
LT		 6399 }
6400
8ae6d9c7
GM		 6401 if (IS_QLAFX00(ha))
6402 goto intr_on_check;
6403
e315cd28
AC		 6404 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6405 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6406 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6407 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6408 }
6409
8ae6d9c7 6410intr_on_check:
1da177e4 6411 if (!ha->interrupts_on)
fd34f556 6412 ha->isp_ops->enable_intrs(ha);
1da177e4 6413
e315cd28 6414 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6415 &base_vha->dpc_flags)) {
6416 if (ha->beacon_blink_led == 1)
6417 ha->isp_ops->beacon_blink(base_vha);
6418 }
f6df144c 6419
d7459527
MH		 6420 /* qpair online check */
6421 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6422 &base_vha->dpc_flags)) {
6423 if (ha->flags.eeh_busy ||
6424 ha->flags.pci_channel_io_perm_failure)
6425 online = 0;
6426 else
6427 online = 1;
6428
6429 mutex_lock(&ha->mq_lock);
6430 list_for_each_entry(qpair, &base_vha->qp_list,
6431 qp_list_elem)
6432 qpair->online = online;
6433 mutex_unlock(&ha->mq_lock);
6434 }
6435
8b4673ba
QT		 6436 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6437 &base_vha->dpc_flags)) {
deeae7a6
DG		 6438 ql_log(ql_log_info, base_vha, 0xffffff,
6439 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6440 ha->nvme_last_rptd_aen);
8b4673ba
QT		 6441 if (qla27xx_set_zio_threshold(base_vha,
6442 ha->nvme_last_rptd_aen)) {
deeae7a6 6443 ql_log(ql_log_info, base_vha, 0xffffff,
8b4673ba
QT		 6444 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6445 ha->nvme_last_rptd_aen);
deeae7a6
DG		 6446 }
6447 }
6448
8b4673ba
QT		 6449 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6450 &base_vha->dpc_flags)) {
6451 ql_log(ql_log_info, base_vha, 0xffffff,
6452 "SET ZIO Activity exchange threshold to %d.\n",
6453 ha->last_zio_threshold);
6454 qla27xx_set_zio_threshold(base_vha,
6455 ha->last_zio_threshold);
6456 }
6457
8ae6d9c7
GM		 6458 if (!IS_QLAFX00(ha))
6459 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6460
48acad09
QT		 6461 if (test_and_clear_bit(N2N_LINK_RESET,
6462 &base_vha->dpc_flags)) {
6463 qla2x00_lip_reset(base_vha);
6464 }
6465
1da177e4 6466 ha->dpc_active = 0;
c142caf0 6467end_loop:
563585ec 6468 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6469 } /* End of while(1) */
563585ec 6470 __set_current_state(TASK_RUNNING);
1da177e4 6471
7c3df132
SK		 6472 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6473 "DPC handler exiting.\n");
1da177e4
LT		 6474
6475 /*
6476 * Make sure that nobody tries to wake us up again.
6477 */
1da177e4
LT		 6478 ha->dpc_active = 0;
6479
ac280b67
AV		 6480 /* Cleanup any residual CTX SRBs. */
6481 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6482
39a11240
CH		 6483 return 0;
6484}
6485
6486void
e315cd28 6487qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6488{
e315cd28 6489 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6490 struct task_struct *t = ha->dpc_thread;
6491
e315cd28 6492 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6493 wake_up_process(t);
1da177e4
LT		 6494}
6495
1da177e4
LT		 6496/*
6497* qla2x00_rst_aen
6498* Processes asynchronous reset.
6499*
6500* Input:
6501* ha = adapter block pointer.
6502*/
6503static void
e315cd28 6504qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6505{
e315cd28
AC		 6506 if (vha->flags.online && !vha->flags.reset_active &&
6507 !atomic_read(&vha->loop_down_timer) &&
6508 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6509 do {
e315cd28 6510 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6511
6512 /*
6513 * Issue marker command only when we are going to start
6514 * the I/O.
6515 */
e315cd28
AC		 6516 vha->marker_needed = 1;
6517 } while (!atomic_read(&vha->loop_down_timer) &&
6518 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6519 }
6520}
6521
1da177e4
LT		 6522/**************************************************************************
6523* qla2x00_timer
6524*
6525* Description:
6526* One second timer
6527*
6528* Context: Interrupt
6529***************************************************************************/
2c3dfe3f 6530void
8e5f4ba0 6531qla2x00_timer(struct timer_list *t)
1da177e4 6532{
8e5f4ba0 6533 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6534 unsigned long cpu_flags = 0;
1da177e4
LT		 6535 int start_dpc = 0;
6536 int index;
6537 srb_t *sp;
85880801 6538 uint16_t w;
e315cd28 6539 struct qla_hw_data *ha = vha->hw;
73208dfd 6540 struct req_que *req;
85880801 6541
a5b36321 6542 if (ha->flags.eeh_busy) {
7c3df132
SK		 6543 ql_dbg(ql_dbg_timer, vha, 0x6000,
6544 "EEH = %d, restarting timer.\n",
6545 ha->flags.eeh_busy);
a5b36321
LC		 6546 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6547 return;
6548 }
6549
f3ddac19
CD		 6550 /*
6551 * Hardware read to raise pending EEH errors during mailbox waits. If
6552 * the read returns -1 then disable the board.
6553 */
6554 if (!pci_channel_offline(ha->pdev)) {
85880801 6555 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6556 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6557 }
1da177e4 6558
cefcaba6 6559 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6560 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6561 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6562 start_dpc++;
7ec0effd
AD		 6563 if (IS_QLA82XX(ha))
6564 qla82xx_watchdog(vha);
6565 else if (IS_QLA8044(ha))
6566 qla8044_watchdog(vha);
579d12b5
SK		 6567 }
6568
8ae6d9c7
GM		 6569 if (!vha->vp_idx && IS_QLAFX00(ha))
6570 qlafx00_timer_routine(vha);
6571
1da177e4 6572 /* Loop down handler. */
e315cd28 6573 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6574 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6575 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6576 && vha->flags.online) {
1da177e4 6577
e315cd28
AC		 6578 if (atomic_read(&vha->loop_down_timer) ==
6579 vha->loop_down_abort_time) {
1da177e4 6580
7c3df132
SK		 6581 ql_log(ql_log_info, vha, 0x6008,
6582 "Loop down - aborting the queues before time expires.\n");
1da177e4 6583
e315cd28
AC		 6584 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6585 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6586
f08b7251
AV		 6587 /*
6588 * Schedule an ISP abort to return any FCP2-device
6589 * commands.
6590 */
2c3dfe3f 6591 /* NPIV - scan physical port only */
e315cd28 6592 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6593 spin_lock_irqsave(&ha->hardware_lock,
6594 cpu_flags);
73208dfd 6595 req = ha->req_q_map[0];
2c3dfe3f 6596 for (index = 1;
8d93f550 6597 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6598 index++) {
6599 fc_port_t *sfcp;
6600
e315cd28 6601 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6602 if (!sp)
6603 continue;
c5419e26
QT		 6604 if (sp->cmd_type != TYPE_SRB)
6605 continue;
9ba56b95 6606 if (sp->type != SRB_SCSI_CMD)
cf53b069 6607 continue;
2c3dfe3f 6608 sfcp = sp->fcport;
f08b7251 6609 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6610 continue;
bdf79621 6611
8f7daead
GM		 6612 if (IS_QLA82XX(ha))
6613 set_bit(FCOE_CTX_RESET_NEEDED,
6614 &vha->dpc_flags);
6615 else
6616 set_bit(ISP_ABORT_NEEDED,
e315cd28 6617 &vha->dpc_flags);
2c3dfe3f
SJ		 6618 break;
6619 }
6620 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6621 cpu_flags);
1da177e4 6622 }
1da177e4
LT		 6623 start_dpc++;
6624 }
6625
6626 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6627 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6628 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6629 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6630 "Loop down - aborting ISP.\n");
6631
8f7daead
GM		 6632 if (IS_QLA82XX(ha))
6633 set_bit(FCOE_CTX_RESET_NEEDED,
6634 &vha->dpc_flags);
6635 else
6636 set_bit(ISP_ABORT_NEEDED,
6637 &vha->dpc_flags);
1da177e4
LT		 6638 }
6639 }
7c3df132
SK		 6640 ql_dbg(ql_dbg_timer, vha, 0x600a,
6641 "Loop down - seconds remaining %d.\n",
6642 atomic_read(&vha->loop_down_timer));
1da177e4 6643 }
cefcaba6
SK		 6644 /* Check if beacon LED needs to be blinked for physical host only */
6645 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6646 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6647 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6648 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6649 start_dpc++;
6650 }
f6df144c 6651 }
6652
550bf57d 6653 /* Process any deferred work. */
9b3e0f4d
QT		 6654 if (!list_empty(&vha->work_list)) {
6655 unsigned long flags;
6656 bool q = false;
6657
6658 spin_lock_irqsave(&vha->work_lock, flags);
6659 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6660 q = true;
6661 spin_unlock_irqrestore(&vha->work_lock, flags);
6662 if (q)
6663 queue_work(vha->hw->wq, &vha->iocb_work);
6664 }
550bf57d 6665
7401bc18
DG		 6666 /*
6667 * FC-NVME
6668 * see if the active AEN count has changed from what was last reported.
6669 */
b2d1453a
GM		 6670 if (!vha->vp_idx &&
6671 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) &&
6672 ha->zio_mode == QLA_ZIO_MODE_6 &&
6673 !ha->flags.host_shutting_down) {
7401bc18 6674 ql_log(ql_log_info, vha, 0x3002,
8b4673ba
QT		 6675 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6676 ha->nvme_last_rptd_aen);
deeae7a6 6677 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
8b4673ba
QT		 6678 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6679 start_dpc++;
6680 }
6681
6682 if (!vha->vp_idx &&
6683 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
6684 (ha->zio_mode == QLA_ZIO_MODE_6) &&
ecc89f25 6685 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
8b4673ba
QT		 6686 ql_log(ql_log_info, vha, 0x3002,
6687 "Sched: Set ZIO exchange threshold to %d.\n",
6688 ha->last_zio_threshold);
6689 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
deeae7a6
DG		 6690 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6691 start_dpc++;
7401bc18
DG		 6692 }
6693
1da177e4 6694 /* Schedule the DPC routine if needed */
e315cd28
AC		 6695 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6696 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6697 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6698 start_dpc ||
e315cd28
AC		 6699 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6700 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6701 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6702 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6703 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6704 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6705 ql_dbg(ql_dbg_timer, vha, 0x600b,
6706 "isp_abort_needed=%d loop_resync_needed=%d "
6707 "fcport_update_needed=%d start_dpc=%d "
6708 "reset_marker_needed=%d",
6709 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6710 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6711 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6712 start_dpc,
6713 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6714 ql_dbg(ql_dbg_timer, vha, 0x600c,
6715 "beacon_blink_needed=%d isp_unrecoverable=%d "
6716 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6717 "relogin_needed=%d.\n",
7c3df132
SK		 6718 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6719 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6720 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6721 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6722 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6723 qla2xxx_wake_dpc(vha);
7c3df132 6724 }
1da177e4 6725
e315cd28 6726 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6727}
6728
5433383e
AV		 6729/* Firmware interface routines. */
6730
5433383e
AV		 6731#define FW_ISP21XX 0
6732#define FW_ISP22XX 1
6733#define FW_ISP2300 2
6734#define FW_ISP2322 3
48c02fde 6735#define FW_ISP24XX 4
c3a2f0df 6736#define FW_ISP25XX 5
3a03eb79 6737#define FW_ISP81XX 6
a9083016 6738#define FW_ISP82XX 7
6246b8a1
GM		 6739#define FW_ISP2031 8
6740#define FW_ISP8031 9
2c5bbbb2 6741#define FW_ISP27XX 10
ecc89f25 6742#define FW_ISP28XX 11
5433383e 6743
bb8ee499
AV		 6744#define FW_FILE_ISP21XX "ql2100_fw.bin"
6745#define FW_FILE_ISP22XX "ql2200_fw.bin"
6746#define FW_FILE_ISP2300 "ql2300_fw.bin"
6747#define FW_FILE_ISP2322 "ql2322_fw.bin"
6748#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6749#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6750#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6751#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6752#define FW_FILE_ISP2031 "ql2600_fw.bin"
6753#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6754#define FW_FILE_ISP27XX "ql2700_fw.bin"
ecc89f25 6755#define FW_FILE_ISP28XX "ql2800_fw.bin"
f73cb695 6756
bb8ee499 6757
e1e82b6f 6758static DEFINE_MUTEX(qla_fw_lock);
5433383e 6759
ecc89f25 6760static struct fw_blob qla_fw_blobs[] = {
bb8ee499
AV		 6761 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6762 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6763 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6764 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6765 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6766 { .name = FW_FILE_ISP25XX, },
3a03eb79 6767 { .name = FW_FILE_ISP81XX, },
a9083016 6768 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6769 { .name = FW_FILE_ISP2031, },
6770 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6771 { .name = FW_FILE_ISP27XX, },
ecc89f25
JC		 6772 { .name = FW_FILE_ISP28XX, },
6773 { .name = NULL, },
5433383e
AV		 6774};
6775
6776struct fw_blob *
e315cd28 6777qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6778{
e315cd28 6779 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6780 struct fw_blob *blob;
6781
5433383e
AV		 6782 if (IS_QLA2100(ha)) {
6783 blob = &qla_fw_blobs[FW_ISP21XX];
6784 } else if (IS_QLA2200(ha)) {
6785 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6786 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6787 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6788 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6789 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6790 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6791 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6792 } else if (IS_QLA25XX(ha)) {
6793 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6794 } else if (IS_QLA81XX(ha)) {
6795 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6796 } else if (IS_QLA82XX(ha)) {
6797 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6798 } else if (IS_QLA2031(ha)) {
6799 blob = &qla_fw_blobs[FW_ISP2031];
6800 } else if (IS_QLA8031(ha)) {
6801 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6802 } else if (IS_QLA27XX(ha)) {
6803 blob = &qla_fw_blobs[FW_ISP27XX];
ecc89f25
JC		 6804 } else if (IS_QLA28XX(ha)) {
6805 blob = &qla_fw_blobs[FW_ISP28XX];
8a655229
DC		 6806 } else {
6807 return NULL;
5433383e
AV		 6808 }
6809
ecc89f25
JC		 6810 if (!blob->name)
6811 return NULL;
6812
e1e82b6f 6813 mutex_lock(&qla_fw_lock);
5433383e
AV		 6814 if (blob->fw)
6815 goto out;
6816
6817 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6818 ql_log(ql_log_warn, vha, 0x0063,
6819 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6820 blob->fw = NULL;
6821 blob = NULL;
5433383e
AV		 6822 }
6823
6824out:
e1e82b6f 6825 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6826 return blob;
6827}
6828
6829static void
6830qla2x00_release_firmware(void)
6831{
ecc89f25 6832 struct fw_blob *blob;
5433383e 6833
e1e82b6f 6834 mutex_lock(&qla_fw_lock);
ecc89f25
JC		 6835 for (blob = qla_fw_blobs; blob->name; blob++)
6836 release_firmware(blob->fw);
e1e82b6f 6837 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6838}
6839
5386a4e6
QT		 6840static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
6841{
6842 struct qla_hw_data *ha = vha->hw;
6843 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6844 struct qla_qpair *qpair = NULL;
6845 struct scsi_qla_host *vp;
6846 fc_port_t *fcport;
6847 int i;
6848 unsigned long flags;
6849
6850 ha->chip_reset++;
6851
6852 ha->base_qpair->chip_reset = ha->chip_reset;
6853 for (i = 0; i < ha->max_qpairs; i++) {
6854 if (ha->queue_pair_map[i])
6855 ha->queue_pair_map[i]->chip_reset =
6856 ha->base_qpair->chip_reset;
6857 }
6858
6859 /* purge MBox commands */
6860 if (atomic_read(&ha->num_pend_mbx_stage3)) {
6861 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
6862 complete(&ha->mbx_intr_comp);
6863 }
6864
6865 i = 0;
6866
6867 while (atomic_read(&ha->num_pend_mbx_stage3) ||
6868 atomic_read(&ha->num_pend_mbx_stage2) ||
6869 atomic_read(&ha->num_pend_mbx_stage1)) {
6870 msleep(20);
6871 i++;
6872 if (i > 50)
6873 break;
6874 }
6875
6876 ha->flags.purge_mbox = 0;
6877
6878 mutex_lock(&ha->mq_lock);
6879 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
6880 qpair->online = 0;
6881 mutex_unlock(&ha->mq_lock);
6882
6883 qla2x00_mark_all_devices_lost(vha, 0);
6884
6885 spin_lock_irqsave(&ha->vport_slock, flags);
6886 list_for_each_entry(vp, &ha->vp_list, list) {
6887 atomic_inc(&vp->vref_count);
6888 spin_unlock_irqrestore(&ha->vport_slock, flags);
6889 qla2x00_mark_all_devices_lost(vp, 0);
6890 spin_lock_irqsave(&ha->vport_slock, flags);
6891 atomic_dec(&vp->vref_count);
6892 }
6893 spin_unlock_irqrestore(&ha->vport_slock, flags);
6894
6895 /* Clear all async request states across all VPs. */
6896 list_for_each_entry(fcport, &vha->vp_fcports, list)
6897 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6898
6899 spin_lock_irqsave(&ha->vport_slock, flags);
6900 list_for_each_entry(vp, &ha->vp_list, list) {
6901 atomic_inc(&vp->vref_count);
6902 spin_unlock_irqrestore(&ha->vport_slock, flags);
6903 list_for_each_entry(fcport, &vp->vp_fcports, list)
6904 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6905 spin_lock_irqsave(&ha->vport_slock, flags);
6906 atomic_dec(&vp->vref_count);
6907 }
6908 spin_unlock_irqrestore(&ha->vport_slock, flags);
6909}
6910
6911
14e660e6
SJ		 6912static pci_ers_result_t
6913qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6914{
85880801
AV		 6915 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6916 struct qla_hw_data *ha = vha->hw;
6917
7c3df132
SK		 6918 ql_dbg(ql_dbg_aer, vha, 0x9000,
6919 "PCI error detected, state %x.\n", state);
b9b12f73 6920
efdb5760
SC		 6921 if (!atomic_read(&pdev->enable_cnt)) {
6922 ql_log(ql_log_info, vha, 0xffff,
6923 "PCI device is disabled,state %x\n", state);
6924 return PCI_ERS_RESULT_NEED_RESET;
6925 }
6926
14e660e6
SJ		 6927 switch (state) {
6928 case pci_channel_io_normal:
85880801 6929 ha->flags.eeh_busy = 0;
c38d1baf 6930 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6931 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6932 qla2xxx_wake_dpc(vha);
6933 }
14e660e6
SJ		 6934 return PCI_ERS_RESULT_CAN_RECOVER;
6935 case pci_channel_io_frozen:
85880801 6936 ha->flags.eeh_busy = 1;
5386a4e6 6937 qla_pci_error_cleanup(vha);
14e660e6
SJ		 6938 return PCI_ERS_RESULT_NEED_RESET;
6939 case pci_channel_io_perm_failure:
85880801
AV		 6940 ha->flags.pci_channel_io_perm_failure = 1;
6941 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6942 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6943 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6944 qla2xxx_wake_dpc(vha);
6945 }
14e660e6
SJ		 6946 return PCI_ERS_RESULT_DISCONNECT;
6947 }
6948 return PCI_ERS_RESULT_NEED_RESET;
6949}
6950
6951static pci_ers_result_t
6952qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6953{
6954 int risc_paused = 0;
6955 uint32_t stat;
6956 unsigned long flags;
e315cd28
AC		 6957 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6958 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6959 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6960 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6961
bcc5b6d3
SK		 6962 if (IS_QLA82XX(ha))
6963 return PCI_ERS_RESULT_RECOVERED;
6964
14e660e6
SJ		 6965 spin_lock_irqsave(&ha->hardware_lock, flags);
6966 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6967 stat = RD_REG_DWORD(&reg->hccr);
6968 if (stat & HCCR_RISC_PAUSE)
6969 risc_paused = 1;
6970 } else if (IS_QLA23XX(ha)) {
6971 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6972 if (stat & HSR_RISC_PAUSED)
6973 risc_paused = 1;
6974 } else if (IS_FWI2_CAPABLE(ha)) {
6975 stat = RD_REG_DWORD(&reg24->host_status);
6976 if (stat & HSRX_RISC_PAUSED)
6977 risc_paused = 1;
6978 }
6979 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6980
6981 if (risc_paused) {
7c3df132
SK		 6982 ql_log(ql_log_info, base_vha, 0x9003,
6983 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6984 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6985
6986 return PCI_ERS_RESULT_NEED_RESET;
6987 } else
6988 return PCI_ERS_RESULT_RECOVERED;
6989}
6990
6991static pci_ers_result_t
6992qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6993{
6994 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6995 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6996 struct qla_hw_data *ha = base_vha->hw;
5386a4e6
QT		 6997 int rc;
6998 struct qla_qpair *qpair = NULL;
09483916 6999
7c3df132
SK		 7000 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
7001 "Slot Reset.\n");
85880801 7002
90a86fc0
JC		 7003 /* Workaround: qla2xxx driver which access hardware earlier
7004 * needs error state to be pci_channel_io_online.
7005 * Otherwise mailbox command timesout.
7006 */
7007 pdev->error_state = pci_channel_io_normal;
7008
7009 pci_restore_state(pdev);
7010
8c1496bd
RL		 7011 /* pci_restore_state() clears the saved_state flag of the device
7012 * save restored state which resets saved_state flag
7013 */
7014 pci_save_state(pdev);
7015
09483916
BH		 7016 if (ha->mem_only)
7017 rc = pci_enable_device_mem(pdev);
7018 else
7019 rc = pci_enable_device(pdev);
14e660e6 7020
09483916 7021 if (rc) {
7c3df132 7022 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 7023 "Can't re-enable PCI device after reset.\n");
a5b36321 7024 goto exit_slot_reset;
14e660e6 7025 }
14e660e6 7026
90a86fc0 7027
e315cd28 7028 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 7029 goto exit_slot_reset;
7030
5386a4e6
QT		 7031 mutex_lock(&ha->mq_lock);
7032 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7033 qpair->online = 1;
7034 mutex_unlock(&ha->mq_lock);
85880801 7035
5386a4e6 7036 base_vha->flags.online = 1;
e315cd28 7037 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 7038 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 7039 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 7040 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 7041
90a86fc0 7042
a5b36321 7043exit_slot_reset:
7c3df132
SK		 7044 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7045 "slot_reset return %x.\n", ret);
85880801 7046
14e660e6
SJ		 7047 return ret;
7048}
7049
7050static void
7051qla2xxx_pci_resume(struct pci_dev *pdev)
7052{
e315cd28
AC		 7053 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7054 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 7055 int ret;
7056
7c3df132
SK		 7057 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7058 "pci_resume.\n");
85880801 7059
5386a4e6
QT		 7060 ha->flags.eeh_busy = 0;
7061
e315cd28 7062 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 7063 if (ret != QLA_SUCCESS) {
7c3df132
SK		 7064 ql_log(ql_log_fatal, base_vha, 0x9002,
7065 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 7066 }
14e660e6
SJ		 7067}
7068
590f806d
QT		 7069static void
7070qla_pci_reset_prepare(struct pci_dev *pdev)
7071{
7072 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7073 struct qla_hw_data *ha = base_vha->hw;
7074 struct qla_qpair *qpair;
7075
7076 ql_log(ql_log_warn, base_vha, 0xffff,
7077 "%s.\n", __func__);
7078
7079 /*
7080 * PCI FLR/function reset is about to reset the
7081 * slot. Stop the chip to stop all DMA access.
7082 * It is assumed that pci_reset_done will be called
7083 * after FLR to resume Chip operation.
7084 */
7085 ha->flags.eeh_busy = 1;
7086 mutex_lock(&ha->mq_lock);
7087 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7088 qpair->online = 0;
7089 mutex_unlock(&ha->mq_lock);
7090
7091 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7092 qla2x00_abort_isp_cleanup(base_vha);
7093 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7094}
7095
7096static void
7097qla_pci_reset_done(struct pci_dev *pdev)
7098{
7099 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7100 struct qla_hw_data *ha = base_vha->hw;
7101 struct qla_qpair *qpair;
7102
7103 ql_log(ql_log_warn, base_vha, 0xffff,
7104 "%s.\n", __func__);
7105
7106 /*
7107 * FLR just completed by PCI layer. Resume adapter
7108 */
7109 ha->flags.eeh_busy = 0;
7110 mutex_lock(&ha->mq_lock);
7111 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7112 qpair->online = 1;
7113 mutex_unlock(&ha->mq_lock);
7114
7115 base_vha->flags.online = 1;
7116 ha->isp_ops->abort_isp(base_vha);
7117 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7118}
7119
5601236b
MH		 7120static int qla2xxx_map_queues(struct Scsi_Host *shost)
7121{
d68b850e 7122 int rc;
5601236b 7123 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
485b0eca 7124 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
5601236b 7125
f3e02695 7126 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
ed76e329 7127 rc = blk_mq_map_queues(qmap);
d68b850e 7128 else
f0783d43 7129 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
d68b850e 7130 return rc;
5601236b
MH		 7131}
7132
6515ad71
BVA		 7133struct scsi_host_template qla2xxx_driver_template = {
7134 .module = THIS_MODULE,
7135 .name = QLA2XXX_DRIVER_NAME,
7136 .queuecommand = qla2xxx_queuecommand,
7137
7138 .eh_timed_out = fc_eh_timed_out,
7139 .eh_abort_handler = qla2xxx_eh_abort,
7140 .eh_device_reset_handler = qla2xxx_eh_device_reset,
7141 .eh_target_reset_handler = qla2xxx_eh_target_reset,
7142 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
7143 .eh_host_reset_handler = qla2xxx_eh_host_reset,
7144
7145 .slave_configure = qla2xxx_slave_configure,
7146
7147 .slave_alloc = qla2xxx_slave_alloc,
7148 .slave_destroy = qla2xxx_slave_destroy,
7149 .scan_finished = qla2xxx_scan_finished,
7150 .scan_start = qla2xxx_scan_start,
7151 .change_queue_depth = scsi_change_queue_depth,
7152 .map_queues = qla2xxx_map_queues,
7153 .this_id = -1,
7154 .cmd_per_lun = 3,
7155 .sg_tablesize = SG_ALL,
7156
7157 .max_sectors = 0xFFFF,
7158 .shost_attrs = qla2x00_host_attrs,
7159
7160 .supported_mode = MODE_INITIATOR,
7161 .track_queue_depth = 1,
7162};
7163
a55b2d21 7164static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 7165 .error_detected = qla2xxx_pci_error_detected,
7166 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7167 .slot_reset = qla2xxx_pci_slot_reset,
7168 .resume = qla2xxx_pci_resume,
590f806d
QT		 7169 .reset_prepare = qla_pci_reset_prepare,
7170 .reset_done = qla_pci_reset_done,
14e660e6
SJ		 7171};
7172
5433383e 7173static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 7174 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7175 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7176 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7177 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7178 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7179 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7180 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7181 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7182 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 7183 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 7184 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7185 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 7186 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 7187 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 7188 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 7189 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 7190 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 7191 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 7192 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 7193 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 7194 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 7195 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
ecc89f25
JC		 7196 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7197 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7198 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7199 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7200 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
5433383e
AV		 7201 { 0 },
7202};
7203MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7204
fca29703 7205static struct pci_driver qla2xxx_pci_driver = {
cb63067a 7206 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 7207 .driver = {
7208 .owner = THIS_MODULE,
7209 },
fca29703 7210 .id_table = qla2xxx_pci_tbl,
7ee61397 7211 .probe = qla2x00_probe_one,
4c993f76 7212 .remove = qla2x00_remove_one,
e30d1756 7213 .shutdown = qla2x00_shutdown,
14e660e6 7214 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 7215};
7216
75ef9de1 7217static const struct file_operations apidev_fops = {
6a03b4cd 7218 .owner = THIS_MODULE,
6038f373 7219 .llseek = noop_llseek,
6a03b4cd
HZ		 7220};
7221
1da177e4
LT		 7222/**
7223 * qla2x00_module_init - Module initialization.
7224 **/
7225static int __init
7226qla2x00_module_init(void)
7227{
fca29703
AV		 7228 int ret = 0;
7229
bc04459c
BVA		 7230 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
7231 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
7232 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
7233 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
7234 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
7235 BUILD_BUG_ON(sizeof(request_t) != 64);
7236 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
7237 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
7238 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
7239 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
7240 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
7241 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
7242 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
7243 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
7244 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
7245 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
7246 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
7247 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
7248 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
7249 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
7250 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
7251 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
7252 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
7253
1da177e4 7254 /* Allocate cache for SRBs. */
354d6b21 7255 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 7256 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 7257 if (srb_cachep == NULL) {
7c3df132
SK		 7258 ql_log(ql_log_fatal, NULL, 0x0001,
7259 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 7260 return -ENOMEM;
7261 }
7262
2d70c103
NB		 7263 /* Initialize target kmem_cache and mem_pools */
7264 ret = qlt_init();
7265 if (ret < 0) {
c794d24e 7266 goto destroy_cache;
2d70c103
NB		 7267 } else if (ret > 0) {
7268 /*
7269 * If initiator mode is explictly disabled by qlt_init(),
7270 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7271 * performing scsi_scan_target() during LOOP UP event.
7272 */
7273 qla2xxx_transport_functions.disable_target_scan = 1;
7274 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7275 }
7276
1da177e4
LT		 7277 /* Derive version string. */
7278 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 7279 if (ql2xextended_error_logging)
0181944f 7280 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 7281 if (ql2xextended_error_logging == 1)
7282 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 7283
0645cb83
QT		 7284 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7285 qla_insert_tgt_attrs();
7286
1c97a12a
AV		 7287 qla2xxx_transport_template =
7288 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f 7289 if (!qla2xxx_transport_template) {
7c3df132
SK		 7290 ql_log(ql_log_fatal, NULL, 0x0002,
7291 "fc_attach_transport failed...Failing load!.\n");
c794d24e
BVA		 7292 ret = -ENODEV;
7293 goto qlt_exit;
2c3dfe3f 7294 }
6a03b4cd
HZ		 7295
7296 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7297 if (apidev_major < 0) {
7c3df132
SK		 7298 ql_log(ql_log_fatal, NULL, 0x0003,
7299 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 7300 }
7301
2c3dfe3f
SJ		 7302 qla2xxx_transport_vport_template =
7303 fc_attach_transport(&qla2xxx_transport_vport_functions);
7304 if (!qla2xxx_transport_vport_template) {
7c3df132
SK		 7305 ql_log(ql_log_fatal, NULL, 0x0004,
7306 "fc_attach_transport vport failed...Failing load!.\n");
c794d24e
BVA		 7307 ret = -ENODEV;
7308 goto unreg_chrdev;
2c3dfe3f 7309 }
7c3df132
SK		 7310 ql_log(ql_log_info, NULL, 0x0005,
7311 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 7312 qla2x00_version_str);
7ee61397 7313 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703 7314 if (ret) {
7c3df132
SK		 7315 ql_log(ql_log_fatal, NULL, 0x0006,
7316 "pci_register_driver failed...ret=%d Failing load!.\n",
7317 ret);
c794d24e 7318 goto release_vport_transport;
fca29703
AV		 7319 }
7320 return ret;
c794d24e
BVA		 7321
7322release_vport_transport:
7323 fc_release_transport(qla2xxx_transport_vport_template);
7324
7325unreg_chrdev:
7326 if (apidev_major >= 0)
7327 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7328 fc_release_transport(qla2xxx_transport_template);
7329
7330qlt_exit:
7331 qlt_exit();
7332
7333destroy_cache:
7334 kmem_cache_destroy(srb_cachep);
7335 return ret;
1da177e4
LT		 7336}
7337
7338/**
7339 * qla2x00_module_exit - Module cleanup.
7340 **/
7341static void __exit
7342qla2x00_module_exit(void)
7343{
7ee61397 7344 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 7345 qla2x00_release_firmware();
75c1d48a 7346 kmem_cache_destroy(ctx_cachep);
2c3dfe3f 7347 fc_release_transport(qla2xxx_transport_vport_template);
59c209a6
BVA		 7348 if (apidev_major >= 0)
7349 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7350 fc_release_transport(qla2xxx_transport_template);
7351 qlt_exit();
7352 kmem_cache_destroy(srb_cachep);
1da177e4
LT		 7353}
7354
7355module_init(qla2x00_module_init);
7356module_exit(qla2x00_module_exit);
7357
7358MODULE_AUTHOR("QLogic Corporation");
7359MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7360MODULE_LICENSE("GPL");
7361MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 7362MODULE_FIRMWARE(FW_FILE_ISP21XX);
7363MODULE_FIRMWARE(FW_FILE_ISP22XX);
7364MODULE_FIRMWARE(FW_FILE_ISP2300);
7365MODULE_FIRMWARE(FW_FILE_ISP2322);
7366MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 7367MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)