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8ae6d9c7 GM |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
bd21eaf9 | 3 | * Copyright (c) 2003-2014 QLogic Corporation |
8ae6d9c7 GM |
4 | * |
5 | * See LICENSE.qla2xxx for copyright and licensing details. | |
6 | */ | |
7 | #include "qla_def.h" | |
8 | #include <linux/delay.h> | |
5ea33eb5 | 9 | #include <linux/ktime.h> |
8ae6d9c7 GM |
10 | #include <linux/pci.h> |
11 | #include <linux/ratelimit.h> | |
12 | #include <linux/vmalloc.h> | |
13 | #include <scsi/scsi_tcq.h> | |
14 | #include <linux/utsname.h> | |
15 | ||
16 | ||
17 | /* QLAFX00 specific Mailbox implementation functions */ | |
18 | ||
19 | /* | |
20 | * qlafx00_mailbox_command | |
21 | * Issue mailbox command and waits for completion. | |
22 | * | |
23 | * Input: | |
24 | * ha = adapter block pointer. | |
25 | * mcp = driver internal mbx struct pointer. | |
26 | * | |
27 | * Output: | |
28 | * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data. | |
29 | * | |
30 | * Returns: | |
31 | * 0 : QLA_SUCCESS = cmd performed success | |
32 | * 1 : QLA_FUNCTION_FAILED (error encountered) | |
33 | * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered) | |
34 | * | |
35 | * Context: | |
36 | * Kernel context. | |
37 | */ | |
38 | static int | |
39 | qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp) | |
40 | ||
41 | { | |
42 | int rval; | |
43 | unsigned long flags = 0; | |
f73cb695 | 44 | device_reg_t *reg; |
8ae6d9c7 GM |
45 | uint8_t abort_active; |
46 | uint8_t io_lock_on; | |
47 | uint16_t command = 0; | |
48 | uint32_t *iptr; | |
49 | uint32_t __iomem *optr; | |
50 | uint32_t cnt; | |
51 | uint32_t mboxes; | |
52 | unsigned long wait_time; | |
53 | struct qla_hw_data *ha = vha->hw; | |
54 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
55 | ||
56 | if (ha->pdev->error_state > pci_channel_io_frozen) { | |
57 | ql_log(ql_log_warn, vha, 0x115c, | |
58 | "error_state is greater than pci_channel_io_frozen, " | |
59 | "exiting.\n"); | |
60 | return QLA_FUNCTION_TIMEOUT; | |
61 | } | |
62 | ||
63 | if (vha->device_flags & DFLG_DEV_FAILED) { | |
64 | ql_log(ql_log_warn, vha, 0x115f, | |
65 | "Device in failed state, exiting.\n"); | |
66 | return QLA_FUNCTION_TIMEOUT; | |
67 | } | |
68 | ||
69 | reg = ha->iobase; | |
70 | io_lock_on = base_vha->flags.init_done; | |
71 | ||
72 | rval = QLA_SUCCESS; | |
73 | abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
74 | ||
75 | if (ha->flags.pci_channel_io_perm_failure) { | |
76 | ql_log(ql_log_warn, vha, 0x1175, | |
77 | "Perm failure on EEH timeout MBX, exiting.\n"); | |
78 | return QLA_FUNCTION_TIMEOUT; | |
79 | } | |
80 | ||
81 | if (ha->flags.isp82xx_fw_hung) { | |
82 | /* Setting Link-Down error */ | |
83 | mcp->mb[0] = MBS_LINK_DOWN_ERROR; | |
84 | ql_log(ql_log_warn, vha, 0x1176, | |
85 | "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); | |
86 | rval = QLA_FUNCTION_FAILED; | |
87 | goto premature_exit; | |
88 | } | |
89 | ||
90 | /* | |
91 | * Wait for active mailbox commands to finish by waiting at most tov | |
92 | * seconds. This is to serialize actual issuing of mailbox cmds during | |
93 | * non ISP abort time. | |
94 | */ | |
95 | if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) { | |
96 | /* Timeout occurred. Return error. */ | |
97 | ql_log(ql_log_warn, vha, 0x1177, | |
98 | "Cmd access timeout, cmd=0x%x, Exiting.\n", | |
99 | mcp->mb[0]); | |
100 | return QLA_FUNCTION_TIMEOUT; | |
101 | } | |
102 | ||
103 | ha->flags.mbox_busy = 1; | |
104 | /* Save mailbox command for debug */ | |
105 | ha->mcp32 = mcp; | |
106 | ||
107 | ql_dbg(ql_dbg_mbx, vha, 0x1178, | |
108 | "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]); | |
109 | ||
110 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
111 | ||
112 | /* Load mailbox registers. */ | |
113 | optr = (uint32_t __iomem *)®->ispfx00.mailbox0; | |
114 | ||
115 | iptr = mcp->mb; | |
116 | command = mcp->mb[0]; | |
117 | mboxes = mcp->out_mb; | |
118 | ||
119 | for (cnt = 0; cnt < ha->mbx_count; cnt++) { | |
120 | if (mboxes & BIT_0) | |
121 | WRT_REG_DWORD(optr, *iptr); | |
122 | ||
123 | mboxes >>= 1; | |
124 | optr++; | |
125 | iptr++; | |
126 | } | |
127 | ||
128 | /* Issue set host interrupt command to send cmd out. */ | |
129 | ha->flags.mbox_int = 0; | |
130 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
131 | ||
132 | ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172, | |
133 | (uint8_t *)mcp->mb, 16); | |
134 | ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173, | |
135 | ((uint8_t *)mcp->mb + 0x10), 16); | |
136 | ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174, | |
137 | ((uint8_t *)mcp->mb + 0x20), 8); | |
138 | ||
139 | /* Unlock mbx registers and wait for interrupt */ | |
140 | ql_dbg(ql_dbg_mbx, vha, 0x1179, | |
141 | "Going to unlock irq & waiting for interrupts. " | |
142 | "jiffies=%lx.\n", jiffies); | |
143 | ||
144 | /* Wait for mbx cmd completion until timeout */ | |
145 | if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { | |
146 | set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); | |
147 | ||
148 | QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code); | |
149 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
150 | ||
58e060e1 BVA |
151 | WARN_ON_ONCE(wait_for_completion_timeout(&ha->mbx_intr_comp, |
152 | mcp->tov * HZ) != 0); | |
8ae6d9c7 GM |
153 | } else { |
154 | ql_dbg(ql_dbg_mbx, vha, 0x112c, | |
155 | "Cmd=%x Polling Mode.\n", command); | |
156 | ||
157 | QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code); | |
158 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
159 | ||
160 | wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */ | |
161 | while (!ha->flags.mbox_int) { | |
162 | if (time_after(jiffies, wait_time)) | |
163 | break; | |
164 | ||
165 | /* Check for pending interrupts. */ | |
166 | qla2x00_poll(ha->rsp_q_map[0]); | |
167 | ||
168 | if (!ha->flags.mbox_int && | |
169 | !(IS_QLA2200(ha) && | |
170 | command == MBC_LOAD_RISC_RAM_EXTENDED)) | |
171 | usleep_range(10000, 11000); | |
172 | } /* while */ | |
173 | ql_dbg(ql_dbg_mbx, vha, 0x112d, | |
174 | "Waited %d sec.\n", | |
175 | (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ)); | |
176 | } | |
177 | ||
178 | /* Check whether we timed out */ | |
179 | if (ha->flags.mbox_int) { | |
180 | uint32_t *iptr2; | |
181 | ||
182 | ql_dbg(ql_dbg_mbx, vha, 0x112e, | |
183 | "Cmd=%x completed.\n", command); | |
184 | ||
185 | /* Got interrupt. Clear the flag. */ | |
186 | ha->flags.mbox_int = 0; | |
187 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
188 | ||
189 | if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE) | |
190 | rval = QLA_FUNCTION_FAILED; | |
191 | ||
192 | /* Load return mailbox registers. */ | |
193 | iptr2 = mcp->mb; | |
194 | iptr = (uint32_t *)&ha->mailbox_out32[0]; | |
195 | mboxes = mcp->in_mb; | |
196 | for (cnt = 0; cnt < ha->mbx_count; cnt++) { | |
197 | if (mboxes & BIT_0) | |
198 | *iptr2 = *iptr; | |
199 | ||
200 | mboxes >>= 1; | |
201 | iptr2++; | |
202 | iptr++; | |
203 | } | |
204 | } else { | |
205 | ||
206 | rval = QLA_FUNCTION_TIMEOUT; | |
207 | } | |
208 | ||
209 | ha->flags.mbox_busy = 0; | |
210 | ||
211 | /* Clean up */ | |
212 | ha->mcp32 = NULL; | |
213 | ||
214 | if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) { | |
215 | ql_dbg(ql_dbg_mbx, vha, 0x113a, | |
216 | "checking for additional resp interrupt.\n"); | |
217 | ||
218 | /* polling mode for non isp_abort commands. */ | |
219 | qla2x00_poll(ha->rsp_q_map[0]); | |
220 | } | |
221 | ||
222 | if (rval == QLA_FUNCTION_TIMEOUT && | |
223 | mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) { | |
224 | if (!io_lock_on || (mcp->flags & IOCTL_CMD) || | |
225 | ha->flags.eeh_busy) { | |
226 | /* not in dpc. schedule it for dpc to take over. */ | |
227 | ql_dbg(ql_dbg_mbx, vha, 0x115d, | |
228 | "Timeout, schedule isp_abort_needed.\n"); | |
229 | ||
230 | if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && | |
231 | !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && | |
232 | !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { | |
233 | ||
234 | ql_log(ql_log_info, base_vha, 0x115e, | |
235 | "Mailbox cmd timeout occurred, cmd=0x%x, " | |
236 | "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP " | |
237 | "abort.\n", command, mcp->mb[0], | |
238 | ha->flags.eeh_busy); | |
239 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
240 | qla2xxx_wake_dpc(vha); | |
241 | } | |
242 | } else if (!abort_active) { | |
243 | /* call abort directly since we are in the DPC thread */ | |
244 | ql_dbg(ql_dbg_mbx, vha, 0x1160, | |
245 | "Timeout, calling abort_isp.\n"); | |
246 | ||
247 | if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && | |
248 | !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && | |
249 | !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { | |
250 | ||
251 | ql_log(ql_log_info, base_vha, 0x1161, | |
252 | "Mailbox cmd timeout occurred, cmd=0x%x, " | |
253 | "mb[0]=0x%x. Scheduling ISP abort ", | |
254 | command, mcp->mb[0]); | |
255 | ||
256 | set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); | |
257 | clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
258 | if (ha->isp_ops->abort_isp(vha)) { | |
259 | /* Failed. retry later. */ | |
260 | set_bit(ISP_ABORT_NEEDED, | |
261 | &vha->dpc_flags); | |
262 | } | |
263 | clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); | |
264 | ql_dbg(ql_dbg_mbx, vha, 0x1162, | |
265 | "Finished abort_isp.\n"); | |
266 | } | |
267 | } | |
268 | } | |
269 | ||
270 | premature_exit: | |
271 | /* Allow next mbx cmd to come in. */ | |
272 | complete(&ha->mbx_cmd_comp); | |
273 | ||
274 | if (rval) { | |
275 | ql_log(ql_log_warn, base_vha, 0x1163, | |
3f918ffa BVA |
276 | "**** Failed=%x mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n", |
277 | rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], | |
278 | command); | |
8ae6d9c7 GM |
279 | } else { |
280 | ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__); | |
281 | } | |
282 | ||
283 | return rval; | |
284 | } | |
285 | ||
286 | /* | |
287 | * qlafx00_driver_shutdown | |
288 | * Indicate a driver shutdown to firmware. | |
289 | * | |
290 | * Input: | |
291 | * ha = adapter block pointer. | |
292 | * | |
293 | * Returns: | |
294 | * local function return status code. | |
295 | * | |
296 | * Context: | |
297 | * Kernel context. | |
298 | */ | |
42479343 | 299 | int |
8ae6d9c7 GM |
300 | qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo) |
301 | { | |
302 | int rval; | |
303 | struct mbx_cmd_32 mc; | |
304 | struct mbx_cmd_32 *mcp = &mc; | |
305 | ||
306 | ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166, | |
307 | "Entered %s.\n", __func__); | |
308 | ||
309 | mcp->mb[0] = MBC_MR_DRV_SHUTDOWN; | |
310 | mcp->out_mb = MBX_0; | |
311 | mcp->in_mb = MBX_0; | |
312 | if (tmo) | |
313 | mcp->tov = tmo; | |
314 | else | |
315 | mcp->tov = MBX_TOV_SECONDS; | |
316 | mcp->flags = 0; | |
317 | rval = qlafx00_mailbox_command(vha, mcp); | |
318 | ||
319 | if (rval != QLA_SUCCESS) { | |
320 | ql_dbg(ql_dbg_mbx, vha, 0x1167, | |
321 | "Failed=%x.\n", rval); | |
322 | } else { | |
323 | ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168, | |
324 | "Done %s.\n", __func__); | |
325 | } | |
326 | ||
327 | return rval; | |
328 | } | |
329 | ||
330 | /* | |
331 | * qlafx00_get_firmware_state | |
332 | * Get adapter firmware state. | |
333 | * | |
334 | * Input: | |
335 | * ha = adapter block pointer. | |
336 | * TARGET_QUEUE_LOCK must be released. | |
337 | * ADAPTER_STATE_LOCK must be released. | |
338 | * | |
339 | * Returns: | |
340 | * qla7xxx local function return status code. | |
341 | * | |
342 | * Context: | |
343 | * Kernel context. | |
344 | */ | |
345 | static int | |
346 | qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states) | |
347 | { | |
348 | int rval; | |
349 | struct mbx_cmd_32 mc; | |
350 | struct mbx_cmd_32 *mcp = &mc; | |
351 | ||
352 | ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169, | |
353 | "Entered %s.\n", __func__); | |
354 | ||
355 | mcp->mb[0] = MBC_GET_FIRMWARE_STATE; | |
356 | mcp->out_mb = MBX_0; | |
357 | mcp->in_mb = MBX_1|MBX_0; | |
358 | mcp->tov = MBX_TOV_SECONDS; | |
359 | mcp->flags = 0; | |
360 | rval = qlafx00_mailbox_command(vha, mcp); | |
361 | ||
362 | /* Return firmware states. */ | |
363 | states[0] = mcp->mb[1]; | |
364 | ||
365 | if (rval != QLA_SUCCESS) { | |
366 | ql_dbg(ql_dbg_mbx, vha, 0x116a, | |
367 | "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); | |
368 | } else { | |
369 | ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b, | |
370 | "Done %s.\n", __func__); | |
371 | } | |
372 | return rval; | |
373 | } | |
374 | ||
375 | /* | |
376 | * qlafx00_init_firmware | |
377 | * Initialize adapter firmware. | |
378 | * | |
379 | * Input: | |
380 | * ha = adapter block pointer. | |
381 | * dptr = Initialization control block pointer. | |
382 | * size = size of initialization control block. | |
383 | * TARGET_QUEUE_LOCK must be released. | |
384 | * ADAPTER_STATE_LOCK must be released. | |
385 | * | |
386 | * Returns: | |
387 | * qlafx00 local function return status code. | |
388 | * | |
389 | * Context: | |
390 | * Kernel context. | |
391 | */ | |
392 | int | |
393 | qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size) | |
394 | { | |
395 | int rval; | |
396 | struct mbx_cmd_32 mc; | |
397 | struct mbx_cmd_32 *mcp = &mc; | |
398 | struct qla_hw_data *ha = vha->hw; | |
399 | ||
400 | ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c, | |
401 | "Entered %s.\n", __func__); | |
402 | ||
403 | mcp->mb[0] = MBC_INITIALIZE_FIRMWARE; | |
404 | ||
405 | mcp->mb[1] = 0; | |
406 | mcp->mb[2] = MSD(ha->init_cb_dma); | |
407 | mcp->mb[3] = LSD(ha->init_cb_dma); | |
408 | ||
409 | mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; | |
410 | mcp->in_mb = MBX_0; | |
411 | mcp->buf_size = size; | |
412 | mcp->flags = MBX_DMA_OUT; | |
413 | mcp->tov = MBX_TOV_SECONDS; | |
414 | rval = qlafx00_mailbox_command(vha, mcp); | |
415 | ||
416 | if (rval != QLA_SUCCESS) { | |
417 | ql_dbg(ql_dbg_mbx, vha, 0x116d, | |
418 | "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); | |
419 | } else { | |
420 | ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e, | |
421 | "Done %s.\n", __func__); | |
422 | } | |
423 | return rval; | |
424 | } | |
425 | ||
426 | /* | |
427 | * qlafx00_mbx_reg_test | |
428 | */ | |
429 | static int | |
430 | qlafx00_mbx_reg_test(scsi_qla_host_t *vha) | |
431 | { | |
432 | int rval; | |
433 | struct mbx_cmd_32 mc; | |
434 | struct mbx_cmd_32 *mcp = &mc; | |
435 | ||
436 | ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f, | |
437 | "Entered %s.\n", __func__); | |
438 | ||
439 | ||
440 | mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST; | |
441 | mcp->mb[1] = 0xAAAA; | |
442 | mcp->mb[2] = 0x5555; | |
443 | mcp->mb[3] = 0xAA55; | |
444 | mcp->mb[4] = 0x55AA; | |
445 | mcp->mb[5] = 0xA5A5; | |
446 | mcp->mb[6] = 0x5A5A; | |
447 | mcp->mb[7] = 0x2525; | |
448 | mcp->mb[8] = 0xBBBB; | |
449 | mcp->mb[9] = 0x6666; | |
450 | mcp->mb[10] = 0xBB66; | |
451 | mcp->mb[11] = 0x66BB; | |
452 | mcp->mb[12] = 0xB6B6; | |
453 | mcp->mb[13] = 0x6B6B; | |
454 | mcp->mb[14] = 0x3636; | |
455 | mcp->mb[15] = 0xCCCC; | |
456 | ||
457 | ||
458 | mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| | |
459 | MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; | |
460 | mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| | |
461 | MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; | |
462 | mcp->buf_size = 0; | |
463 | mcp->flags = MBX_DMA_OUT; | |
464 | mcp->tov = MBX_TOV_SECONDS; | |
465 | rval = qlafx00_mailbox_command(vha, mcp); | |
466 | if (rval == QLA_SUCCESS) { | |
467 | if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 || | |
468 | mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA) | |
469 | rval = QLA_FUNCTION_FAILED; | |
470 | if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A || | |
471 | mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB) | |
472 | rval = QLA_FUNCTION_FAILED; | |
473 | if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 || | |
474 | mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6) | |
475 | rval = QLA_FUNCTION_FAILED; | |
476 | if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 || | |
477 | mcp->mb[31] != 0xCCCC) | |
478 | rval = QLA_FUNCTION_FAILED; | |
479 | } | |
480 | ||
481 | if (rval != QLA_SUCCESS) { | |
482 | ql_dbg(ql_dbg_mbx, vha, 0x1170, | |
483 | "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); | |
484 | } else { | |
485 | ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171, | |
486 | "Done %s.\n", __func__); | |
487 | } | |
488 | return rval; | |
489 | } | |
490 | ||
491 | /** | |
492 | * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers. | |
2db6228d | 493 | * @vha: HA context |
8ae6d9c7 GM |
494 | * |
495 | * Returns 0 on success. | |
496 | */ | |
497 | int | |
498 | qlafx00_pci_config(scsi_qla_host_t *vha) | |
499 | { | |
500 | uint16_t w; | |
501 | struct qla_hw_data *ha = vha->hw; | |
502 | ||
503 | pci_set_master(ha->pdev); | |
504 | pci_try_set_mwi(ha->pdev); | |
505 | ||
506 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); | |
507 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); | |
508 | w &= ~PCI_COMMAND_INTX_DISABLE; | |
509 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); | |
510 | ||
511 | /* PCIe -- adjust Maximum Read Request Size (2048). */ | |
ce9f7ed9 | 512 | if (pci_is_pcie(ha->pdev)) |
8ae6d9c7 GM |
513 | pcie_set_readrq(ha->pdev, 2048); |
514 | ||
515 | ha->chip_revision = ha->pdev->revision; | |
516 | ||
517 | return QLA_SUCCESS; | |
518 | } | |
519 | ||
520 | /** | |
521 | * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC). | |
2db6228d | 522 | * @vha: HA context |
8ae6d9c7 | 523 | * |
2db6228d | 524 | */ |
8ae6d9c7 GM |
525 | static inline void |
526 | qlafx00_soc_cpu_reset(scsi_qla_host_t *vha) | |
527 | { | |
528 | unsigned long flags = 0; | |
529 | struct qla_hw_data *ha = vha->hw; | |
530 | int i, core; | |
531 | uint32_t cnt; | |
42543fb9 AB |
532 | uint32_t reg_val; |
533 | ||
534 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
535 | ||
536 | QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0); | |
537 | QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0); | |
538 | ||
539 | /* stop the XOR DMA engines */ | |
540 | QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02); | |
541 | QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02); | |
542 | QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02); | |
543 | QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02); | |
544 | ||
545 | /* stop the IDMA engines */ | |
546 | reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840); | |
547 | reg_val &= ~(1<<12); | |
548 | QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val); | |
549 | ||
550 | reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844); | |
551 | reg_val &= ~(1<<12); | |
552 | QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val); | |
553 | ||
554 | reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848); | |
555 | reg_val &= ~(1<<12); | |
556 | QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val); | |
557 | ||
558 | reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C); | |
559 | reg_val &= ~(1<<12); | |
560 | QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val); | |
561 | ||
562 | for (i = 0; i < 100000; i++) { | |
563 | if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 && | |
564 | (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0) | |
565 | break; | |
566 | udelay(100); | |
567 | } | |
8ae6d9c7 GM |
568 | |
569 | /* Set all 4 cores in reset */ | |
570 | for (i = 0; i < 4; i++) { | |
571 | QLAFX00_SET_HBA_SOC_REG(ha, | |
572 | (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01)); | |
8ae6d9c7 GM |
573 | QLAFX00_SET_HBA_SOC_REG(ha, |
574 | (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101)); | |
575 | } | |
576 | ||
577 | /* Reset all units in Fabric */ | |
42543fb9 AB |
578 | QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101)); |
579 | ||
580 | /* */ | |
581 | QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1); | |
582 | QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0); | |
583 | ||
584 | /* Set all 4 core Memory Power Down Registers */ | |
585 | for (i = 0; i < 5; i++) { | |
586 | QLAFX00_SET_HBA_SOC_REG(ha, | |
587 | (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0)); | |
588 | } | |
8ae6d9c7 GM |
589 | |
590 | /* Reset all interrupt control registers */ | |
591 | for (i = 0; i < 115; i++) { | |
592 | QLAFX00_SET_HBA_SOC_REG(ha, | |
593 | (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0)); | |
594 | } | |
595 | ||
596 | /* Reset Timers control registers. per core */ | |
597 | for (core = 0; core < 4; core++) | |
598 | for (i = 0; i < 8; i++) | |
599 | QLAFX00_SET_HBA_SOC_REG(ha, | |
600 | (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0)); | |
601 | ||
602 | /* Reset per core IRQ ack register */ | |
603 | for (core = 0; core < 4; core++) | |
604 | QLAFX00_SET_HBA_SOC_REG(ha, | |
605 | (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF)); | |
606 | ||
607 | /* Set Fabric control and config to defaults */ | |
608 | QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2)); | |
609 | QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3)); | |
610 | ||
8ae6d9c7 GM |
611 | /* Kick in Fabric units */ |
612 | QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0)); | |
613 | ||
614 | /* Kick in Core0 to start boot process */ | |
615 | QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00)); | |
616 | ||
ec1937a2 SK |
617 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
618 | ||
8ae6d9c7 GM |
619 | /* Wait 10secs for soft-reset to complete. */ |
620 | for (cnt = 10; cnt; cnt--) { | |
621 | msleep(1000); | |
622 | barrier(); | |
623 | } | |
8ae6d9c7 GM |
624 | } |
625 | ||
626 | /** | |
627 | * qlafx00_soft_reset() - Soft Reset ISPFx00. | |
2db6228d | 628 | * @vha: HA context |
8ae6d9c7 GM |
629 | * |
630 | * Returns 0 on success. | |
631 | */ | |
3f006ac3 | 632 | int |
8ae6d9c7 GM |
633 | qlafx00_soft_reset(scsi_qla_host_t *vha) |
634 | { | |
635 | struct qla_hw_data *ha = vha->hw; | |
3f006ac3 | 636 | int rval = QLA_FUNCTION_FAILED; |
8ae6d9c7 GM |
637 | |
638 | if (unlikely(pci_channel_offline(ha->pdev) && | |
639 | ha->flags.pci_channel_io_perm_failure)) | |
3f006ac3 | 640 | return rval; |
8ae6d9c7 GM |
641 | |
642 | ha->isp_ops->disable_intrs(ha); | |
643 | qlafx00_soc_cpu_reset(vha); | |
3f006ac3 MH |
644 | |
645 | return QLA_SUCCESS; | |
8ae6d9c7 GM |
646 | } |
647 | ||
648 | /** | |
649 | * qlafx00_chip_diag() - Test ISPFx00 for proper operation. | |
2db6228d | 650 | * @vha: HA context |
8ae6d9c7 GM |
651 | * |
652 | * Returns 0 on success. | |
653 | */ | |
654 | int | |
655 | qlafx00_chip_diag(scsi_qla_host_t *vha) | |
656 | { | |
657 | int rval = 0; | |
658 | struct qla_hw_data *ha = vha->hw; | |
659 | struct req_que *req = ha->req_q_map[0]; | |
660 | ||
661 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; | |
662 | ||
663 | rval = qlafx00_mbx_reg_test(vha); | |
664 | if (rval) { | |
665 | ql_log(ql_log_warn, vha, 0x1165, | |
666 | "Failed mailbox send register test\n"); | |
667 | } else { | |
668 | /* Flag a successful rval */ | |
669 | rval = QLA_SUCCESS; | |
670 | } | |
671 | return rval; | |
672 | } | |
673 | ||
674 | void | |
675 | qlafx00_config_rings(struct scsi_qla_host *vha) | |
676 | { | |
677 | struct qla_hw_data *ha = vha->hw; | |
678 | struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; | |
8ae6d9c7 GM |
679 | |
680 | WRT_REG_DWORD(®->req_q_in, 0); | |
681 | WRT_REG_DWORD(®->req_q_out, 0); | |
682 | ||
683 | WRT_REG_DWORD(®->rsp_q_in, 0); | |
684 | WRT_REG_DWORD(®->rsp_q_out, 0); | |
685 | ||
686 | /* PCI posting */ | |
687 | RD_REG_DWORD(®->rsp_q_out); | |
688 | } | |
689 | ||
690 | char * | |
dc6d6d34 | 691 | qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) |
8ae6d9c7 GM |
692 | { |
693 | struct qla_hw_data *ha = vha->hw; | |
8ae6d9c7 | 694 | |
dc6d6d34 BVA |
695 | if (pci_is_pcie(ha->pdev)) |
696 | strlcpy(str, "PCIe iSA", str_len); | |
8ae6d9c7 GM |
697 | return str; |
698 | } | |
699 | ||
700 | char * | |
df57caba | 701 | qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) |
8ae6d9c7 GM |
702 | { |
703 | struct qla_hw_data *ha = vha->hw; | |
704 | ||
df57caba | 705 | snprintf(str, size, "%s", ha->mr.fw_version); |
8ae6d9c7 GM |
706 | return str; |
707 | } | |
708 | ||
709 | void | |
710 | qlafx00_enable_intrs(struct qla_hw_data *ha) | |
711 | { | |
712 | unsigned long flags = 0; | |
713 | ||
714 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
715 | ha->interrupts_on = 1; | |
716 | QLAFX00_ENABLE_ICNTRL_REG(ha); | |
717 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
718 | } | |
719 | ||
720 | void | |
721 | qlafx00_disable_intrs(struct qla_hw_data *ha) | |
722 | { | |
723 | unsigned long flags = 0; | |
724 | ||
725 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
726 | ha->interrupts_on = 0; | |
727 | QLAFX00_DISABLE_ICNTRL_REG(ha); | |
728 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
729 | } | |
730 | ||
8ae6d9c7 | 731 | int |
9cb78c16 | 732 | qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag) |
8ae6d9c7 | 733 | { |
faef62d1 | 734 | return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag); |
8ae6d9c7 GM |
735 | } |
736 | ||
737 | int | |
9cb78c16 | 738 | qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag) |
8ae6d9c7 | 739 | { |
faef62d1 | 740 | return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag); |
8ae6d9c7 GM |
741 | } |
742 | ||
5854771e AB |
743 | int |
744 | qlafx00_loop_reset(scsi_qla_host_t *vha) | |
745 | { | |
746 | int ret; | |
747 | struct fc_port *fcport; | |
748 | struct qla_hw_data *ha = vha->hw; | |
749 | ||
750 | if (ql2xtargetreset) { | |
751 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
752 | if (fcport->port_type != FCT_TARGET) | |
753 | continue; | |
754 | ||
755 | ret = ha->isp_ops->target_reset(fcport, 0, 0); | |
756 | if (ret != QLA_SUCCESS) { | |
757 | ql_dbg(ql_dbg_taskm, vha, 0x803d, | |
758 | "Bus Reset failed: Reset=%d " | |
759 | "d_id=%x.\n", ret, fcport->d_id.b24); | |
760 | } | |
761 | } | |
762 | } | |
763 | return QLA_SUCCESS; | |
764 | } | |
765 | ||
8ae6d9c7 GM |
766 | int |
767 | qlafx00_iospace_config(struct qla_hw_data *ha) | |
768 | { | |
769 | if (pci_request_selected_regions(ha->pdev, ha->bars, | |
770 | QLA2XXX_DRIVER_NAME)) { | |
771 | ql_log_pci(ql_log_fatal, ha->pdev, 0x014e, | |
772 | "Failed to reserve PIO/MMIO regions (%s), aborting.\n", | |
773 | pci_name(ha->pdev)); | |
774 | goto iospace_error_exit; | |
775 | } | |
776 | ||
777 | /* Use MMIO operations for all accesses. */ | |
778 | if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { | |
779 | ql_log_pci(ql_log_warn, ha->pdev, 0x014f, | |
780 | "Invalid pci I/O region size (%s).\n", | |
781 | pci_name(ha->pdev)); | |
782 | goto iospace_error_exit; | |
783 | } | |
784 | if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) { | |
785 | ql_log_pci(ql_log_warn, ha->pdev, 0x0127, | |
786 | "Invalid PCI mem BAR0 region size (%s), aborting\n", | |
787 | pci_name(ha->pdev)); | |
788 | goto iospace_error_exit; | |
789 | } | |
790 | ||
791 | ha->cregbase = | |
792 | ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00); | |
793 | if (!ha->cregbase) { | |
794 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0128, | |
795 | "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev)); | |
796 | goto iospace_error_exit; | |
797 | } | |
798 | ||
799 | if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) { | |
800 | ql_log_pci(ql_log_warn, ha->pdev, 0x0129, | |
801 | "region #2 not an MMIO resource (%s), aborting\n", | |
802 | pci_name(ha->pdev)); | |
803 | goto iospace_error_exit; | |
804 | } | |
805 | if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) { | |
806 | ql_log_pci(ql_log_warn, ha->pdev, 0x012a, | |
807 | "Invalid PCI mem BAR2 region size (%s), aborting\n", | |
808 | pci_name(ha->pdev)); | |
809 | goto iospace_error_exit; | |
810 | } | |
811 | ||
812 | ha->iobase = | |
813 | ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00); | |
814 | if (!ha->iobase) { | |
815 | ql_log_pci(ql_log_fatal, ha->pdev, 0x012b, | |
816 | "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev)); | |
817 | goto iospace_error_exit; | |
818 | } | |
819 | ||
820 | /* Determine queue resources */ | |
821 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
822 | ||
823 | ql_log_pci(ql_log_info, ha->pdev, 0x012c, | |
824 | "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n", | |
825 | ha->bars, ha->cregbase, ha->iobase); | |
826 | ||
827 | return 0; | |
828 | ||
829 | iospace_error_exit: | |
830 | return -ENOMEM; | |
831 | } | |
832 | ||
833 | static void | |
834 | qlafx00_save_queue_ptrs(struct scsi_qla_host *vha) | |
835 | { | |
836 | struct qla_hw_data *ha = vha->hw; | |
837 | struct req_que *req = ha->req_q_map[0]; | |
838 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
839 | ||
840 | req->length_fx00 = req->length; | |
841 | req->ring_fx00 = req->ring; | |
842 | req->dma_fx00 = req->dma; | |
843 | ||
844 | rsp->length_fx00 = rsp->length; | |
845 | rsp->ring_fx00 = rsp->ring; | |
846 | rsp->dma_fx00 = rsp->dma; | |
847 | ||
848 | ql_dbg(ql_dbg_init, vha, 0x012d, | |
849 | "req: %p, ring_fx00: %p, length_fx00: 0x%x," | |
850 | "req->dma_fx00: 0x%llx\n", req, req->ring_fx00, | |
851 | req->length_fx00, (u64)req->dma_fx00); | |
852 | ||
853 | ql_dbg(ql_dbg_init, vha, 0x012e, | |
854 | "rsp: %p, ring_fx00: %p, length_fx00: 0x%x," | |
855 | "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00, | |
856 | rsp->length_fx00, (u64)rsp->dma_fx00); | |
857 | } | |
858 | ||
859 | static int | |
860 | qlafx00_config_queues(struct scsi_qla_host *vha) | |
861 | { | |
862 | struct qla_hw_data *ha = vha->hw; | |
863 | struct req_que *req = ha->req_q_map[0]; | |
864 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
865 | dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2); | |
866 | ||
867 | req->length = ha->req_que_len; | |
8dfa4b5a | 868 | req->ring = (void __force *)ha->iobase + ha->req_que_off; |
8ae6d9c7 GM |
869 | req->dma = bar2_hdl + ha->req_que_off; |
870 | if ((!req->ring) || (req->length == 0)) { | |
871 | ql_log_pci(ql_log_info, ha->pdev, 0x012f, | |
872 | "Unable to allocate memory for req_ring\n"); | |
873 | return QLA_FUNCTION_FAILED; | |
874 | } | |
875 | ||
876 | ql_dbg(ql_dbg_init, vha, 0x0130, | |
877 | "req: %p req_ring pointer %p req len 0x%x " | |
878 | "req off 0x%x\n, req->dma: 0x%llx", | |
879 | req, req->ring, req->length, | |
880 | ha->req_que_off, (u64)req->dma); | |
881 | ||
882 | rsp->length = ha->rsp_que_len; | |
8dfa4b5a | 883 | rsp->ring = (void __force *)ha->iobase + ha->rsp_que_off; |
8ae6d9c7 GM |
884 | rsp->dma = bar2_hdl + ha->rsp_que_off; |
885 | if ((!rsp->ring) || (rsp->length == 0)) { | |
886 | ql_log_pci(ql_log_info, ha->pdev, 0x0131, | |
887 | "Unable to allocate memory for rsp_ring\n"); | |
888 | return QLA_FUNCTION_FAILED; | |
889 | } | |
890 | ||
891 | ql_dbg(ql_dbg_init, vha, 0x0132, | |
892 | "rsp: %p rsp_ring pointer %p rsp len 0x%x " | |
893 | "rsp off 0x%x, rsp->dma: 0x%llx\n", | |
894 | rsp, rsp->ring, rsp->length, | |
895 | ha->rsp_que_off, (u64)rsp->dma); | |
896 | ||
897 | return QLA_SUCCESS; | |
898 | } | |
899 | ||
900 | static int | |
901 | qlafx00_init_fw_ready(scsi_qla_host_t *vha) | |
902 | { | |
903 | int rval = 0; | |
904 | unsigned long wtime; | |
905 | uint16_t wait_time; /* Wait time */ | |
906 | struct qla_hw_data *ha = vha->hw; | |
907 | struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; | |
908 | uint32_t aenmbx, aenmbx7 = 0; | |
f9a2a543 | 909 | uint32_t pseudo_aen; |
8ae6d9c7 GM |
910 | uint32_t state[5]; |
911 | bool done = false; | |
912 | ||
913 | /* 30 seconds wait - Adjust if required */ | |
914 | wait_time = 30; | |
915 | ||
f9a2a543 AB |
916 | pseudo_aen = RD_REG_DWORD(®->pseudoaen); |
917 | if (pseudo_aen == 1) { | |
918 | aenmbx7 = RD_REG_DWORD(®->initval7); | |
919 | ha->mbx_intr_code = MSW(aenmbx7); | |
920 | ha->rqstq_intr_code = LSW(aenmbx7); | |
921 | rval = qlafx00_driver_shutdown(vha, 10); | |
922 | if (rval != QLA_SUCCESS) | |
923 | qlafx00_soft_reset(vha); | |
924 | } | |
925 | ||
8ae6d9c7 GM |
926 | /* wait time before firmware ready */ |
927 | wtime = jiffies + (wait_time * HZ); | |
928 | do { | |
929 | aenmbx = RD_REG_DWORD(®->aenmailbox0); | |
930 | barrier(); | |
931 | ql_dbg(ql_dbg_mbx, vha, 0x0133, | |
932 | "aenmbx: 0x%x\n", aenmbx); | |
933 | ||
934 | switch (aenmbx) { | |
935 | case MBA_FW_NOT_STARTED: | |
936 | case MBA_FW_STARTING: | |
937 | break; | |
938 | ||
939 | case MBA_SYSTEM_ERR: | |
940 | case MBA_REQ_TRANSFER_ERR: | |
941 | case MBA_RSP_TRANSFER_ERR: | |
942 | case MBA_FW_INIT_FAILURE: | |
943 | qlafx00_soft_reset(vha); | |
944 | break; | |
945 | ||
946 | case MBA_FW_RESTART_CMPLT: | |
947 | /* Set the mbx and rqstq intr code */ | |
948 | aenmbx7 = RD_REG_DWORD(®->aenmailbox7); | |
949 | ha->mbx_intr_code = MSW(aenmbx7); | |
950 | ha->rqstq_intr_code = LSW(aenmbx7); | |
951 | ha->req_que_off = RD_REG_DWORD(®->aenmailbox1); | |
952 | ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3); | |
953 | ha->req_que_len = RD_REG_DWORD(®->aenmailbox5); | |
954 | ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6); | |
955 | WRT_REG_DWORD(®->aenmailbox0, 0); | |
956 | RD_REG_DWORD_RELAXED(®->aenmailbox0); | |
957 | ql_dbg(ql_dbg_init, vha, 0x0134, | |
958 | "f/w returned mbx_intr_code: 0x%x, " | |
959 | "rqstq_intr_code: 0x%x\n", | |
960 | ha->mbx_intr_code, ha->rqstq_intr_code); | |
961 | QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS); | |
962 | rval = QLA_SUCCESS; | |
963 | done = true; | |
964 | break; | |
965 | ||
966 | default: | |
0f8cdff5 AB |
967 | if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS) |
968 | break; | |
969 | ||
8ae6d9c7 GM |
970 | /* If fw is apparently not ready. In order to continue, |
971 | * we might need to issue Mbox cmd, but the problem is | |
972 | * that the DoorBell vector values that come with the | |
973 | * 8060 AEN are most likely gone by now (and thus no | |
974 | * bell would be rung on the fw side when mbox cmd is | |
975 | * issued). We have to therefore grab the 8060 AEN | |
976 | * shadow regs (filled in by FW when the last 8060 | |
977 | * AEN was being posted). | |
978 | * Do the following to determine what is needed in | |
979 | * order to get the FW ready: | |
980 | * 1. reload the 8060 AEN values from the shadow regs | |
981 | * 2. clear int status to get rid of possible pending | |
982 | * interrupts | |
983 | * 3. issue Get FW State Mbox cmd to determine fw state | |
984 | * Set the mbx and rqstq intr code from Shadow Regs | |
985 | */ | |
986 | aenmbx7 = RD_REG_DWORD(®->initval7); | |
987 | ha->mbx_intr_code = MSW(aenmbx7); | |
988 | ha->rqstq_intr_code = LSW(aenmbx7); | |
989 | ha->req_que_off = RD_REG_DWORD(®->initval1); | |
990 | ha->rsp_que_off = RD_REG_DWORD(®->initval3); | |
991 | ha->req_que_len = RD_REG_DWORD(®->initval5); | |
992 | ha->rsp_que_len = RD_REG_DWORD(®->initval6); | |
993 | ql_dbg(ql_dbg_init, vha, 0x0135, | |
994 | "f/w returned mbx_intr_code: 0x%x, " | |
995 | "rqstq_intr_code: 0x%x\n", | |
996 | ha->mbx_intr_code, ha->rqstq_intr_code); | |
997 | QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS); | |
998 | ||
999 | /* Get the FW state */ | |
1000 | rval = qlafx00_get_firmware_state(vha, state); | |
1001 | if (rval != QLA_SUCCESS) { | |
1002 | /* Retry if timer has not expired */ | |
1003 | break; | |
1004 | } | |
1005 | ||
1006 | if (state[0] == FSTATE_FX00_CONFIG_WAIT) { | |
1007 | /* Firmware is waiting to be | |
1008 | * initialized by driver | |
1009 | */ | |
1010 | rval = QLA_SUCCESS; | |
1011 | done = true; | |
1012 | break; | |
1013 | } | |
1014 | ||
1015 | /* Issue driver shutdown and wait until f/w recovers. | |
1016 | * Driver should continue to poll until 8060 AEN is | |
1017 | * received indicating firmware recovery. | |
1018 | */ | |
1019 | ql_dbg(ql_dbg_init, vha, 0x0136, | |
1020 | "Sending Driver shutdown fw_state 0x%x\n", | |
1021 | state[0]); | |
1022 | ||
1023 | rval = qlafx00_driver_shutdown(vha, 10); | |
1024 | if (rval != QLA_SUCCESS) { | |
1025 | rval = QLA_FUNCTION_FAILED; | |
1026 | break; | |
1027 | } | |
1028 | msleep(500); | |
1029 | ||
1030 | wtime = jiffies + (wait_time * HZ); | |
1031 | break; | |
1032 | } | |
1033 | ||
1034 | if (!done) { | |
1035 | if (time_after_eq(jiffies, wtime)) { | |
1036 | ql_dbg(ql_dbg_init, vha, 0x0137, | |
1037 | "Init f/w failed: aen[7]: 0x%x\n", | |
1038 | RD_REG_DWORD(®->aenmailbox7)); | |
1039 | rval = QLA_FUNCTION_FAILED; | |
1040 | done = true; | |
1041 | break; | |
1042 | } | |
1043 | /* Delay for a while */ | |
1044 | msleep(500); | |
1045 | } | |
1046 | } while (!done); | |
1047 | ||
1048 | if (rval) | |
1049 | ql_dbg(ql_dbg_init, vha, 0x0138, | |
1050 | "%s **** FAILED ****.\n", __func__); | |
1051 | else | |
1052 | ql_dbg(ql_dbg_init, vha, 0x0139, | |
1053 | "%s **** SUCCESS ****.\n", __func__); | |
1054 | ||
1055 | return rval; | |
1056 | } | |
1057 | ||
1058 | /* | |
1059 | * qlafx00_fw_ready() - Waits for firmware ready. | |
1060 | * @ha: HA context | |
1061 | * | |
1062 | * Returns 0 on success. | |
1063 | */ | |
1064 | int | |
1065 | qlafx00_fw_ready(scsi_qla_host_t *vha) | |
1066 | { | |
1067 | int rval; | |
1068 | unsigned long wtime; | |
1069 | uint16_t wait_time; /* Wait time if loop is coming ready */ | |
1070 | uint32_t state[5]; | |
1071 | ||
1072 | rval = QLA_SUCCESS; | |
1073 | ||
1074 | wait_time = 10; | |
1075 | ||
1076 | /* wait time before firmware ready */ | |
1077 | wtime = jiffies + (wait_time * HZ); | |
1078 | ||
1079 | /* Wait for ISP to finish init */ | |
1080 | if (!vha->flags.init_done) | |
1081 | ql_dbg(ql_dbg_init, vha, 0x013a, | |
1082 | "Waiting for init to complete...\n"); | |
1083 | ||
1084 | do { | |
1085 | rval = qlafx00_get_firmware_state(vha, state); | |
1086 | ||
1087 | if (rval == QLA_SUCCESS) { | |
1088 | if (state[0] == FSTATE_FX00_INITIALIZED) { | |
1089 | ql_dbg(ql_dbg_init, vha, 0x013b, | |
1090 | "fw_state=%x\n", state[0]); | |
1091 | rval = QLA_SUCCESS; | |
1092 | break; | |
1093 | } | |
1094 | } | |
1095 | rval = QLA_FUNCTION_FAILED; | |
1096 | ||
1097 | if (time_after_eq(jiffies, wtime)) | |
1098 | break; | |
1099 | ||
1100 | /* Delay for a while */ | |
1101 | msleep(500); | |
1102 | ||
1103 | ql_dbg(ql_dbg_init, vha, 0x013c, | |
1104 | "fw_state=%x curr time=%lx.\n", state[0], jiffies); | |
1105 | } while (1); | |
1106 | ||
1107 | ||
1108 | if (rval) | |
1109 | ql_dbg(ql_dbg_init, vha, 0x013d, | |
1110 | "Firmware ready **** FAILED ****.\n"); | |
1111 | else | |
1112 | ql_dbg(ql_dbg_init, vha, 0x013e, | |
1113 | "Firmware ready **** SUCCESS ****.\n"); | |
1114 | ||
1115 | return rval; | |
1116 | } | |
1117 | ||
1118 | static int | |
1119 | qlafx00_find_all_targets(scsi_qla_host_t *vha, | |
1120 | struct list_head *new_fcports) | |
1121 | { | |
1122 | int rval; | |
1123 | uint16_t tgt_id; | |
1124 | fc_port_t *fcport, *new_fcport; | |
1125 | int found; | |
1126 | struct qla_hw_data *ha = vha->hw; | |
1127 | ||
1128 | rval = QLA_SUCCESS; | |
1129 | ||
1130 | if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags)) | |
1131 | return QLA_FUNCTION_FAILED; | |
1132 | ||
1133 | if ((atomic_read(&vha->loop_down_timer) || | |
1134 | STATE_TRANSITION(vha))) { | |
1135 | atomic_set(&vha->loop_down_timer, 0); | |
1136 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
1137 | return QLA_FUNCTION_FAILED; | |
1138 | } | |
1139 | ||
1140 | ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088, | |
1141 | "Listing Target bit map...\n"); | |
f8f97b0c JC |
1142 | ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha, 0x2089, |
1143 | ha->gid_list, 32); | |
8ae6d9c7 GM |
1144 | |
1145 | /* Allocate temporary rmtport for any new rmtports discovered. */ | |
1146 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); | |
1147 | if (new_fcport == NULL) | |
1148 | return QLA_MEMORY_ALLOC_FAILED; | |
1149 | ||
1150 | for_each_set_bit(tgt_id, (void *)ha->gid_list, | |
1151 | QLAFX00_TGT_NODE_LIST_SIZE) { | |
1152 | ||
1153 | /* Send get target node info */ | |
1154 | new_fcport->tgt_id = tgt_id; | |
1155 | rval = qlafx00_fx_disc(vha, new_fcport, | |
1156 | FXDISC_GET_TGT_NODE_INFO); | |
1157 | if (rval != QLA_SUCCESS) { | |
1158 | ql_log(ql_log_warn, vha, 0x208a, | |
1159 | "Target info scan failed -- assuming zero-entry " | |
1160 | "result...\n"); | |
1161 | continue; | |
1162 | } | |
1163 | ||
1164 | /* Locate matching device in database. */ | |
1165 | found = 0; | |
1166 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
1167 | if (memcmp(new_fcport->port_name, | |
1168 | fcport->port_name, WWN_SIZE)) | |
1169 | continue; | |
1170 | ||
1171 | found++; | |
1172 | ||
1173 | /* | |
1174 | * If tgt_id is same and state FCS_ONLINE, nothing | |
1175 | * changed. | |
1176 | */ | |
1177 | if (fcport->tgt_id == new_fcport->tgt_id && | |
1178 | atomic_read(&fcport->state) == FCS_ONLINE) | |
1179 | break; | |
1180 | ||
1181 | /* | |
1182 | * Tgt ID changed or device was marked to be updated. | |
1183 | */ | |
1184 | ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b, | |
1185 | "TGT-ID Change(%s): Present tgt id: " | |
1186 | "0x%x state: 0x%x " | |
1187 | "wwnn = %llx wwpn = %llx.\n", | |
1188 | __func__, fcport->tgt_id, | |
1189 | atomic_read(&fcport->state), | |
1190 | (unsigned long long)wwn_to_u64(fcport->node_name), | |
1191 | (unsigned long long)wwn_to_u64(fcport->port_name)); | |
1192 | ||
1193 | ql_log(ql_log_info, vha, 0x208c, | |
1194 | "TGT-ID Announce(%s): Discovered tgt " | |
1195 | "id 0x%x wwnn = %llx " | |
1196 | "wwpn = %llx.\n", __func__, new_fcport->tgt_id, | |
1197 | (unsigned long long) | |
1198 | wwn_to_u64(new_fcport->node_name), | |
1199 | (unsigned long long) | |
1200 | wwn_to_u64(new_fcport->port_name)); | |
1201 | ||
1202 | if (atomic_read(&fcport->state) != FCS_ONLINE) { | |
1203 | fcport->old_tgt_id = fcport->tgt_id; | |
1204 | fcport->tgt_id = new_fcport->tgt_id; | |
1205 | ql_log(ql_log_info, vha, 0x208d, | |
1206 | "TGT-ID: New fcport Added: %p\n", fcport); | |
1207 | qla2x00_update_fcport(vha, fcport); | |
1208 | } else { | |
1209 | ql_log(ql_log_info, vha, 0x208e, | |
1210 | " Existing TGT-ID %x did not get " | |
1211 | " offline event from firmware.\n", | |
1212 | fcport->old_tgt_id); | |
1213 | qla2x00_mark_device_lost(vha, fcport, 0, 0); | |
1214 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
1215 | kfree(new_fcport); | |
1216 | return rval; | |
1217 | } | |
1218 | break; | |
1219 | } | |
1220 | ||
1221 | if (found) | |
1222 | continue; | |
1223 | ||
1224 | /* If device was not in our fcports list, then add it. */ | |
1225 | list_add_tail(&new_fcport->list, new_fcports); | |
1226 | ||
1227 | /* Allocate a new replacement fcport. */ | |
1228 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); | |
1229 | if (new_fcport == NULL) | |
1230 | return QLA_MEMORY_ALLOC_FAILED; | |
1231 | } | |
1232 | ||
1233 | kfree(new_fcport); | |
1234 | return rval; | |
1235 | } | |
1236 | ||
1237 | /* | |
1238 | * qlafx00_configure_all_targets | |
1239 | * Setup target devices with node ID's. | |
1240 | * | |
1241 | * Input: | |
1242 | * ha = adapter block pointer. | |
1243 | * | |
1244 | * Returns: | |
1245 | * 0 = success. | |
1246 | * BIT_0 = error | |
1247 | */ | |
1248 | static int | |
1249 | qlafx00_configure_all_targets(scsi_qla_host_t *vha) | |
1250 | { | |
1251 | int rval; | |
1252 | fc_port_t *fcport, *rmptemp; | |
1253 | LIST_HEAD(new_fcports); | |
1254 | ||
1255 | rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport, | |
1256 | FXDISC_GET_TGT_NODE_LIST); | |
1257 | if (rval != QLA_SUCCESS) { | |
1258 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
1259 | return rval; | |
1260 | } | |
1261 | ||
1262 | rval = qlafx00_find_all_targets(vha, &new_fcports); | |
1263 | if (rval != QLA_SUCCESS) { | |
1264 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
1265 | return rval; | |
1266 | } | |
1267 | ||
1268 | /* | |
1269 | * Delete all previous devices marked lost. | |
1270 | */ | |
1271 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
1272 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
1273 | break; | |
1274 | ||
1275 | if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) { | |
1276 | if (fcport->port_type != FCT_INITIATOR) | |
1277 | qla2x00_mark_device_lost(vha, fcport, 0, 0); | |
1278 | } | |
1279 | } | |
1280 | ||
1281 | /* | |
1282 | * Add the new devices to our devices list. | |
1283 | */ | |
1284 | list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) { | |
1285 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
1286 | break; | |
1287 | ||
1288 | qla2x00_update_fcport(vha, fcport); | |
1289 | list_move_tail(&fcport->list, &vha->vp_fcports); | |
1290 | ql_log(ql_log_info, vha, 0x208f, | |
1291 | "Attach new target id 0x%x wwnn = %llx " | |
1292 | "wwpn = %llx.\n", | |
1293 | fcport->tgt_id, | |
1294 | (unsigned long long)wwn_to_u64(fcport->node_name), | |
1295 | (unsigned long long)wwn_to_u64(fcport->port_name)); | |
1296 | } | |
1297 | ||
1298 | /* Free all new device structures not processed. */ | |
1299 | list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) { | |
1300 | list_del(&fcport->list); | |
1301 | kfree(fcport); | |
1302 | } | |
1303 | ||
1304 | return rval; | |
1305 | } | |
1306 | ||
1307 | /* | |
1308 | * qlafx00_configure_devices | |
1309 | * Updates Fibre Channel Device Database with what is actually on loop. | |
1310 | * | |
1311 | * Input: | |
1312 | * ha = adapter block pointer. | |
1313 | * | |
1314 | * Returns: | |
1315 | * 0 = success. | |
1316 | * 1 = error. | |
1317 | * 2 = database was full and device was not configured. | |
1318 | */ | |
1319 | int | |
1320 | qlafx00_configure_devices(scsi_qla_host_t *vha) | |
1321 | { | |
1322 | int rval; | |
52c82823 | 1323 | unsigned long flags; |
bd432bb5 | 1324 | |
8ae6d9c7 GM |
1325 | rval = QLA_SUCCESS; |
1326 | ||
52c82823 | 1327 | flags = vha->dpc_flags; |
8ae6d9c7 GM |
1328 | |
1329 | ql_dbg(ql_dbg_disc, vha, 0x2090, | |
1330 | "Configure devices -- dpc flags =0x%lx\n", flags); | |
1331 | ||
1332 | rval = qlafx00_configure_all_targets(vha); | |
1333 | ||
1334 | if (rval == QLA_SUCCESS) { | |
1335 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { | |
1336 | rval = QLA_FUNCTION_FAILED; | |
1337 | } else { | |
1338 | atomic_set(&vha->loop_state, LOOP_READY); | |
1339 | ql_log(ql_log_info, vha, 0x2091, | |
1340 | "Device Ready\n"); | |
1341 | } | |
1342 | } | |
1343 | ||
1344 | if (rval) { | |
1345 | ql_dbg(ql_dbg_disc, vha, 0x2092, | |
1346 | "%s *** FAILED ***.\n", __func__); | |
1347 | } else { | |
1348 | ql_dbg(ql_dbg_disc, vha, 0x2093, | |
1349 | "%s: exiting normally.\n", __func__); | |
1350 | } | |
1351 | return rval; | |
1352 | } | |
1353 | ||
1354 | static void | |
71e56003 | 1355 | qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp) |
8ae6d9c7 GM |
1356 | { |
1357 | struct qla_hw_data *ha = vha->hw; | |
1358 | fc_port_t *fcport; | |
1359 | ||
1360 | vha->flags.online = 0; | |
8ae6d9c7 | 1361 | ha->mr.fw_hbt_en = 0; |
8ae6d9c7 | 1362 | |
71e56003 AB |
1363 | if (!critemp) { |
1364 | ha->flags.chip_reset_done = 0; | |
1365 | clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
1366 | vha->qla_stats.total_isp_aborts++; | |
1367 | ql_log(ql_log_info, vha, 0x013f, | |
1368 | "Performing ISP error recovery - ha = %p.\n", ha); | |
1369 | ha->isp_ops->reset_chip(vha); | |
1370 | } | |
8ae6d9c7 GM |
1371 | |
1372 | if (atomic_read(&vha->loop_state) != LOOP_DOWN) { | |
1373 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
1374 | atomic_set(&vha->loop_down_timer, | |
1375 | QLAFX00_LOOP_DOWN_TIME); | |
1376 | } else { | |
1377 | if (!atomic_read(&vha->loop_down_timer)) | |
1378 | atomic_set(&vha->loop_down_timer, | |
1379 | QLAFX00_LOOP_DOWN_TIME); | |
1380 | } | |
1381 | ||
1382 | /* Clear all async request states across all VPs. */ | |
1383 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
1384 | fcport->flags = 0; | |
1385 | if (atomic_read(&fcport->state) == FCS_ONLINE) | |
1386 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); | |
1387 | } | |
1388 | ||
1389 | if (!ha->flags.eeh_busy) { | |
71e56003 AB |
1390 | if (critemp) { |
1391 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); | |
1392 | } else { | |
1393 | /* Requeue all commands in outstanding command list. */ | |
1394 | qla2x00_abort_all_cmds(vha, DID_RESET << 16); | |
1395 | } | |
8ae6d9c7 GM |
1396 | } |
1397 | ||
1398 | qla2x00_free_irqs(vha); | |
71e56003 AB |
1399 | if (critemp) |
1400 | set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags); | |
1401 | else | |
1402 | set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags); | |
8ae6d9c7 GM |
1403 | |
1404 | /* Clear the Interrupts */ | |
1405 | QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS); | |
1406 | ||
1407 | ql_log(ql_log_info, vha, 0x0140, | |
1408 | "%s Done done - ha=%p.\n", __func__, ha); | |
1409 | } | |
1410 | ||
1411 | /** | |
1412 | * qlafx00_init_response_q_entries() - Initializes response queue entries. | |
2db6228d | 1413 | * @rsp: response queue |
8ae6d9c7 GM |
1414 | * |
1415 | * Beginning of request ring has initialization control block already built | |
1416 | * by nvram config routine. | |
1417 | * | |
1418 | * Returns 0 on success. | |
1419 | */ | |
1420 | void | |
1421 | qlafx00_init_response_q_entries(struct rsp_que *rsp) | |
1422 | { | |
1423 | uint16_t cnt; | |
1424 | response_t *pkt; | |
1425 | ||
1426 | rsp->ring_ptr = rsp->ring; | |
1427 | rsp->ring_index = 0; | |
1428 | rsp->status_srb = NULL; | |
1429 | pkt = rsp->ring_ptr; | |
1430 | for (cnt = 0; cnt < rsp->length; cnt++) { | |
1431 | pkt->signature = RESPONSE_PROCESSED; | |
8dfa4b5a | 1432 | WRT_REG_DWORD((void __force __iomem *)&pkt->signature, |
1f8deefe | 1433 | RESPONSE_PROCESSED); |
8ae6d9c7 GM |
1434 | pkt++; |
1435 | } | |
1436 | } | |
1437 | ||
1438 | int | |
1439 | qlafx00_rescan_isp(scsi_qla_host_t *vha) | |
1440 | { | |
1441 | uint32_t status = QLA_FUNCTION_FAILED; | |
1442 | struct qla_hw_data *ha = vha->hw; | |
1443 | struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; | |
1444 | uint32_t aenmbx7; | |
1445 | ||
1446 | qla2x00_request_irqs(ha, ha->rsp_q_map[0]); | |
1447 | ||
1448 | aenmbx7 = RD_REG_DWORD(®->aenmailbox7); | |
1449 | ha->mbx_intr_code = MSW(aenmbx7); | |
1450 | ha->rqstq_intr_code = LSW(aenmbx7); | |
1451 | ha->req_que_off = RD_REG_DWORD(®->aenmailbox1); | |
1452 | ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3); | |
1453 | ha->req_que_len = RD_REG_DWORD(®->aenmailbox5); | |
1454 | ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6); | |
1455 | ||
1456 | ql_dbg(ql_dbg_disc, vha, 0x2094, | |
1457 | "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x " | |
1458 | " Req que offset 0x%x Rsp que offset 0x%x\n", | |
1459 | ha->mbx_intr_code, ha->rqstq_intr_code, | |
1460 | ha->req_que_off, ha->rsp_que_len); | |
1461 | ||
1462 | /* Clear the Interrupts */ | |
1463 | QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS); | |
1464 | ||
1465 | status = qla2x00_init_rings(vha); | |
1466 | if (!status) { | |
1467 | vha->flags.online = 1; | |
1468 | ||
1469 | /* if no cable then assume it's good */ | |
1470 | if ((vha->device_flags & DFLG_NO_CABLE)) | |
1471 | status = 0; | |
1472 | /* Register system information */ | |
1473 | if (qlafx00_fx_disc(vha, | |
1474 | &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO)) | |
1475 | ql_dbg(ql_dbg_disc, vha, 0x2095, | |
1476 | "failed to register host info\n"); | |
1477 | } | |
1478 | scsi_unblock_requests(vha->host); | |
1479 | return status; | |
1480 | } | |
1481 | ||
1482 | void | |
1483 | qlafx00_timer_routine(scsi_qla_host_t *vha) | |
1484 | { | |
1485 | struct qla_hw_data *ha = vha->hw; | |
1486 | uint32_t fw_heart_beat; | |
1487 | uint32_t aenmbx0; | |
1488 | struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; | |
71e56003 | 1489 | uint32_t tempc; |
8ae6d9c7 GM |
1490 | |
1491 | /* Check firmware health */ | |
1492 | if (ha->mr.fw_hbt_cnt) | |
1493 | ha->mr.fw_hbt_cnt--; | |
1494 | else { | |
1495 | if ((!ha->flags.mr_reset_hdlr_active) && | |
1496 | (!test_bit(UNLOADING, &vha->dpc_flags)) && | |
1497 | (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && | |
1498 | (ha->mr.fw_hbt_en)) { | |
1499 | fw_heart_beat = RD_REG_DWORD(®->fwheartbeat); | |
1500 | if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) { | |
1501 | ha->mr.old_fw_hbt_cnt = fw_heart_beat; | |
1502 | ha->mr.fw_hbt_miss_cnt = 0; | |
1503 | } else { | |
1504 | ha->mr.fw_hbt_miss_cnt++; | |
1505 | if (ha->mr.fw_hbt_miss_cnt == | |
1506 | QLAFX00_HEARTBEAT_MISS_CNT) { | |
1507 | set_bit(ISP_ABORT_NEEDED, | |
1508 | &vha->dpc_flags); | |
1509 | qla2xxx_wake_dpc(vha); | |
1510 | ha->mr.fw_hbt_miss_cnt = 0; | |
1511 | } | |
1512 | } | |
1513 | } | |
1514 | ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; | |
1515 | } | |
1516 | ||
1517 | if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) { | |
1518 | /* Reset recovery to be performed in timer routine */ | |
1519 | aenmbx0 = RD_REG_DWORD(®->aenmailbox0); | |
1520 | if (ha->mr.fw_reset_timer_exp) { | |
1521 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
1522 | qla2xxx_wake_dpc(vha); | |
1523 | ha->mr.fw_reset_timer_exp = 0; | |
1524 | } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) { | |
1525 | /* Wake up DPC to rescan the targets */ | |
1526 | set_bit(FX00_TARGET_SCAN, &vha->dpc_flags); | |
1527 | clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags); | |
1528 | qla2xxx_wake_dpc(vha); | |
1529 | ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; | |
1530 | } else if ((aenmbx0 == MBA_FW_STARTING) && | |
1531 | (!ha->mr.fw_hbt_en)) { | |
1532 | ha->mr.fw_hbt_en = 1; | |
1533 | } else if (!ha->mr.fw_reset_timer_tick) { | |
1534 | if (aenmbx0 == ha->mr.old_aenmbx0_state) | |
1535 | ha->mr.fw_reset_timer_exp = 1; | |
1536 | ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; | |
1537 | } else if (aenmbx0 == 0xFFFFFFFF) { | |
1538 | uint32_t data0, data1; | |
1539 | ||
1540 | data0 = QLAFX00_RD_REG(ha, | |
1541 | QLAFX00_BAR1_BASE_ADDR_REG); | |
1542 | data1 = QLAFX00_RD_REG(ha, | |
1543 | QLAFX00_PEX0_WIN0_BASE_ADDR_REG); | |
1544 | ||
1545 | data0 &= 0xffff0000; | |
1546 | data1 &= 0x0000ffff; | |
1547 | ||
1548 | QLAFX00_WR_REG(ha, | |
1549 | QLAFX00_PEX0_WIN0_BASE_ADDR_REG, | |
1550 | (data0 | data1)); | |
1551 | } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) { | |
1552 | ha->mr.fw_reset_timer_tick = | |
1553 | QLAFX00_MAX_RESET_INTERVAL; | |
b6511d99 AB |
1554 | } else if (aenmbx0 == MBA_FW_RESET_FCT) { |
1555 | ha->mr.fw_reset_timer_tick = | |
1556 | QLAFX00_MAX_RESET_INTERVAL; | |
8ae6d9c7 | 1557 | } |
e475f9c0 JK |
1558 | if (ha->mr.old_aenmbx0_state != aenmbx0) { |
1559 | ha->mr.old_aenmbx0_state = aenmbx0; | |
1560 | ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; | |
1561 | } | |
8ae6d9c7 GM |
1562 | ha->mr.fw_reset_timer_tick--; |
1563 | } | |
71e56003 AB |
1564 | if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) { |
1565 | /* | |
1566 | * Critical temperature recovery to be | |
1567 | * performed in timer routine | |
1568 | */ | |
1569 | if (ha->mr.fw_critemp_timer_tick == 0) { | |
1570 | tempc = QLAFX00_GET_TEMPERATURE(ha); | |
6ddcfef7 | 1571 | ql_dbg(ql_dbg_timer, vha, 0x6012, |
71e56003 AB |
1572 | "ISPFx00(%s): Critical temp timer, " |
1573 | "current SOC temperature: %d\n", | |
1574 | __func__, tempc); | |
1575 | if (tempc < ha->mr.critical_temperature) { | |
1576 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
1577 | clear_bit(FX00_CRITEMP_RECOVERY, | |
1578 | &vha->dpc_flags); | |
1579 | qla2xxx_wake_dpc(vha); | |
1580 | } | |
1581 | ha->mr.fw_critemp_timer_tick = | |
1582 | QLAFX00_CRITEMP_INTERVAL; | |
1583 | } else { | |
1584 | ha->mr.fw_critemp_timer_tick--; | |
1585 | } | |
1586 | } | |
e8f5e95d AB |
1587 | if (ha->mr.host_info_resend) { |
1588 | /* | |
1589 | * Incomplete host info might be sent to firmware | |
1590 | * durinng system boot - info should be resend | |
1591 | */ | |
1592 | if (ha->mr.hinfo_resend_timer_tick == 0) { | |
1593 | ha->mr.host_info_resend = false; | |
1594 | set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags); | |
1595 | ha->mr.hinfo_resend_timer_tick = | |
1596 | QLAFX00_HINFO_RESEND_INTERVAL; | |
1597 | qla2xxx_wake_dpc(vha); | |
1598 | } else { | |
1599 | ha->mr.hinfo_resend_timer_tick--; | |
1600 | } | |
1601 | } | |
1602 | ||
8ae6d9c7 GM |
1603 | } |
1604 | ||
1605 | /* | |
1606 | * qlfx00a_reset_initialize | |
1607 | * Re-initialize after a iSA device reset. | |
1608 | * | |
1609 | * Input: | |
1610 | * ha = adapter block pointer. | |
1611 | * | |
1612 | * Returns: | |
1613 | * 0 = success | |
1614 | */ | |
1615 | int | |
1616 | qlafx00_reset_initialize(scsi_qla_host_t *vha) | |
1617 | { | |
1618 | struct qla_hw_data *ha = vha->hw; | |
1619 | ||
1620 | if (vha->device_flags & DFLG_DEV_FAILED) { | |
1621 | ql_dbg(ql_dbg_init, vha, 0x0142, | |
1622 | "Device in failed state\n"); | |
1623 | return QLA_SUCCESS; | |
1624 | } | |
1625 | ||
1626 | ha->flags.mr_reset_hdlr_active = 1; | |
1627 | ||
1628 | if (vha->flags.online) { | |
1629 | scsi_block_requests(vha->host); | |
71e56003 | 1630 | qlafx00_abort_isp_cleanup(vha, false); |
8ae6d9c7 GM |
1631 | } |
1632 | ||
1633 | ql_log(ql_log_info, vha, 0x0143, | |
1634 | "(%s): succeeded.\n", __func__); | |
1635 | ha->flags.mr_reset_hdlr_active = 0; | |
1636 | return QLA_SUCCESS; | |
1637 | } | |
1638 | ||
1639 | /* | |
1640 | * qlafx00_abort_isp | |
1641 | * Resets ISP and aborts all outstanding commands. | |
1642 | * | |
1643 | * Input: | |
1644 | * ha = adapter block pointer. | |
1645 | * | |
1646 | * Returns: | |
1647 | * 0 = success | |
1648 | */ | |
1649 | int | |
1650 | qlafx00_abort_isp(scsi_qla_host_t *vha) | |
1651 | { | |
1652 | struct qla_hw_data *ha = vha->hw; | |
1653 | ||
1654 | if (vha->flags.online) { | |
1655 | if (unlikely(pci_channel_offline(ha->pdev) && | |
1656 | ha->flags.pci_channel_io_perm_failure)) { | |
1657 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); | |
1658 | return QLA_SUCCESS; | |
1659 | } | |
1660 | ||
1661 | scsi_block_requests(vha->host); | |
71e56003 | 1662 | qlafx00_abort_isp_cleanup(vha, false); |
e601d778 AB |
1663 | } else { |
1664 | scsi_block_requests(vha->host); | |
1665 | clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
1666 | vha->qla_stats.total_isp_aborts++; | |
1667 | ha->isp_ops->reset_chip(vha); | |
1668 | set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags); | |
1669 | /* Clear the Interrupts */ | |
1670 | QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS); | |
8ae6d9c7 GM |
1671 | } |
1672 | ||
1673 | ql_log(ql_log_info, vha, 0x0145, | |
1674 | "(%s): succeeded.\n", __func__); | |
1675 | ||
1676 | return QLA_SUCCESS; | |
1677 | } | |
1678 | ||
1679 | static inline fc_port_t* | |
1680 | qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id) | |
1681 | { | |
1682 | fc_port_t *fcport; | |
1683 | ||
1684 | /* Check for matching device in remote port list. */ | |
8ae6d9c7 GM |
1685 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1686 | if (fcport->tgt_id == tgt_id) { | |
1687 | ql_dbg(ql_dbg_async, vha, 0x5072, | |
1688 | "Matching fcport(%p) found with TGT-ID: 0x%x " | |
1689 | "and Remote TGT_ID: 0x%x\n", | |
1690 | fcport, fcport->tgt_id, tgt_id); | |
24a42d50 | 1691 | return fcport; |
8ae6d9c7 GM |
1692 | } |
1693 | } | |
24a42d50 | 1694 | return NULL; |
8ae6d9c7 GM |
1695 | } |
1696 | ||
1697 | static void | |
1698 | qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id) | |
1699 | { | |
1700 | fc_port_t *fcport; | |
1701 | ||
1702 | ql_log(ql_log_info, vha, 0x5073, | |
1703 | "Detach TGT-ID: 0x%x\n", tgt_id); | |
1704 | ||
1705 | fcport = qlafx00_get_fcport(vha, tgt_id); | |
1706 | if (!fcport) | |
1707 | return; | |
1708 | ||
1709 | qla2x00_mark_device_lost(vha, fcport, 0, 0); | |
1710 | ||
1711 | return; | |
1712 | } | |
1713 | ||
1714 | int | |
1715 | qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt) | |
1716 | { | |
1717 | int rval = 0; | |
1718 | uint32_t aen_code, aen_data; | |
1719 | ||
1720 | aen_code = FCH_EVT_VENDOR_UNIQUE; | |
1721 | aen_data = evt->u.aenfx.evtcode; | |
1722 | ||
1723 | switch (evt->u.aenfx.evtcode) { | |
1724 | case QLAFX00_MBA_PORT_UPDATE: /* Port database update */ | |
1725 | if (evt->u.aenfx.mbx[1] == 0) { | |
1726 | if (evt->u.aenfx.mbx[2] == 1) { | |
1727 | if (!vha->flags.fw_tgt_reported) | |
1728 | vha->flags.fw_tgt_reported = 1; | |
1729 | atomic_set(&vha->loop_down_timer, 0); | |
1730 | atomic_set(&vha->loop_state, LOOP_UP); | |
1731 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
1732 | qla2xxx_wake_dpc(vha); | |
1733 | } else if (evt->u.aenfx.mbx[2] == 2) { | |
1734 | qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]); | |
1735 | } | |
1736 | } else if (evt->u.aenfx.mbx[1] == 0xffff) { | |
1737 | if (evt->u.aenfx.mbx[2] == 1) { | |
1738 | if (!vha->flags.fw_tgt_reported) | |
1739 | vha->flags.fw_tgt_reported = 1; | |
1740 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
1741 | } else if (evt->u.aenfx.mbx[2] == 2) { | |
1742 | vha->device_flags |= DFLG_NO_CABLE; | |
1743 | qla2x00_mark_all_devices_lost(vha, 1); | |
1744 | } | |
1745 | } | |
1746 | break; | |
1747 | case QLAFX00_MBA_LINK_UP: | |
1748 | aen_code = FCH_EVT_LINKUP; | |
1749 | aen_data = 0; | |
1750 | break; | |
1751 | case QLAFX00_MBA_LINK_DOWN: | |
1752 | aen_code = FCH_EVT_LINKDOWN; | |
1753 | aen_data = 0; | |
1754 | break; | |
71e56003 AB |
1755 | case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */ |
1756 | ql_log(ql_log_info, vha, 0x5082, | |
1757 | "Process critical temperature event " | |
1758 | "aenmb[0]: %x\n", | |
1759 | evt->u.aenfx.evtcode); | |
1760 | scsi_block_requests(vha->host); | |
1761 | qlafx00_abort_isp_cleanup(vha, true); | |
1762 | scsi_unblock_requests(vha->host); | |
1763 | break; | |
8ae6d9c7 GM |
1764 | } |
1765 | ||
1766 | fc_host_post_event(vha->host, fc_get_event_number(), | |
1767 | aen_code, aen_data); | |
1768 | ||
1769 | return rval; | |
1770 | } | |
1771 | ||
1772 | static void | |
1773 | qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo) | |
1774 | { | |
1775 | u64 port_name = 0, node_name = 0; | |
1776 | ||
1777 | port_name = (unsigned long long)wwn_to_u64(pinfo->port_name); | |
1778 | node_name = (unsigned long long)wwn_to_u64(pinfo->node_name); | |
1779 | ||
1780 | fc_host_node_name(vha->host) = node_name; | |
1781 | fc_host_port_name(vha->host) = port_name; | |
1782 | if (!pinfo->port_type) | |
1783 | vha->hw->current_topology = ISP_CFG_F; | |
1784 | if (pinfo->link_status == QLAFX00_LINK_STATUS_UP) | |
1785 | atomic_set(&vha->loop_state, LOOP_READY); | |
1786 | else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN) | |
1787 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
1788 | vha->hw->link_data_rate = (uint16_t)pinfo->link_config; | |
1789 | } | |
1790 | ||
1791 | static void | |
1792 | qla2x00_fxdisc_iocb_timeout(void *data) | |
1793 | { | |
25ff6af1 | 1794 | srb_t *sp = data; |
8ae6d9c7 GM |
1795 | struct srb_iocb *lio = &sp->u.iocb_cmd; |
1796 | ||
1797 | complete(&lio->u.fxiocb.fxiocb_comp); | |
1798 | } | |
1799 | ||
6c18a43e | 1800 | static void qla2x00_fxdisc_sp_done(srb_t *sp, int res) |
8ae6d9c7 | 1801 | { |
8ae6d9c7 GM |
1802 | struct srb_iocb *lio = &sp->u.iocb_cmd; |
1803 | ||
1804 | complete(&lio->u.fxiocb.fxiocb_comp); | |
1805 | } | |
1806 | ||
1807 | int | |
1f8deefe | 1808 | qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type) |
8ae6d9c7 GM |
1809 | { |
1810 | srb_t *sp; | |
1811 | struct srb_iocb *fdisc; | |
1812 | int rval = QLA_FUNCTION_FAILED; | |
1813 | struct qla_hw_data *ha = vha->hw; | |
1814 | struct host_system_info *phost_info; | |
1815 | struct register_host_info *preg_hsi; | |
1816 | struct new_utsname *p_sysid = NULL; | |
8ae6d9c7 GM |
1817 | |
1818 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); | |
1819 | if (!sp) | |
1820 | goto done; | |
1821 | ||
e0824e69 JC |
1822 | sp->type = SRB_FXIOCB_DCMD; |
1823 | sp->name = "fxdisc"; | |
e0824e69 | 1824 | |
8ae6d9c7 | 1825 | fdisc = &sp->u.iocb_cmd; |
e74e7d95 BH |
1826 | fdisc->timeout = qla2x00_fxdisc_iocb_timeout; |
1827 | qla2x00_init_timer(sp, FXDISC_TIMEOUT); | |
1828 | ||
8ae6d9c7 GM |
1829 | switch (fx_type) { |
1830 | case FXDISC_GET_CONFIG_INFO: | |
1831 | fdisc->u.fxiocb.flags = | |
1832 | SRB_FXDISC_RESP_DMA_VALID; | |
1833 | fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data); | |
1834 | break; | |
1835 | case FXDISC_GET_PORT_INFO: | |
1836 | fdisc->u.fxiocb.flags = | |
1837 | SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID; | |
1838 | fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO; | |
1f8deefe | 1839 | fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id); |
8ae6d9c7 GM |
1840 | break; |
1841 | case FXDISC_GET_TGT_NODE_INFO: | |
1842 | fdisc->u.fxiocb.flags = | |
1843 | SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID; | |
1844 | fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO; | |
1f8deefe | 1845 | fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id); |
8ae6d9c7 GM |
1846 | break; |
1847 | case FXDISC_GET_TGT_NODE_LIST: | |
1848 | fdisc->u.fxiocb.flags = | |
1849 | SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID; | |
1850 | fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE; | |
1851 | break; | |
1852 | case FXDISC_REG_HOST_INFO: | |
1853 | fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID; | |
1854 | fdisc->u.fxiocb.req_len = sizeof(struct register_host_info); | |
1855 | p_sysid = utsname(); | |
1856 | if (!p_sysid) { | |
1857 | ql_log(ql_log_warn, vha, 0x303c, | |
0b1587b1 | 1858 | "Not able to get the system information\n"); |
8ae6d9c7 GM |
1859 | goto done_free_sp; |
1860 | } | |
1861 | break; | |
767157c5 | 1862 | case FXDISC_ABORT_IOCTL: |
8ae6d9c7 GM |
1863 | default: |
1864 | break; | |
1865 | } | |
1866 | ||
1867 | if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) { | |
1868 | fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev, | |
1869 | fdisc->u.fxiocb.req_len, | |
1870 | &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL); | |
1871 | if (!fdisc->u.fxiocb.req_addr) | |
1872 | goto done_free_sp; | |
1873 | ||
1874 | if (fx_type == FXDISC_REG_HOST_INFO) { | |
1875 | preg_hsi = (struct register_host_info *) | |
1876 | fdisc->u.fxiocb.req_addr; | |
1877 | phost_info = &preg_hsi->hsi; | |
1878 | memset(preg_hsi, 0, sizeof(struct register_host_info)); | |
1879 | phost_info->os_type = OS_TYPE_LINUX; | |
cc74049f BVA |
1880 | strlcpy(phost_info->sysname, p_sysid->sysname, |
1881 | sizeof(phost_info->sysname)); | |
1882 | strlcpy(phost_info->nodename, p_sysid->nodename, | |
1883 | sizeof(phost_info->nodename)); | |
e8f5e95d AB |
1884 | if (!strcmp(phost_info->nodename, "(none)")) |
1885 | ha->mr.host_info_resend = true; | |
cc74049f BVA |
1886 | strlcpy(phost_info->release, p_sysid->release, |
1887 | sizeof(phost_info->release)); | |
1888 | strlcpy(phost_info->version, p_sysid->version, | |
1889 | sizeof(phost_info->version)); | |
1890 | strlcpy(phost_info->machine, p_sysid->machine, | |
1891 | sizeof(phost_info->machine)); | |
1892 | strlcpy(phost_info->domainname, p_sysid->domainname, | |
1893 | sizeof(phost_info->domainname)); | |
1894 | strlcpy(phost_info->hostdriver, QLA2XXX_VERSION, | |
1895 | sizeof(phost_info->hostdriver)); | |
5ea33eb5 | 1896 | preg_hsi->utc = (uint64_t)ktime_get_real_seconds(); |
8ae6d9c7 GM |
1897 | ql_dbg(ql_dbg_init, vha, 0x0149, |
1898 | "ISP%04X: Host registration with firmware\n", | |
1899 | ha->pdev->device); | |
1900 | ql_dbg(ql_dbg_init, vha, 0x014a, | |
1901 | "os_type = '%d', sysname = '%s', nodname = '%s'\n", | |
1902 | phost_info->os_type, | |
1903 | phost_info->sysname, | |
1904 | phost_info->nodename); | |
1905 | ql_dbg(ql_dbg_init, vha, 0x014b, | |
1906 | "release = '%s', version = '%s'\n", | |
1907 | phost_info->release, | |
1908 | phost_info->version); | |
1909 | ql_dbg(ql_dbg_init, vha, 0x014c, | |
1910 | "machine = '%s' " | |
1911 | "domainname = '%s', hostdriver = '%s'\n", | |
1912 | phost_info->machine, | |
1913 | phost_info->domainname, | |
1914 | phost_info->hostdriver); | |
1915 | ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d, | |
f8f97b0c | 1916 | phost_info, sizeof(*phost_info)); |
8ae6d9c7 GM |
1917 | } |
1918 | } | |
1919 | ||
1920 | if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) { | |
1921 | fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev, | |
1922 | fdisc->u.fxiocb.rsp_len, | |
1923 | &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL); | |
1924 | if (!fdisc->u.fxiocb.rsp_addr) | |
1925 | goto done_unmap_req; | |
1926 | } | |
1927 | ||
1f8deefe | 1928 | fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type); |
8ae6d9c7 GM |
1929 | sp->done = qla2x00_fxdisc_sp_done; |
1930 | ||
1931 | rval = qla2x00_start_sp(sp); | |
1932 | if (rval != QLA_SUCCESS) | |
1933 | goto done_unmap_dma; | |
1934 | ||
1935 | wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp); | |
1936 | ||
1937 | if (fx_type == FXDISC_GET_CONFIG_INFO) { | |
1938 | struct config_info_data *pinfo = | |
1939 | (struct config_info_data *) fdisc->u.fxiocb.rsp_addr; | |
527e9b70 BVA |
1940 | strlcpy(vha->hw->model_number, pinfo->model_num, |
1941 | ARRAY_SIZE(vha->hw->model_number)); | |
1942 | strlcpy(vha->hw->model_desc, pinfo->model_description, | |
1943 | ARRAY_SIZE(vha->hw->model_desc)); | |
8ae6d9c7 GM |
1944 | memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name, |
1945 | sizeof(vha->hw->mr.symbolic_name)); | |
1946 | memcpy(&vha->hw->mr.serial_num, pinfo->serial_num, | |
1947 | sizeof(vha->hw->mr.serial_num)); | |
1948 | memcpy(&vha->hw->mr.hw_version, pinfo->hw_version, | |
1949 | sizeof(vha->hw->mr.hw_version)); | |
1950 | memcpy(&vha->hw->mr.fw_version, pinfo->fw_version, | |
1951 | sizeof(vha->hw->mr.fw_version)); | |
1952 | strim(vha->hw->mr.fw_version); | |
1953 | memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version, | |
1954 | sizeof(vha->hw->mr.uboot_version)); | |
1955 | memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num, | |
1956 | sizeof(vha->hw->mr.fru_serial_num)); | |
f875cd4c AB |
1957 | vha->hw->mr.critical_temperature = |
1958 | (pinfo->nominal_temp_value) ? | |
1959 | pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD; | |
1fe19ee4 AB |
1960 | ha->mr.extended_io_enabled = (pinfo->enabled_capabilities & |
1961 | QLAFX00_EXTENDED_IO_EN_MASK) != 0; | |
8ae6d9c7 GM |
1962 | } else if (fx_type == FXDISC_GET_PORT_INFO) { |
1963 | struct port_info_data *pinfo = | |
1964 | (struct port_info_data *) fdisc->u.fxiocb.rsp_addr; | |
1965 | memcpy(vha->node_name, pinfo->node_name, WWN_SIZE); | |
1966 | memcpy(vha->port_name, pinfo->port_name, WWN_SIZE); | |
1967 | vha->d_id.b.domain = pinfo->port_id[0]; | |
1968 | vha->d_id.b.area = pinfo->port_id[1]; | |
1969 | vha->d_id.b.al_pa = pinfo->port_id[2]; | |
1970 | qlafx00_update_host_attr(vha, pinfo); | |
1971 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141, | |
f8f97b0c | 1972 | pinfo, 16); |
8ae6d9c7 GM |
1973 | } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) { |
1974 | struct qlafx00_tgt_node_info *pinfo = | |
1975 | (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr; | |
1976 | memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE); | |
1977 | memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE); | |
1978 | fcport->port_type = FCT_TARGET; | |
1979 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144, | |
f8f97b0c | 1980 | pinfo, 16); |
8ae6d9c7 GM |
1981 | } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) { |
1982 | struct qlafx00_tgt_node_info *pinfo = | |
1983 | (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr; | |
1984 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146, | |
f8f97b0c | 1985 | pinfo, 16); |
8ae6d9c7 | 1986 | memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE); |
767157c5 AB |
1987 | } else if (fx_type == FXDISC_ABORT_IOCTL) |
1988 | fdisc->u.fxiocb.result = | |
b593931d AB |
1989 | (fdisc->u.fxiocb.result == |
1990 | cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ? | |
767157c5 AB |
1991 | cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED); |
1992 | ||
1f8deefe | 1993 | rval = le32_to_cpu(fdisc->u.fxiocb.result); |
8ae6d9c7 GM |
1994 | |
1995 | done_unmap_dma: | |
1996 | if (fdisc->u.fxiocb.rsp_addr) | |
1997 | dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len, | |
1998 | fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle); | |
1999 | ||
2000 | done_unmap_req: | |
2001 | if (fdisc->u.fxiocb.req_addr) | |
2002 | dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len, | |
2003 | fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle); | |
2004 | done_free_sp: | |
25ff6af1 | 2005 | sp->free(sp); |
8ae6d9c7 GM |
2006 | done: |
2007 | return rval; | |
2008 | } | |
2009 | ||
8ae6d9c7 GM |
2010 | /* |
2011 | * qlafx00_initialize_adapter | |
2012 | * Initialize board. | |
2013 | * | |
2014 | * Input: | |
2015 | * ha = adapter block pointer. | |
2016 | * | |
2017 | * Returns: | |
2018 | * 0 = success | |
2019 | */ | |
2020 | int | |
2021 | qlafx00_initialize_adapter(scsi_qla_host_t *vha) | |
2022 | { | |
2023 | int rval; | |
2024 | struct qla_hw_data *ha = vha->hw; | |
71e56003 | 2025 | uint32_t tempc; |
8ae6d9c7 GM |
2026 | |
2027 | /* Clear adapter flags. */ | |
2028 | vha->flags.online = 0; | |
2029 | ha->flags.chip_reset_done = 0; | |
2030 | vha->flags.reset_active = 0; | |
2031 | ha->flags.pci_channel_io_perm_failure = 0; | |
2032 | ha->flags.eeh_busy = 0; | |
8ae6d9c7 GM |
2033 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); |
2034 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
2035 | vha->device_flags = DFLG_NO_CABLE; | |
2036 | vha->dpc_flags = 0; | |
2037 | vha->flags.management_server_logged_in = 0; | |
8ae6d9c7 GM |
2038 | ha->isp_abort_cnt = 0; |
2039 | ha->beacon_blink_led = 0; | |
2040 | ||
2041 | set_bit(0, ha->req_qid_map); | |
2042 | set_bit(0, ha->rsp_qid_map); | |
2043 | ||
2044 | ql_dbg(ql_dbg_init, vha, 0x0147, | |
2045 | "Configuring PCI space...\n"); | |
2046 | ||
2047 | rval = ha->isp_ops->pci_config(vha); | |
2048 | if (rval) { | |
2049 | ql_log(ql_log_warn, vha, 0x0148, | |
2050 | "Unable to configure PCI space.\n"); | |
2051 | return rval; | |
2052 | } | |
2053 | ||
2054 | rval = qlafx00_init_fw_ready(vha); | |
2055 | if (rval != QLA_SUCCESS) | |
2056 | return rval; | |
2057 | ||
2058 | qlafx00_save_queue_ptrs(vha); | |
2059 | ||
2060 | rval = qlafx00_config_queues(vha); | |
2061 | if (rval != QLA_SUCCESS) | |
2062 | return rval; | |
2063 | ||
2064 | /* | |
2065 | * Allocate the array of outstanding commands | |
2066 | * now that we know the firmware resources. | |
2067 | */ | |
2068 | rval = qla2x00_alloc_outstanding_cmds(ha, vha->req); | |
2069 | if (rval != QLA_SUCCESS) | |
2070 | return rval; | |
2071 | ||
2072 | rval = qla2x00_init_rings(vha); | |
2073 | ha->flags.chip_reset_done = 1; | |
2074 | ||
71e56003 AB |
2075 | tempc = QLAFX00_GET_TEMPERATURE(ha); |
2076 | ql_dbg(ql_dbg_init, vha, 0x0152, | |
2077 | "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n", | |
2078 | __func__, tempc); | |
2079 | ||
8ae6d9c7 GM |
2080 | return rval; |
2081 | } | |
2082 | ||
2083 | uint32_t | |
2084 | qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr, | |
2085 | char *buf) | |
2086 | { | |
2087 | scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); | |
2088 | int rval = QLA_FUNCTION_FAILED; | |
2089 | uint32_t state[1]; | |
2090 | ||
2091 | if (qla2x00_reset_active(vha)) | |
2092 | ql_log(ql_log_warn, vha, 0x70ce, | |
2093 | "ISP reset active.\n"); | |
2094 | else if (!vha->hw->flags.eeh_busy) { | |
2095 | rval = qlafx00_get_firmware_state(vha, state); | |
2096 | } | |
2097 | if (rval != QLA_SUCCESS) | |
2098 | memset(state, -1, sizeof(state)); | |
2099 | ||
2100 | return state[0]; | |
2101 | } | |
2102 | ||
2103 | void | |
2104 | qlafx00_get_host_speed(struct Scsi_Host *shost) | |
2105 | { | |
2106 | struct qla_hw_data *ha = ((struct scsi_qla_host *) | |
2107 | (shost_priv(shost)))->hw; | |
2108 | u32 speed = FC_PORTSPEED_UNKNOWN; | |
2109 | ||
2110 | switch (ha->link_data_rate) { | |
2111 | case QLAFX00_PORT_SPEED_2G: | |
2112 | speed = FC_PORTSPEED_2GBIT; | |
2113 | break; | |
2114 | case QLAFX00_PORT_SPEED_4G: | |
2115 | speed = FC_PORTSPEED_4GBIT; | |
2116 | break; | |
2117 | case QLAFX00_PORT_SPEED_8G: | |
2118 | speed = FC_PORTSPEED_8GBIT; | |
2119 | break; | |
2120 | case QLAFX00_PORT_SPEED_10G: | |
2121 | speed = FC_PORTSPEED_10GBIT; | |
2122 | break; | |
2123 | } | |
2124 | fc_host_speed(shost) = speed; | |
2125 | } | |
2126 | ||
2127 | /** QLAFX00 specific ISR implementation functions */ | |
2128 | ||
2129 | static inline void | |
2130 | qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len, | |
2131 | uint32_t sense_len, struct rsp_que *rsp, int res) | |
2132 | { | |
25ff6af1 | 2133 | struct scsi_qla_host *vha = sp->vha; |
8ae6d9c7 GM |
2134 | struct scsi_cmnd *cp = GET_CMD_SP(sp); |
2135 | uint32_t track_sense_len; | |
2136 | ||
2137 | SET_FW_SENSE_LEN(sp, sense_len); | |
2138 | ||
2139 | if (sense_len >= SCSI_SENSE_BUFFERSIZE) | |
2140 | sense_len = SCSI_SENSE_BUFFERSIZE; | |
2141 | ||
2142 | SET_CMD_SENSE_LEN(sp, sense_len); | |
2143 | SET_CMD_SENSE_PTR(sp, cp->sense_buffer); | |
2144 | track_sense_len = sense_len; | |
2145 | ||
2146 | if (sense_len > par_sense_len) | |
2147 | sense_len = par_sense_len; | |
2148 | ||
2149 | memcpy(cp->sense_buffer, sense_data, sense_len); | |
2150 | ||
2151 | SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len); | |
2152 | ||
2153 | SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len); | |
2154 | track_sense_len -= sense_len; | |
2155 | SET_CMD_SENSE_LEN(sp, track_sense_len); | |
2156 | ||
2157 | ql_dbg(ql_dbg_io, vha, 0x304d, | |
2158 | "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n", | |
2159 | sense_len, par_sense_len, track_sense_len); | |
2160 | if (GET_FW_SENSE_LEN(sp) > 0) { | |
2161 | rsp->status_srb = sp; | |
2162 | cp->result = res; | |
2163 | } | |
2164 | ||
2165 | if (sense_len) { | |
2166 | ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039, | |
9cb78c16 | 2167 | "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n", |
25ff6af1 | 2168 | sp->vha->host_no, cp->device->id, cp->device->lun, |
8ae6d9c7 GM |
2169 | cp); |
2170 | ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049, | |
2171 | cp->sense_buffer, sense_len); | |
2172 | } | |
2173 | } | |
2174 | ||
2175 | static void | |
2176 | qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, | |
2177 | struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp, | |
1f8deefe | 2178 | __le16 sstatus, __le16 cpstatus) |
8ae6d9c7 GM |
2179 | { |
2180 | struct srb_iocb *tmf; | |
2181 | ||
2182 | tmf = &sp->u.iocb_cmd; | |
1f8deefe SK |
2183 | if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) || |
2184 | (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID))) | |
2185 | cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE); | |
8ae6d9c7 | 2186 | tmf->u.tmf.comp_status = cpstatus; |
25ff6af1 | 2187 | sp->done(sp, 0); |
8ae6d9c7 GM |
2188 | } |
2189 | ||
2190 | static void | |
2191 | qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, | |
2192 | struct abort_iocb_entry_fx00 *pkt) | |
2193 | { | |
2194 | const char func[] = "ABT_IOCB"; | |
2195 | srb_t *sp; | |
2196 | struct srb_iocb *abt; | |
2197 | ||
2198 | sp = qla2x00_get_sp_from_handle(vha, func, req, pkt); | |
2199 | if (!sp) | |
2200 | return; | |
2201 | ||
2202 | abt = &sp->u.iocb_cmd; | |
1f8deefe | 2203 | abt->u.abt.comp_status = pkt->tgt_id_sts; |
25ff6af1 | 2204 | sp->done(sp, 0); |
8ae6d9c7 GM |
2205 | } |
2206 | ||
2207 | static void | |
2208 | qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req, | |
2209 | struct ioctl_iocb_entry_fx00 *pkt) | |
2210 | { | |
2211 | const char func[] = "IOSB_IOCB"; | |
2212 | srb_t *sp; | |
75cc8cfc | 2213 | struct bsg_job *bsg_job; |
01e0e15c | 2214 | struct fc_bsg_reply *bsg_reply; |
8ae6d9c7 | 2215 | struct srb_iocb *iocb_job; |
5b0af477 | 2216 | int res = 0; |
8ae6d9c7 GM |
2217 | struct qla_mt_iocb_rsp_fx00 fstatus; |
2218 | uint8_t *fw_sts_ptr; | |
2219 | ||
2220 | sp = qla2x00_get_sp_from_handle(vha, func, req, pkt); | |
2221 | if (!sp) | |
2222 | return; | |
2223 | ||
2224 | if (sp->type == SRB_FXIOCB_DCMD) { | |
2225 | iocb_job = &sp->u.iocb_cmd; | |
1f8deefe SK |
2226 | iocb_job->u.fxiocb.seq_number = pkt->seq_no; |
2227 | iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags; | |
2228 | iocb_job->u.fxiocb.result = pkt->status; | |
8ae6d9c7 GM |
2229 | if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID) |
2230 | iocb_job->u.fxiocb.req_data = | |
1f8deefe | 2231 | pkt->dataword_r; |
8ae6d9c7 GM |
2232 | } else { |
2233 | bsg_job = sp->u.bsg_job; | |
01e0e15c | 2234 | bsg_reply = bsg_job->reply; |
8ae6d9c7 GM |
2235 | |
2236 | memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00)); | |
2237 | ||
2238 | fstatus.reserved_1 = pkt->reserved_0; | |
2239 | fstatus.func_type = pkt->comp_func_num; | |
2240 | fstatus.ioctl_flags = pkt->fw_iotcl_flags; | |
2241 | fstatus.ioctl_data = pkt->dataword_r; | |
2242 | fstatus.adapid = pkt->adapid; | |
d68b3e01 | 2243 | fstatus.reserved_2 = pkt->dataword_r_extra; |
8ae6d9c7 GM |
2244 | fstatus.res_count = pkt->residuallen; |
2245 | fstatus.status = pkt->status; | |
2246 | fstatus.seq_number = pkt->seq_no; | |
2247 | memcpy(fstatus.reserved_3, | |
2248 | pkt->reserved_2, 20 * sizeof(uint8_t)); | |
2249 | ||
05231a3b | 2250 | fw_sts_ptr = bsg_job->reply + sizeof(struct fc_bsg_reply); |
8ae6d9c7 | 2251 | |
f8f97b0c | 2252 | memcpy(fw_sts_ptr, &fstatus, sizeof(fstatus)); |
8ae6d9c7 GM |
2253 | bsg_job->reply_len = sizeof(struct fc_bsg_reply) + |
2254 | sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t); | |
2255 | ||
2256 | ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, | |
f8f97b0c | 2257 | sp->vha, 0x5080, pkt, sizeof(*pkt)); |
8ae6d9c7 GM |
2258 | |
2259 | ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, | |
f8f97b0c JC |
2260 | sp->vha, 0x5074, |
2261 | fw_sts_ptr, sizeof(fstatus)); | |
8ae6d9c7 | 2262 | |
01e0e15c JT |
2263 | res = bsg_reply->result = DID_OK << 16; |
2264 | bsg_reply->reply_payload_rcv_len = | |
8ae6d9c7 GM |
2265 | bsg_job->reply_payload.payload_len; |
2266 | } | |
25ff6af1 | 2267 | sp->done(sp, res); |
8ae6d9c7 GM |
2268 | } |
2269 | ||
2270 | /** | |
2271 | * qlafx00_status_entry() - Process a Status IOCB entry. | |
2db6228d BVA |
2272 | * @vha: SCSI driver HA context |
2273 | * @rsp: response queue | |
8ae6d9c7 GM |
2274 | * @pkt: Entry pointer |
2275 | */ | |
2276 | static void | |
2277 | qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt) | |
2278 | { | |
2279 | srb_t *sp; | |
2280 | fc_port_t *fcport; | |
2281 | struct scsi_cmnd *cp; | |
2282 | struct sts_entry_fx00 *sts; | |
1f8deefe SK |
2283 | __le16 comp_status; |
2284 | __le16 scsi_status; | |
1f8deefe | 2285 | __le16 lscsi_status; |
8ae6d9c7 GM |
2286 | int32_t resid; |
2287 | uint32_t sense_len, par_sense_len, rsp_info_len, resid_len, | |
2288 | fw_resid_len; | |
2289 | uint8_t *rsp_info = NULL, *sense_data = NULL; | |
2290 | struct qla_hw_data *ha = vha->hw; | |
2291 | uint32_t hindex, handle; | |
2292 | uint16_t que; | |
2293 | struct req_que *req; | |
2294 | int logit = 1; | |
2295 | int res = 0; | |
2296 | ||
2297 | sts = (struct sts_entry_fx00 *) pkt; | |
2298 | ||
1f8deefe SK |
2299 | comp_status = sts->comp_status; |
2300 | scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK); | |
8ae6d9c7 GM |
2301 | hindex = sts->handle; |
2302 | handle = LSW(hindex); | |
2303 | ||
2304 | que = MSW(hindex); | |
2305 | req = ha->req_q_map[que]; | |
2306 | ||
2307 | /* Validate handle. */ | |
2308 | if (handle < req->num_outstanding_cmds) | |
2309 | sp = req->outstanding_cmds[handle]; | |
2310 | else | |
2311 | sp = NULL; | |
2312 | ||
2313 | if (sp == NULL) { | |
2314 | ql_dbg(ql_dbg_io, vha, 0x3034, | |
2315 | "Invalid status handle (0x%x).\n", handle); | |
2316 | ||
2317 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
2318 | qla2xxx_wake_dpc(vha); | |
2319 | return; | |
2320 | } | |
2321 | ||
2322 | if (sp->type == SRB_TM_CMD) { | |
2323 | req->outstanding_cmds[handle] = NULL; | |
2324 | qlafx00_tm_iocb_entry(vha, req, pkt, sp, | |
2325 | scsi_status, comp_status); | |
2326 | return; | |
2327 | } | |
2328 | ||
2329 | /* Fast path completion. */ | |
2330 | if (comp_status == CS_COMPLETE && scsi_status == 0) { | |
8ae6d9c7 GM |
2331 | qla2x00_process_completed_request(vha, req, handle); |
2332 | return; | |
2333 | } | |
2334 | ||
2335 | req->outstanding_cmds[handle] = NULL; | |
2336 | cp = GET_CMD_SP(sp); | |
2337 | if (cp == NULL) { | |
2338 | ql_dbg(ql_dbg_io, vha, 0x3048, | |
2339 | "Command already returned (0x%x/%p).\n", | |
2340 | handle, sp); | |
2341 | ||
2342 | return; | |
2343 | } | |
2344 | ||
1f8deefe | 2345 | lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK); |
8ae6d9c7 GM |
2346 | |
2347 | fcport = sp->fcport; | |
2348 | ||
8ae6d9c7 GM |
2349 | sense_len = par_sense_len = rsp_info_len = resid_len = |
2350 | fw_resid_len = 0; | |
1f8deefe SK |
2351 | if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)) |
2352 | sense_len = sts->sense_len; | |
2353 | if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER | |
2354 | | (uint16_t)SS_RESIDUAL_OVER))) | |
8ae6d9c7 | 2355 | resid_len = le32_to_cpu(sts->residual_len); |
1f8deefe | 2356 | if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN)) |
8ae6d9c7 GM |
2357 | fw_resid_len = le32_to_cpu(sts->residual_len); |
2358 | rsp_info = sense_data = sts->data; | |
2359 | par_sense_len = sizeof(sts->data); | |
2360 | ||
2361 | /* Check for overrun. */ | |
2362 | if (comp_status == CS_COMPLETE && | |
1f8deefe SK |
2363 | scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER)) |
2364 | comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN); | |
8ae6d9c7 GM |
2365 | |
2366 | /* | |
2367 | * Based on Host and scsi status generate status code for Linux | |
2368 | */ | |
1f8deefe | 2369 | switch (le16_to_cpu(comp_status)) { |
8ae6d9c7 GM |
2370 | case CS_COMPLETE: |
2371 | case CS_QUEUE_FULL: | |
2372 | if (scsi_status == 0) { | |
2373 | res = DID_OK << 16; | |
2374 | break; | |
2375 | } | |
1f8deefe SK |
2376 | if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER |
2377 | | (uint16_t)SS_RESIDUAL_OVER))) { | |
8ae6d9c7 GM |
2378 | resid = resid_len; |
2379 | scsi_set_resid(cp, resid); | |
2380 | ||
2381 | if (!lscsi_status && | |
2382 | ((unsigned)(scsi_bufflen(cp) - resid) < | |
2383 | cp->underflow)) { | |
2384 | ql_dbg(ql_dbg_io, fcport->vha, 0x3050, | |
2385 | "Mid-layer underflow " | |
2386 | "detected (0x%x of 0x%x bytes).\n", | |
2387 | resid, scsi_bufflen(cp)); | |
2388 | ||
2389 | res = DID_ERROR << 16; | |
2390 | break; | |
2391 | } | |
2392 | } | |
1f8deefe | 2393 | res = DID_OK << 16 | le16_to_cpu(lscsi_status); |
8ae6d9c7 | 2394 | |
1f8deefe SK |
2395 | if (lscsi_status == |
2396 | cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) { | |
8ae6d9c7 GM |
2397 | ql_dbg(ql_dbg_io, fcport->vha, 0x3051, |
2398 | "QUEUE FULL detected.\n"); | |
2399 | break; | |
2400 | } | |
2401 | logit = 0; | |
1f8deefe | 2402 | if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION)) |
8ae6d9c7 GM |
2403 | break; |
2404 | ||
2405 | memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE); | |
1f8deefe | 2406 | if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))) |
8ae6d9c7 GM |
2407 | break; |
2408 | ||
2409 | qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len, | |
2410 | rsp, res); | |
2411 | break; | |
2412 | ||
2413 | case CS_DATA_UNDERRUN: | |
2414 | /* Use F/W calculated residual length. */ | |
2415 | if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha)) | |
2416 | resid = fw_resid_len; | |
2417 | else | |
2418 | resid = resid_len; | |
2419 | scsi_set_resid(cp, resid); | |
1f8deefe | 2420 | if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) { |
8ae6d9c7 GM |
2421 | if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha)) |
2422 | && fw_resid_len != resid_len) { | |
2423 | ql_dbg(ql_dbg_io, fcport->vha, 0x3052, | |
2424 | "Dropped frame(s) detected " | |
2425 | "(0x%x of 0x%x bytes).\n", | |
2426 | resid, scsi_bufflen(cp)); | |
2427 | ||
1f8deefe SK |
2428 | res = DID_ERROR << 16 | |
2429 | le16_to_cpu(lscsi_status); | |
8ae6d9c7 GM |
2430 | goto check_scsi_status; |
2431 | } | |
2432 | ||
2433 | if (!lscsi_status && | |
2434 | ((unsigned)(scsi_bufflen(cp) - resid) < | |
2435 | cp->underflow)) { | |
2436 | ql_dbg(ql_dbg_io, fcport->vha, 0x3053, | |
2437 | "Mid-layer underflow " | |
2438 | "detected (0x%x of 0x%x bytes, " | |
2439 | "cp->underflow: 0x%x).\n", | |
2440 | resid, scsi_bufflen(cp), cp->underflow); | |
2441 | ||
2442 | res = DID_ERROR << 16; | |
2443 | break; | |
2444 | } | |
1f8deefe SK |
2445 | } else if (lscsi_status != |
2446 | cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) && | |
2447 | lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) { | |
8ae6d9c7 GM |
2448 | /* |
2449 | * scsi status of task set and busy are considered | |
2450 | * to be task not completed. | |
2451 | */ | |
2452 | ||
2453 | ql_dbg(ql_dbg_io, fcport->vha, 0x3054, | |
2454 | "Dropped frame(s) detected (0x%x " | |
2455 | "of 0x%x bytes).\n", resid, | |
2456 | scsi_bufflen(cp)); | |
2457 | ||
1f8deefe | 2458 | res = DID_ERROR << 16 | le16_to_cpu(lscsi_status); |
8ae6d9c7 GM |
2459 | goto check_scsi_status; |
2460 | } else { | |
2461 | ql_dbg(ql_dbg_io, fcport->vha, 0x3055, | |
2462 | "scsi_status: 0x%x, lscsi_status: 0x%x\n", | |
2463 | scsi_status, lscsi_status); | |
2464 | } | |
2465 | ||
1f8deefe | 2466 | res = DID_OK << 16 | le16_to_cpu(lscsi_status); |
8ae6d9c7 GM |
2467 | logit = 0; |
2468 | ||
2469 | check_scsi_status: | |
2470 | /* | |
2471 | * Check to see if SCSI Status is non zero. If so report SCSI | |
2472 | * Status. | |
2473 | */ | |
2474 | if (lscsi_status != 0) { | |
1f8deefe SK |
2475 | if (lscsi_status == |
2476 | cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) { | |
8ae6d9c7 GM |
2477 | ql_dbg(ql_dbg_io, fcport->vha, 0x3056, |
2478 | "QUEUE FULL detected.\n"); | |
2479 | logit = 1; | |
2480 | break; | |
2481 | } | |
1f8deefe SK |
2482 | if (lscsi_status != |
2483 | cpu_to_le16((uint16_t)SS_CHECK_CONDITION)) | |
8ae6d9c7 GM |
2484 | break; |
2485 | ||
2486 | memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE); | |
1f8deefe SK |
2487 | if (!(scsi_status & |
2488 | cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))) | |
8ae6d9c7 GM |
2489 | break; |
2490 | ||
2491 | qlafx00_handle_sense(sp, sense_data, par_sense_len, | |
2492 | sense_len, rsp, res); | |
2493 | } | |
2494 | break; | |
2495 | ||
2496 | case CS_PORT_LOGGED_OUT: | |
2497 | case CS_PORT_CONFIG_CHG: | |
2498 | case CS_PORT_BUSY: | |
2499 | case CS_INCOMPLETE: | |
2500 | case CS_PORT_UNAVAILABLE: | |
2501 | case CS_TIMEOUT: | |
2502 | case CS_RESET: | |
2503 | ||
2504 | /* | |
2505 | * We are going to have the fc class block the rport | |
2506 | * while we try to recover so instruct the mid layer | |
2507 | * to requeue until the class decides how to handle this. | |
2508 | */ | |
2509 | res = DID_TRANSPORT_DISRUPTED << 16; | |
2510 | ||
2511 | ql_dbg(ql_dbg_io, fcport->vha, 0x3057, | |
2512 | "Port down status: port-state=0x%x.\n", | |
2513 | atomic_read(&fcport->state)); | |
2514 | ||
2515 | if (atomic_read(&fcport->state) == FCS_ONLINE) | |
2516 | qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1); | |
2517 | break; | |
2518 | ||
2519 | case CS_ABORTED: | |
2520 | res = DID_RESET << 16; | |
2521 | break; | |
2522 | ||
2523 | default: | |
2524 | res = DID_ERROR << 16; | |
2525 | break; | |
2526 | } | |
2527 | ||
2528 | if (logit) | |
2529 | ql_dbg(ql_dbg_io, fcport->vha, 0x3058, | |
9cb78c16 | 2530 | "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu " |
7b833558 | 2531 | "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x " |
c3ff356d | 2532 | "rsp_info=%p resid=0x%x fw_resid=0x%x sense_len=0x%x, " |
7b833558 | 2533 | "par_sense_len=0x%x, rsp_info_len=0x%x\n", |
8ae6d9c7 GM |
2534 | comp_status, scsi_status, res, vha->host_no, |
2535 | cp->device->id, cp->device->lun, fcport->tgt_id, | |
7b833558 | 2536 | lscsi_status, cp->cmnd, scsi_bufflen(cp), |
c3ff356d | 2537 | rsp_info, resid_len, fw_resid_len, sense_len, |
8ae6d9c7 GM |
2538 | par_sense_len, rsp_info_len); |
2539 | ||
8ae6d9c7 | 2540 | if (rsp->status_srb == NULL) |
25ff6af1 | 2541 | sp->done(sp, res); |
8ae6d9c7 GM |
2542 | } |
2543 | ||
2544 | /** | |
2545 | * qlafx00_status_cont_entry() - Process a Status Continuations entry. | |
2db6228d | 2546 | * @rsp: response queue |
8ae6d9c7 GM |
2547 | * @pkt: Entry pointer |
2548 | * | |
2549 | * Extended sense data. | |
2550 | */ | |
2551 | static void | |
2552 | qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt) | |
2553 | { | |
2554 | uint8_t sense_sz = 0; | |
2555 | struct qla_hw_data *ha = rsp->hw; | |
2556 | struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev); | |
2557 | srb_t *sp = rsp->status_srb; | |
2558 | struct scsi_cmnd *cp; | |
2559 | uint32_t sense_len; | |
2560 | uint8_t *sense_ptr; | |
2561 | ||
2562 | if (!sp) { | |
2563 | ql_dbg(ql_dbg_io, vha, 0x3037, | |
2564 | "no SP, sp = %p\n", sp); | |
2565 | return; | |
2566 | } | |
2567 | ||
2568 | if (!GET_FW_SENSE_LEN(sp)) { | |
2569 | ql_dbg(ql_dbg_io, vha, 0x304b, | |
2570 | "no fw sense data, sp = %p\n", sp); | |
2571 | return; | |
2572 | } | |
2573 | cp = GET_CMD_SP(sp); | |
2574 | if (cp == NULL) { | |
2575 | ql_log(ql_log_warn, vha, 0x303b, | |
2576 | "cmd is NULL: already returned to OS (sp=%p).\n", sp); | |
2577 | ||
2578 | rsp->status_srb = NULL; | |
2579 | return; | |
2580 | } | |
2581 | ||
2582 | if (!GET_CMD_SENSE_LEN(sp)) { | |
2583 | ql_dbg(ql_dbg_io, vha, 0x304c, | |
2584 | "no sense data, sp = %p\n", sp); | |
2585 | } else { | |
2586 | sense_len = GET_CMD_SENSE_LEN(sp); | |
2587 | sense_ptr = GET_CMD_SENSE_PTR(sp); | |
2588 | ql_dbg(ql_dbg_io, vha, 0x304f, | |
2589 | "sp=%p sense_len=0x%x sense_ptr=%p.\n", | |
2590 | sp, sense_len, sense_ptr); | |
2591 | ||
2592 | if (sense_len > sizeof(pkt->data)) | |
2593 | sense_sz = sizeof(pkt->data); | |
2594 | else | |
2595 | sense_sz = sense_len; | |
2596 | ||
2597 | /* Move sense data. */ | |
2598 | ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e, | |
f8f97b0c | 2599 | pkt, sizeof(*pkt)); |
8ae6d9c7 GM |
2600 | memcpy(sense_ptr, pkt->data, sense_sz); |
2601 | ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a, | |
2602 | sense_ptr, sense_sz); | |
2603 | ||
2604 | sense_len -= sense_sz; | |
2605 | sense_ptr += sense_sz; | |
2606 | ||
2607 | SET_CMD_SENSE_PTR(sp, sense_ptr); | |
2608 | SET_CMD_SENSE_LEN(sp, sense_len); | |
2609 | } | |
2610 | sense_len = GET_FW_SENSE_LEN(sp); | |
2611 | sense_len = (sense_len > sizeof(pkt->data)) ? | |
2612 | (sense_len - sizeof(pkt->data)) : 0; | |
2613 | SET_FW_SENSE_LEN(sp, sense_len); | |
2614 | ||
2615 | /* Place command on done queue. */ | |
2616 | if (sense_len == 0) { | |
2617 | rsp->status_srb = NULL; | |
25ff6af1 | 2618 | sp->done(sp, cp->result); |
8ae6d9c7 GM |
2619 | } |
2620 | } | |
2621 | ||
2622 | /** | |
2623 | * qlafx00_multistatus_entry() - Process Multi response queue entries. | |
2db6228d BVA |
2624 | * @vha: SCSI driver HA context |
2625 | * @rsp: response queue | |
807eb907 | 2626 | * @pkt: received packet |
8ae6d9c7 GM |
2627 | */ |
2628 | static void | |
2629 | qlafx00_multistatus_entry(struct scsi_qla_host *vha, | |
2630 | struct rsp_que *rsp, void *pkt) | |
2631 | { | |
2632 | srb_t *sp; | |
2633 | struct multi_sts_entry_fx00 *stsmfx; | |
2634 | struct qla_hw_data *ha = vha->hw; | |
2635 | uint32_t handle, hindex, handle_count, i; | |
2636 | uint16_t que; | |
2637 | struct req_que *req; | |
1f8deefe | 2638 | __le32 *handle_ptr; |
8ae6d9c7 GM |
2639 | |
2640 | stsmfx = (struct multi_sts_entry_fx00 *) pkt; | |
2641 | ||
2642 | handle_count = stsmfx->handle_count; | |
2643 | ||
2644 | if (handle_count > MAX_HANDLE_COUNT) { | |
2645 | ql_dbg(ql_dbg_io, vha, 0x3035, | |
2646 | "Invalid handle count (0x%x).\n", handle_count); | |
2647 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
2648 | qla2xxx_wake_dpc(vha); | |
2649 | return; | |
2650 | } | |
2651 | ||
1f8deefe | 2652 | handle_ptr = &stsmfx->handles[0]; |
8ae6d9c7 GM |
2653 | |
2654 | for (i = 0; i < handle_count; i++) { | |
2655 | hindex = le32_to_cpu(*handle_ptr); | |
2656 | handle = LSW(hindex); | |
2657 | que = MSW(hindex); | |
2658 | req = ha->req_q_map[que]; | |
2659 | ||
2660 | /* Validate handle. */ | |
2661 | if (handle < req->num_outstanding_cmds) | |
2662 | sp = req->outstanding_cmds[handle]; | |
2663 | else | |
2664 | sp = NULL; | |
2665 | ||
2666 | if (sp == NULL) { | |
2667 | ql_dbg(ql_dbg_io, vha, 0x3044, | |
2668 | "Invalid status handle (0x%x).\n", handle); | |
2669 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
2670 | qla2xxx_wake_dpc(vha); | |
2671 | return; | |
2672 | } | |
2673 | qla2x00_process_completed_request(vha, req, handle); | |
2674 | handle_ptr++; | |
2675 | } | |
2676 | } | |
2677 | ||
2678 | /** | |
2679 | * qlafx00_error_entry() - Process an error entry. | |
2db6228d BVA |
2680 | * @vha: SCSI driver HA context |
2681 | * @rsp: response queue | |
8ae6d9c7 GM |
2682 | * @pkt: Entry pointer |
2683 | */ | |
2684 | static void | |
2685 | qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, | |
2c309aee | 2686 | struct sts_entry_fx00 *pkt) |
8ae6d9c7 GM |
2687 | { |
2688 | srb_t *sp; | |
2689 | struct qla_hw_data *ha = vha->hw; | |
2690 | const char func[] = "ERROR-IOCB"; | |
d550dd27 | 2691 | uint16_t que = 0; |
8ae6d9c7 GM |
2692 | struct req_que *req = NULL; |
2693 | int res = DID_ERROR << 16; | |
2694 | ||
8ae6d9c7 GM |
2695 | req = ha->req_q_map[que]; |
2696 | ||
2697 | sp = qla2x00_get_sp_from_handle(vha, func, req, pkt); | |
2698 | if (sp) { | |
25ff6af1 | 2699 | sp->done(sp, res); |
8ae6d9c7 GM |
2700 | return; |
2701 | } | |
2702 | ||
2703 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
2704 | qla2xxx_wake_dpc(vha); | |
2705 | } | |
2706 | ||
2707 | /** | |
2708 | * qlafx00_process_response_queue() - Process response queue entries. | |
2db6228d BVA |
2709 | * @vha: SCSI driver HA context |
2710 | * @rsp: response queue | |
8ae6d9c7 GM |
2711 | */ |
2712 | static void | |
2713 | qlafx00_process_response_queue(struct scsi_qla_host *vha, | |
2714 | struct rsp_que *rsp) | |
2715 | { | |
2716 | struct sts_entry_fx00 *pkt; | |
2717 | response_t *lptr; | |
6ac1f3b5 SK |
2718 | uint16_t lreq_q_in = 0; |
2719 | uint16_t lreq_q_out = 0; | |
8ae6d9c7 | 2720 | |
6ac1f3b5 | 2721 | lreq_q_in = RD_REG_DWORD(rsp->rsp_q_in); |
9929c478 | 2722 | lreq_q_out = rsp->ring_index; |
6ac1f3b5 SK |
2723 | |
2724 | while (lreq_q_in != lreq_q_out) { | |
8ae6d9c7 | 2725 | lptr = rsp->ring_ptr; |
1f8deefe SK |
2726 | memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr, |
2727 | sizeof(rsp->rsp_pkt)); | |
8ae6d9c7 GM |
2728 | pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt; |
2729 | ||
2730 | rsp->ring_index++; | |
6ac1f3b5 | 2731 | lreq_q_out++; |
8ae6d9c7 | 2732 | if (rsp->ring_index == rsp->length) { |
6ac1f3b5 | 2733 | lreq_q_out = 0; |
8ae6d9c7 GM |
2734 | rsp->ring_index = 0; |
2735 | rsp->ring_ptr = rsp->ring; | |
2736 | } else { | |
2737 | rsp->ring_ptr++; | |
2738 | } | |
2739 | ||
2740 | if (pkt->entry_status != 0 && | |
2741 | pkt->entry_type != IOCTL_IOSB_TYPE_FX00) { | |
2c309aee BVA |
2742 | ql_dbg(ql_dbg_async, vha, 0x507f, |
2743 | "type of error status in response: 0x%x\n", | |
2744 | pkt->entry_status); | |
8ae6d9c7 | 2745 | qlafx00_error_entry(vha, rsp, |
2c309aee | 2746 | (struct sts_entry_fx00 *)pkt); |
8ae6d9c7 GM |
2747 | continue; |
2748 | } | |
2749 | ||
2750 | switch (pkt->entry_type) { | |
2751 | case STATUS_TYPE_FX00: | |
2752 | qlafx00_status_entry(vha, rsp, pkt); | |
2753 | break; | |
2754 | ||
2755 | case STATUS_CONT_TYPE_FX00: | |
2756 | qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt); | |
2757 | break; | |
2758 | ||
2759 | case MULTI_STATUS_TYPE_FX00: | |
2760 | qlafx00_multistatus_entry(vha, rsp, pkt); | |
2761 | break; | |
2762 | ||
2763 | case ABORT_IOCB_TYPE_FX00: | |
2764 | qlafx00_abort_iocb_entry(vha, rsp->req, | |
2765 | (struct abort_iocb_entry_fx00 *)pkt); | |
2766 | break; | |
2767 | ||
2768 | case IOCTL_IOSB_TYPE_FX00: | |
2769 | qlafx00_ioctl_iosb_entry(vha, rsp->req, | |
2770 | (struct ioctl_iocb_entry_fx00 *)pkt); | |
2771 | break; | |
2772 | default: | |
2773 | /* Type Not Supported. */ | |
2774 | ql_dbg(ql_dbg_async, vha, 0x5081, | |
2775 | "Received unknown response pkt type %x " | |
2776 | "entry status=%x.\n", | |
2777 | pkt->entry_type, pkt->entry_status); | |
2778 | break; | |
2779 | } | |
8ae6d9c7 GM |
2780 | } |
2781 | ||
2782 | /* Adjust ring index */ | |
2783 | WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index); | |
2784 | } | |
2785 | ||
2786 | /** | |
2787 | * qlafx00_async_event() - Process aynchronous events. | |
2db6228d | 2788 | * @vha: SCSI driver HA context |
8ae6d9c7 GM |
2789 | */ |
2790 | static void | |
2791 | qlafx00_async_event(scsi_qla_host_t *vha) | |
2792 | { | |
2793 | struct qla_hw_data *ha = vha->hw; | |
2794 | struct device_reg_fx00 __iomem *reg; | |
2795 | int data_size = 1; | |
2796 | ||
2797 | reg = &ha->iobase->ispfx00; | |
2798 | /* Setup to process RIO completion. */ | |
2799 | switch (ha->aenmb[0]) { | |
2800 | case QLAFX00_MBA_SYSTEM_ERR: /* System Error */ | |
2801 | ql_log(ql_log_warn, vha, 0x5079, | |
2802 | "ISP System Error - mbx1=%x\n", ha->aenmb[0]); | |
2803 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
2804 | break; | |
2805 | ||
2806 | case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */ | |
2807 | ql_dbg(ql_dbg_async, vha, 0x5076, | |
2808 | "Asynchronous FW shutdown requested.\n"); | |
2809 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
2810 | qla2xxx_wake_dpc(vha); | |
2811 | break; | |
2812 | ||
2813 | case QLAFX00_MBA_PORT_UPDATE: /* Port database update */ | |
965c77a6 SK |
2814 | ha->aenmb[1] = RD_REG_DWORD(®->aenmailbox1); |
2815 | ha->aenmb[2] = RD_REG_DWORD(®->aenmailbox2); | |
2816 | ha->aenmb[3] = RD_REG_DWORD(®->aenmailbox3); | |
8ae6d9c7 GM |
2817 | ql_dbg(ql_dbg_async, vha, 0x5077, |
2818 | "Asynchronous port Update received " | |
2819 | "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n", | |
2820 | ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]); | |
2821 | data_size = 4; | |
2822 | break; | |
71e56003 AB |
2823 | |
2824 | case QLAFX00_MBA_TEMP_OVER: /* Over temperature event */ | |
4881d095 AB |
2825 | ql_log(ql_log_info, vha, 0x5085, |
2826 | "Asynchronous over temperature event received " | |
2827 | "aenmb[0]: %x\n", | |
2828 | ha->aenmb[0]); | |
2829 | break; | |
2830 | ||
2831 | case QLAFX00_MBA_TEMP_NORM: /* Normal temperature event */ | |
2832 | ql_log(ql_log_info, vha, 0x5086, | |
2833 | "Asynchronous normal temperature event received " | |
2834 | "aenmb[0]: %x\n", | |
2835 | ha->aenmb[0]); | |
2836 | break; | |
2837 | ||
71e56003 AB |
2838 | case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */ |
2839 | ql_log(ql_log_info, vha, 0x5083, | |
2840 | "Asynchronous critical temperature event received " | |
2841 | "aenmb[0]: %x\n", | |
2842 | ha->aenmb[0]); | |
71e56003 AB |
2843 | break; |
2844 | ||
8ae6d9c7 GM |
2845 | default: |
2846 | ha->aenmb[1] = RD_REG_WORD(®->aenmailbox1); | |
2847 | ha->aenmb[2] = RD_REG_WORD(®->aenmailbox2); | |
2848 | ha->aenmb[3] = RD_REG_WORD(®->aenmailbox3); | |
2849 | ha->aenmb[4] = RD_REG_WORD(®->aenmailbox4); | |
2850 | ha->aenmb[5] = RD_REG_WORD(®->aenmailbox5); | |
2851 | ha->aenmb[6] = RD_REG_WORD(®->aenmailbox6); | |
2852 | ha->aenmb[7] = RD_REG_WORD(®->aenmailbox7); | |
2853 | ql_dbg(ql_dbg_async, vha, 0x5078, | |
2854 | "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n", | |
2855 | ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3], | |
2856 | ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]); | |
2857 | break; | |
2858 | } | |
2859 | qlafx00_post_aenfx_work(vha, ha->aenmb[0], | |
2860 | (uint32_t *)ha->aenmb, data_size); | |
2861 | } | |
2862 | ||
2863 | /** | |
8ae6d9c7 | 2864 | * qlafx00x_mbx_completion() - Process mailbox command completions. |
2db6228d | 2865 | * @vha: SCSI driver HA context |
807eb907 | 2866 | * @mb0: value to be written into mailbox register 0 |
8ae6d9c7 GM |
2867 | */ |
2868 | static void | |
2869 | qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0) | |
2870 | { | |
2871 | uint16_t cnt; | |
965c77a6 | 2872 | uint32_t __iomem *wptr; |
8ae6d9c7 GM |
2873 | struct qla_hw_data *ha = vha->hw; |
2874 | struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; | |
2875 | ||
2876 | if (!ha->mcp32) | |
2877 | ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n"); | |
2878 | ||
2879 | /* Load return mailbox registers. */ | |
2880 | ha->flags.mbox_int = 1; | |
2881 | ha->mailbox_out32[0] = mb0; | |
965c77a6 | 2882 | wptr = (uint32_t __iomem *)®->mailbox17; |
8ae6d9c7 GM |
2883 | |
2884 | for (cnt = 1; cnt < ha->mbx_count; cnt++) { | |
965c77a6 | 2885 | ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr); |
8ae6d9c7 GM |
2886 | wptr++; |
2887 | } | |
2888 | } | |
2889 | ||
2890 | /** | |
2891 | * qlafx00_intr_handler() - Process interrupts for the ISPFX00. | |
807eb907 | 2892 | * @irq: interrupt number |
8ae6d9c7 GM |
2893 | * @dev_id: SCSI driver HA context |
2894 | * | |
2895 | * Called by system whenever the host adapter generates an interrupt. | |
2896 | * | |
2897 | * Returns handled flag. | |
2898 | */ | |
2899 | irqreturn_t | |
2900 | qlafx00_intr_handler(int irq, void *dev_id) | |
2901 | { | |
2902 | scsi_qla_host_t *vha; | |
2903 | struct qla_hw_data *ha; | |
2904 | struct device_reg_fx00 __iomem *reg; | |
2905 | int status; | |
2906 | unsigned long iter; | |
2907 | uint32_t stat; | |
2908 | uint32_t mb[8]; | |
2909 | struct rsp_que *rsp; | |
2910 | unsigned long flags; | |
2911 | uint32_t clr_intr = 0; | |
fbe9c54b | 2912 | uint32_t intr_stat = 0; |
8ae6d9c7 GM |
2913 | |
2914 | rsp = (struct rsp_que *) dev_id; | |
2915 | if (!rsp) { | |
2916 | ql_log(ql_log_info, NULL, 0x507d, | |
2917 | "%s: NULL response queue pointer.\n", __func__); | |
2918 | return IRQ_NONE; | |
2919 | } | |
2920 | ||
2921 | ha = rsp->hw; | |
2922 | reg = &ha->iobase->ispfx00; | |
2923 | status = 0; | |
2924 | ||
2925 | if (unlikely(pci_channel_offline(ha->pdev))) | |
2926 | return IRQ_HANDLED; | |
2927 | ||
2928 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2929 | vha = pci_get_drvdata(ha->pdev); | |
2930 | for (iter = 50; iter--; clr_intr = 0) { | |
2931 | stat = QLAFX00_RD_INTR_REG(ha); | |
c821e0d5 | 2932 | if (qla2x00_check_reg32_for_disconnect(vha, stat)) |
f3ddac19 | 2933 | break; |
fbe9c54b SK |
2934 | intr_stat = stat & QLAFX00_HST_INT_STS_BITS; |
2935 | if (!intr_stat) | |
8ae6d9c7 GM |
2936 | break; |
2937 | ||
fbe9c54b | 2938 | if (stat & QLAFX00_INTR_MB_CMPLT) { |
8ae6d9c7 GM |
2939 | mb[0] = RD_REG_WORD(®->mailbox16); |
2940 | qlafx00_mbx_completion(vha, mb[0]); | |
2941 | status |= MBX_INTERRUPT; | |
2942 | clr_intr |= QLAFX00_INTR_MB_CMPLT; | |
fbe9c54b SK |
2943 | } |
2944 | if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) { | |
8ae6d9c7 GM |
2945 | ha->aenmb[0] = RD_REG_WORD(®->aenmailbox0); |
2946 | qlafx00_async_event(vha); | |
2947 | clr_intr |= QLAFX00_INTR_ASYNC_CMPLT; | |
fbe9c54b SK |
2948 | } |
2949 | if (intr_stat & QLAFX00_INTR_RSP_CMPLT) { | |
8ae6d9c7 GM |
2950 | qlafx00_process_response_queue(vha, rsp); |
2951 | clr_intr |= QLAFX00_INTR_RSP_CMPLT; | |
8ae6d9c7 | 2952 | } |
fbe9c54b | 2953 | |
8ae6d9c7 GM |
2954 | QLAFX00_CLR_INTR_REG(ha, clr_intr); |
2955 | QLAFX00_RD_INTR_REG(ha); | |
2956 | } | |
36439832 | 2957 | |
2958 | qla2x00_handle_mbx_completion(ha, status); | |
8ae6d9c7 GM |
2959 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
2960 | ||
8ae6d9c7 GM |
2961 | return IRQ_HANDLED; |
2962 | } | |
2963 | ||
2964 | /** QLAFX00 specific IOCB implementation functions */ | |
2965 | ||
2966 | static inline cont_a64_entry_t * | |
2967 | qlafx00_prep_cont_type1_iocb(struct req_que *req, | |
2968 | cont_a64_entry_t *lcont_pkt) | |
2969 | { | |
2970 | cont_a64_entry_t *cont_pkt; | |
2971 | ||
2972 | /* Adjust ring index. */ | |
2973 | req->ring_index++; | |
2974 | if (req->ring_index == req->length) { | |
2975 | req->ring_index = 0; | |
2976 | req->ring_ptr = req->ring; | |
2977 | } else { | |
2978 | req->ring_ptr++; | |
2979 | } | |
2980 | ||
2981 | cont_pkt = (cont_a64_entry_t *)req->ring_ptr; | |
2982 | ||
2983 | /* Load packet defaults. */ | |
1f8deefe | 2984 | lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00; |
8ae6d9c7 GM |
2985 | |
2986 | return cont_pkt; | |
2987 | } | |
2988 | ||
2989 | static inline void | |
2990 | qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt, | |
2991 | uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt) | |
2992 | { | |
2993 | uint16_t avail_dsds; | |
15b7a68c | 2994 | struct dsd64 *cur_dsd; |
8ae6d9c7 GM |
2995 | scsi_qla_host_t *vha; |
2996 | struct scsi_cmnd *cmd; | |
2997 | struct scatterlist *sg; | |
2998 | int i, cont; | |
2999 | struct req_que *req; | |
3000 | cont_a64_entry_t lcont_pkt; | |
3001 | cont_a64_entry_t *cont_pkt; | |
3002 | ||
25ff6af1 | 3003 | vha = sp->vha; |
8ae6d9c7 GM |
3004 | req = vha->req; |
3005 | ||
3006 | cmd = GET_CMD_SP(sp); | |
3007 | cont = 0; | |
3008 | cont_pkt = NULL; | |
3009 | ||
3010 | /* Update entry type to indicate Command Type 3 IOCB */ | |
1f8deefe | 3011 | lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7; |
8ae6d9c7 GM |
3012 | |
3013 | /* No data transfer */ | |
3014 | if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { | |
ad950360 | 3015 | lcmd_pkt->byte_count = cpu_to_le32(0); |
8ae6d9c7 GM |
3016 | return; |
3017 | } | |
3018 | ||
3019 | /* Set transfer direction */ | |
3020 | if (cmd->sc_data_direction == DMA_TO_DEVICE) { | |
378c538d | 3021 | lcmd_pkt->cntrl_flags = TMF_WRITE_DATA; |
8ae6d9c7 GM |
3022 | vha->qla_stats.output_bytes += scsi_bufflen(cmd); |
3023 | } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) { | |
378c538d | 3024 | lcmd_pkt->cntrl_flags = TMF_READ_DATA; |
8ae6d9c7 GM |
3025 | vha->qla_stats.input_bytes += scsi_bufflen(cmd); |
3026 | } | |
3027 | ||
3028 | /* One DSD is available in the Command Type 3 IOCB */ | |
3029 | avail_dsds = 1; | |
15b7a68c | 3030 | cur_dsd = &lcmd_pkt->dsd; |
8ae6d9c7 GM |
3031 | |
3032 | /* Load data segments */ | |
3033 | scsi_for_each_sg(cmd, sg, tot_dsds, i) { | |
8ae6d9c7 GM |
3034 | /* Allocate additional continuation packets? */ |
3035 | if (avail_dsds == 0) { | |
3036 | /* | |
3037 | * Five DSDs are available in the Continuation | |
3038 | * Type 1 IOCB. | |
3039 | */ | |
3040 | memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE); | |
3041 | cont_pkt = | |
3042 | qlafx00_prep_cont_type1_iocb(req, &lcont_pkt); | |
15b7a68c | 3043 | cur_dsd = lcont_pkt.dsd; |
8ae6d9c7 GM |
3044 | avail_dsds = 5; |
3045 | cont = 1; | |
3046 | } | |
3047 | ||
15b7a68c | 3048 | append_dsd64(&cur_dsd, sg); |
8ae6d9c7 GM |
3049 | avail_dsds--; |
3050 | if (avail_dsds == 0 && cont == 1) { | |
3051 | cont = 0; | |
3052 | memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt, | |
f8f97b0c | 3053 | sizeof(lcont_pkt)); |
8ae6d9c7 GM |
3054 | } |
3055 | ||
3056 | } | |
3057 | if (avail_dsds != 0 && cont == 1) { | |
3058 | memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt, | |
f8f97b0c | 3059 | sizeof(lcont_pkt)); |
8ae6d9c7 GM |
3060 | } |
3061 | } | |
3062 | ||
3063 | /** | |
3064 | * qlafx00_start_scsi() - Send a SCSI command to the ISP | |
3065 | * @sp: command to send to the ISP | |
3066 | * | |
3067 | * Returns non-zero if a failure occurred, else zero. | |
3068 | */ | |
3069 | int | |
3070 | qlafx00_start_scsi(srb_t *sp) | |
3071 | { | |
52c82823 | 3072 | int nseg; |
8ae6d9c7 GM |
3073 | unsigned long flags; |
3074 | uint32_t index; | |
3075 | uint32_t handle; | |
3076 | uint16_t cnt; | |
3077 | uint16_t req_cnt; | |
3078 | uint16_t tot_dsds; | |
3079 | struct req_que *req = NULL; | |
3080 | struct rsp_que *rsp = NULL; | |
3081 | struct scsi_cmnd *cmd = GET_CMD_SP(sp); | |
25ff6af1 | 3082 | struct scsi_qla_host *vha = sp->vha; |
8ae6d9c7 GM |
3083 | struct qla_hw_data *ha = vha->hw; |
3084 | struct cmd_type_7_fx00 *cmd_pkt; | |
3085 | struct cmd_type_7_fx00 lcmd_pkt; | |
3086 | struct scsi_lun llun; | |
8ae6d9c7 GM |
3087 | |
3088 | /* Setup device pointers. */ | |
8ae6d9c7 GM |
3089 | rsp = ha->rsp_q_map[0]; |
3090 | req = vha->req; | |
3091 | ||
3092 | /* So we know we haven't pci_map'ed anything yet */ | |
3093 | tot_dsds = 0; | |
3094 | ||
8ae6d9c7 GM |
3095 | /* Acquire ring specific lock */ |
3096 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
3097 | ||
3098 | /* Check for room in outstanding command list. */ | |
3099 | handle = req->current_outstanding_cmd; | |
3100 | for (index = 1; index < req->num_outstanding_cmds; index++) { | |
3101 | handle++; | |
3102 | if (handle == req->num_outstanding_cmds) | |
3103 | handle = 1; | |
3104 | if (!req->outstanding_cmds[handle]) | |
3105 | break; | |
3106 | } | |
3107 | if (index == req->num_outstanding_cmds) | |
3108 | goto queuing_error; | |
3109 | ||
3110 | /* Map the sg table so we have an accurate count of sg entries needed */ | |
3111 | if (scsi_sg_count(cmd)) { | |
3112 | nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd), | |
3113 | scsi_sg_count(cmd), cmd->sc_data_direction); | |
3114 | if (unlikely(!nseg)) | |
3115 | goto queuing_error; | |
3116 | } else | |
3117 | nseg = 0; | |
3118 | ||
3119 | tot_dsds = nseg; | |
3120 | req_cnt = qla24xx_calc_iocbs(vha, tot_dsds); | |
3121 | if (req->cnt < (req_cnt + 2)) { | |
3122 | cnt = RD_REG_DWORD_RELAXED(req->req_q_out); | |
3123 | ||
3124 | if (req->ring_index < cnt) | |
3125 | req->cnt = cnt - req->ring_index; | |
3126 | else | |
3127 | req->cnt = req->length - | |
3128 | (req->ring_index - cnt); | |
3129 | if (req->cnt < (req_cnt + 2)) | |
3130 | goto queuing_error; | |
3131 | } | |
3132 | ||
3133 | /* Build command packet. */ | |
3134 | req->current_outstanding_cmd = handle; | |
3135 | req->outstanding_cmds[handle] = sp; | |
3136 | sp->handle = handle; | |
3137 | cmd->host_scribble = (unsigned char *)(unsigned long)handle; | |
3138 | req->cnt -= req_cnt; | |
3139 | ||
3140 | cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr; | |
3141 | ||
3142 | memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE); | |
3143 | ||
3144 | lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle); | |
d68b3e01 AB |
3145 | lcmd_pkt.reserved_0 = 0; |
3146 | lcmd_pkt.port_path_ctrl = 0; | |
3147 | lcmd_pkt.reserved_1 = 0; | |
8ae6d9c7 GM |
3148 | lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds); |
3149 | lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id); | |
3150 | ||
3151 | int_to_scsilun(cmd->device->lun, &llun); | |
3152 | host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun, | |
3153 | sizeof(lcmd_pkt.lun)); | |
3154 | ||
8ae6d9c7 GM |
3155 | /* Load SCSI command packet. */ |
3156 | host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb)); | |
3157 | lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); | |
3158 | ||
3159 | /* Build IOCB segments */ | |
3160 | qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt); | |
3161 | ||
3162 | /* Set total data segment count. */ | |
3163 | lcmd_pkt.entry_count = (uint8_t)req_cnt; | |
3164 | ||
3165 | /* Specify response queue number where completion should happen */ | |
3166 | lcmd_pkt.entry_status = (uint8_t) rsp->id; | |
3167 | ||
3168 | ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e, | |
f8f97b0c | 3169 | cmd->cmnd, cmd->cmd_len); |
8ae6d9c7 | 3170 | ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032, |
f8f97b0c | 3171 | &lcmd_pkt, sizeof(lcmd_pkt)); |
8ae6d9c7 GM |
3172 | |
3173 | memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE); | |
3174 | wmb(); | |
3175 | ||
3176 | /* Adjust ring index. */ | |
3177 | req->ring_index++; | |
3178 | if (req->ring_index == req->length) { | |
3179 | req->ring_index = 0; | |
3180 | req->ring_ptr = req->ring; | |
3181 | } else | |
3182 | req->ring_ptr++; | |
3183 | ||
3184 | sp->flags |= SRB_DMA_VALID; | |
3185 | ||
3186 | /* Set chip new ring index. */ | |
3187 | WRT_REG_DWORD(req->req_q_in, req->ring_index); | |
3188 | QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code); | |
3189 | ||
3190 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
3191 | return QLA_SUCCESS; | |
3192 | ||
3193 | queuing_error: | |
3194 | if (tot_dsds) | |
3195 | scsi_dma_unmap(cmd); | |
3196 | ||
3197 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
3198 | ||
3199 | return QLA_FUNCTION_FAILED; | |
3200 | } | |
3201 | ||
3202 | void | |
3203 | qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb) | |
3204 | { | |
3205 | struct srb_iocb *fxio = &sp->u.iocb_cmd; | |
25ff6af1 | 3206 | scsi_qla_host_t *vha = sp->vha; |
8ae6d9c7 GM |
3207 | struct req_que *req = vha->req; |
3208 | struct tsk_mgmt_entry_fx00 tm_iocb; | |
3209 | struct scsi_lun llun; | |
3210 | ||
3211 | memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00)); | |
3212 | tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00; | |
3213 | tm_iocb.entry_count = 1; | |
3214 | tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle)); | |
d68b3e01 | 3215 | tm_iocb.reserved_0 = 0; |
8ae6d9c7 GM |
3216 | tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id); |
3217 | tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags); | |
1f8deefe | 3218 | if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) { |
8ae6d9c7 GM |
3219 | int_to_scsilun(fxio->u.tmf.lun, &llun); |
3220 | host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun, | |
3221 | sizeof(struct scsi_lun)); | |
3222 | } | |
3223 | ||
1f8deefe | 3224 | memcpy((void *)ptm_iocb, &tm_iocb, |
8ae6d9c7 GM |
3225 | sizeof(struct tsk_mgmt_entry_fx00)); |
3226 | wmb(); | |
3227 | } | |
3228 | ||
3229 | void | |
3230 | qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb) | |
3231 | { | |
3232 | struct srb_iocb *fxio = &sp->u.iocb_cmd; | |
25ff6af1 | 3233 | scsi_qla_host_t *vha = sp->vha; |
8ae6d9c7 GM |
3234 | struct req_que *req = vha->req; |
3235 | struct abort_iocb_entry_fx00 abt_iocb; | |
3236 | ||
3237 | memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00)); | |
3238 | abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00; | |
3239 | abt_iocb.entry_count = 1; | |
3240 | abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle)); | |
3241 | abt_iocb.abort_handle = | |
3242 | cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl)); | |
3243 | abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id); | |
3244 | abt_iocb.req_que_no = cpu_to_le16(req->id); | |
3245 | ||
1f8deefe | 3246 | memcpy((void *)pabt_iocb, &abt_iocb, |
8ae6d9c7 GM |
3247 | sizeof(struct abort_iocb_entry_fx00)); |
3248 | wmb(); | |
3249 | } | |
3250 | ||
3251 | void | |
3252 | qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb) | |
3253 | { | |
3254 | struct srb_iocb *fxio = &sp->u.iocb_cmd; | |
3255 | struct qla_mt_iocb_rqst_fx00 *piocb_rqst; | |
75cc8cfc | 3256 | struct bsg_job *bsg_job; |
01e0e15c | 3257 | struct fc_bsg_request *bsg_request; |
8ae6d9c7 GM |
3258 | struct fxdisc_entry_fx00 fx_iocb; |
3259 | uint8_t entry_cnt = 1; | |
3260 | ||
3261 | memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00)); | |
3262 | fx_iocb.entry_type = FX00_IOCB_TYPE; | |
3263 | fx_iocb.handle = cpu_to_le32(sp->handle); | |
3264 | fx_iocb.entry_count = entry_cnt; | |
3265 | ||
3266 | if (sp->type == SRB_FXIOCB_DCMD) { | |
3267 | fx_iocb.func_num = | |
1f8deefe SK |
3268 | sp->u.iocb_cmd.u.fxiocb.req_func_type; |
3269 | fx_iocb.adapid = fxio->u.fxiocb.adapter_id; | |
3270 | fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi; | |
3271 | fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0; | |
3272 | fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1; | |
3273 | fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra; | |
8ae6d9c7 GM |
3274 | |
3275 | if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) { | |
3276 | fx_iocb.req_dsdcnt = cpu_to_le16(1); | |
3277 | fx_iocb.req_xfrcnt = | |
3278 | cpu_to_le16(fxio->u.fxiocb.req_len); | |
d4556a49 BVA |
3279 | put_unaligned_le64(fxio->u.fxiocb.req_dma_handle, |
3280 | &fx_iocb.dseg_rq.address); | |
15b7a68c | 3281 | fx_iocb.dseg_rq.length = |
8ae6d9c7 GM |
3282 | cpu_to_le32(fxio->u.fxiocb.req_len); |
3283 | } | |
3284 | ||
3285 | if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) { | |
3286 | fx_iocb.rsp_dsdcnt = cpu_to_le16(1); | |
3287 | fx_iocb.rsp_xfrcnt = | |
3288 | cpu_to_le16(fxio->u.fxiocb.rsp_len); | |
d4556a49 BVA |
3289 | put_unaligned_le64(fxio->u.fxiocb.rsp_dma_handle, |
3290 | &fx_iocb.dseg_rsp.address); | |
15b7a68c | 3291 | fx_iocb.dseg_rsp.length = |
8ae6d9c7 GM |
3292 | cpu_to_le32(fxio->u.fxiocb.rsp_len); |
3293 | } | |
3294 | ||
3295 | if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) { | |
1f8deefe | 3296 | fx_iocb.dataword = fxio->u.fxiocb.req_data; |
8ae6d9c7 GM |
3297 | } |
3298 | fx_iocb.flags = fxio->u.fxiocb.flags; | |
3299 | } else { | |
3300 | struct scatterlist *sg; | |
bd432bb5 | 3301 | |
8ae6d9c7 | 3302 | bsg_job = sp->u.bsg_job; |
01e0e15c | 3303 | bsg_request = bsg_job->request; |
8ae6d9c7 | 3304 | piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *) |
01e0e15c | 3305 | &bsg_request->rqst_data.h_vendor.vendor_cmd[1]; |
8ae6d9c7 GM |
3306 | |
3307 | fx_iocb.func_num = piocb_rqst->func_type; | |
3308 | fx_iocb.adapid = piocb_rqst->adapid; | |
3309 | fx_iocb.adapid_hi = piocb_rqst->adapid_hi; | |
3310 | fx_iocb.reserved_0 = piocb_rqst->reserved_0; | |
3311 | fx_iocb.reserved_1 = piocb_rqst->reserved_1; | |
3312 | fx_iocb.dataword_extra = piocb_rqst->dataword_extra; | |
3313 | fx_iocb.dataword = piocb_rqst->dataword; | |
1f8deefe SK |
3314 | fx_iocb.req_xfrcnt = piocb_rqst->req_len; |
3315 | fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len; | |
8ae6d9c7 GM |
3316 | |
3317 | if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) { | |
3318 | int avail_dsds, tot_dsds; | |
3319 | cont_a64_entry_t lcont_pkt; | |
3320 | cont_a64_entry_t *cont_pkt = NULL; | |
15b7a68c | 3321 | struct dsd64 *cur_dsd; |
8ae6d9c7 GM |
3322 | int index = 0, cont = 0; |
3323 | ||
3324 | fx_iocb.req_dsdcnt = | |
3325 | cpu_to_le16(bsg_job->request_payload.sg_cnt); | |
3326 | tot_dsds = | |
1f8deefe | 3327 | bsg_job->request_payload.sg_cnt; |
15b7a68c | 3328 | cur_dsd = &fx_iocb.dseg_rq; |
8ae6d9c7 GM |
3329 | avail_dsds = 1; |
3330 | for_each_sg(bsg_job->request_payload.sg_list, sg, | |
3331 | tot_dsds, index) { | |
8ae6d9c7 GM |
3332 | /* Allocate additional continuation packets? */ |
3333 | if (avail_dsds == 0) { | |
3334 | /* | |
3335 | * Five DSDs are available in the Cont. | |
3336 | * Type 1 IOCB. | |
3337 | */ | |
3338 | memset(&lcont_pkt, 0, | |
3339 | REQUEST_ENTRY_SIZE); | |
3340 | cont_pkt = | |
3341 | qlafx00_prep_cont_type1_iocb( | |
25ff6af1 | 3342 | sp->vha->req, &lcont_pkt); |
15b7a68c | 3343 | cur_dsd = lcont_pkt.dsd; |
8ae6d9c7 GM |
3344 | avail_dsds = 5; |
3345 | cont = 1; | |
3346 | entry_cnt++; | |
3347 | } | |
3348 | ||
15b7a68c | 3349 | append_dsd64(&cur_dsd, sg); |
8ae6d9c7 GM |
3350 | avail_dsds--; |
3351 | ||
3352 | if (avail_dsds == 0 && cont == 1) { | |
3353 | cont = 0; | |
3354 | memcpy_toio( | |
3355 | (void __iomem *)cont_pkt, | |
3356 | &lcont_pkt, REQUEST_ENTRY_SIZE); | |
3357 | ql_dump_buffer( | |
3358 | ql_dbg_user + ql_dbg_verbose, | |
25ff6af1 | 3359 | sp->vha, 0x3042, |
8ae6d9c7 GM |
3360 | (uint8_t *)&lcont_pkt, |
3361 | REQUEST_ENTRY_SIZE); | |
3362 | } | |
3363 | } | |
3364 | if (avail_dsds != 0 && cont == 1) { | |
3365 | memcpy_toio((void __iomem *)cont_pkt, | |
3366 | &lcont_pkt, REQUEST_ENTRY_SIZE); | |
3367 | ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, | |
25ff6af1 | 3368 | sp->vha, 0x3043, |
8ae6d9c7 GM |
3369 | (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE); |
3370 | } | |
3371 | } | |
3372 | ||
3373 | if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) { | |
3374 | int avail_dsds, tot_dsds; | |
3375 | cont_a64_entry_t lcont_pkt; | |
3376 | cont_a64_entry_t *cont_pkt = NULL; | |
15b7a68c | 3377 | struct dsd64 *cur_dsd; |
8ae6d9c7 GM |
3378 | int index = 0, cont = 0; |
3379 | ||
3380 | fx_iocb.rsp_dsdcnt = | |
3381 | cpu_to_le16(bsg_job->reply_payload.sg_cnt); | |
1f8deefe | 3382 | tot_dsds = bsg_job->reply_payload.sg_cnt; |
15b7a68c | 3383 | cur_dsd = &fx_iocb.dseg_rsp; |
8ae6d9c7 GM |
3384 | avail_dsds = 1; |
3385 | ||
3386 | for_each_sg(bsg_job->reply_payload.sg_list, sg, | |
3387 | tot_dsds, index) { | |
8ae6d9c7 GM |
3388 | /* Allocate additional continuation packets? */ |
3389 | if (avail_dsds == 0) { | |
3390 | /* | |
3391 | * Five DSDs are available in the Cont. | |
3392 | * Type 1 IOCB. | |
3393 | */ | |
3394 | memset(&lcont_pkt, 0, | |
3395 | REQUEST_ENTRY_SIZE); | |
3396 | cont_pkt = | |
3397 | qlafx00_prep_cont_type1_iocb( | |
25ff6af1 | 3398 | sp->vha->req, &lcont_pkt); |
15b7a68c | 3399 | cur_dsd = lcont_pkt.dsd; |
8ae6d9c7 GM |
3400 | avail_dsds = 5; |
3401 | cont = 1; | |
3402 | entry_cnt++; | |
3403 | } | |
3404 | ||
15b7a68c | 3405 | append_dsd64(&cur_dsd, sg); |
8ae6d9c7 GM |
3406 | avail_dsds--; |
3407 | ||
3408 | if (avail_dsds == 0 && cont == 1) { | |
3409 | cont = 0; | |
3410 | memcpy_toio((void __iomem *)cont_pkt, | |
3411 | &lcont_pkt, | |
3412 | REQUEST_ENTRY_SIZE); | |
3413 | ql_dump_buffer( | |
3414 | ql_dbg_user + ql_dbg_verbose, | |
25ff6af1 | 3415 | sp->vha, 0x3045, |
8ae6d9c7 GM |
3416 | (uint8_t *)&lcont_pkt, |
3417 | REQUEST_ENTRY_SIZE); | |
3418 | } | |
3419 | } | |
3420 | if (avail_dsds != 0 && cont == 1) { | |
3421 | memcpy_toio((void __iomem *)cont_pkt, | |
3422 | &lcont_pkt, REQUEST_ENTRY_SIZE); | |
3423 | ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, | |
25ff6af1 | 3424 | sp->vha, 0x3046, |
8ae6d9c7 GM |
3425 | (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE); |
3426 | } | |
3427 | } | |
3428 | ||
3429 | if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID) | |
1f8deefe | 3430 | fx_iocb.dataword = piocb_rqst->dataword; |
8ae6d9c7 GM |
3431 | fx_iocb.flags = piocb_rqst->flags; |
3432 | fx_iocb.entry_count = entry_cnt; | |
3433 | } | |
3434 | ||
3435 | ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, | |
f8f97b0c | 3436 | sp->vha, 0x3047, &fx_iocb, sizeof(fx_iocb)); |
8ae6d9c7 | 3437 | |
f8f97b0c | 3438 | memcpy_toio((void __iomem *)pfxiocb, &fx_iocb, sizeof(fx_iocb)); |
8ae6d9c7 GM |
3439 | wmb(); |
3440 | } |