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scsi: qla2xxx: Enable type checking for the SRB free and done callback functions
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_mbx.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
2d70c103 8#include "qla_target.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/gfp.h>
1da177e4 12
15f30a57
QT		 13static struct mb_cmd_name {
14 uint16_t cmd;
15 const char *str;
16} mb_str[] = {
17 {MBC_GET_PORT_DATABASE, "GPDB"},
18 {MBC_GET_ID_LIST, "GIDList"},
19 {MBC_GET_LINK_PRIV_STATS, "Stats"},
94d83e36 20 {MBC_GET_RESOURCE_COUNTS, "ResCnt"},
15f30a57
QT		 21};
22
23static const char *mb_to_str(uint16_t cmd)
24{
25 int i;
26 struct mb_cmd_name *e;
27
28 for (i = 0; i < ARRAY_SIZE(mb_str); i++) {
29 e = mb_str + i;
30 if (cmd == e->cmd)
31 return e->str;
32 }
33 return "unknown";
34}
35
ca825828 36static struct rom_cmd {
77ddb94a 37 uint16_t cmd;
38} rom_cmds[] = {
39 { MBC_LOAD_RAM },
40 { MBC_EXECUTE_FIRMWARE },
41 { MBC_READ_RAM_WORD },
42 { MBC_MAILBOX_REGISTER_TEST },
43 { MBC_VERIFY_CHECKSUM },
44 { MBC_GET_FIRMWARE_VERSION },
45 { MBC_LOAD_RISC_RAM },
46 { MBC_DUMP_RISC_RAM },
47 { MBC_LOAD_RISC_RAM_EXTENDED },
48 { MBC_DUMP_RISC_RAM_EXTENDED },
49 { MBC_WRITE_RAM_WORD_EXTENDED },
50 { MBC_READ_RAM_EXTENDED },
51 { MBC_GET_RESOURCE_COUNTS },
52 { MBC_SET_FIRMWARE_OPTION },
53 { MBC_MID_INITIALIZE_FIRMWARE },
54 { MBC_GET_FIRMWARE_STATE },
55 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT },
56 { MBC_GET_RETRY_COUNT },
57 { MBC_TRACE_CONTROL },
b7edfa23 58 { MBC_INITIALIZE_MULTIQ },
1608cc4a
QT		 59 { MBC_IOCB_COMMAND_A64 },
60 { MBC_GET_ADAPTER_LOOP_ID },
e4e3a2ce 61 { MBC_READ_SFP },
8777e431 62 { MBC_GET_RNID_PARAMS },
8b4673ba 63 { MBC_GET_SET_ZIO_THRESHOLD },
77ddb94a 64};
65
66static int is_rom_cmd(uint16_t cmd)
67{
68 int i;
69 struct rom_cmd *wc;
70
71 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) {
72 wc = rom_cmds + i;
73 if (wc->cmd == cmd)
74 return 1;
75 }
76
77 return 0;
78}
1da177e4
LT		 79
80/*
81 * qla2x00_mailbox_command
82 * Issue mailbox command and waits for completion.
83 *
84 * Input:
85 * ha = adapter block pointer.
86 * mcp = driver internal mbx struct pointer.
87 *
88 * Output:
89 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
90 *
91 * Returns:
92 * 0 : QLA_SUCCESS = cmd performed success
93 * 1 : QLA_FUNCTION_FAILED (error encountered)
94 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
95 *
96 * Context:
97 * Kernel context.
98 */
99static int
7b867cf7 100qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
1da177e4 101{
d14e72fb 102 int rval, i;
1da177e4 103 unsigned long flags = 0;
f73cb695 104 device_reg_t *reg;
1c7c6357 105 uint8_t abort_active;
2c3dfe3f 106 uint8_t io_lock_on;
cdbb0a4f 107 uint16_t command = 0;
1da177e4
LT		 108 uint16_t *iptr;
109 uint16_t __iomem *optr;
110 uint32_t cnt;
111 uint32_t mboxes;
1da177e4 112 unsigned long wait_time;
7b867cf7
AC		 113 struct qla_hw_data *ha = vha->hw;
114 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
b2000805 115 u32 chip_reset;
2c3dfe3f 116
d14e72fb 117
5e19ed90 118 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
7c3df132
SK		 119
120 if (ha->pdev->error_state > pci_channel_io_frozen) {
5e19ed90 121 ql_log(ql_log_warn, vha, 0x1001,
7c3df132
SK		 122 "error_state is greater than pci_channel_io_frozen, "
123 "exiting.\n");
b9b12f73 124 return QLA_FUNCTION_TIMEOUT;
7c3df132 125 }
b9b12f73 126
a9083016 127 if (vha->device_flags & DFLG_DEV_FAILED) {
5e19ed90 128 ql_log(ql_log_warn, vha, 0x1002,
7c3df132 129 "Device in failed state, exiting.\n");
a9083016
GM		 130 return QLA_FUNCTION_TIMEOUT;
131 }
132
c2a5d94f 133 /* if PCI error, then avoid mbx processing.*/
ba175891
SC		 134 if (test_bit(PFLG_DISCONNECTED, &base_vha->dpc_flags) &&
135 test_bit(UNLOADING, &base_vha->dpc_flags)) {
83548fe2 136 ql_log(ql_log_warn, vha, 0xd04e,
783e0dc4
SC		 137 "PCI error, exiting.\n");
138 return QLA_FUNCTION_TIMEOUT;
c2a5d94f 139 }
783e0dc4 140
2c3dfe3f 141 reg = ha->iobase;
7b867cf7 142 io_lock_on = base_vha->flags.init_done;
1da177e4
LT		 143
144 rval = QLA_SUCCESS;
7b867cf7 145 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
b2000805 146 chip_reset = ha->chip_reset;
1da177e4 147
85880801 148 if (ha->flags.pci_channel_io_perm_failure) {
5e19ed90 149 ql_log(ql_log_warn, vha, 0x1003,
7c3df132 150 "Perm failure on EEH timeout MBX, exiting.\n");
85880801
AV		 151 return QLA_FUNCTION_TIMEOUT;
152 }
153
7ec0effd 154 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
862cd01e
GM		 155 /* Setting Link-Down error */
156 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
5e19ed90 157 ql_log(ql_log_warn, vha, 0x1004,
7c3df132 158 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
1806fcd5 159 return QLA_FUNCTION_TIMEOUT;
862cd01e
GM		 160 }
161
77ddb94a 162 /* check if ISP abort is active and return cmd with timeout */
163 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
164 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
165 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) &&
166 !is_rom_cmd(mcp->mb[0])) {
167 ql_log(ql_log_info, vha, 0x1005,
168 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n",
169 mcp->mb[0]);
170 return QLA_FUNCTION_TIMEOUT;
171 }
172
b2000805 173 atomic_inc(&ha->num_pend_mbx_stage1);
1da177e4 174 /*
1c7c6357
AV		 175 * Wait for active mailbox commands to finish by waiting at most tov
176 * seconds. This is to serialize actual issuing of mailbox cmds during
177 * non ISP abort time.
1da177e4 178 */
8eca3f39
AV		 179 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
180 /* Timeout occurred. Return error. */
83548fe2 181 ql_log(ql_log_warn, vha, 0xd035,
d8c0d546
CD		 182 "Cmd access timeout, cmd=0x%x, Exiting.\n",
183 mcp->mb[0]);
b2000805 184 atomic_dec(&ha->num_pend_mbx_stage1);
8eca3f39 185 return QLA_FUNCTION_TIMEOUT;
1da177e4 186 }
b2000805
QT		 187 atomic_dec(&ha->num_pend_mbx_stage1);
188 if (ha->flags.purge_mbox || chip_reset != ha->chip_reset) {
189 rval = QLA_ABORTED;
190 goto premature_exit;
191 }
1da177e4 192
b6faaaf7 193
1da177e4
LT		 194 /* Save mailbox command for debug */
195 ha->mcp = mcp;
196
5e19ed90 197 ql_dbg(ql_dbg_mbx, vha, 0x1006,
7c3df132 198 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
1da177e4
LT		 199
200 spin_lock_irqsave(&ha->hardware_lock, flags);
201
b6faaaf7
QT		 202 if (ha->flags.purge_mbox || chip_reset != ha->chip_reset ||
203 ha->flags.mbox_busy) {
b2000805 204 rval = QLA_ABORTED;
b2000805
QT		 205 spin_unlock_irqrestore(&ha->hardware_lock, flags);
206 goto premature_exit;
207 }
b6faaaf7 208 ha->flags.mbox_busy = 1;
b2000805 209
1da177e4 210 /* Load mailbox registers. */
7ec0effd 211 if (IS_P3P_TYPE(ha))
a9083016 212 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
7ec0effd 213 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
1c7c6357
AV		 214 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
215 else
216 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
1da177e4
LT		 217
218 iptr = mcp->mb;
219 command = mcp->mb[0];
220 mboxes = mcp->out_mb;
221
7b711623 222 ql_dbg(ql_dbg_mbx, vha, 0x1111,
0e31a2c8 223 "Mailbox registers (OUT):\n");
1da177e4
LT		 224 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
225 if (IS_QLA2200(ha) && cnt == 8)
1c7c6357
AV		 226 optr =
227 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
0e31a2c8
JC		 228 if (mboxes & BIT_0) {
229 ql_dbg(ql_dbg_mbx, vha, 0x1112,
230 "mbox[%d]<-0x%04x\n", cnt, *iptr);
1da177e4 231 WRT_REG_WORD(optr, *iptr);
0e31a2c8 232 }
1da177e4
LT		 233
234 mboxes >>= 1;
235 optr++;
236 iptr++;
237 }
238
5e19ed90 239 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
7c3df132 240 "I/O Address = %p.\n", optr);
1da177e4
LT		 241
242 /* Issue set host interrupt command to send cmd out. */
243 ha->flags.mbox_int = 0;
244 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
245
246 /* Unlock mbx registers and wait for interrupt */
5e19ed90 247 ql_dbg(ql_dbg_mbx, vha, 0x100f,
7c3df132
SK		 248 "Going to unlock irq & waiting for interrupts. "
249 "jiffies=%lx.\n", jiffies);
1da177e4
LT		 250
251 /* Wait for mbx cmd completion until timeout */
b2000805 252 atomic_inc(&ha->num_pend_mbx_stage2);
124f85e6 253 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
1da177e4
LT		 254 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
255
7ec0effd 256 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 257 if (RD_REG_DWORD(&reg->isp82.hint) &
258 HINT_MBX_INT_PENDING) {
b6faaaf7 259 ha->flags.mbox_busy = 0;
a9083016
GM		 260 spin_unlock_irqrestore(&ha->hardware_lock,
261 flags);
b6faaaf7 262
b2000805 263 atomic_dec(&ha->num_pend_mbx_stage2);
5e19ed90 264 ql_dbg(ql_dbg_mbx, vha, 0x1010,
7c3df132 265 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 266 rval = QLA_FUNCTION_TIMEOUT;
267 goto premature_exit;
a9083016
GM		 268 }
269 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
270 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 271 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
272 else
273 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4
LT		 274 spin_unlock_irqrestore(&ha->hardware_lock, flags);
275
77ddb94a 276 wait_time = jiffies;
b2000805 277 atomic_inc(&ha->num_pend_mbx_stage3);
754d1243
GM		 278 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
279 mcp->tov * HZ)) {
b6faaaf7
QT		 280 if (chip_reset != ha->chip_reset) {
281 spin_lock_irqsave(&ha->hardware_lock, flags);
282 ha->flags.mbox_busy = 0;
283 spin_unlock_irqrestore(&ha->hardware_lock,
284 flags);
285 atomic_dec(&ha->num_pend_mbx_stage2);
286 atomic_dec(&ha->num_pend_mbx_stage3);
287 rval = QLA_ABORTED;
288 goto premature_exit;
289 }
754d1243
GM		 290 ql_dbg(ql_dbg_mbx, vha, 0x117a,
291 "cmd=%x Timeout.\n", command);
292 spin_lock_irqsave(&ha->hardware_lock, flags);
293 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
294 spin_unlock_irqrestore(&ha->hardware_lock, flags);
b2000805
QT		 295
296 } else if (ha->flags.purge_mbox ||
297 chip_reset != ha->chip_reset) {
b6faaaf7 298 spin_lock_irqsave(&ha->hardware_lock, flags);
b2000805 299 ha->flags.mbox_busy = 0;
b6faaaf7 300 spin_unlock_irqrestore(&ha->hardware_lock, flags);
b2000805
QT		 301 atomic_dec(&ha->num_pend_mbx_stage2);
302 atomic_dec(&ha->num_pend_mbx_stage3);
303 rval = QLA_ABORTED;
304 goto premature_exit;
754d1243 305 }
b2000805
QT		 306 atomic_dec(&ha->num_pend_mbx_stage3);
307
77ddb94a 308 if (time_after(jiffies, wait_time + 5 * HZ))
309 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
310 command, jiffies_to_msecs(jiffies - wait_time));
1da177e4 311 } else {
5e19ed90 312 ql_dbg(ql_dbg_mbx, vha, 0x1011,
7c3df132 313 "Cmd=%x Polling Mode.\n", command);
1da177e4 314
7ec0effd 315 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 316 if (RD_REG_DWORD(&reg->isp82.hint) &
317 HINT_MBX_INT_PENDING) {
b6faaaf7 318 ha->flags.mbox_busy = 0;
a9083016
GM		 319 spin_unlock_irqrestore(&ha->hardware_lock,
320 flags);
b2000805 321 atomic_dec(&ha->num_pend_mbx_stage2);
5e19ed90 322 ql_dbg(ql_dbg_mbx, vha, 0x1012,
7c3df132 323 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 324 rval = QLA_FUNCTION_TIMEOUT;
325 goto premature_exit;
a9083016
GM		 326 }
327 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
328 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 329 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
330 else
331 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4 332 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 333
334 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
335 while (!ha->flags.mbox_int) {
b2000805
QT		 336 if (ha->flags.purge_mbox ||
337 chip_reset != ha->chip_reset) {
b6faaaf7 338 spin_lock_irqsave(&ha->hardware_lock, flags);
b2000805 339 ha->flags.mbox_busy = 0;
b6faaaf7
QT		 340 spin_unlock_irqrestore(&ha->hardware_lock,
341 flags);
b2000805
QT		 342 atomic_dec(&ha->num_pend_mbx_stage2);
343 rval = QLA_ABORTED;
344 goto premature_exit;
345 }
346
1da177e4
LT		 347 if (time_after(jiffies, wait_time))
348 break;
349
3cb182b3
RG		 350 /*
351 * Check if it's UNLOADING, cause we cannot poll in
352 * this case, or else a NULL pointer dereference
353 * is triggered.
354 */
355 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)))
356 return QLA_FUNCTION_TIMEOUT;
357
1da177e4 358 /* Check for pending interrupts. */
73208dfd 359 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4 360
85880801
AV		 361 if (!ha->flags.mbox_int &&
362 !(IS_QLA2200(ha) &&
363 command == MBC_LOAD_RISC_RAM_EXTENDED))
59989831 364 msleep(10);
1da177e4 365 } /* while */
5e19ed90 366 ql_dbg(ql_dbg_mbx, vha, 0x1013,
7c3df132
SK		 367 "Waited %d sec.\n",
368 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
1da177e4 369 }
b2000805 370 atomic_dec(&ha->num_pend_mbx_stage2);
1da177e4 371
1da177e4
LT		 372 /* Check whether we timed out */
373 if (ha->flags.mbox_int) {
374 uint16_t *iptr2;
375
5e19ed90 376 ql_dbg(ql_dbg_mbx, vha, 0x1014,
7c3df132 377 "Cmd=%x completed.\n", command);
1da177e4
LT		 378
379 /* Got interrupt. Clear the flag. */
380 ha->flags.mbox_int = 0;
381 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
382
7ec0effd 383 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
b6faaaf7 384 spin_lock_irqsave(&ha->hardware_lock, flags);
cdbb0a4f 385 ha->flags.mbox_busy = 0;
b6faaaf7
QT		 386 spin_unlock_irqrestore(&ha->hardware_lock, flags);
387
cdbb0a4f
SV		 388 /* Setting Link-Down error */
389 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
390 ha->mcp = NULL;
391 rval = QLA_FUNCTION_FAILED;
83548fe2 392 ql_log(ql_log_warn, vha, 0xd048,
7c3df132 393 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
cdbb0a4f
SV		 394 goto premature_exit;
395 }
396
b3e9772d
BVA		 397 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) {
398 ql_dbg(ql_dbg_mbx, vha, 0x11ff,
399 "mb_out[0] = %#x <> %#x\n", ha->mailbox_out[0],
400 MBS_COMMAND_COMPLETE);
1da177e4 401 rval = QLA_FUNCTION_FAILED;
b3e9772d 402 }
1da177e4
LT		 403
404 /* Load return mailbox registers. */
405 iptr2 = mcp->mb;
406 iptr = (uint16_t *)&ha->mailbox_out[0];
407 mboxes = mcp->in_mb;
0e31a2c8
JC		 408
409 ql_dbg(ql_dbg_mbx, vha, 0x1113,
410 "Mailbox registers (IN):\n");
1da177e4 411 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
0e31a2c8 412 if (mboxes & BIT_0) {
1da177e4 413 *iptr2 = *iptr;
0e31a2c8
JC		 414 ql_dbg(ql_dbg_mbx, vha, 0x1114,
415 "mbox[%d]->0x%04x\n", cnt, *iptr2);
416 }
1da177e4
LT		 417
418 mboxes >>= 1;
419 iptr2++;
420 iptr++;
421 }
422 } else {
423
8d3c9c23
QT		 424 uint16_t mb[8];
425 uint32_t ictrl, host_status, hccr;
783e0dc4 426 uint16_t w;
1c7c6357 427
e428924c 428 if (IS_FWI2_CAPABLE(ha)) {
8d3c9c23
QT		 429 mb[0] = RD_REG_WORD(&reg->isp24.mailbox0);
430 mb[1] = RD_REG_WORD(&reg->isp24.mailbox1);
431 mb[2] = RD_REG_WORD(&reg->isp24.mailbox2);
432 mb[3] = RD_REG_WORD(&reg->isp24.mailbox3);
433 mb[7] = RD_REG_WORD(&reg->isp24.mailbox7);
1c7c6357 434 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
8d3c9c23
QT		 435 host_status = RD_REG_DWORD(&reg->isp24.host_status);
436 hccr = RD_REG_DWORD(&reg->isp24.hccr);
437
83548fe2 438 ql_log(ql_log_warn, vha, 0xd04c,
8d3c9c23
QT		 439 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
440 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n",
441 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3],
442 mb[7], host_status, hccr);
443
1c7c6357 444 } else {
8d3c9c23 445 mb[0] = RD_MAILBOX_REG(ha, &reg->isp, 0);
1c7c6357 446 ictrl = RD_REG_WORD(&reg->isp.ictrl);
8d3c9c23
QT		 447 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
448 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
449 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
1c7c6357 450 }
5e19ed90 451 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
1da177e4 452
783e0dc4
SC		 453 /* Capture FW dump only, if PCI device active */
454 if (!pci_channel_offline(vha->hw->pdev)) {
455 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
b2000805
QT		 456 if (w == 0xffff || ictrl == 0xffffffff ||
457 (chip_reset != ha->chip_reset)) {
783e0dc4
SC		 458 /* This is special case if there is unload
459 * of driver happening and if PCI device go
460 * into bad state due to PCI error condition
461 * then only PCI ERR flag would be set.
462 * we will do premature exit for above case.
463 */
b6faaaf7 464 spin_lock_irqsave(&ha->hardware_lock, flags);
783e0dc4 465 ha->flags.mbox_busy = 0;
b6faaaf7
QT		 466 spin_unlock_irqrestore(&ha->hardware_lock,
467 flags);
783e0dc4
SC		 468 rval = QLA_FUNCTION_TIMEOUT;
469 goto premature_exit;
470 }
f55bfc88 471
783e0dc4
SC		 472 /* Attempt to capture firmware dump for further
473 * anallysis of the current formware state. we do not
474 * need to do this if we are intentionally generating
475 * a dump
476 */
477 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
478 ha->isp_ops->fw_dump(vha, 0);
479 rval = QLA_FUNCTION_TIMEOUT;
480 }
1da177e4 481 }
b6faaaf7 482 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 483 ha->flags.mbox_busy = 0;
b6faaaf7 484 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 485
486 /* Clean up */
487 ha->mcp = NULL;
488
124f85e6 489 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
5e19ed90 490 ql_dbg(ql_dbg_mbx, vha, 0x101a,
7c3df132 491 "Checking for additional resp interrupt.\n");
1da177e4
LT		 492
493 /* polling mode for non isp_abort commands. */
73208dfd 494 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4
LT		 495 }
496
1c7c6357
AV		 497 if (rval == QLA_FUNCTION_TIMEOUT &&
498 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
85880801
AV		 499 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
500 ha->flags.eeh_busy) {
1da177e4 501 /* not in dpc. schedule it for dpc to take over. */
5e19ed90 502 ql_dbg(ql_dbg_mbx, vha, 0x101b,
7c3df132 503 "Timeout, schedule isp_abort_needed.\n");
cdbb0a4f
SV		 504
505 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
506 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
507 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 508 if (IS_QLA82XX(ha)) {
509 ql_dbg(ql_dbg_mbx, vha, 0x112a,
510 "disabling pause transmit on port "
511 "0 & 1.\n");
512 qla82xx_wr_32(ha,
513 QLA82XX_CRB_NIU + 0x98,
514 CRB_NIU_XG_PAUSE_CTL_P0|
515 CRB_NIU_XG_PAUSE_CTL_P1);
516 }
7c3df132 517 ql_log(ql_log_info, base_vha, 0x101c,
24d9ee85 518 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 519 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
520 "abort.\n", command, mcp->mb[0],
521 ha->flags.eeh_busy);
cdbb0a4f
SV		 522 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
523 qla2xxx_wake_dpc(vha);
524 }
710bc78f 525 } else if (current == ha->dpc_thread) {
1da177e4 526 /* call abort directly since we are in the DPC thread */
5e19ed90 527 ql_dbg(ql_dbg_mbx, vha, 0x101d,
7c3df132 528 "Timeout, calling abort_isp.\n");
cdbb0a4f
SV		 529
530 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
531 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
532 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 533 if (IS_QLA82XX(ha)) {
534 ql_dbg(ql_dbg_mbx, vha, 0x112b,
535 "disabling pause transmit on port "
536 "0 & 1.\n");
537 qla82xx_wr_32(ha,
538 QLA82XX_CRB_NIU + 0x98,
539 CRB_NIU_XG_PAUSE_CTL_P0|
540 CRB_NIU_XG_PAUSE_CTL_P1);
541 }
7c3df132 542 ql_log(ql_log_info, base_vha, 0x101e,
24d9ee85 543 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 544 "mb[0]=0x%x. Scheduling ISP abort ",
545 command, mcp->mb[0]);
cdbb0a4f
SV		 546 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
547 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
d3360960
GM		 548 /* Allow next mbx cmd to come in. */
549 complete(&ha->mbx_cmd_comp);
cdbb0a4f
SV		 550 if (ha->isp_ops->abort_isp(vha)) {
551 /* Failed. retry later. */
552 set_bit(ISP_ABORT_NEEDED,
553 &vha->dpc_flags);
554 }
555 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
5e19ed90 556 ql_dbg(ql_dbg_mbx, vha, 0x101f,
7c3df132 557 "Finished abort_isp.\n");
d3360960 558 goto mbx_done;
1da177e4 559 }
1da177e4
LT		 560 }
561 }
562
cdbb0a4f 563premature_exit:
1da177e4 564 /* Allow next mbx cmd to come in. */
8eca3f39 565 complete(&ha->mbx_cmd_comp);
1da177e4 566
d3360960 567mbx_done:
b2000805
QT		 568 if (rval == QLA_ABORTED) {
569 ql_log(ql_log_info, vha, 0xd035,
570 "Chip Reset in progress. Purging Mbox cmd=0x%x.\n",
571 mcp->mb[0]);
572 } else if (rval) {
050dc76a 573 if (ql2xextended_error_logging & (ql_dbg_disc|ql_dbg_mbx)) {
3f918ffa 574 pr_warn("%s [%s]-%04x:%ld: **** Failed=%x", QL_MSGHDR,
050dc76a 575 dev_name(&ha->pdev->dev), 0x1020+0x800,
3f918ffa 576 vha->host_no, rval);
050dc76a
JC		 577 mboxes = mcp->in_mb;
578 cnt = 4;
579 for (i = 0; i < ha->mbx_count && cnt; i++, mboxes >>= 1)
580 if (mboxes & BIT_0) {
581 printk(" mb[%u]=%x", i, mcp->mb[i]);
582 cnt--;
583 }
584 pr_warn(" cmd=%x ****\n", command);
585 }
f7e59e99
MR		 586 if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) {
587 ql_dbg(ql_dbg_mbx, vha, 0x1198,
588 "host_status=%#x intr_ctrl=%#x intr_status=%#x\n",
589 RD_REG_DWORD(&reg->isp24.host_status),
590 RD_REG_DWORD(&reg->isp24.ictrl),
591 RD_REG_DWORD(&reg->isp24.istatus));
592 } else {
593 ql_dbg(ql_dbg_mbx, vha, 0x1206,
594 "ctrl_status=%#x ictrl=%#x istatus=%#x\n",
595 RD_REG_WORD(&reg->isp.ctrl_status),
596 RD_REG_WORD(&reg->isp.ictrl),
597 RD_REG_WORD(&reg->isp.istatus));
598 }
1da177e4 599 } else {
7c3df132 600 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
1da177e4
LT		 601 }
602
1da177e4
LT		 603 return rval;
604}
605
1da177e4 606int
7b867cf7 607qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
590f98e5 608 uint32_t risc_code_size)
1da177e4
LT		 609{
610 int rval;
7b867cf7 611 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 612 mbx_cmd_t mc;
613 mbx_cmd_t *mcp = &mc;
1da177e4 614
5f28d2d7
SK		 615 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
616 "Entered %s.\n", __func__);
1da177e4 617
e428924c 618 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
590f98e5 619 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
620 mcp->mb[8] = MSW(risc_addr);
621 mcp->out_mb = MBX_8|MBX_0;
1da177e4 622 } else {
590f98e5 623 mcp->mb[0] = MBC_LOAD_RISC_RAM;
624 mcp->out_mb = MBX_0;
1da177e4 625 }
1da177e4
LT		 626 mcp->mb[1] = LSW(risc_addr);
627 mcp->mb[2] = MSW(req_dma);
628 mcp->mb[3] = LSW(req_dma);
1da177e4
LT		 629 mcp->mb[6] = MSW(MSD(req_dma));
630 mcp->mb[7] = LSW(MSD(req_dma));
590f98e5 631 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
e428924c 632 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 633 mcp->mb[4] = MSW(risc_code_size);
634 mcp->mb[5] = LSW(risc_code_size);
635 mcp->out_mb |= MBX_5|MBX_4;
636 } else {
637 mcp->mb[4] = LSW(risc_code_size);
638 mcp->out_mb |= MBX_4;
639 }
640
2a3192a3 641 mcp->in_mb = MBX_1|MBX_0;
b93480e3 642 mcp->tov = MBX_TOV_SECONDS;
1da177e4 643 mcp->flags = 0;
7b867cf7 644 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 645
1da177e4 646 if (rval != QLA_SUCCESS) {
7c3df132 647 ql_dbg(ql_dbg_mbx, vha, 0x1023,
2a3192a3
JC		 648 "Failed=%x mb[0]=%x mb[1]=%x.\n",
649 rval, mcp->mb[0], mcp->mb[1]);
1da177e4 650 } else {
5f28d2d7
SK		 651 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
652 "Done %s.\n", __func__);
1da177e4
LT		 653 }
654
655 return rval;
656}
657
cad454b1 658#define EXTENDED_BB_CREDITS BIT_0
e84067d7 659#define NVME_ENABLE_FLAG BIT_3
1f4c7c38
JC		 660static inline uint16_t qla25xx_set_sfp_lr_dist(struct qla_hw_data *ha)
661{
662 uint16_t mb4 = BIT_0;
663
ecc89f25 664 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
1f4c7c38
JC		 665 mb4 |= ha->long_range_distance << LR_DIST_FW_POS;
666
667 return mb4;
668}
669
670static inline uint16_t qla25xx_set_nvr_lr_dist(struct qla_hw_data *ha)
671{
672 uint16_t mb4 = BIT_0;
673
ecc89f25 674 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
1f4c7c38
JC		 675 struct nvram_81xx *nv = ha->nvram;
676
677 mb4 |= LR_DIST_FW_FIELD(nv->enhanced_features);
678 }
679
680 return mb4;
681}
e84067d7 682
1da177e4
LT		 683/*
684 * qla2x00_execute_fw
1c7c6357 685 * Start adapter firmware.
1da177e4
LT		 686 *
687 * Input:
1c7c6357
AV		 688 * ha = adapter block pointer.
689 * TARGET_QUEUE_LOCK must be released.
690 * ADAPTER_STATE_LOCK must be released.
1da177e4
LT		 691 *
692 * Returns:
1c7c6357 693 * qla2x00 local function return status code.
1da177e4
LT		 694 *
695 * Context:
1c7c6357 696 * Kernel context.
1da177e4
LT		 697 */
698int
7b867cf7 699qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 700{
701 int rval;
7b867cf7 702 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 703 mbx_cmd_t mc;
704 mbx_cmd_t *mcp = &mc;
705
5f28d2d7
SK		 706 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
707 "Entered %s.\n", __func__);
1da177e4
LT		 708
709 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
1c7c6357
AV		 710 mcp->out_mb = MBX_0;
711 mcp->in_mb = MBX_0;
e428924c 712 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 713 mcp->mb[1] = MSW(risc_addr);
714 mcp->mb[2] = LSW(risc_addr);
715 mcp->mb[3] = 0;
e4e3a2ce 716 mcp->mb[4] = 0;
1f4c7c38 717 ha->flags.using_lr_setting = 0;
f73cb695 718 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
ecc89f25 719 IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
e4e3a2ce
QT		 720 if (ql2xautodetectsfp) {
721 if (ha->flags.detected_lr_sfp) {
1f4c7c38
JC		 722 mcp->mb[4] |=
723 qla25xx_set_sfp_lr_dist(ha);
e4e3a2ce
QT		 724 ha->flags.using_lr_setting = 1;
725 }
726 } else {
727 struct nvram_81xx *nv = ha->nvram;
1f4c7c38 728 /* set LR distance if specified in nvram */
e4e3a2ce 729 if (nv->enhanced_features &
1f4c7c38
JC		 730 NEF_LR_DIST_ENABLE) {
731 mcp->mb[4] |=
732 qla25xx_set_nvr_lr_dist(ha);
e4e3a2ce
QT		 733 ha->flags.using_lr_setting = 1;
734 }
735 }
e4e3a2ce 736 }
b0d6cabd 737
ecc89f25 738 if (ql2xnvmeenable && (IS_QLA27XX(ha) || IS_QLA28XX(ha)))
e84067d7
DG		 739 mcp->mb[4] |= NVME_ENABLE_FLAG;
740
ecc89f25 741 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
92d4408e
SC		 742 struct nvram_81xx *nv = ha->nvram;
743 /* set minimum speed if specified in nvram */
72a92df2
JC		 744 if (nv->min_supported_speed >= 2 &&
745 nv->min_supported_speed <= 5) {
92d4408e 746 mcp->mb[4] |= BIT_4;
72a92df2 747 mcp->mb[11] |= nv->min_supported_speed & 0xF;
92d4408e
SC		 748 mcp->out_mb |= MBX_11;
749 mcp->in_mb |= BIT_5;
72a92df2
JC		 750 vha->min_supported_speed =
751 nv->min_supported_speed;
92d4408e
SC		 752 }
753 }
754
b0d6cabd
HM		 755 if (ha->flags.exlogins_enabled)
756 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN;
757
2f56a7f1
HM		 758 if (ha->flags.exchoffld_enabled)
759 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD;
760
8b3253d1 761 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
1f4c7c38 762 mcp->in_mb |= MBX_3 | MBX_2 | MBX_1;
1c7c6357
AV		 763 } else {
764 mcp->mb[1] = LSW(risc_addr);
765 mcp->out_mb |= MBX_1;
766 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
767 mcp->mb[2] = 0;
768 mcp->out_mb |= MBX_2;
769 }
1da177e4
LT		 770 }
771
b93480e3 772 mcp->tov = MBX_TOV_SECONDS;
1da177e4 773 mcp->flags = 0;
7b867cf7 774 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 775
1c7c6357 776 if (rval != QLA_SUCCESS) {
7c3df132
SK		 777 ql_dbg(ql_dbg_mbx, vha, 0x1026,
778 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
72a92df2
JC		 779 return rval;
780 }
781
782 if (!IS_FWI2_CAPABLE(ha))
783 goto done;
784
785 ha->fw_ability_mask = mcp->mb[3] << 16 | mcp->mb[2];
786 ql_dbg(ql_dbg_mbx, vha, 0x119a,
787 "fw_ability_mask=%x.\n", ha->fw_ability_mask);
788 ql_dbg(ql_dbg_mbx, vha, 0x1027, "exchanges=%x.\n", mcp->mb[1]);
789 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
790 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1);
791 ql_dbg(ql_dbg_mbx, vha, 0x119b, "max_supported_speed=%s.\n",
792 ha->max_supported_speed == 0 ? "16Gps" :
793 ha->max_supported_speed == 1 ? "32Gps" :
794 ha->max_supported_speed == 2 ? "64Gps" : "unknown");
795 if (vha->min_supported_speed) {
796 ha->min_supported_speed = mcp->mb[5] &
797 (BIT_0 | BIT_1 | BIT_2);
798 ql_dbg(ql_dbg_mbx, vha, 0x119c,
799 "min_supported_speed=%s.\n",
800 ha->min_supported_speed == 6 ? "64Gps" :
801 ha->min_supported_speed == 5 ? "32Gps" :
802 ha->min_supported_speed == 4 ? "16Gps" :
803 ha->min_supported_speed == 3 ? "8Gps" :
804 ha->min_supported_speed == 2 ? "4Gps" : "unknown");
1c7c6357
AV		 805 }
806 }
1da177e4 807
72a92df2
JC		 808done:
809 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
810 "Done %s.\n", __func__);
811
1da177e4
LT		 812 return rval;
813}
814
b0d6cabd
HM		 815/*
816 * qla_get_exlogin_status
817 * Get extended login status
818 * uses the memory offload control/status Mailbox
819 *
820 * Input:
821 * ha: adapter state pointer.
822 * fwopt: firmware options
823 *
824 * Returns:
825 * qla2x00 local function status
826 *
827 * Context:
828 * Kernel context.
829 */
830#define FETCH_XLOGINS_STAT 0x8
831int
832qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
833 uint16_t *ex_logins_cnt)
834{
835 int rval;
836 mbx_cmd_t mc;
837 mbx_cmd_t *mcp = &mc;
838
839 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f,
840 "Entered %s\n", __func__);
841
842 memset(mcp->mb, 0 , sizeof(mcp->mb));
843 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
844 mcp->mb[1] = FETCH_XLOGINS_STAT;
845 mcp->out_mb = MBX_1|MBX_0;
846 mcp->in_mb = MBX_10|MBX_4|MBX_0;
847 mcp->tov = MBX_TOV_SECONDS;
848 mcp->flags = 0;
849
850 rval = qla2x00_mailbox_command(vha, mcp);
851 if (rval != QLA_SUCCESS) {
852 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval);
853 } else {
854 *buf_sz = mcp->mb[4];
855 *ex_logins_cnt = mcp->mb[10];
856
857 ql_log(ql_log_info, vha, 0x1190,
858 "buffer size 0x%x, exchange login count=%d\n",
859 mcp->mb[4], mcp->mb[10]);
860
861 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116,
862 "Done %s.\n", __func__);
863 }
864
865 return rval;
866}
867
868/*
869 * qla_set_exlogin_mem_cfg
870 * set extended login memory configuration
871 * Mbx needs to be issues before init_cb is set
872 *
873 * Input:
874 * ha: adapter state pointer.
875 * buffer: buffer pointer
876 * phys_addr: physical address of buffer
877 * size: size of buffer
878 * TARGET_QUEUE_LOCK must be released
879 * ADAPTER_STATE_LOCK must be release
880 *
881 * Returns:
882 * qla2x00 local funxtion status code.
883 *
884 * Context:
885 * Kernel context.
886 */
887#define CONFIG_XLOGINS_MEM 0x3
888int
889qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
890{
891 int rval;
892 mbx_cmd_t mc;
893 mbx_cmd_t *mcp = &mc;
894 struct qla_hw_data *ha = vha->hw;
b0d6cabd
HM		 895
896 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a,
897 "Entered %s.\n", __func__);
898
899 memset(mcp->mb, 0 , sizeof(mcp->mb));
900 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
901 mcp->mb[1] = CONFIG_XLOGINS_MEM;
902 mcp->mb[2] = MSW(phys_addr);
903 mcp->mb[3] = LSW(phys_addr);
904 mcp->mb[6] = MSW(MSD(phys_addr));
905 mcp->mb[7] = LSW(MSD(phys_addr));
906 mcp->mb[8] = MSW(ha->exlogin_size);
907 mcp->mb[9] = LSW(ha->exlogin_size);
908 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
909 mcp->in_mb = MBX_11|MBX_0;
910 mcp->tov = MBX_TOV_SECONDS;
911 mcp->flags = 0;
912 rval = qla2x00_mailbox_command(vha, mcp);
913 if (rval != QLA_SUCCESS) {
914 /*EMPTY*/
915 ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval);
916 } else {
b0d6cabd
HM		 917 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
918 "Done %s.\n", __func__);
919 }
920
921 return rval;
922}
923
2f56a7f1
HM		 924/*
925 * qla_get_exchoffld_status
926 * Get exchange offload status
927 * uses the memory offload control/status Mailbox
928 *
929 * Input:
930 * ha: adapter state pointer.
931 * fwopt: firmware options
932 *
933 * Returns:
934 * qla2x00 local function status
935 *
936 * Context:
937 * Kernel context.
938 */
939#define FETCH_XCHOFFLD_STAT 0x2
940int
941qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
942 uint16_t *ex_logins_cnt)
943{
944 int rval;
945 mbx_cmd_t mc;
946 mbx_cmd_t *mcp = &mc;
947
948 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019,
949 "Entered %s\n", __func__);
950
951 memset(mcp->mb, 0 , sizeof(mcp->mb));
952 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
953 mcp->mb[1] = FETCH_XCHOFFLD_STAT;
954 mcp->out_mb = MBX_1|MBX_0;
955 mcp->in_mb = MBX_10|MBX_4|MBX_0;
956 mcp->tov = MBX_TOV_SECONDS;
957 mcp->flags = 0;
958
959 rval = qla2x00_mailbox_command(vha, mcp);
960 if (rval != QLA_SUCCESS) {
961 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval);
962 } else {
963 *buf_sz = mcp->mb[4];
964 *ex_logins_cnt = mcp->mb[10];
965
966 ql_log(ql_log_info, vha, 0x118e,
967 "buffer size 0x%x, exchange offload count=%d\n",
968 mcp->mb[4], mcp->mb[10]);
969
970 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156,
971 "Done %s.\n", __func__);
972 }
973
974 return rval;
975}
976
977/*
978 * qla_set_exchoffld_mem_cfg
979 * Set exchange offload memory configuration
980 * Mbx needs to be issues before init_cb is set
981 *
982 * Input:
983 * ha: adapter state pointer.
984 * buffer: buffer pointer
985 * phys_addr: physical address of buffer
986 * size: size of buffer
987 * TARGET_QUEUE_LOCK must be released
988 * ADAPTER_STATE_LOCK must be release
989 *
990 * Returns:
991 * qla2x00 local funxtion status code.
992 *
993 * Context:
994 * Kernel context.
995 */
996#define CONFIG_XCHOFFLD_MEM 0x3
997int
99e1b683 998qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha)
2f56a7f1
HM		 999{
1000 int rval;
1001 mbx_cmd_t mc;
1002 mbx_cmd_t *mcp = &mc;
1003 struct qla_hw_data *ha = vha->hw;
1004
1005 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157,
1006 "Entered %s.\n", __func__);
1007
1008 memset(mcp->mb, 0 , sizeof(mcp->mb));
1009 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
1010 mcp->mb[1] = CONFIG_XCHOFFLD_MEM;
99e1b683
QT		 1011 mcp->mb[2] = MSW(ha->exchoffld_buf_dma);
1012 mcp->mb[3] = LSW(ha->exchoffld_buf_dma);
1013 mcp->mb[6] = MSW(MSD(ha->exchoffld_buf_dma));
1014 mcp->mb[7] = LSW(MSD(ha->exchoffld_buf_dma));
1015 mcp->mb[8] = MSW(ha->exchoffld_size);
1016 mcp->mb[9] = LSW(ha->exchoffld_size);
2f56a7f1
HM		 1017 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1018 mcp->in_mb = MBX_11|MBX_0;
1019 mcp->tov = MBX_TOV_SECONDS;
1020 mcp->flags = 0;
1021 rval = qla2x00_mailbox_command(vha, mcp);
1022 if (rval != QLA_SUCCESS) {
1023 /*EMPTY*/
1024 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval);
1025 } else {
1026 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
1027 "Done %s.\n", __func__);
1028 }
1029
1030 return rval;
1031}
1032
1da177e4
LT		 1033/*
1034 * qla2x00_get_fw_version
1035 * Get firmware version.
1036 *
1037 * Input:
1038 * ha: adapter state pointer.
1039 * major: pointer for major number.
1040 * minor: pointer for minor number.
1041 * subminor: pointer for subminor number.
1042 *
1043 * Returns:
1044 * qla2x00 local function return status code.
1045 *
1046 * Context:
1047 * Kernel context.
1048 */
ca9e9c3e 1049int
6246b8a1 1050qla2x00_get_fw_version(scsi_qla_host_t *vha)
1da177e4
LT		 1051{
1052 int rval;
1053 mbx_cmd_t mc;
1054 mbx_cmd_t *mcp = &mc;
6246b8a1 1055 struct qla_hw_data *ha = vha->hw;
1da177e4 1056
5f28d2d7
SK		 1057 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
1058 "Entered %s.\n", __func__);
1da177e4
LT		 1059
1060 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
1061 mcp->out_mb = MBX_0;
1062 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
7ec0effd 1063 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
55a96158 1064 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
fb0effee 1065 if (IS_FWI2_CAPABLE(ha))
6246b8a1 1066 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
ecc89f25 1067 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
ad1ef177
JC		 1068 mcp->in_mb |=
1069 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18|
2a3192a3 1070 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7;
03aa868c 1071
1da177e4 1072 mcp->flags = 0;
b93480e3 1073 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1074 rval = qla2x00_mailbox_command(vha, mcp);
ca9e9c3e
AV		 1075 if (rval != QLA_SUCCESS)
1076 goto failed;
1da177e4
LT		 1077
1078 /* Return mailbox data. */
6246b8a1
GM		 1079 ha->fw_major_version = mcp->mb[1];
1080 ha->fw_minor_version = mcp->mb[2];
1081 ha->fw_subminor_version = mcp->mb[3];
1082 ha->fw_attributes = mcp->mb[6];
7b867cf7 1083 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
6246b8a1 1084 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
1da177e4 1085 else
6246b8a1 1086 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
03aa868c 1087
7ec0effd 1088 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
6246b8a1
GM		 1089 ha->mpi_version[0] = mcp->mb[10] & 0xff;
1090 ha->mpi_version[1] = mcp->mb[11] >> 8;
1091 ha->mpi_version[2] = mcp->mb[11] & 0xff;
1092 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
1093 ha->phy_version[0] = mcp->mb[8] & 0xff;
1094 ha->phy_version[1] = mcp->mb[9] >> 8;
1095 ha->phy_version[2] = mcp->mb[9] & 0xff;
1096 }
03aa868c 1097
81178772
SK		 1098 if (IS_FWI2_CAPABLE(ha)) {
1099 ha->fw_attributes_h = mcp->mb[15];
1100 ha->fw_attributes_ext[0] = mcp->mb[16];
1101 ha->fw_attributes_ext[1] = mcp->mb[17];
1102 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
1103 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
1104 __func__, mcp->mb[15], mcp->mb[6]);
1105 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
1106 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
1107 __func__, mcp->mb[17], mcp->mb[16]);
2f56a7f1 1108
b0d6cabd
HM		 1109 if (ha->fw_attributes_h & 0x4)
1110 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d,
1111 "%s: Firmware supports Extended Login 0x%x\n",
1112 __func__, ha->fw_attributes_h);
2f56a7f1
HM		 1113
1114 if (ha->fw_attributes_h & 0x8)
1115 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191,
1116 "%s: Firmware supports Exchange Offload 0x%x\n",
1117 __func__, ha->fw_attributes_h);
e84067d7 1118
deeae7a6
DG		 1119 /*
1120 * FW supports nvme and driver load parameter requested nvme.
1121 * BIT 26 of fw_attributes indicates NVMe support.
1122 */
171e4909
GM		 1123 if ((ha->fw_attributes_h &
1124 (FW_ATTR_H_NVME | FW_ATTR_H_NVME_UPDATED)) &&
1125 ql2xnvmeenable) {
03aaa89f
DT		 1126 if (ha->fw_attributes_h & FW_ATTR_H_NVME_FBURST)
1127 vha->flags.nvme_first_burst = 1;
1128
e84067d7 1129 vha->flags.nvme_enabled = 1;
1cbc0efc
DT		 1130 ql_log(ql_log_info, vha, 0xd302,
1131 "%s: FC-NVMe is Enabled (0x%x)\n",
1132 __func__, ha->fw_attributes_h);
1133 }
3a03eb79 1134 }
03aa868c 1135
ecc89f25 1136 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
2a3192a3
JC		 1137 ha->serdes_version[0] = mcp->mb[7] & 0xff;
1138 ha->serdes_version[1] = mcp->mb[8] >> 8;
1139 ha->serdes_version[2] = mcp->mb[8] & 0xff;
03aa868c
SC		 1140 ha->mpi_version[0] = mcp->mb[10] & 0xff;
1141 ha->mpi_version[1] = mcp->mb[11] >> 8;
1142 ha->mpi_version[2] = mcp->mb[11] & 0xff;
1143 ha->pep_version[0] = mcp->mb[13] & 0xff;
1144 ha->pep_version[1] = mcp->mb[14] >> 8;
1145 ha->pep_version[2] = mcp->mb[14] & 0xff;
f73cb695
CD		 1146 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
1147 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
ad1ef177
JC		 1148 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22];
1149 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24];
3f006ac3
MH		 1150 if (IS_QLA28XX(ha)) {
1151 if (mcp->mb[16] & BIT_10) {
1152 ql_log(ql_log_info, vha, 0xffff,
1153 "FW support secure flash updates\n");
1154 ha->flags.secure_fw = 1;
1155 }
1156 }
f73cb695 1157 }
6246b8a1 1158
ca9e9c3e 1159failed:
1da177e4
LT		 1160 if (rval != QLA_SUCCESS) {
1161 /*EMPTY*/
7c3df132 1162 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
1da177e4
LT		 1163 } else {
1164 /*EMPTY*/
5f28d2d7
SK		 1165 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
1166 "Done %s.\n", __func__);
1da177e4 1167 }
ca9e9c3e 1168 return rval;
1da177e4
LT		 1169}
1170
1171/*
1172 * qla2x00_get_fw_options
1173 * Set firmware options.
1174 *
1175 * Input:
1176 * ha = adapter block pointer.
1177 * fwopt = pointer for firmware options.
1178 *
1179 * Returns:
1180 * qla2x00 local function return status code.
1181 *
1182 * Context:
1183 * Kernel context.
1184 */
1185int
7b867cf7 1186qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 1187{
1188 int rval;
1189 mbx_cmd_t mc;
1190 mbx_cmd_t *mcp = &mc;
1191
5f28d2d7
SK		 1192 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
1193 "Entered %s.\n", __func__);
1da177e4
LT		 1194
1195 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
1196 mcp->out_mb = MBX_0;
1197 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1198 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1199 mcp->flags = 0;
7b867cf7 1200 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1201
1202 if (rval != QLA_SUCCESS) {
1203 /*EMPTY*/
7c3df132 1204 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
1da177e4 1205 } else {
1c7c6357 1206 fwopts[0] = mcp->mb[0];
1da177e4
LT		 1207 fwopts[1] = mcp->mb[1];
1208 fwopts[2] = mcp->mb[2];
1209 fwopts[3] = mcp->mb[3];
1210
5f28d2d7
SK		 1211 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
1212 "Done %s.\n", __func__);
1da177e4
LT		 1213 }
1214
1215 return rval;
1216}
1217
1218
1219/*
1220 * qla2x00_set_fw_options
1221 * Set firmware options.
1222 *
1223 * Input:
1224 * ha = adapter block pointer.
1225 * fwopt = pointer for firmware options.
1226 *
1227 * Returns:
1228 * qla2x00 local function return status code.
1229 *
1230 * Context:
1231 * Kernel context.
1232 */
1233int
7b867cf7 1234qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 1235{
1236 int rval;
1237 mbx_cmd_t mc;
1238 mbx_cmd_t *mcp = &mc;
1239
5f28d2d7
SK		 1240 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
1241 "Entered %s.\n", __func__);
1da177e4
LT		 1242
1243 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
1244 mcp->mb[1] = fwopts[1];
1245 mcp->mb[2] = fwopts[2];
1246 mcp->mb[3] = fwopts[3];
1c7c6357 1247 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 1248 mcp->in_mb = MBX_0;
7b867cf7 1249 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 1250 mcp->in_mb |= MBX_1;
2da52737
QT		 1251 mcp->mb[10] = fwopts[10];
1252 mcp->out_mb |= MBX_10;
1c7c6357
AV		 1253 } else {
1254 mcp->mb[10] = fwopts[10];
1255 mcp->mb[11] = fwopts[11];
1256 mcp->mb[12] = 0; /* Undocumented, but used */
1257 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
1258 }
b93480e3 1259 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1260 mcp->flags = 0;
7b867cf7 1261 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1262
1c7c6357
AV		 1263 fwopts[0] = mcp->mb[0];
1264
1da177e4
LT		 1265 if (rval != QLA_SUCCESS) {
1266 /*EMPTY*/
7c3df132
SK		 1267 ql_dbg(ql_dbg_mbx, vha, 0x1030,
1268 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 1269 } else {
1270 /*EMPTY*/
5f28d2d7
SK		 1271 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
1272 "Done %s.\n", __func__);
1da177e4
LT		 1273 }
1274
1275 return rval;
1276}
1277
1278/*
1279 * qla2x00_mbx_reg_test
1280 * Mailbox register wrap test.
1281 *
1282 * Input:
1283 * ha = adapter block pointer.
1284 * TARGET_QUEUE_LOCK must be released.
1285 * ADAPTER_STATE_LOCK must be released.
1286 *
1287 * Returns:
1288 * qla2x00 local function return status code.
1289 *
1290 * Context:
1291 * Kernel context.
1292 */
1293int
7b867cf7 1294qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1da177e4
LT		 1295{
1296 int rval;
1297 mbx_cmd_t mc;
1298 mbx_cmd_t *mcp = &mc;
1299
5f28d2d7
SK		 1300 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
1301 "Entered %s.\n", __func__);
1da177e4
LT		 1302
1303 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
1304 mcp->mb[1] = 0xAAAA;
1305 mcp->mb[2] = 0x5555;
1306 mcp->mb[3] = 0xAA55;
1307 mcp->mb[4] = 0x55AA;
1308 mcp->mb[5] = 0xA5A5;
1309 mcp->mb[6] = 0x5A5A;
1310 mcp->mb[7] = 0x2525;
1311 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1312 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1313 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1314 mcp->flags = 0;
7b867cf7 1315 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1316
1317 if (rval == QLA_SUCCESS) {
1318 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
1319 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
1320 rval = QLA_FUNCTION_FAILED;
1321 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
1322 mcp->mb[7] != 0x2525)
1323 rval = QLA_FUNCTION_FAILED;
1324 }
1325
1326 if (rval != QLA_SUCCESS) {
1327 /*EMPTY*/
7c3df132 1328 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1da177e4
LT		 1329 } else {
1330 /*EMPTY*/
5f28d2d7
SK		 1331 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
1332 "Done %s.\n", __func__);
1da177e4
LT		 1333 }
1334
1335 return rval;
1336}
1337
1338/*
1339 * qla2x00_verify_checksum
1340 * Verify firmware checksum.
1341 *
1342 * Input:
1343 * ha = adapter block pointer.
1344 * TARGET_QUEUE_LOCK must be released.
1345 * ADAPTER_STATE_LOCK must be released.
1346 *
1347 * Returns:
1348 * qla2x00 local function return status code.
1349 *
1350 * Context:
1351 * Kernel context.
1352 */
1353int
7b867cf7 1354qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 1355{
1356 int rval;
1357 mbx_cmd_t mc;
1358 mbx_cmd_t *mcp = &mc;
1359
5f28d2d7
SK		 1360 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
1361 "Entered %s.\n", __func__);
1da177e4
LT		 1362
1363 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1c7c6357
AV		 1364 mcp->out_mb = MBX_0;
1365 mcp->in_mb = MBX_0;
7b867cf7 1366 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 1367 mcp->mb[1] = MSW(risc_addr);
1368 mcp->mb[2] = LSW(risc_addr);
1369 mcp->out_mb |= MBX_2|MBX_1;
1370 mcp->in_mb |= MBX_2|MBX_1;
1371 } else {
1372 mcp->mb[1] = LSW(risc_addr);
1373 mcp->out_mb |= MBX_1;
1374 mcp->in_mb |= MBX_1;
1375 }
1376
b93480e3 1377 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1378 mcp->flags = 0;
7b867cf7 1379 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1380
1381 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1382 ql_dbg(ql_dbg_mbx, vha, 0x1036,
1383 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
1384 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1da177e4 1385 } else {
5f28d2d7
SK		 1386 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
1387 "Done %s.\n", __func__);
1da177e4
LT		 1388 }
1389
1390 return rval;
1391}
1392
1393/*
1394 * qla2x00_issue_iocb
1395 * Issue IOCB using mailbox command
1396 *
1397 * Input:
1398 * ha = adapter state pointer.
1399 * buffer = buffer pointer.
1400 * phys_addr = physical address of buffer.
1401 * size = size of buffer.
1402 * TARGET_QUEUE_LOCK must be released.
1403 * ADAPTER_STATE_LOCK must be released.
1404 *
1405 * Returns:
1406 * qla2x00 local function return status code.
1407 *
1408 * Context:
1409 * Kernel context.
1410 */
6e98016c 1411int
7b867cf7 1412qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
4d4df193 1413 dma_addr_t phys_addr, size_t size, uint32_t tov)
1da177e4
LT		 1414{
1415 int rval;
1416 mbx_cmd_t mc;
1417 mbx_cmd_t *mcp = &mc;
1418
5f28d2d7
SK		 1419 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
1420 "Entered %s.\n", __func__);
7c3df132 1421
1da177e4
LT		 1422 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
1423 mcp->mb[1] = 0;
1424 mcp->mb[2] = MSW(phys_addr);
1425 mcp->mb[3] = LSW(phys_addr);
1426 mcp->mb[6] = MSW(MSD(phys_addr));
1427 mcp->mb[7] = LSW(MSD(phys_addr));
1428 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1429 mcp->in_mb = MBX_2|MBX_0;
4d4df193 1430 mcp->tov = tov;
1da177e4 1431 mcp->flags = 0;
7b867cf7 1432 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1433
1434 if (rval != QLA_SUCCESS) {
1435 /*EMPTY*/
7c3df132 1436 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1da177e4 1437 } else {
8c958a99
AV		 1438 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
1439
1440 /* Mask reserved bits. */
1441 sts_entry->entry_status &=
7b867cf7 1442 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
5f28d2d7
SK		 1443 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
1444 "Done %s.\n", __func__);
1da177e4
LT		 1445 }
1446
1447 return rval;
1448}
1449
4d4df193 1450int
7b867cf7 1451qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
4d4df193
HK		 1452 size_t size)
1453{
7b867cf7 1454 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
4d4df193
HK		 1455 MBX_TOV_SECONDS);
1456}
1457
1da177e4
LT		 1458/*
1459 * qla2x00_abort_command
1460 * Abort command aborts a specified IOCB.
1461 *
1462 * Input:
1463 * ha = adapter block pointer.
1464 * sp = SB structure pointer.
1465 *
1466 * Returns:
1467 * qla2x00 local function return status code.
1468 *
1469 * Context:
1470 * Kernel context.
1471 */
1472int
2afa19a9 1473qla2x00_abort_command(srb_t *sp)
1da177e4
LT		 1474{
1475 unsigned long flags = 0;
1da177e4 1476 int rval;
73208dfd 1477 uint32_t handle = 0;
1da177e4
LT		 1478 mbx_cmd_t mc;
1479 mbx_cmd_t *mcp = &mc;
2afa19a9
AC		 1480 fc_port_t *fcport = sp->fcport;
1481 scsi_qla_host_t *vha = fcport->vha;
7b867cf7 1482 struct qla_hw_data *ha = vha->hw;
d7459527 1483 struct req_que *req;
9ba56b95 1484 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1da177e4 1485
5f28d2d7
SK		 1486 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
1487 "Entered %s.\n", __func__);
1da177e4 1488
d7459527
MH		 1489 if (vha->flags.qpairs_available && sp->qpair)
1490 req = sp->qpair->req;
1491 else
1492 req = vha->req;
1493
c9c5ced9 1494 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 1495 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 1496 if (req->outstanding_cmds[handle] == sp)
1da177e4
LT		 1497 break;
1498 }
c9c5ced9 1499 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1500
8d93f550 1501 if (handle == req->num_outstanding_cmds) {
1da177e4
LT		 1502 /* command not found */
1503 return QLA_FUNCTION_FAILED;
1504 }
1505
1506 mcp->mb[0] = MBC_ABORT_COMMAND;
1507 if (HAS_EXTENDED_IDS(ha))
1508 mcp->mb[1] = fcport->loop_id;
1509 else
1510 mcp->mb[1] = fcport->loop_id << 8;
1511 mcp->mb[2] = (uint16_t)handle;
1512 mcp->mb[3] = (uint16_t)(handle >> 16);
9ba56b95 1513 mcp->mb[6] = (uint16_t)cmd->device->lun;
1da177e4
LT		 1514 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1515 mcp->in_mb = MBX_0;
b93480e3 1516 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1517 mcp->flags = 0;
7b867cf7 1518 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1519
1520 if (rval != QLA_SUCCESS) {
7c3df132 1521 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1da177e4 1522 } else {
5f28d2d7
SK		 1523 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
1524 "Done %s.\n", __func__);
1da177e4
LT		 1525 }
1526
1527 return rval;
1528}
1529
1da177e4 1530int
9cb78c16 1531qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
1da177e4 1532{
523ec773 1533 int rval, rval2;
1da177e4
LT		 1534 mbx_cmd_t mc;
1535 mbx_cmd_t *mcp = &mc;
7b867cf7 1536 scsi_qla_host_t *vha;
1da177e4 1537
7b867cf7 1538 vha = fcport->vha;
7c3df132 1539
5f28d2d7
SK		 1540 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
1541 "Entered %s.\n", __func__);
7c3df132 1542
1da177e4 1543 mcp->mb[0] = MBC_ABORT_TARGET;
523ec773 1544 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
7b867cf7 1545 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1546 mcp->mb[1] = fcport->loop_id;
1547 mcp->mb[10] = 0;
1548 mcp->out_mb |= MBX_10;
1549 } else {
1550 mcp->mb[1] = fcport->loop_id << 8;
1551 }
7b867cf7
AC		 1552 mcp->mb[2] = vha->hw->loop_reset_delay;
1553 mcp->mb[9] = vha->vp_idx;
1da177e4
LT		 1554
1555 mcp->in_mb = MBX_0;
b93480e3 1556 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1557 mcp->flags = 0;
7b867cf7 1558 rval = qla2x00_mailbox_command(vha, mcp);
523ec773 1559 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 1560 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
1561 "Failed=%x.\n", rval);
523ec773
AV		 1562 }
1563
1564 /* Issue marker IOCB. */
9eb9c6dc 1565 rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, 0,
73208dfd 1566 MK_SYNC_ID);
523ec773 1567 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1568 ql_dbg(ql_dbg_mbx, vha, 0x1040,
1569 "Failed to issue marker IOCB (%x).\n", rval2);
523ec773 1570 } else {
5f28d2d7
SK		 1571 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
1572 "Done %s.\n", __func__);
523ec773
AV		 1573 }
1574
1575 return rval;
1576}
1577
1578int
9cb78c16 1579qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773
AV		 1580{
1581 int rval, rval2;
1582 mbx_cmd_t mc;
1583 mbx_cmd_t *mcp = &mc;
7b867cf7 1584 scsi_qla_host_t *vha;
523ec773 1585
7b867cf7 1586 vha = fcport->vha;
7c3df132 1587
5f28d2d7
SK		 1588 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1589 "Entered %s.\n", __func__);
7c3df132 1590
523ec773
AV		 1591 mcp->mb[0] = MBC_LUN_RESET;
1592 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 1593 if (HAS_EXTENDED_IDS(vha->hw))
523ec773
AV		 1594 mcp->mb[1] = fcport->loop_id;
1595 else
1596 mcp->mb[1] = fcport->loop_id << 8;
9cb78c16 1597 mcp->mb[2] = (u32)l;
523ec773 1598 mcp->mb[3] = 0;
7b867cf7 1599 mcp->mb[9] = vha->vp_idx;
1da177e4 1600
523ec773 1601 mcp->in_mb = MBX_0;
b93480e3 1602 mcp->tov = MBX_TOV_SECONDS;
523ec773 1603 mcp->flags = 0;
7b867cf7 1604 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1605 if (rval != QLA_SUCCESS) {
7c3df132 1606 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
523ec773
AV		 1607 }
1608
1609 /* Issue marker IOCB. */
9eb9c6dc 1610 rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, l,
73208dfd 1611 MK_SYNC_ID_LUN);
523ec773 1612 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1613 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1614 "Failed to issue marker IOCB (%x).\n", rval2);
1da177e4 1615 } else {
5f28d2d7
SK		 1616 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1617 "Done %s.\n", __func__);
1da177e4
LT		 1618 }
1619
1620 return rval;
1621}
1da177e4 1622
1da177e4
LT		 1623/*
1624 * qla2x00_get_adapter_id
1625 * Get adapter ID and topology.
1626 *
1627 * Input:
1628 * ha = adapter block pointer.
1629 * id = pointer for loop ID.
1630 * al_pa = pointer for AL_PA.
1631 * area = pointer for area.
1632 * domain = pointer for domain.
1633 * top = pointer for topology.
1634 * TARGET_QUEUE_LOCK must be released.
1635 * ADAPTER_STATE_LOCK must be released.
1636 *
1637 * Returns:
1638 * qla2x00 local function return status code.
1639 *
1640 * Context:
1641 * Kernel context.
1642 */
1643int
7b867cf7 1644qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
2c3dfe3f 1645 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1da177e4
LT		 1646{
1647 int rval;
1648 mbx_cmd_t mc;
1649 mbx_cmd_t *mcp = &mc;
1650
5f28d2d7
SK		 1651 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1652 "Entered %s.\n", __func__);
1da177e4
LT		 1653
1654 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
7b867cf7 1655 mcp->mb[9] = vha->vp_idx;
eb66dc60 1656 mcp->out_mb = MBX_9|MBX_0;
2c3dfe3f 1657 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6246b8a1 1658 if (IS_CNA_CAPABLE(vha->hw))
bad7001c 1659 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
7c9c4766
JC		 1660 if (IS_FWI2_CAPABLE(vha->hw))
1661 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
ecc89f25 1662 if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw))
969a6199 1663 mcp->in_mb |= MBX_15;
b93480e3 1664 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1665 mcp->flags = 0;
7b867cf7 1666 rval = qla2x00_mailbox_command(vha, mcp);
33135aa2
RA		 1667 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1668 rval = QLA_COMMAND_ERROR;
42e421b1
AV		 1669 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1670 rval = QLA_INVALID_COMMAND;
1da177e4
LT		 1671
1672 /* Return data. */
1673 *id = mcp->mb[1];
1674 *al_pa = LSB(mcp->mb[2]);
1675 *area = MSB(mcp->mb[2]);
1676 *domain = LSB(mcp->mb[3]);
1677 *top = mcp->mb[6];
2c3dfe3f 1678 *sw_cap = mcp->mb[7];
1da177e4
LT		 1679
1680 if (rval != QLA_SUCCESS) {
1681 /*EMPTY*/
7c3df132 1682 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1da177e4 1683 } else {
5f28d2d7
SK		 1684 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1685 "Done %s.\n", __func__);
bad7001c 1686
6246b8a1 1687 if (IS_CNA_CAPABLE(vha->hw)) {
bad7001c
AV		 1688 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1689 vha->fcoe_fcf_idx = mcp->mb[10];
1690 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1691 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1692 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1693 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1694 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1695 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1696 }
7c9c4766 1697 /* If FA-WWN supported */
d6b9b42b
SK		 1698 if (IS_FAWWN_CAPABLE(vha->hw)) {
1699 if (mcp->mb[7] & BIT_14) {
1700 vha->port_name[0] = MSB(mcp->mb[16]);
1701 vha->port_name[1] = LSB(mcp->mb[16]);
1702 vha->port_name[2] = MSB(mcp->mb[17]);
1703 vha->port_name[3] = LSB(mcp->mb[17]);
1704 vha->port_name[4] = MSB(mcp->mb[18]);
1705 vha->port_name[5] = LSB(mcp->mb[18]);
1706 vha->port_name[6] = MSB(mcp->mb[19]);
1707 vha->port_name[7] = LSB(mcp->mb[19]);
1708 fc_host_port_name(vha->host) =
1709 wwn_to_u64(vha->port_name);
1710 ql_dbg(ql_dbg_mbx, vha, 0x10ca,
1711 "FA-WWN acquired %016llx\n",
1712 wwn_to_u64(vha->port_name));
1713 }
7c9c4766 1714 }
969a6199 1715
ecc89f25 1716 if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw))
969a6199 1717 vha->bbcr = mcp->mb[15];
1da177e4
LT		 1718 }
1719
1720 return rval;
1721}
1722
1723/*
1724 * qla2x00_get_retry_cnt
1725 * Get current firmware login retry count and delay.
1726 *
1727 * Input:
1728 * ha = adapter block pointer.
1729 * retry_cnt = pointer to login retry count.
1730 * tov = pointer to login timeout value.
1731 *
1732 * Returns:
1733 * qla2x00 local function return status code.
1734 *
1735 * Context:
1736 * Kernel context.
1737 */
1738int
7b867cf7 1739qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1da177e4
LT		 1740 uint16_t *r_a_tov)
1741{
1742 int rval;
1743 uint16_t ratov;
1744 mbx_cmd_t mc;
1745 mbx_cmd_t *mcp = &mc;
1746
5f28d2d7
SK		 1747 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1748 "Entered %s.\n", __func__);
1da177e4
LT		 1749
1750 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1751 mcp->out_mb = MBX_0;
1752 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1753 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1754 mcp->flags = 0;
7b867cf7 1755 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1756
1757 if (rval != QLA_SUCCESS) {
1758 /*EMPTY*/
7c3df132
SK		 1759 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1760 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4
LT		 1761 } else {
1762 /* Convert returned data and check our values. */
1763 *r_a_tov = mcp->mb[3] / 2;
1764 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1765 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1766 /* Update to the larger values */
1767 *retry_cnt = (uint8_t)mcp->mb[1];
1768 *tov = ratov;
1769 }
1770
5f28d2d7 1771 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
7c3df132 1772 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1da177e4
LT		 1773 }
1774
1775 return rval;
1776}
1777
1778/*
1779 * qla2x00_init_firmware
1780 * Initialize adapter firmware.
1781 *
1782 * Input:
1783 * ha = adapter block pointer.
1784 * dptr = Initialization control block pointer.
1785 * size = size of initialization control block.
1786 * TARGET_QUEUE_LOCK must be released.
1787 * ADAPTER_STATE_LOCK must be released.
1788 *
1789 * Returns:
1790 * qla2x00 local function return status code.
1791 *
1792 * Context:
1793 * Kernel context.
1794 */
1795int
7b867cf7 1796qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1da177e4
LT		 1797{
1798 int rval;
1799 mbx_cmd_t mc;
1800 mbx_cmd_t *mcp = &mc;
7b867cf7 1801 struct qla_hw_data *ha = vha->hw;
1da177e4 1802
5f28d2d7
SK		 1803 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1804 "Entered %s.\n", __func__);
1da177e4 1805
7ec0effd 1806 if (IS_P3P_TYPE(ha) && ql2xdbwr)
8dfa4b5a 1807 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
a9083016
GM		 1808 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1809
e6e074f1 1810 if (ha->flags.npiv_supported)
2c3dfe3f
SJ		 1811 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1812 else
1813 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1814
b64b0e8f 1815 mcp->mb[1] = 0;
1da177e4
LT		 1816 mcp->mb[2] = MSW(ha->init_cb_dma);
1817 mcp->mb[3] = LSW(ha->init_cb_dma);
1da177e4
LT		 1818 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1819 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
b64b0e8f 1820 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4ef21bd4 1821 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
b64b0e8f
AV		 1822 mcp->mb[1] = BIT_0;
1823 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1824 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1825 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1826 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1827 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1828 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1829 }
6246b8a1
GM		 1830 /* 1 and 2 should normally be captured. */
1831 mcp->in_mb = MBX_2|MBX_1|MBX_0;
ecc89f25 1832 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
6246b8a1
GM		 1833 /* mb3 is additional info about the installed SFP. */
1834 mcp->in_mb |= MBX_3;
1da177e4
LT		 1835 mcp->buf_size = size;
1836 mcp->flags = MBX_DMA_OUT;
b93480e3 1837 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1838 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1839
1840 if (rval != QLA_SUCCESS) {
1841 /*EMPTY*/
7c3df132 1842 ql_dbg(ql_dbg_mbx, vha, 0x104d,
f8f97b0c 1843 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x.\n",
6246b8a1 1844 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
f8f97b0c
JC		 1845 if (ha->init_cb) {
1846 ql_dbg(ql_dbg_mbx, vha, 0x104d, "init_cb:\n");
1847 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
1848 0x0104d, ha->init_cb, sizeof(*ha->init_cb));
1849 }
1850 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
1851 ql_dbg(ql_dbg_mbx, vha, 0x104d, "ex_init_cb:\n");
1852 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
1853 0x0104d, ha->ex_init_cb, sizeof(*ha->ex_init_cb));
1854 }
1da177e4 1855 } else {
ecc89f25 1856 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
92d4408e
SC		 1857 if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
1858 ql_dbg(ql_dbg_mbx, vha, 0x119d,
1859 "Invalid SFP/Validation Failed\n");
1860 }
5f28d2d7
SK		 1861 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1862 "Done %s.\n", __func__);
1da177e4
LT		 1863 }
1864
1865 return rval;
1866}
1867
2d70c103 1868
1da177e4
LT		 1869/*
1870 * qla2x00_get_port_database
1871 * Issue normal/enhanced get port database mailbox command
1872 * and copy device name as necessary.
1873 *
1874 * Input:
1875 * ha = adapter state pointer.
1876 * dev = structure pointer.
1877 * opt = enhanced cmd option byte.
1878 *
1879 * Returns:
1880 * qla2x00 local function return status code.
1881 *
1882 * Context:
1883 * Kernel context.
1884 */
1885int
7b867cf7 1886qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1da177e4
LT		 1887{
1888 int rval;
1889 mbx_cmd_t mc;
1890 mbx_cmd_t *mcp = &mc;
1891 port_database_t *pd;
1c7c6357 1892 struct port_database_24xx *pd24;
1da177e4 1893 dma_addr_t pd_dma;
7b867cf7 1894 struct qla_hw_data *ha = vha->hw;
1da177e4 1895
5f28d2d7
SK		 1896 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1897 "Entered %s.\n", __func__);
1da177e4 1898
1c7c6357 1899 pd24 = NULL;
08eb7f45 1900 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1da177e4 1901 if (pd == NULL) {
7c3df132
SK		 1902 ql_log(ql_log_warn, vha, 0x1050,
1903 "Failed to allocate port database structure.\n");
edd05de1 1904 fcport->query = 0;
1da177e4
LT		 1905 return QLA_MEMORY_ALLOC_FAILED;
1906 }
1da177e4 1907
1c7c6357 1908 mcp->mb[0] = MBC_GET_PORT_DATABASE;
e428924c 1909 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1da177e4 1910 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1da177e4
LT		 1911 mcp->mb[2] = MSW(pd_dma);
1912 mcp->mb[3] = LSW(pd_dma);
1913 mcp->mb[6] = MSW(MSD(pd_dma));
1914 mcp->mb[7] = LSW(MSD(pd_dma));
7b867cf7 1915 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1916 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1da177e4 1917 mcp->in_mb = MBX_0;
e428924c 1918 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 1919 mcp->mb[1] = fcport->loop_id;
1920 mcp->mb[10] = opt;
1921 mcp->out_mb |= MBX_10|MBX_1;
1922 mcp->in_mb |= MBX_1;
1923 } else if (HAS_EXTENDED_IDS(ha)) {
1924 mcp->mb[1] = fcport->loop_id;
1925 mcp->mb[10] = opt;
1926 mcp->out_mb |= MBX_10|MBX_1;
1927 } else {
1928 mcp->mb[1] = fcport->loop_id << 8 | opt;
1929 mcp->out_mb |= MBX_1;
1930 }
e428924c
AV		 1931 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1932 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1da177e4
LT		 1933 mcp->flags = MBX_DMA_IN;
1934 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 1935 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1936 if (rval != QLA_SUCCESS)
1937 goto gpd_error_out;
1938
e428924c 1939 if (IS_FWI2_CAPABLE(ha)) {
0eba25df 1940 uint64_t zero = 0;
c0c462c8
DG		 1941 u8 current_login_state, last_login_state;
1942
1c7c6357
AV		 1943 pd24 = (struct port_database_24xx *) pd;
1944
1945 /* Check for logged in state. */
c0c462c8
DG		 1946 if (fcport->fc4f_nvme) {
1947 current_login_state = pd24->current_login_state >> 4;
1948 last_login_state = pd24->last_login_state >> 4;
1949 } else {
1950 current_login_state = pd24->current_login_state & 0xf;
1951 last_login_state = pd24->last_login_state & 0xf;
1952 }
1953 fcport->current_login_state = pd24->current_login_state;
1954 fcport->last_login_state = pd24->last_login_state;
1955
1956 /* Check for logged in state. */
1957 if (current_login_state != PDS_PRLI_COMPLETE &&
1958 last_login_state != PDS_PRLI_COMPLETE) {
1959 ql_dbg(ql_dbg_mbx, vha, 0x119a,
1960 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
1961 current_login_state, last_login_state,
1962 fcport->loop_id);
1c7c6357 1963 rval = QLA_FUNCTION_FAILED;
c0c462c8
DG		 1964
1965 if (!fcport->query)
1966 goto gpd_error_out;
1c7c6357 1967 }
1da177e4 1968
0eba25df
AE		 1969 if (fcport->loop_id == FC_NO_LOOP_ID ||
1970 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1971 memcmp(fcport->port_name, pd24->port_name, 8))) {
1972 /* We lost the device mid way. */
1973 rval = QLA_NOT_LOGGED_IN;
1974 goto gpd_error_out;
1975 }
1976
1c7c6357
AV		 1977 /* Names are little-endian. */
1978 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1979 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1980
1981 /* Get port_id of device. */
1982 fcport->d_id.b.domain = pd24->port_id[0];
1983 fcport->d_id.b.area = pd24->port_id[1];
1984 fcport->d_id.b.al_pa = pd24->port_id[2];
1985 fcport->d_id.b.rsvd_1 = 0;
1986
1987 /* If not target must be initiator or unknown type. */
1988 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1989 fcport->port_type = FCT_INITIATOR;
1990 else
1991 fcport->port_type = FCT_TARGET;
2d70c103
NB		 1992
1993 /* Passback COS information. */
1994 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
1995 FC_COS_CLASS2 : FC_COS_CLASS3;
1996
1997 if (pd24->prli_svc_param_word_3[0] & BIT_7)
1998 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1c7c6357 1999 } else {
0eba25df
AE		 2000 uint64_t zero = 0;
2001
1c7c6357
AV		 2002 /* Check for logged in state. */
2003 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
2004 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
7c3df132
SK		 2005 ql_dbg(ql_dbg_mbx, vha, 0x100a,
2006 "Unable to verify login-state (%x/%x) - "
2007 "portid=%02x%02x%02x.\n", pd->master_state,
2008 pd->slave_state, fcport->d_id.b.domain,
2009 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1c7c6357
AV		 2010 rval = QLA_FUNCTION_FAILED;
2011 goto gpd_error_out;
2012 }
1da177e4 2013
0eba25df
AE		 2014 if (fcport->loop_id == FC_NO_LOOP_ID ||
2015 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
2016 memcmp(fcport->port_name, pd->port_name, 8))) {
2017 /* We lost the device mid way. */
2018 rval = QLA_NOT_LOGGED_IN;
2019 goto gpd_error_out;
2020 }
2021
1c7c6357
AV		 2022 /* Names are little-endian. */
2023 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
2024 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
2025
2026 /* Get port_id of device. */
2027 fcport->d_id.b.domain = pd->port_id[0];
2028 fcport->d_id.b.area = pd->port_id[3];
2029 fcport->d_id.b.al_pa = pd->port_id[2];
2030 fcport->d_id.b.rsvd_1 = 0;
2031
1c7c6357
AV		 2032 /* If not target must be initiator or unknown type. */
2033 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
2034 fcport->port_type = FCT_INITIATOR;
2035 else
2036 fcport->port_type = FCT_TARGET;
ad3e0eda
AV		 2037
2038 /* Passback COS information. */
2039 fcport->supported_classes = (pd->options & BIT_4) ?
58e2753c 2040 FC_COS_CLASS2 : FC_COS_CLASS3;
1c7c6357 2041 }
1da177e4
LT		 2042
2043gpd_error_out:
2044 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
edd05de1 2045 fcport->query = 0;
1da177e4
LT		 2046
2047 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2048 ql_dbg(ql_dbg_mbx, vha, 0x1052,
2049 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
2050 mcp->mb[0], mcp->mb[1]);
1da177e4 2051 } else {
5f28d2d7
SK		 2052 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
2053 "Done %s.\n", __func__);
1da177e4
LT		 2054 }
2055
2056 return rval;
2057}
2058
2059/*
2060 * qla2x00_get_firmware_state
2061 * Get adapter firmware state.
2062 *
2063 * Input:
2064 * ha = adapter block pointer.
2065 * dptr = pointer for firmware state.
2066 * TARGET_QUEUE_LOCK must be released.
2067 * ADAPTER_STATE_LOCK must be released.
2068 *
2069 * Returns:
2070 * qla2x00 local function return status code.
2071 *
2072 * Context:
2073 * Kernel context.
2074 */
2075int
7b867cf7 2076qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1da177e4
LT		 2077{
2078 int rval;
2079 mbx_cmd_t mc;
2080 mbx_cmd_t *mcp = &mc;
92d4408e 2081 struct qla_hw_data *ha = vha->hw;
1da177e4 2082
5f28d2d7
SK		 2083 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
2084 "Entered %s.\n", __func__);
1da177e4
LT		 2085
2086 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
2087 mcp->out_mb = MBX_0;
9d2683c0 2088 if (IS_FWI2_CAPABLE(vha->hw))
b5a340dd 2089 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
9d2683c0
AV		 2090 else
2091 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2092 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2093 mcp->flags = 0;
7b867cf7 2094 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 2095
4d4df193
HK		 2096 /* Return firmware states. */
2097 states[0] = mcp->mb[1];
9d2683c0
AV		 2098 if (IS_FWI2_CAPABLE(vha->hw)) {
2099 states[1] = mcp->mb[2];
ec891462 2100 states[2] = mcp->mb[3]; /* SFP info */
9d2683c0
AV		 2101 states[3] = mcp->mb[4];
2102 states[4] = mcp->mb[5];
b5a340dd 2103 states[5] = mcp->mb[6]; /* DPORT status */
9d2683c0 2104 }
1da177e4
LT		 2105
2106 if (rval != QLA_SUCCESS) {
2107 /*EMPTY*/
7c3df132 2108 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1da177e4 2109 } else {
ecc89f25 2110 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
92d4408e
SC		 2111 if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
2112 ql_dbg(ql_dbg_mbx, vha, 0x119e,
2113 "Invalid SFP/Validation Failed\n");
2114 }
5f28d2d7
SK		 2115 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
2116 "Done %s.\n", __func__);
1da177e4
LT		 2117 }
2118
2119 return rval;
2120}
2121
2122/*
2123 * qla2x00_get_port_name
2124 * Issue get port name mailbox command.
2125 * Returned name is in big endian format.
2126 *
2127 * Input:
2128 * ha = adapter block pointer.
2129 * loop_id = loop ID of device.
2130 * name = pointer for name.
2131 * TARGET_QUEUE_LOCK must be released.
2132 * ADAPTER_STATE_LOCK must be released.
2133 *
2134 * Returns:
2135 * qla2x00 local function return status code.
2136 *
2137 * Context:
2138 * Kernel context.
2139 */
2140int
7b867cf7 2141qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1da177e4
LT		 2142 uint8_t opt)
2143{
2144 int rval;
2145 mbx_cmd_t mc;
2146 mbx_cmd_t *mcp = &mc;
2147
5f28d2d7
SK		 2148 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
2149 "Entered %s.\n", __func__);
1da177e4
LT		 2150
2151 mcp->mb[0] = MBC_GET_PORT_NAME;
7b867cf7 2152 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2153 mcp->out_mb = MBX_9|MBX_1|MBX_0;
7b867cf7 2154 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2155 mcp->mb[1] = loop_id;
2156 mcp->mb[10] = opt;
2157 mcp->out_mb |= MBX_10;
2158 } else {
2159 mcp->mb[1] = loop_id << 8 | opt;
2160 }
2161
2162 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 2163 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2164 mcp->flags = 0;
7b867cf7 2165 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2166
2167 if (rval != QLA_SUCCESS) {
2168 /*EMPTY*/
7c3df132 2169 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1da177e4
LT		 2170 } else {
2171 if (name != NULL) {
2172 /* This function returns name in big endian. */
1196ae02
RL		 2173 name[0] = MSB(mcp->mb[2]);
2174 name[1] = LSB(mcp->mb[2]);
2175 name[2] = MSB(mcp->mb[3]);
2176 name[3] = LSB(mcp->mb[3]);
2177 name[4] = MSB(mcp->mb[6]);
2178 name[5] = LSB(mcp->mb[6]);
2179 name[6] = MSB(mcp->mb[7]);
2180 name[7] = LSB(mcp->mb[7]);
1da177e4
LT		 2181 }
2182
5f28d2d7
SK		 2183 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
2184 "Done %s.\n", __func__);
1da177e4
LT		 2185 }
2186
2187 return rval;
2188}
2189
61e1b269
JC		 2190/*
2191 * qla24xx_link_initialization
2192 * Issue link initialization mailbox command.
2193 *
2194 * Input:
2195 * ha = adapter block pointer.
2196 * TARGET_QUEUE_LOCK must be released.
2197 * ADAPTER_STATE_LOCK must be released.
2198 *
2199 * Returns:
2200 * qla2x00 local function return status code.
2201 *
2202 * Context:
2203 * Kernel context.
2204 */
2205int
2206qla24xx_link_initialize(scsi_qla_host_t *vha)
2207{
2208 int rval;
2209 mbx_cmd_t mc;
2210 mbx_cmd_t *mcp = &mc;
2211
2212 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
2213 "Entered %s.\n", __func__);
2214
2215 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
2216 return QLA_FUNCTION_FAILED;
2217
2218 mcp->mb[0] = MBC_LINK_INITIALIZATION;
5a5c27b6
JC		 2219 mcp->mb[1] = BIT_4;
2220 if (vha->hw->operating_mode == LOOP)
2221 mcp->mb[1] |= BIT_6;
2222 else
2223 mcp->mb[1] |= BIT_5;
61e1b269
JC		 2224 mcp->mb[2] = 0;
2225 mcp->mb[3] = 0;
2226 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2227 mcp->in_mb = MBX_0;
2228 mcp->tov = MBX_TOV_SECONDS;
2229 mcp->flags = 0;
2230 rval = qla2x00_mailbox_command(vha, mcp);
2231
2232 if (rval != QLA_SUCCESS) {
2233 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
2234 } else {
2235 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
2236 "Done %s.\n", __func__);
2237 }
2238
2239 return rval;
2240}
2241
1da177e4
LT		 2242/*
2243 * qla2x00_lip_reset
2244 * Issue LIP reset mailbox command.
2245 *
2246 * Input:
2247 * ha = adapter block pointer.
2248 * TARGET_QUEUE_LOCK must be released.
2249 * ADAPTER_STATE_LOCK must be released.
2250 *
2251 * Returns:
2252 * qla2x00 local function return status code.
2253 *
2254 * Context:
2255 * Kernel context.
2256 */
2257int
7b867cf7 2258qla2x00_lip_reset(scsi_qla_host_t *vha)
1da177e4
LT		 2259{
2260 int rval;
2261 mbx_cmd_t mc;
2262 mbx_cmd_t *mcp = &mc;
2263
5f28d2d7
SK		 2264 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
2265 "Entered %s.\n", __func__);
1da177e4 2266
6246b8a1 2267 if (IS_CNA_CAPABLE(vha->hw)) {
3a03eb79
AV		 2268 /* Logout across all FCFs. */
2269 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2270 mcp->mb[1] = BIT_1;
2271 mcp->mb[2] = 0;
2272 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2273 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 2274 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
87d6814a 2275 mcp->mb[1] = BIT_4;
0c8c39af 2276 mcp->mb[2] = 0;
7b867cf7 2277 mcp->mb[3] = vha->hw->loop_reset_delay;
1c7c6357 2278 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 2279 } else {
1c7c6357
AV		 2280 mcp->mb[0] = MBC_LIP_RESET;
2281 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 2282 if (HAS_EXTENDED_IDS(vha->hw)) {
1c7c6357
AV		 2283 mcp->mb[1] = 0x00ff;
2284 mcp->mb[10] = 0;
2285 mcp->out_mb |= MBX_10;
2286 } else {
2287 mcp->mb[1] = 0xff00;
2288 }
7b867cf7 2289 mcp->mb[2] = vha->hw->loop_reset_delay;
1c7c6357 2290 mcp->mb[3] = 0;
1da177e4 2291 }
1da177e4 2292 mcp->in_mb = MBX_0;
b93480e3 2293 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2294 mcp->flags = 0;
7b867cf7 2295 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2296
2297 if (rval != QLA_SUCCESS) {
2298 /*EMPTY*/
7c3df132 2299 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1da177e4
LT		 2300 } else {
2301 /*EMPTY*/
5f28d2d7
SK		 2302 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
2303 "Done %s.\n", __func__);
1da177e4
LT		 2304 }
2305
2306 return rval;
2307}
2308
2309/*
2310 * qla2x00_send_sns
2311 * Send SNS command.
2312 *
2313 * Input:
2314 * ha = adapter block pointer.
2315 * sns = pointer for command.
2316 * cmd_size = command size.
2317 * buf_size = response/command size.
2318 * TARGET_QUEUE_LOCK must be released.
2319 * ADAPTER_STATE_LOCK must be released.
2320 *
2321 * Returns:
2322 * qla2x00 local function return status code.
2323 *
2324 * Context:
2325 * Kernel context.
2326 */
2327int
7b867cf7 2328qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1da177e4
LT		 2329 uint16_t cmd_size, size_t buf_size)
2330{
2331 int rval;
2332 mbx_cmd_t mc;
2333 mbx_cmd_t *mcp = &mc;
2334
5f28d2d7
SK		 2335 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
2336 "Entered %s.\n", __func__);
1da177e4 2337
5f28d2d7 2338 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
7c3df132
SK		 2339 "Retry cnt=%d ratov=%d total tov=%d.\n",
2340 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1da177e4
LT		 2341
2342 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
2343 mcp->mb[1] = cmd_size;
2344 mcp->mb[2] = MSW(sns_phys_address);
2345 mcp->mb[3] = LSW(sns_phys_address);
2346 mcp->mb[6] = MSW(MSD(sns_phys_address));
2347 mcp->mb[7] = LSW(MSD(sns_phys_address));
2348 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2349 mcp->in_mb = MBX_0|MBX_1;
2350 mcp->buf_size = buf_size;
2351 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
7b867cf7
AC		 2352 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
2353 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2354
2355 if (rval != QLA_SUCCESS) {
2356 /*EMPTY*/
7c3df132
SK		 2357 ql_dbg(ql_dbg_mbx, vha, 0x105f,
2358 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2359 rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 2360 } else {
2361 /*EMPTY*/
5f28d2d7
SK		 2362 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
2363 "Done %s.\n", __func__);
1da177e4
LT		 2364 }
2365
2366 return rval;
2367}
2368
1c7c6357 2369int
7b867cf7 2370qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2371 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2372{
2373 int rval;
2374
2375 struct logio_entry_24xx *lg;
2376 dma_addr_t lg_dma;
2377 uint32_t iop[2];
7b867cf7 2378 struct qla_hw_data *ha = vha->hw;
2afa19a9 2379 struct req_que *req;
1c7c6357 2380
5f28d2d7
SK		 2381 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
2382 "Entered %s.\n", __func__);
1c7c6357 2383
d7459527
MH		 2384 if (vha->vp_idx && vha->qpair)
2385 req = vha->qpair->req;
68ca949c 2386 else
d7459527 2387 req = ha->req_q_map[0];
2afa19a9 2388
08eb7f45 2389 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1c7c6357 2390 if (lg == NULL) {
7c3df132
SK		 2391 ql_log(ql_log_warn, vha, 0x1062,
2392 "Failed to allocate login IOCB.\n");
1c7c6357
AV		 2393 return QLA_MEMORY_ALLOC_FAILED;
2394 }
1c7c6357
AV		 2395
2396 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2397 lg->entry_count = 1;
2afa19a9 2398 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357 2399 lg->nport_handle = cpu_to_le16(loop_id);
ad950360 2400 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
1c7c6357 2401 if (opt & BIT_0)
ad950360 2402 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI);
8baa51a6 2403 if (opt & BIT_1)
ad950360 2404 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI);
1c7c6357
AV		 2405 lg->port_id[0] = al_pa;
2406 lg->port_id[1] = area;
2407 lg->port_id[2] = domain;
7b867cf7 2408 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2409 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2410 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2411 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2412 ql_dbg(ql_dbg_mbx, vha, 0x1063,
2413 "Failed to issue login IOCB (%x).\n", rval);
1c7c6357 2414 } else if (lg->entry_status != 0) {
7c3df132
SK		 2415 ql_dbg(ql_dbg_mbx, vha, 0x1064,
2416 "Failed to complete IOCB -- error status (%x).\n",
2417 lg->entry_status);
1c7c6357 2418 rval = QLA_FUNCTION_FAILED;
ad950360 2419 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
1c7c6357
AV		 2420 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2421 iop[1] = le32_to_cpu(lg->io_parameter[1]);
2422
7c3df132
SK		 2423 ql_dbg(ql_dbg_mbx, vha, 0x1065,
2424 "Failed to complete IOCB -- completion status (%x) "
2425 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2426 iop[0], iop[1]);
1c7c6357
AV		 2427
2428 switch (iop[0]) {
2429 case LSC_SCODE_PORTID_USED:
2430 mb[0] = MBS_PORT_ID_USED;
2431 mb[1] = LSW(iop[1]);
2432 break;
2433 case LSC_SCODE_NPORT_USED:
2434 mb[0] = MBS_LOOP_ID_USED;
2435 break;
2436 case LSC_SCODE_NOLINK:
2437 case LSC_SCODE_NOIOCB:
2438 case LSC_SCODE_NOXCB:
2439 case LSC_SCODE_CMD_FAILED:
2440 case LSC_SCODE_NOFABRIC:
2441 case LSC_SCODE_FW_NOT_READY:
2442 case LSC_SCODE_NOT_LOGGED_IN:
2443 case LSC_SCODE_NOPCB:
2444 case LSC_SCODE_ELS_REJECT:
2445 case LSC_SCODE_CMD_PARAM_ERR:
2446 case LSC_SCODE_NONPORT:
2447 case LSC_SCODE_LOGGED_IN:
2448 case LSC_SCODE_NOFLOGI_ACC:
2449 default:
2450 mb[0] = MBS_COMMAND_ERROR;
2451 break;
2452 }
2453 } else {
5f28d2d7
SK		 2454 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
2455 "Done %s.\n", __func__);
1c7c6357
AV		 2456
2457 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2458
2459 mb[0] = MBS_COMMAND_COMPLETE;
2460 mb[1] = 0;
2461 if (iop[0] & BIT_4) {
2462 if (iop[0] & BIT_8)
2463 mb[1] |= BIT_1;
2464 } else
2465 mb[1] = BIT_0;
ad3e0eda
AV		 2466
2467 /* Passback COS information. */
2468 mb[10] = 0;
2469 if (lg->io_parameter[7] || lg->io_parameter[8])
2470 mb[10] |= BIT_0; /* Class 2. */
2471 if (lg->io_parameter[9] || lg->io_parameter[10])
2472 mb[10] |= BIT_1; /* Class 3. */
ad950360 2473 if (lg->io_parameter[0] & cpu_to_le32(BIT_7))
2d70c103
NB		 2474 mb[10] |= BIT_7; /* Confirmed Completion
2475 * Allowed
2476 */
1c7c6357
AV		 2477 }
2478
2479 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2480
2481 return rval;
2482}
2483
1da177e4
LT		 2484/*
2485 * qla2x00_login_fabric
2486 * Issue login fabric port mailbox command.
2487 *
2488 * Input:
2489 * ha = adapter block pointer.
2490 * loop_id = device loop ID.
2491 * domain = device domain.
2492 * area = device area.
2493 * al_pa = device AL_PA.
2494 * status = pointer for return status.
2495 * opt = command options.
2496 * TARGET_QUEUE_LOCK must be released.
2497 * ADAPTER_STATE_LOCK must be released.
2498 *
2499 * Returns:
2500 * qla2x00 local function return status code.
2501 *
2502 * Context:
2503 * Kernel context.
2504 */
2505int
7b867cf7 2506qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1da177e4
LT		 2507 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2508{
2509 int rval;
2510 mbx_cmd_t mc;
2511 mbx_cmd_t *mcp = &mc;
7b867cf7 2512 struct qla_hw_data *ha = vha->hw;
1da177e4 2513
5f28d2d7
SK		 2514 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
2515 "Entered %s.\n", __func__);
1da177e4
LT		 2516
2517 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
2518 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2519 if (HAS_EXTENDED_IDS(ha)) {
2520 mcp->mb[1] = loop_id;
2521 mcp->mb[10] = opt;
2522 mcp->out_mb |= MBX_10;
2523 } else {
2524 mcp->mb[1] = (loop_id << 8) | opt;
2525 }
2526 mcp->mb[2] = domain;
2527 mcp->mb[3] = area << 8 | al_pa;
2528
2529 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
2530 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2531 mcp->flags = 0;
7b867cf7 2532 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2533
2534 /* Return mailbox statuses. */
2535 if (mb != NULL) {
2536 mb[0] = mcp->mb[0];
2537 mb[1] = mcp->mb[1];
2538 mb[2] = mcp->mb[2];
2539 mb[6] = mcp->mb[6];
2540 mb[7] = mcp->mb[7];
ad3e0eda
AV		 2541 /* COS retrieved from Get-Port-Database mailbox command. */
2542 mb[10] = 0;
1da177e4
LT		 2543 }
2544
2545 if (rval != QLA_SUCCESS) {
2546 /* RLU tmp code: need to change main mailbox_command function to
2547 * return ok even when the mailbox completion value is not
2548 * SUCCESS. The caller needs to be responsible to interpret
2549 * the return values of this mailbox command if we're not
2550 * to change too much of the existing code.
2551 */
2552 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2553 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2554 mcp->mb[0] == 0x4006)
2555 rval = QLA_SUCCESS;
2556
2557 /*EMPTY*/
7c3df132
SK		 2558 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2559 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2560 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1da177e4
LT		 2561 } else {
2562 /*EMPTY*/
5f28d2d7
SK		 2563 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2564 "Done %s.\n", __func__);
1da177e4
LT		 2565 }
2566
2567 return rval;
2568}
2569
2570/*
2571 * qla2x00_login_local_device
2572 * Issue login loop port mailbox command.
fa2a1ce5 2573 *
1da177e4
LT		 2574 * Input:
2575 * ha = adapter block pointer.
2576 * loop_id = device loop ID.
2577 * opt = command options.
fa2a1ce5 2578 *
1da177e4
LT		 2579 * Returns:
2580 * Return status code.
fa2a1ce5 2581 *
1da177e4
LT		 2582 * Context:
2583 * Kernel context.
fa2a1ce5 2584 *
1da177e4
LT		 2585 */
2586int
7b867cf7 2587qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 2588 uint16_t *mb_ret, uint8_t opt)
2589{
2590 int rval;
2591 mbx_cmd_t mc;
2592 mbx_cmd_t *mcp = &mc;
7b867cf7 2593 struct qla_hw_data *ha = vha->hw;
1da177e4 2594
5f28d2d7
SK		 2595 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2596 "Entered %s.\n", __func__);
7c3df132 2597
e428924c 2598 if (IS_FWI2_CAPABLE(ha))
7b867cf7 2599 return qla24xx_login_fabric(vha, fcport->loop_id,
9a52a57c 2600 fcport->d_id.b.domain, fcport->d_id.b.area,
2601 fcport->d_id.b.al_pa, mb_ret, opt);
2602
1da177e4
LT		 2603 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2604 if (HAS_EXTENDED_IDS(ha))
9a52a57c 2605 mcp->mb[1] = fcport->loop_id;
1da177e4 2606 else
9a52a57c 2607 mcp->mb[1] = fcport->loop_id << 8;
1da177e4
LT		 2608 mcp->mb[2] = opt;
2609 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2610 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2611 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2612 mcp->flags = 0;
7b867cf7 2613 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2614
2615 /* Return mailbox statuses. */
2616 if (mb_ret != NULL) {
2617 mb_ret[0] = mcp->mb[0];
2618 mb_ret[1] = mcp->mb[1];
2619 mb_ret[6] = mcp->mb[6];
2620 mb_ret[7] = mcp->mb[7];
2621 }
2622
2623 if (rval != QLA_SUCCESS) {
2624 /* AV tmp code: need to change main mailbox_command function to
2625 * return ok even when the mailbox completion value is not
2626 * SUCCESS. The caller needs to be responsible to interpret
2627 * the return values of this mailbox command if we're not
2628 * to change too much of the existing code.
2629 */
2630 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2631 rval = QLA_SUCCESS;
2632
7c3df132
SK		 2633 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2634 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2635 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
1da177e4
LT		 2636 } else {
2637 /*EMPTY*/
5f28d2d7
SK		 2638 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2639 "Done %s.\n", __func__);
1da177e4
LT		 2640 }
2641
2642 return (rval);
2643}
2644
1c7c6357 2645int
7b867cf7 2646qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2647 uint8_t area, uint8_t al_pa)
2648{
2649 int rval;
2650 struct logio_entry_24xx *lg;
2651 dma_addr_t lg_dma;
7b867cf7 2652 struct qla_hw_data *ha = vha->hw;
2afa19a9 2653 struct req_que *req;
1c7c6357 2654
5f28d2d7
SK		 2655 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2656 "Entered %s.\n", __func__);
1c7c6357 2657
08eb7f45 2658 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1c7c6357 2659 if (lg == NULL) {
7c3df132
SK		 2660 ql_log(ql_log_warn, vha, 0x106e,
2661 "Failed to allocate logout IOCB.\n");
1c7c6357
AV		 2662 return QLA_MEMORY_ALLOC_FAILED;
2663 }
1c7c6357 2664
d7459527 2665 req = vha->req;
1c7c6357
AV		 2666 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2667 lg->entry_count = 1;
2afa19a9 2668 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357
AV		 2669 lg->nport_handle = cpu_to_le16(loop_id);
2670 lg->control_flags =
ad950360 2671 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
c8d6691b 2672 LCF_FREE_NPORT);
1c7c6357
AV		 2673 lg->port_id[0] = al_pa;
2674 lg->port_id[1] = area;
2675 lg->port_id[2] = domain;
7b867cf7 2676 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2677 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2678 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2679 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2680 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2681 "Failed to issue logout IOCB (%x).\n", rval);
1c7c6357 2682 } else if (lg->entry_status != 0) {
7c3df132
SK		 2683 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2684 "Failed to complete IOCB -- error status (%x).\n",
2685 lg->entry_status);
1c7c6357 2686 rval = QLA_FUNCTION_FAILED;
ad950360 2687 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2688 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2689 "Failed to complete IOCB -- completion status (%x) "
2690 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1c7c6357 2691 le32_to_cpu(lg->io_parameter[0]),
7c3df132 2692 le32_to_cpu(lg->io_parameter[1]));
1c7c6357
AV		 2693 } else {
2694 /*EMPTY*/
5f28d2d7
SK		 2695 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2696 "Done %s.\n", __func__);
1c7c6357
AV		 2697 }
2698
2699 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2700
2701 return rval;
2702}
2703
1da177e4
LT		 2704/*
2705 * qla2x00_fabric_logout
2706 * Issue logout fabric port mailbox command.
2707 *
2708 * Input:
2709 * ha = adapter block pointer.
2710 * loop_id = device loop ID.
2711 * TARGET_QUEUE_LOCK must be released.
2712 * ADAPTER_STATE_LOCK must be released.
2713 *
2714 * Returns:
2715 * qla2x00 local function return status code.
2716 *
2717 * Context:
2718 * Kernel context.
2719 */
2720int
7b867cf7 2721qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357 2722 uint8_t area, uint8_t al_pa)
1da177e4
LT		 2723{
2724 int rval;
2725 mbx_cmd_t mc;
2726 mbx_cmd_t *mcp = &mc;
2727
5f28d2d7
SK		 2728 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2729 "Entered %s.\n", __func__);
1da177e4
LT		 2730
2731 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2732 mcp->out_mb = MBX_1|MBX_0;
7b867cf7 2733 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2734 mcp->mb[1] = loop_id;
2735 mcp->mb[10] = 0;
2736 mcp->out_mb |= MBX_10;
2737 } else {
2738 mcp->mb[1] = loop_id << 8;
2739 }
2740
2741 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2742 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2743 mcp->flags = 0;
7b867cf7 2744 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2745
2746 if (rval != QLA_SUCCESS) {
2747 /*EMPTY*/
7c3df132
SK		 2748 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2749 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
1da177e4
LT		 2750 } else {
2751 /*EMPTY*/
5f28d2d7
SK		 2752 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2753 "Done %s.\n", __func__);
1da177e4
LT		 2754 }
2755
2756 return rval;
2757}
2758
2759/*
2760 * qla2x00_full_login_lip
2761 * Issue full login LIP mailbox command.
2762 *
2763 * Input:
2764 * ha = adapter block pointer.
2765 * TARGET_QUEUE_LOCK must be released.
2766 * ADAPTER_STATE_LOCK must be released.
2767 *
2768 * Returns:
2769 * qla2x00 local function return status code.
2770 *
2771 * Context:
2772 * Kernel context.
2773 */
2774int
7b867cf7 2775qla2x00_full_login_lip(scsi_qla_host_t *vha)
1da177e4
LT		 2776{
2777 int rval;
2778 mbx_cmd_t mc;
2779 mbx_cmd_t *mcp = &mc;
2780
5f28d2d7
SK		 2781 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2782 "Entered %s.\n", __func__);
1da177e4
LT		 2783
2784 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
87d6814a 2785 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_4 : 0;
0c8c39af 2786 mcp->mb[2] = 0;
1da177e4
LT		 2787 mcp->mb[3] = 0;
2788 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2789 mcp->in_mb = MBX_0;
b93480e3 2790 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2791 mcp->flags = 0;
7b867cf7 2792 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2793
2794 if (rval != QLA_SUCCESS) {
2795 /*EMPTY*/
7c3df132 2796 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
1da177e4
LT		 2797 } else {
2798 /*EMPTY*/
5f28d2d7
SK		 2799 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2800 "Done %s.\n", __func__);
1da177e4
LT		 2801 }
2802
2803 return rval;
2804}
2805
2806/*
2807 * qla2x00_get_id_list
2808 *
2809 * Input:
2810 * ha = adapter block pointer.
2811 *
2812 * Returns:
2813 * qla2x00 local function return status code.
2814 *
2815 * Context:
2816 * Kernel context.
2817 */
2818int
7b867cf7 2819qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
1da177e4
LT		 2820 uint16_t *entries)
2821{
2822 int rval;
2823 mbx_cmd_t mc;
2824 mbx_cmd_t *mcp = &mc;
2825
5f28d2d7
SK		 2826 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2827 "Entered %s.\n", __func__);
1da177e4
LT		 2828
2829 if (id_list == NULL)
2830 return QLA_FUNCTION_FAILED;
2831
2832 mcp->mb[0] = MBC_GET_ID_LIST;
1c7c6357 2833 mcp->out_mb = MBX_0;
7b867cf7 2834 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 2835 mcp->mb[2] = MSW(id_list_dma);
2836 mcp->mb[3] = LSW(id_list_dma);
2837 mcp->mb[6] = MSW(MSD(id_list_dma));
2838 mcp->mb[7] = LSW(MSD(id_list_dma));
247ec457 2839 mcp->mb[8] = 0;
7b867cf7 2840 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2841 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
1c7c6357
AV		 2842 } else {
2843 mcp->mb[1] = MSW(id_list_dma);
2844 mcp->mb[2] = LSW(id_list_dma);
2845 mcp->mb[3] = MSW(MSD(id_list_dma));
2846 mcp->mb[6] = LSW(MSD(id_list_dma));
2847 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2848 }
1da177e4 2849 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2850 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2851 mcp->flags = 0;
7b867cf7 2852 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2853
2854 if (rval != QLA_SUCCESS) {
2855 /*EMPTY*/
7c3df132 2856 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
1da177e4
LT		 2857 } else {
2858 *entries = mcp->mb[1];
5f28d2d7
SK		 2859 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2860 "Done %s.\n", __func__);
1da177e4
LT		 2861 }
2862
2863 return rval;
2864}
2865
2866/*
2867 * qla2x00_get_resource_cnts
2868 * Get current firmware resource counts.
2869 *
2870 * Input:
2871 * ha = adapter block pointer.
2872 *
2873 * Returns:
2874 * qla2x00 local function return status code.
2875 *
2876 * Context:
2877 * Kernel context.
2878 */
2879int
03e8c680 2880qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
1da177e4 2881{
03e8c680 2882 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2883 int rval;
2884 mbx_cmd_t mc;
2885 mbx_cmd_t *mcp = &mc;
2886
5f28d2d7
SK		 2887 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2888 "Entered %s.\n", __func__);
1da177e4
LT		 2889
2890 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2891 mcp->out_mb = MBX_0;
4d0ea247 2892 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
ecc89f25
JC		 2893 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
2894 IS_QLA27XX(ha) || IS_QLA28XX(ha))
f3a0a77e 2895 mcp->in_mb |= MBX_12;
b93480e3 2896 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2897 mcp->flags = 0;
7b867cf7 2898 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2899
2900 if (rval != QLA_SUCCESS) {
2901 /*EMPTY*/
7c3df132
SK		 2902 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2903 "Failed mb[0]=%x.\n", mcp->mb[0]);
1da177e4 2904 } else {
5f28d2d7 2905 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
7c3df132
SK		 2906 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2907 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2908 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2909 mcp->mb[11], mcp->mb[12]);
1da177e4 2910
03e8c680
QT		 2911 ha->orig_fw_tgt_xcb_count = mcp->mb[1];
2912 ha->cur_fw_tgt_xcb_count = mcp->mb[2];
2913 ha->cur_fw_xcb_count = mcp->mb[3];
2914 ha->orig_fw_xcb_count = mcp->mb[6];
2915 ha->cur_fw_iocb_count = mcp->mb[7];
2916 ha->orig_fw_iocb_count = mcp->mb[10];
2917 if (ha->flags.npiv_supported)
2918 ha->max_npiv_vports = mcp->mb[11];
ecc89f25
JC		 2919 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
2920 IS_QLA28XX(ha))
03e8c680 2921 ha->fw_max_fcf_count = mcp->mb[12];
1da177e4
LT		 2922 }
2923
2924 return (rval);
2925}
2926
1da177e4
LT		 2927/*
2928 * qla2x00_get_fcal_position_map
2929 * Get FCAL (LILP) position map using mailbox command
2930 *
2931 * Input:
2932 * ha = adapter state pointer.
2933 * pos_map = buffer pointer (can be NULL).
2934 *
2935 * Returns:
2936 * qla2x00 local function return status code.
2937 *
2938 * Context:
2939 * Kernel context.
2940 */
2941int
7b867cf7 2942qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
1da177e4
LT		 2943{
2944 int rval;
2945 mbx_cmd_t mc;
2946 mbx_cmd_t *mcp = &mc;
2947 char *pmap;
2948 dma_addr_t pmap_dma;
7b867cf7 2949 struct qla_hw_data *ha = vha->hw;
1da177e4 2950
5f28d2d7
SK		 2951 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
2952 "Entered %s.\n", __func__);
7c3df132 2953
08eb7f45 2954 pmap = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
1da177e4 2955 if (pmap == NULL) {
7c3df132
SK		 2956 ql_log(ql_log_warn, vha, 0x1080,
2957 "Memory alloc failed.\n");
1da177e4
LT		 2958 return QLA_MEMORY_ALLOC_FAILED;
2959 }
1da177e4
LT		 2960
2961 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2962 mcp->mb[2] = MSW(pmap_dma);
2963 mcp->mb[3] = LSW(pmap_dma);
2964 mcp->mb[6] = MSW(MSD(pmap_dma));
2965 mcp->mb[7] = LSW(MSD(pmap_dma));
2966 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2967 mcp->in_mb = MBX_1|MBX_0;
2968 mcp->buf_size = FCAL_MAP_SIZE;
2969 mcp->flags = MBX_DMA_IN;
2970 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 2971 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2972
2973 if (rval == QLA_SUCCESS) {
5f28d2d7 2974 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
7c3df132
SK		 2975 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2976 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2977 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2978 pmap, pmap[0] + 1);
1da177e4
LT		 2979
2980 if (pos_map)
2981 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2982 }
2983 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2984
2985 if (rval != QLA_SUCCESS) {
7c3df132 2986 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
1da177e4 2987 } else {
5f28d2d7
SK		 2988 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
2989 "Done %s.\n", __func__);
1da177e4
LT		 2990 }
2991
2992 return rval;
2993}
392e2f65 2994
2995/*
2996 * qla2x00_get_link_status
2997 *
2998 * Input:
2999 * ha = adapter block pointer.
3000 * loop_id = device loop ID.
3001 * ret_buf = pointer to link status return buffer.
3002 *
3003 * Returns:
3004 * 0 = success.
3005 * BIT_0 = mem alloc error.
3006 * BIT_1 = mailbox error.
3007 */
3008int
7b867cf7 3009qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
43ef0580 3010 struct link_statistics *stats, dma_addr_t stats_dma)
392e2f65 3011{
3012 int rval;
3013 mbx_cmd_t mc;
3014 mbx_cmd_t *mcp = &mc;
c6dc9905
JC		 3015 uint32_t *iter = (void *)stats;
3016 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter);
7b867cf7 3017 struct qla_hw_data *ha = vha->hw;
392e2f65 3018
5f28d2d7
SK		 3019 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
3020 "Entered %s.\n", __func__);
392e2f65 3021
392e2f65 3022 mcp->mb[0] = MBC_GET_LINK_STATUS;
c6dc9905
JC		 3023 mcp->mb[2] = MSW(LSD(stats_dma));
3024 mcp->mb[3] = LSW(LSD(stats_dma));
43ef0580
AV		 3025 mcp->mb[6] = MSW(MSD(stats_dma));
3026 mcp->mb[7] = LSW(MSD(stats_dma));
392e2f65 3027 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
3028 mcp->in_mb = MBX_0;
e428924c 3029 if (IS_FWI2_CAPABLE(ha)) {
392e2f65 3030 mcp->mb[1] = loop_id;
3031 mcp->mb[4] = 0;
3032 mcp->mb[10] = 0;
3033 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
3034 mcp->in_mb |= MBX_1;
3035 } else if (HAS_EXTENDED_IDS(ha)) {
3036 mcp->mb[1] = loop_id;
3037 mcp->mb[10] = 0;
3038 mcp->out_mb |= MBX_10|MBX_1;
3039 } else {
3040 mcp->mb[1] = loop_id << 8;
3041 mcp->out_mb |= MBX_1;
3042 }
b93480e3 3043 mcp->tov = MBX_TOV_SECONDS;
392e2f65 3044 mcp->flags = IOCTL_CMD;
7b867cf7 3045 rval = qla2x00_mailbox_command(vha, mcp);
392e2f65 3046
3047 if (rval == QLA_SUCCESS) {
3048 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3049 ql_dbg(ql_dbg_mbx, vha, 0x1085,
3050 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
43ef0580 3051 rval = QLA_FUNCTION_FAILED;
392e2f65 3052 } else {
c6dc9905 3053 /* Re-endianize - firmware data is le32. */
5f28d2d7
SK		 3054 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
3055 "Done %s.\n", __func__);
da08ef5c
JC		 3056 for ( ; dwords--; iter++)
3057 le32_to_cpus(iter);
392e2f65 3058 }
3059 } else {
3060 /* Failed. */
7c3df132 3061 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
392e2f65 3062 }
3063
392e2f65 3064 return rval;
3065}
3066
3067int
7b867cf7 3068qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
15f30a57 3069 dma_addr_t stats_dma, uint16_t options)
1c7c6357
AV		 3070{
3071 int rval;
3072 mbx_cmd_t mc;
3073 mbx_cmd_t *mcp = &mc;
da08ef5c 3074 uint32_t *iter, dwords;
1c7c6357 3075
5f28d2d7
SK		 3076 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
3077 "Entered %s.\n", __func__);
1c7c6357 3078
15f30a57
QT		 3079 memset(&mc, 0, sizeof(mc));
3080 mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
3081 mc.mb[2] = MSW(stats_dma);
3082 mc.mb[3] = LSW(stats_dma);
3083 mc.mb[6] = MSW(MSD(stats_dma));
3084 mc.mb[7] = LSW(MSD(stats_dma));
3085 mc.mb[8] = sizeof(struct link_statistics) / 4;
3086 mc.mb[9] = cpu_to_le16(vha->vp_idx);
3087 mc.mb[10] = cpu_to_le16(options);
3088
3089 rval = qla24xx_send_mb_cmd(vha, &mc);
1c7c6357
AV		 3090
3091 if (rval == QLA_SUCCESS) {
3092 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3093 ql_dbg(ql_dbg_mbx, vha, 0x1089,
3094 "Failed mb[0]=%x.\n", mcp->mb[0]);
43ef0580 3095 rval = QLA_FUNCTION_FAILED;
1c7c6357 3096 } else {
5f28d2d7
SK		 3097 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
3098 "Done %s.\n", __func__);
c6dc9905 3099 /* Re-endianize - firmware data is le32. */
43ef0580 3100 dwords = sizeof(struct link_statistics) / 4;
da08ef5c
JC		 3101 iter = &stats->link_fail_cnt;
3102 for ( ; dwords--; iter++)
3103 le32_to_cpus(iter);
1c7c6357
AV		 3104 }
3105 } else {
3106 /* Failed. */
7c3df132 3107 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
1c7c6357
AV		 3108 }
3109
1c7c6357
AV		 3110 return rval;
3111}
1c7c6357
AV		 3112
3113int
2afa19a9 3114qla24xx_abort_command(srb_t *sp)
1c7c6357
AV		 3115{
3116 int rval;
1c7c6357
AV		 3117 unsigned long flags = 0;
3118
3119 struct abort_entry_24xx *abt;
3120 dma_addr_t abt_dma;
3121 uint32_t handle;
2afa19a9
AC		 3122 fc_port_t *fcport = sp->fcport;
3123 struct scsi_qla_host *vha = fcport->vha;
7b867cf7 3124 struct qla_hw_data *ha = vha->hw;
67c2e93a 3125 struct req_que *req = vha->req;
585def9b 3126 struct qla_qpair *qpair = sp->qpair;
1c7c6357 3127
5f28d2d7
SK		 3128 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
3129 "Entered %s.\n", __func__);
1c7c6357 3130
d7459527
MH		 3131 if (vha->flags.qpairs_available && sp->qpair)
3132 req = sp->qpair->req;
585def9b
QT		 3133 else
3134 return QLA_FUNCTION_FAILED;
d7459527 3135
4440e46d
AB		 3136 if (ql2xasynctmfenable)
3137 return qla24xx_async_abort_command(sp);
3138
585def9b 3139 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
8d93f550 3140 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 3141 if (req->outstanding_cmds[handle] == sp)
1c7c6357
AV		 3142 break;
3143 }
585def9b 3144 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
8d93f550 3145 if (handle == req->num_outstanding_cmds) {
1c7c6357
AV		 3146 /* Command not found. */
3147 return QLA_FUNCTION_FAILED;
3148 }
3149
08eb7f45 3150 abt = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
1c7c6357 3151 if (abt == NULL) {
7c3df132
SK		 3152 ql_log(ql_log_warn, vha, 0x108d,
3153 "Failed to allocate abort IOCB.\n");
1c7c6357
AV		 3154 return QLA_MEMORY_ALLOC_FAILED;
3155 }
1c7c6357
AV		 3156
3157 abt->entry_type = ABORT_IOCB_TYPE;
3158 abt->entry_count = 1;
2afa19a9 3159 abt->handle = MAKE_HANDLE(req->id, abt->handle);
1c7c6357 3160 abt->nport_handle = cpu_to_le16(fcport->loop_id);
a74ec14f 3161 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
1c7c6357
AV		 3162 abt->port_id[0] = fcport->d_id.b.al_pa;
3163 abt->port_id[1] = fcport->d_id.b.area;
3164 abt->port_id[2] = fcport->d_id.b.domain;
c6d39e23 3165 abt->vp_index = fcport->vha->vp_idx;
73208dfd
AC		 3166
3167 abt->req_que_no = cpu_to_le16(req->id);
3168
7b867cf7 3169 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
1c7c6357 3170 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3171 ql_dbg(ql_dbg_mbx, vha, 0x108e,
3172 "Failed to issue IOCB (%x).\n", rval);
1c7c6357 3173 } else if (abt->entry_status != 0) {
7c3df132
SK		 3174 ql_dbg(ql_dbg_mbx, vha, 0x108f,
3175 "Failed to complete IOCB -- error status (%x).\n",
3176 abt->entry_status);
1c7c6357 3177 rval = QLA_FUNCTION_FAILED;
ad950360 3178 } else if (abt->nport_handle != cpu_to_le16(0)) {
7c3df132
SK		 3179 ql_dbg(ql_dbg_mbx, vha, 0x1090,
3180 "Failed to complete IOCB -- completion status (%x).\n",
3181 le16_to_cpu(abt->nport_handle));
f934c9d0
CD		 3182 if (abt->nport_handle == CS_IOCB_ERROR)
3183 rval = QLA_FUNCTION_PARAMETER_ERROR;
3184 else
3185 rval = QLA_FUNCTION_FAILED;
1c7c6357 3186 } else {
5f28d2d7
SK		 3187 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
3188 "Done %s.\n", __func__);
1c7c6357
AV		 3189 }
3190
3191 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
3192
3193 return rval;
3194}
3195
3196struct tsk_mgmt_cmd {
3197 union {
3198 struct tsk_mgmt_entry tsk;
3199 struct sts_entry_24xx sts;
3200 } p;
3201};
3202
523ec773
AV		 3203static int
3204__qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
9cb78c16 3205 uint64_t l, int tag)
1c7c6357 3206{
523ec773 3207 int rval, rval2;
1c7c6357 3208 struct tsk_mgmt_cmd *tsk;
9ca1d01f 3209 struct sts_entry_24xx *sts;
1c7c6357 3210 dma_addr_t tsk_dma;
7b867cf7
AC		 3211 scsi_qla_host_t *vha;
3212 struct qla_hw_data *ha;
73208dfd 3213 struct req_que *req;
d7459527 3214 struct qla_qpair *qpair;
1c7c6357 3215
7b867cf7
AC		 3216 vha = fcport->vha;
3217 ha = vha->hw;
2afa19a9 3218 req = vha->req;
7c3df132 3219
5f28d2d7
SK		 3220 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
3221 "Entered %s.\n", __func__);
7c3df132 3222
d7459527
MH		 3223 if (vha->vp_idx && vha->qpair) {
3224 /* NPIV port */
3225 qpair = vha->qpair;
d7459527 3226 req = qpair->req;
d7459527
MH		 3227 }
3228
08eb7f45 3229 tsk = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
1c7c6357 3230 if (tsk == NULL) {
7c3df132
SK		 3231 ql_log(ql_log_warn, vha, 0x1093,
3232 "Failed to allocate task management IOCB.\n");
1c7c6357
AV		 3233 return QLA_MEMORY_ALLOC_FAILED;
3234 }
1c7c6357
AV		 3235
3236 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
3237 tsk->p.tsk.entry_count = 1;
2afa19a9 3238 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
1c7c6357 3239 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
00a537b8 3240 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
523ec773 3241 tsk->p.tsk.control_flags = cpu_to_le32(type);
1c7c6357
AV		 3242 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
3243 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
3244 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
c6d39e23 3245 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
523ec773
AV		 3246 if (type == TCF_LUN_RESET) {
3247 int_to_scsilun(l, &tsk->p.tsk.lun);
3248 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
3249 sizeof(tsk->p.tsk.lun));
3250 }
2c3dfe3f 3251
9ca1d01f 3252 sts = &tsk->p.sts;
7b867cf7 3253 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
1c7c6357 3254 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3255 ql_dbg(ql_dbg_mbx, vha, 0x1094,
3256 "Failed to issue %s reset IOCB (%x).\n", name, rval);
9ca1d01f 3257 } else if (sts->entry_status != 0) {
7c3df132
SK		 3258 ql_dbg(ql_dbg_mbx, vha, 0x1095,
3259 "Failed to complete IOCB -- error status (%x).\n",
3260 sts->entry_status);
1c7c6357 3261 rval = QLA_FUNCTION_FAILED;
ad950360 3262 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3263 ql_dbg(ql_dbg_mbx, vha, 0x1096,
3264 "Failed to complete IOCB -- completion status (%x).\n",
3265 le16_to_cpu(sts->comp_status));
9ca1d01f 3266 rval = QLA_FUNCTION_FAILED;
97dec564
AV		 3267 } else if (le16_to_cpu(sts->scsi_status) &
3268 SS_RESPONSE_INFO_LEN_VALID) {
3269 if (le32_to_cpu(sts->rsp_data_len) < 4) {
5f28d2d7 3270 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
7c3df132
SK		 3271 "Ignoring inconsistent data length -- not enough "
3272 "response info (%d).\n",
3273 le32_to_cpu(sts->rsp_data_len));
97dec564 3274 } else if (sts->data[3]) {
7c3df132
SK		 3275 ql_dbg(ql_dbg_mbx, vha, 0x1098,
3276 "Failed to complete IOCB -- response (%x).\n",
3277 sts->data[3]);
97dec564
AV		 3278 rval = QLA_FUNCTION_FAILED;
3279 }
1c7c6357
AV		 3280 }
3281
3282 /* Issue marker IOCB. */
9eb9c6dc 3283 rval2 = qla2x00_marker(vha, ha->base_qpair, fcport->loop_id, l,
58e2753c 3284 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
523ec773 3285 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3286 ql_dbg(ql_dbg_mbx, vha, 0x1099,
3287 "Failed to issue marker IOCB (%x).\n", rval2);
1c7c6357 3288 } else {
5f28d2d7
SK		 3289 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
3290 "Done %s.\n", __func__);
1c7c6357
AV		 3291 }
3292
7b867cf7 3293 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
1c7c6357
AV		 3294
3295 return rval;
3296}
3297
523ec773 3298int
9cb78c16 3299qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3300{
3822263e
MI		 3301 struct qla_hw_data *ha = fcport->vha->hw;
3302
3303 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3304 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
3305
2afa19a9 3306 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
523ec773
AV		 3307}
3308
3309int
9cb78c16 3310qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3311{
3822263e
MI		 3312 struct qla_hw_data *ha = fcport->vha->hw;
3313
3314 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3315 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
3316
2afa19a9 3317 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
523ec773
AV		 3318}
3319
1c7c6357 3320int
7b867cf7 3321qla2x00_system_error(scsi_qla_host_t *vha)
1c7c6357
AV		 3322{
3323 int rval;
3324 mbx_cmd_t mc;
3325 mbx_cmd_t *mcp = &mc;
7b867cf7 3326 struct qla_hw_data *ha = vha->hw;
1c7c6357 3327
68af0811 3328 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 3329 return QLA_FUNCTION_FAILED;
3330
5f28d2d7
SK		 3331 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
3332 "Entered %s.\n", __func__);
1c7c6357
AV		 3333
3334 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
3335 mcp->out_mb = MBX_0;
3336 mcp->in_mb = MBX_0;
3337 mcp->tov = 5;
3338 mcp->flags = 0;
7b867cf7 3339 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3340
3341 if (rval != QLA_SUCCESS) {
7c3df132 3342 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
1c7c6357 3343 } else {
5f28d2d7
SK		 3344 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
3345 "Done %s.\n", __func__);
1c7c6357
AV		 3346 }
3347
3348 return rval;
3349}
3350
db64e930
JC		 3351int
3352qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
3353{
3354 int rval;
3355 mbx_cmd_t mc;
3356 mbx_cmd_t *mcp = &mc;
3357
f299c7c2 3358 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
ecc89f25 3359 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
db64e930
JC		 3360 return QLA_FUNCTION_FAILED;
3361
3362 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
3363 "Entered %s.\n", __func__);
3364
3365 mcp->mb[0] = MBC_WRITE_SERDES;
3366 mcp->mb[1] = addr;
064135e0
AV		 3367 if (IS_QLA2031(vha->hw))
3368 mcp->mb[2] = data & 0xff;
3369 else
3370 mcp->mb[2] = data;
3371
db64e930
JC		 3372 mcp->mb[3] = 0;
3373 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
3374 mcp->in_mb = MBX_0;
3375 mcp->tov = MBX_TOV_SECONDS;
3376 mcp->flags = 0;
3377 rval = qla2x00_mailbox_command(vha, mcp);
3378
3379 if (rval != QLA_SUCCESS) {
3380 ql_dbg(ql_dbg_mbx, vha, 0x1183,
3381 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3382 } else {
3383 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
3384 "Done %s.\n", __func__);
3385 }
3386
3387 return rval;
3388}
3389
3390int
3391qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
3392{
3393 int rval;
3394 mbx_cmd_t mc;
3395 mbx_cmd_t *mcp = &mc;
3396
f299c7c2 3397 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
ecc89f25 3398 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
db64e930
JC		 3399 return QLA_FUNCTION_FAILED;
3400
3401 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
3402 "Entered %s.\n", __func__);
3403
3404 mcp->mb[0] = MBC_READ_SERDES;
3405 mcp->mb[1] = addr;
3406 mcp->mb[3] = 0;
3407 mcp->out_mb = MBX_3|MBX_1|MBX_0;
3408 mcp->in_mb = MBX_1|MBX_0;
3409 mcp->tov = MBX_TOV_SECONDS;
3410 mcp->flags = 0;
3411 rval = qla2x00_mailbox_command(vha, mcp);
3412
064135e0
AV		 3413 if (IS_QLA2031(vha->hw))
3414 *data = mcp->mb[1] & 0xff;
3415 else
3416 *data = mcp->mb[1];
db64e930
JC		 3417
3418 if (rval != QLA_SUCCESS) {
3419 ql_dbg(ql_dbg_mbx, vha, 0x1186,
3420 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3421 } else {
3422 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
3423 "Done %s.\n", __func__);
3424 }
3425
3426 return rval;
3427}
3428
e8887c51
JC		 3429int
3430qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
3431{
3432 int rval;
3433 mbx_cmd_t mc;
3434 mbx_cmd_t *mcp = &mc;
3435
3436 if (!IS_QLA8044(vha->hw))
3437 return QLA_FUNCTION_FAILED;
3438
83548fe2 3439 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x11a0,
e8887c51
JC		 3440 "Entered %s.\n", __func__);
3441
3442 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3443 mcp->mb[1] = HCS_WRITE_SERDES;
3444 mcp->mb[3] = LSW(addr);
3445 mcp->mb[4] = MSW(addr);
3446 mcp->mb[5] = LSW(data);
3447 mcp->mb[6] = MSW(data);
3448 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
3449 mcp->in_mb = MBX_0;
3450 mcp->tov = MBX_TOV_SECONDS;
3451 mcp->flags = 0;
3452 rval = qla2x00_mailbox_command(vha, mcp);
3453
3454 if (rval != QLA_SUCCESS) {
83548fe2 3455 ql_dbg(ql_dbg_mbx, vha, 0x11a1,
e8887c51
JC		 3456 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3457 } else {
3458 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
3459 "Done %s.\n", __func__);
3460 }
3461
3462 return rval;
3463}
3464
3465int
3466qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
3467{
3468 int rval;
3469 mbx_cmd_t mc;
3470 mbx_cmd_t *mcp = &mc;
3471
3472 if (!IS_QLA8044(vha->hw))
3473 return QLA_FUNCTION_FAILED;
3474
3475 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
3476 "Entered %s.\n", __func__);
3477
3478 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3479 mcp->mb[1] = HCS_READ_SERDES;
3480 mcp->mb[3] = LSW(addr);
3481 mcp->mb[4] = MSW(addr);
3482 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
3483 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3484 mcp->tov = MBX_TOV_SECONDS;
3485 mcp->flags = 0;
3486 rval = qla2x00_mailbox_command(vha, mcp);
3487
3488 *data = mcp->mb[2] << 16 | mcp->mb[1];
3489
3490 if (rval != QLA_SUCCESS) {
3491 ql_dbg(ql_dbg_mbx, vha, 0x118a,
3492 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3493 } else {
3494 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
3495 "Done %s.\n", __func__);
3496 }
3497
3498 return rval;
3499}
3500
1c7c6357
AV		 3501/**
3502 * qla2x00_set_serdes_params() -
2db6228d 3503 * @vha: HA context
807eb907
BVA		 3504 * @sw_em_1g: serial link options
3505 * @sw_em_2g: serial link options
3506 * @sw_em_4g: serial link options
1c7c6357
AV		 3507 *
3508 * Returns
3509 */
3510int
7b867cf7 3511qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
1c7c6357
AV		 3512 uint16_t sw_em_2g, uint16_t sw_em_4g)
3513{
3514 int rval;
3515 mbx_cmd_t mc;
3516 mbx_cmd_t *mcp = &mc;
3517
5f28d2d7
SK		 3518 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
3519 "Entered %s.\n", __func__);
1c7c6357
AV		 3520
3521 mcp->mb[0] = MBC_SERDES_PARAMS;
3522 mcp->mb[1] = BIT_0;
fdbc6833 3523 mcp->mb[2] = sw_em_1g | BIT_15;
3524 mcp->mb[3] = sw_em_2g | BIT_15;
3525 mcp->mb[4] = sw_em_4g | BIT_15;
1c7c6357
AV		 3526 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3527 mcp->in_mb = MBX_0;
b93480e3 3528 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 3529 mcp->flags = 0;
7b867cf7 3530 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3531
3532 if (rval != QLA_SUCCESS) {
3533 /*EMPTY*/
7c3df132
SK		 3534 ql_dbg(ql_dbg_mbx, vha, 0x109f,
3535 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357
AV		 3536 } else {
3537 /*EMPTY*/
5f28d2d7
SK		 3538 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
3539 "Done %s.\n", __func__);
1c7c6357
AV		 3540 }
3541
3542 return rval;
3543}
f6ef3b18
AV		 3544
3545int
7b867cf7 3546qla2x00_stop_firmware(scsi_qla_host_t *vha)
f6ef3b18
AV		 3547{
3548 int rval;
3549 mbx_cmd_t mc;
3550 mbx_cmd_t *mcp = &mc;
3551
7b867cf7 3552 if (!IS_FWI2_CAPABLE(vha->hw))
f6ef3b18
AV		 3553 return QLA_FUNCTION_FAILED;
3554
5f28d2d7
SK		 3555 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
3556 "Entered %s.\n", __func__);
f6ef3b18
AV		 3557
3558 mcp->mb[0] = MBC_STOP_FIRMWARE;
4ba988db
AV		 3559 mcp->mb[1] = 0;
3560 mcp->out_mb = MBX_1|MBX_0;
f6ef3b18
AV		 3561 mcp->in_mb = MBX_0;
3562 mcp->tov = 5;
3563 mcp->flags = 0;
7b867cf7 3564 rval = qla2x00_mailbox_command(vha, mcp);
f6ef3b18
AV		 3565
3566 if (rval != QLA_SUCCESS) {
7c3df132 3567 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
b469a7cb
AV		 3568 if (mcp->mb[0] == MBS_INVALID_COMMAND)
3569 rval = QLA_INVALID_COMMAND;
f6ef3b18 3570 } else {
5f28d2d7
SK		 3571 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
3572 "Done %s.\n", __func__);
f6ef3b18
AV		 3573 }
3574
3575 return rval;
3576}
a7a167bf
AV		 3577
3578int
7b867cf7 3579qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
a7a167bf
AV		 3580 uint16_t buffers)
3581{
3582 int rval;
3583 mbx_cmd_t mc;
3584 mbx_cmd_t *mcp = &mc;
3585
5f28d2d7
SK		 3586 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
3587 "Entered %s.\n", __func__);
7c3df132 3588
7b867cf7 3589 if (!IS_FWI2_CAPABLE(vha->hw))
a7a167bf
AV		 3590 return QLA_FUNCTION_FAILED;
3591
85880801
AV		 3592 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3593 return QLA_FUNCTION_FAILED;
3594
a7a167bf 3595 mcp->mb[0] = MBC_TRACE_CONTROL;
00b6bd25
AV		 3596 mcp->mb[1] = TC_EFT_ENABLE;
3597 mcp->mb[2] = LSW(eft_dma);
3598 mcp->mb[3] = MSW(eft_dma);
3599 mcp->mb[4] = LSW(MSD(eft_dma));
3600 mcp->mb[5] = MSW(MSD(eft_dma));
3601 mcp->mb[6] = buffers;
3602 mcp->mb[7] = TC_AEN_DISABLE;
3603 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
a7a167bf 3604 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3605 mcp->tov = MBX_TOV_SECONDS;
a7a167bf 3606 mcp->flags = 0;
7b867cf7 3607 rval = qla2x00_mailbox_command(vha, mcp);
00b6bd25 3608 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3609 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
3610 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3611 rval, mcp->mb[0], mcp->mb[1]);
00b6bd25 3612 } else {
5f28d2d7
SK		 3613 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
3614 "Done %s.\n", __func__);
00b6bd25
AV		 3615 }
3616
3617 return rval;
3618}
a7a167bf 3619
00b6bd25 3620int
7b867cf7 3621qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
00b6bd25
AV		 3622{
3623 int rval;
3624 mbx_cmd_t mc;
3625 mbx_cmd_t *mcp = &mc;
3626
5f28d2d7
SK		 3627 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3628 "Entered %s.\n", __func__);
7c3df132 3629
7b867cf7 3630 if (!IS_FWI2_CAPABLE(vha->hw))
00b6bd25
AV		 3631 return QLA_FUNCTION_FAILED;
3632
85880801
AV		 3633 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3634 return QLA_FUNCTION_FAILED;
3635
00b6bd25
AV		 3636 mcp->mb[0] = MBC_TRACE_CONTROL;
3637 mcp->mb[1] = TC_EFT_DISABLE;
3638 mcp->out_mb = MBX_1|MBX_0;
3639 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3640 mcp->tov = MBX_TOV_SECONDS;
00b6bd25 3641 mcp->flags = 0;
7b867cf7 3642 rval = qla2x00_mailbox_command(vha, mcp);
a7a167bf 3643 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3644 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3645 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3646 rval, mcp->mb[0], mcp->mb[1]);
a7a167bf 3647 } else {
5f28d2d7
SK		 3648 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3649 "Done %s.\n", __func__);
a7a167bf
AV		 3650 }
3651
3652 return rval;
3653}
3654
df613b96 3655int
7b867cf7 3656qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
df613b96
AV		 3657 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3658{
3659 int rval;
3660 mbx_cmd_t mc;
3661 mbx_cmd_t *mcp = &mc;
3662
5f28d2d7
SK		 3663 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3664 "Entered %s.\n", __func__);
7c3df132 3665
6246b8a1 3666 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
ecc89f25
JC		 3667 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
3668 !IS_QLA28XX(vha->hw))
df613b96
AV		 3669 return QLA_FUNCTION_FAILED;
3670
85880801
AV		 3671 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3672 return QLA_FUNCTION_FAILED;
3673
df613b96
AV		 3674 mcp->mb[0] = MBC_TRACE_CONTROL;
3675 mcp->mb[1] = TC_FCE_ENABLE;
3676 mcp->mb[2] = LSW(fce_dma);
3677 mcp->mb[3] = MSW(fce_dma);
3678 mcp->mb[4] = LSW(MSD(fce_dma));
3679 mcp->mb[5] = MSW(MSD(fce_dma));
3680 mcp->mb[6] = buffers;
3681 mcp->mb[7] = TC_AEN_DISABLE;
3682 mcp->mb[8] = 0;
3683 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3684 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3685 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3686 MBX_1|MBX_0;
3687 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 3688 mcp->tov = MBX_TOV_SECONDS;
df613b96 3689 mcp->flags = 0;
7b867cf7 3690 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3691 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3692 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3693 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3694 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3695 } else {
5f28d2d7
SK		 3696 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3697 "Done %s.\n", __func__);
df613b96
AV		 3698
3699 if (mb)
3700 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3701 if (dwords)
fa0926df 3702 *dwords = buffers;
df613b96
AV		 3703 }
3704
3705 return rval;
3706}
3707
3708int
7b867cf7 3709qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
df613b96
AV		 3710{
3711 int rval;
3712 mbx_cmd_t mc;
3713 mbx_cmd_t *mcp = &mc;
3714
5f28d2d7
SK		 3715 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3716 "Entered %s.\n", __func__);
7c3df132 3717
7b867cf7 3718 if (!IS_FWI2_CAPABLE(vha->hw))
df613b96
AV		 3719 return QLA_FUNCTION_FAILED;
3720
85880801
AV		 3721 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3722 return QLA_FUNCTION_FAILED;
3723
df613b96
AV		 3724 mcp->mb[0] = MBC_TRACE_CONTROL;
3725 mcp->mb[1] = TC_FCE_DISABLE;
3726 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3727 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3728 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3729 MBX_1|MBX_0;
b93480e3 3730 mcp->tov = MBX_TOV_SECONDS;
df613b96 3731 mcp->flags = 0;
7b867cf7 3732 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3733 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3734 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3735 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3736 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3737 } else {
5f28d2d7
SK		 3738 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3739 "Done %s.\n", __func__);
df613b96
AV		 3740
3741 if (wr)
3742 *wr = (uint64_t) mcp->mb[5] << 48 |
3743 (uint64_t) mcp->mb[4] << 32 |
3744 (uint64_t) mcp->mb[3] << 16 |
3745 (uint64_t) mcp->mb[2];
3746 if (rd)
3747 *rd = (uint64_t) mcp->mb[9] << 48 |
3748 (uint64_t) mcp->mb[8] << 32 |
3749 (uint64_t) mcp->mb[7] << 16 |
3750 (uint64_t) mcp->mb[6];
3751 }
3752
3753 return rval;
3754}
3755
6e98016c
GM		 3756int
3757qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3758 uint16_t *port_speed, uint16_t *mb)
3759{
3760 int rval;
3761 mbx_cmd_t mc;
3762 mbx_cmd_t *mcp = &mc;
3763
5f28d2d7
SK		 3764 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3765 "Entered %s.\n", __func__);
7c3df132 3766
6e98016c
GM		 3767 if (!IS_IIDMA_CAPABLE(vha->hw))
3768 return QLA_FUNCTION_FAILED;
3769
6e98016c
GM		 3770 mcp->mb[0] = MBC_PORT_PARAMS;
3771 mcp->mb[1] = loop_id;
3772 mcp->mb[2] = mcp->mb[3] = 0;
3773 mcp->mb[9] = vha->vp_idx;
3774 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3775 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3776 mcp->tov = MBX_TOV_SECONDS;
3777 mcp->flags = 0;
3778 rval = qla2x00_mailbox_command(vha, mcp);
3779
3780 /* Return mailbox statuses. */
2a3192a3 3781 if (mb) {
6e98016c
GM		 3782 mb[0] = mcp->mb[0];
3783 mb[1] = mcp->mb[1];
3784 mb[3] = mcp->mb[3];
3785 }
3786
3787 if (rval != QLA_SUCCESS) {
7c3df132 3788 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
6e98016c 3789 } else {
5f28d2d7
SK		 3790 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3791 "Done %s.\n", __func__);
6e98016c
GM		 3792 if (port_speed)
3793 *port_speed = mcp->mb[3];
3794 }
3795
3796 return rval;
3797}
3798
d8b45213 3799int
7b867cf7 3800qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
d8b45213
AV		 3801 uint16_t port_speed, uint16_t *mb)
3802{
3803 int rval;
3804 mbx_cmd_t mc;
3805 mbx_cmd_t *mcp = &mc;
3806
5f28d2d7
SK		 3807 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3808 "Entered %s.\n", __func__);
7c3df132 3809
7b867cf7 3810 if (!IS_IIDMA_CAPABLE(vha->hw))
d8b45213
AV		 3811 return QLA_FUNCTION_FAILED;
3812
d8b45213
AV		 3813 mcp->mb[0] = MBC_PORT_PARAMS;
3814 mcp->mb[1] = loop_id;
3815 mcp->mb[2] = BIT_0;
2a3192a3 3816 mcp->mb[3] = port_speed & 0x3F;
1bb39548
HZ		 3817 mcp->mb[9] = vha->vp_idx;
3818 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3819 mcp->in_mb = MBX_3|MBX_1|MBX_0;
b93480e3 3820 mcp->tov = MBX_TOV_SECONDS;
d8b45213 3821 mcp->flags = 0;
7b867cf7 3822 rval = qla2x00_mailbox_command(vha, mcp);
d8b45213
AV		 3823
3824 /* Return mailbox statuses. */
2a3192a3 3825 if (mb) {
d8b45213
AV		 3826 mb[0] = mcp->mb[0];
3827 mb[1] = mcp->mb[1];
3828 mb[3] = mcp->mb[3];
d8b45213
AV		 3829 }
3830
3831 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 3832 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3833 "Failed=%x.\n", rval);
d8b45213 3834 } else {
5f28d2d7
SK		 3835 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3836 "Done %s.\n", __func__);
d8b45213
AV		 3837 }
3838
3839 return rval;
3840}
2c3dfe3f 3841
2c3dfe3f 3842void
7b867cf7 3843qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
2c3dfe3f
SJ		 3844 struct vp_rpt_id_entry_24xx *rptid_entry)
3845{
7b867cf7 3846 struct qla_hw_data *ha = vha->hw;
41dc529a 3847 scsi_qla_host_t *vp = NULL;
feafb7b1 3848 unsigned long flags;
4ac8d4ca 3849 int found;
482c9dc7 3850 port_id_t id;
9cd883f0 3851 struct fc_port *fcport;
2c3dfe3f 3852
5f28d2d7
SK		 3853 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3854 "Entered %s.\n", __func__);
7c3df132 3855
2c3dfe3f
SJ		 3856 if (rptid_entry->entry_status != 0)
3857 return;
2c3dfe3f 3858
482c9dc7
QT		 3859 id.b.domain = rptid_entry->port_id[2];
3860 id.b.area = rptid_entry->port_id[1];
3861 id.b.al_pa = rptid_entry->port_id[0];
3862 id.b.rsvd_1 = 0;
1763c1fd 3863 ha->flags.n2n_ae = 0;
482c9dc7 3864
2c3dfe3f 3865 if (rptid_entry->format == 0) {
41dc529a 3866 /* loop */
ec7193e2 3867 ql_dbg(ql_dbg_async, vha, 0x10b7,
7c3df132 3868 "Format 0 : Number of VPs setup %d, number of "
41dc529a
QT		 3869 "VPs acquired %d.\n", rptid_entry->vp_setup,
3870 rptid_entry->vp_acquired);
ec7193e2 3871 ql_dbg(ql_dbg_async, vha, 0x10b8,
7c3df132
SK		 3872 "Primary port id %02x%02x%02x.\n",
3873 rptid_entry->port_id[2], rptid_entry->port_id[1],
3874 rptid_entry->port_id[0]);
9cd883f0 3875 ha->current_topology = ISP_CFG_NL;
482c9dc7 3876 qlt_update_host_map(vha, id);
41dc529a 3877
2c3dfe3f 3878 } else if (rptid_entry->format == 1) {
41dc529a 3879 /* fabric */
ec7193e2 3880 ql_dbg(ql_dbg_async, vha, 0x10b9,
7c3df132 3881 "Format 1: VP[%d] enabled - status %d - with "
41dc529a
QT		 3882 "port id %02x%02x%02x.\n", rptid_entry->vp_idx,
3883 rptid_entry->vp_status,
2c3dfe3f 3884 rptid_entry->port_id[2], rptid_entry->port_id[1],
7c3df132 3885 rptid_entry->port_id[0]);
edd05de1
DG		 3886 ql_dbg(ql_dbg_async, vha, 0x5075,
3887 "Format 1: Remote WWPN %8phC.\n",
3888 rptid_entry->u.f1.port_name);
3889
3890 ql_dbg(ql_dbg_async, vha, 0x5075,
3891 "Format 1: WWPN %8phC.\n",
3892 vha->port_name);
3893
8777e431
QT		 3894 switch (rptid_entry->u.f1.flags & TOPO_MASK) {
3895 case TOPO_N2N:
3896 ha->current_topology = ISP_CFG_N;
3897 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
3898 fcport = qla2x00_find_fcport_by_wwpn(vha,
3899 rptid_entry->u.f1.port_name, 1);
3900 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
3901
3902 if (fcport) {
3903 fcport->plogi_nack_done_deadline = jiffies + HZ;
3904 fcport->dm_login_expire = jiffies + 3*HZ;
3905 fcport->scan_state = QLA_FCPORT_FOUND;
3906 switch (fcport->disc_state) {
3907 case DSC_DELETED:
3908 set_bit(RELOGIN_NEEDED,
3909 &vha->dpc_flags);
3910 break;
3911 case DSC_DELETE_PEND:
3912 break;
3913 default:
3914 qlt_schedule_sess_for_deletion(fcport);
3915 break;
3916 }
edd05de1 3917 } else {
8777e431
QT		 3918 id.b24 = 0;
3919 if (wwn_to_u64(vha->port_name) >
3920 wwn_to_u64(rptid_entry->u.f1.port_name)) {
3921 vha->d_id.b24 = 0;
3922 vha->d_id.b.al_pa = 1;
3923 ha->flags.n2n_bigger = 1;
3924
3925 id.b.al_pa = 2;
3926 ql_dbg(ql_dbg_async, vha, 0x5075,
3927 "Format 1: assign local id %x remote id %x\n",
3928 vha->d_id.b24, id.b24);
3929 } else {
3930 ql_dbg(ql_dbg_async, vha, 0x5075,
3931 "Format 1: Remote login - Waiting for WWPN %8phC.\n",
3932 rptid_entry->u.f1.port_name);
3933 ha->flags.n2n_bigger = 0;
3934 }
3935 qla24xx_post_newsess_work(vha, &id,
3936 rptid_entry->u.f1.port_name,
3937 rptid_entry->u.f1.node_name,
3938 NULL,
3939 FC4_TYPE_UNKNOWN);
edd05de1
DG		 3940 }
3941
8777e431
QT		 3942 /* if our portname is higher then initiate N2N login */
3943
edd05de1 3944 set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags);
1763c1fd 3945 ha->flags.n2n_ae = 1;
edd05de1 3946 return;
8777e431
QT		 3947 break;
3948 case TOPO_FL:
3949 ha->current_topology = ISP_CFG_FL;
3950 break;
3951 case TOPO_F:
3952 ha->current_topology = ISP_CFG_F;
3953 break;
3954 default:
3955 break;
edd05de1 3956 }
531a82d1 3957
9cd883f0
QT		 3958 ha->flags.gpsc_supported = 1;
3959 ha->current_topology = ISP_CFG_F;
969a6199 3960 /* buffer to buffer credit flag */
41dc529a
QT		 3961 vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0;
3962
3963 if (rptid_entry->vp_idx == 0) {
3964 if (rptid_entry->vp_status == VP_STAT_COMPL) {
3965 /* FA-WWN is only for physical port */
3966 if (qla_ini_mode_enabled(vha) &&
3967 ha->flags.fawwpn_enabled &&
3968 (rptid_entry->u.f1.flags &
fcc5b5cd 3969 BIT_6)) {
41dc529a
QT		 3970 memcpy(vha->port_name,
3971 rptid_entry->u.f1.port_name,
3972 WWN_SIZE);
3973 }
7c9c4766 3974
482c9dc7 3975 qlt_update_host_map(vha, id);
7c9c4766 3976 }
41dc529a 3977
41dc529a
QT		 3978 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
3979 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
3980 } else {
3981 if (rptid_entry->vp_status != VP_STAT_COMPL &&
3982 rptid_entry->vp_status != VP_STAT_ID_CHG) {
3983 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
3984 "Could not acquire ID for VP[%d].\n",
3985 rptid_entry->vp_idx);
3986 return;
4ac8d4ca 3987 }
feafb7b1 3988
41dc529a
QT		 3989 found = 0;
3990 spin_lock_irqsave(&ha->vport_slock, flags);
3991 list_for_each_entry(vp, &ha->vp_list, list) {
3992 if (rptid_entry->vp_idx == vp->vp_idx) {
3993 found = 1;
3994 break;
3995 }
3996 }
3997 spin_unlock_irqrestore(&ha->vport_slock, flags);
2c3dfe3f 3998
41dc529a
QT		 3999 if (!found)
4000 return;
2c3dfe3f 4001
482c9dc7 4002 qlt_update_host_map(vp, id);
2c3dfe3f 4003
41dc529a
QT		 4004 /*
4005 * Cannot configure here as we are still sitting on the
4006 * response queue. Handle it in dpc context.
4007 */
4008 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
4009 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
4010 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
4011 }
531a82d1 4012 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
7b867cf7 4013 qla2xxx_wake_dpc(vha);
41dc529a 4014 } else if (rptid_entry->format == 2) {
83548fe2 4015 ql_dbg(ql_dbg_async, vha, 0x505f,
41dc529a
QT		 4016 "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n",
4017 rptid_entry->port_id[2], rptid_entry->port_id[1],
4018 rptid_entry->port_id[0]);
4019
83548fe2 4020 ql_dbg(ql_dbg_async, vha, 0x5075,
41dc529a
QT		 4021 "N2N: Remote WWPN %8phC.\n",
4022 rptid_entry->u.f2.port_name);
4023
4024 /* N2N. direct connect */
9cd883f0
QT		 4025 ha->current_topology = ISP_CFG_N;
4026 ha->flags.rida_fmt2 = 1;
41dc529a
QT		 4027 vha->d_id.b.domain = rptid_entry->port_id[2];
4028 vha->d_id.b.area = rptid_entry->port_id[1];
4029 vha->d_id.b.al_pa = rptid_entry->port_id[0];
4030
1763c1fd 4031 ha->flags.n2n_ae = 1;
41dc529a
QT		 4032 spin_lock_irqsave(&ha->vport_slock, flags);
4033 qlt_update_vp_map(vha, SET_AL_PA);
4034 spin_unlock_irqrestore(&ha->vport_slock, flags);
9cd883f0
QT		 4035
4036 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4037 fcport->scan_state = QLA_FCPORT_SCAN;
4038 }
4039
4040 fcport = qla2x00_find_fcport_by_wwpn(vha,
4041 rptid_entry->u.f2.port_name, 1);
4042
4043 if (fcport) {
23dd98a6 4044 fcport->login_retry = vha->hw->login_retry_count;
9cd883f0
QT		 4045 fcport->plogi_nack_done_deadline = jiffies + HZ;
4046 fcport->scan_state = QLA_FCPORT_FOUND;
9cd883f0 4047 }
2c3dfe3f
SJ		 4048 }
4049}
4050
4051/*
4052 * qla24xx_modify_vp_config
4053 * Change VP configuration for vha
4054 *
4055 * Input:
4056 * vha = adapter block pointer.
4057 *
4058 * Returns:
4059 * qla2xxx local function return status code.
4060 *
4061 * Context:
4062 * Kernel context.
4063 */
4064int
4065qla24xx_modify_vp_config(scsi_qla_host_t *vha)
4066{
4067 int rval;
4068 struct vp_config_entry_24xx *vpmod;
4069 dma_addr_t vpmod_dma;
7b867cf7
AC		 4070 struct qla_hw_data *ha = vha->hw;
4071 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f
SJ		 4072
4073 /* This can be called by the parent */
2c3dfe3f 4074
5f28d2d7
SK		 4075 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
4076 "Entered %s.\n", __func__);
7c3df132 4077
08eb7f45 4078 vpmod = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
2c3dfe3f 4079 if (!vpmod) {
7c3df132
SK		 4080 ql_log(ql_log_warn, vha, 0x10bc,
4081 "Failed to allocate modify VP IOCB.\n");
2c3dfe3f
SJ		 4082 return QLA_MEMORY_ALLOC_FAILED;
4083 }
4084
2c3dfe3f
SJ		 4085 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
4086 vpmod->entry_count = 1;
4087 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
4088 vpmod->vp_count = 1;
4089 vpmod->vp_index1 = vha->vp_idx;
4090 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
2d70c103
NB		 4091
4092 qlt_modify_vp_config(vha, vpmod);
4093
2c3dfe3f
SJ		 4094 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
4095 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
4096 vpmod->entry_count = 1;
4097
7b867cf7 4098 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
2c3dfe3f 4099 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4100 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
4101 "Failed to issue VP config IOCB (%x).\n", rval);
2c3dfe3f 4102 } else if (vpmod->comp_status != 0) {
7c3df132
SK		 4103 ql_dbg(ql_dbg_mbx, vha, 0x10be,
4104 "Failed to complete IOCB -- error status (%x).\n",
4105 vpmod->comp_status);
2c3dfe3f 4106 rval = QLA_FUNCTION_FAILED;
ad950360 4107 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 4108 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
4109 "Failed to complete IOCB -- completion status (%x).\n",
4110 le16_to_cpu(vpmod->comp_status));
2c3dfe3f
SJ		 4111 rval = QLA_FUNCTION_FAILED;
4112 } else {
4113 /* EMPTY */
5f28d2d7
SK		 4114 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
4115 "Done %s.\n", __func__);
2c3dfe3f
SJ		 4116 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
4117 }
7b867cf7 4118 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
2c3dfe3f
SJ		 4119
4120 return rval;
4121}
4122
2c3dfe3f
SJ		 4123/*
4124 * qla2x00_send_change_request
4125 * Receive or disable RSCN request from fabric controller
4126 *
4127 * Input:
4128 * ha = adapter block pointer
4129 * format = registration format:
4130 * 0 - Reserved
4131 * 1 - Fabric detected registration
4132 * 2 - N_port detected registration
4133 * 3 - Full registration
4134 * FF - clear registration
4135 * vp_idx = Virtual port index
4136 *
4137 * Returns:
4138 * qla2x00 local function return status code.
4139 *
4140 * Context:
4141 * Kernel Context
4142 */
4143
4144int
7b867cf7 4145qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
2c3dfe3f
SJ		 4146 uint16_t vp_idx)
4147{
4148 int rval;
4149 mbx_cmd_t mc;
4150 mbx_cmd_t *mcp = &mc;
4151
5f28d2d7
SK		 4152 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
4153 "Entered %s.\n", __func__);
7c3df132 4154
2c3dfe3f
SJ		 4155 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
4156 mcp->mb[1] = format;
4157 mcp->mb[9] = vp_idx;
4158 mcp->out_mb = MBX_9|MBX_1|MBX_0;
4159 mcp->in_mb = MBX_0|MBX_1;
4160 mcp->tov = MBX_TOV_SECONDS;
4161 mcp->flags = 0;
7b867cf7 4162 rval = qla2x00_mailbox_command(vha, mcp);
2c3dfe3f
SJ		 4163
4164 if (rval == QLA_SUCCESS) {
4165 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
4166 rval = BIT_1;
4167 }
4168 } else
4169 rval = BIT_1;
4170
4171 return rval;
4172}
338c9161
AV		 4173
4174int
7b867cf7 4175qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
338c9161
AV		 4176 uint32_t size)
4177{
4178 int rval;
4179 mbx_cmd_t mc;
4180 mbx_cmd_t *mcp = &mc;
4181
5f28d2d7
SK		 4182 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
4183 "Entered %s.\n", __func__);
338c9161 4184
7b867cf7 4185 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 4186 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
4187 mcp->mb[8] = MSW(addr);
4188 mcp->out_mb = MBX_8|MBX_0;
4189 } else {
4190 mcp->mb[0] = MBC_DUMP_RISC_RAM;
4191 mcp->out_mb = MBX_0;
4192 }
4193 mcp->mb[1] = LSW(addr);
4194 mcp->mb[2] = MSW(req_dma);
4195 mcp->mb[3] = LSW(req_dma);
4196 mcp->mb[6] = MSW(MSD(req_dma));
4197 mcp->mb[7] = LSW(MSD(req_dma));
4198 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
7b867cf7 4199 if (IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 4200 mcp->mb[4] = MSW(size);
4201 mcp->mb[5] = LSW(size);
4202 mcp->out_mb |= MBX_5|MBX_4;
4203 } else {
4204 mcp->mb[4] = LSW(size);
4205 mcp->out_mb |= MBX_4;
4206 }
4207
4208 mcp->in_mb = MBX_0;
b93480e3 4209 mcp->tov = MBX_TOV_SECONDS;
338c9161 4210 mcp->flags = 0;
7b867cf7 4211 rval = qla2x00_mailbox_command(vha, mcp);
338c9161
AV		 4212
4213 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4214 ql_dbg(ql_dbg_mbx, vha, 0x1008,
4215 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
338c9161 4216 } else {
5f28d2d7
SK		 4217 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
4218 "Done %s.\n", __func__);
338c9161
AV		 4219 }
4220
4221 return rval;
4222}
4d4df193
HK		 4223/* 84XX Support **************************************************************/
4224
4225struct cs84xx_mgmt_cmd {
4226 union {
4227 struct verify_chip_entry_84xx req;
4228 struct verify_chip_rsp_84xx rsp;
4229 } p;
4230};
4231
4232int
7b867cf7 4233qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4d4df193
HK		 4234{
4235 int rval, retry;
4236 struct cs84xx_mgmt_cmd *mn;
4237 dma_addr_t mn_dma;
4238 uint16_t options;
4239 unsigned long flags;
7b867cf7 4240 struct qla_hw_data *ha = vha->hw;
4d4df193 4241
5f28d2d7
SK		 4242 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
4243 "Entered %s.\n", __func__);
4d4df193
HK		 4244
4245 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
4246 if (mn == NULL) {
4d4df193
HK		 4247 return QLA_MEMORY_ALLOC_FAILED;
4248 }
4249
4250 /* Force Update? */
4251 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
4252 /* Diagnostic firmware? */
4253 /* options |= MENLO_DIAG_FW; */
4254 /* We update the firmware with only one data sequence. */
4255 options |= VCO_END_OF_DATA;
4256
4d4df193 4257 do {
c1ec1f1b 4258 retry = 0;
4d4df193
HK		 4259 memset(mn, 0, sizeof(*mn));
4260 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
4261 mn->p.req.entry_count = 1;
4262 mn->p.req.options = cpu_to_le16(options);
4263
7c3df132
SK		 4264 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
4265 "Dump of Verify Request.\n");
4266 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
f8f97b0c 4267 mn, sizeof(*mn));
4d4df193 4268
7b867cf7 4269 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4d4df193 4270 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4271 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
4272 "Failed to issue verify IOCB (%x).\n", rval);
4d4df193
HK		 4273 goto verify_done;
4274 }
4275
7c3df132
SK		 4276 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
4277 "Dump of Verify Response.\n");
4278 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
f8f97b0c 4279 mn, sizeof(*mn));
4d4df193
HK		 4280
4281 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
4282 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
4283 le16_to_cpu(mn->p.rsp.failure_code) : 0;
5f28d2d7 4284 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
7c3df132 4285 "cs=%x fc=%x.\n", status[0], status[1]);
4d4df193
HK		 4286
4287 if (status[0] != CS_COMPLETE) {
4288 rval = QLA_FUNCTION_FAILED;
4289 if (!(options & VCO_DONT_UPDATE_FW)) {
7c3df132
SK		 4290 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
4291 "Firmware update failed. Retrying "
4292 "without update firmware.\n");
4d4df193
HK		 4293 options |= VCO_DONT_UPDATE_FW;
4294 options &= ~VCO_FORCE_UPDATE;
4295 retry = 1;
4296 }
4297 } else {
5f28d2d7 4298 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
7c3df132
SK		 4299 "Firmware updated to %x.\n",
4300 le32_to_cpu(mn->p.rsp.fw_ver));
4d4df193
HK		 4301
4302 /* NOTE: we only update OP firmware. */
4303 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
4304 ha->cs84xx->op_fw_version =
4305 le32_to_cpu(mn->p.rsp.fw_ver);
4306 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
4307 flags);
4308 }
4309 } while (retry);
4310
4311verify_done:
4312 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
4313
4314 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 4315 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
4316 "Failed=%x.\n", rval);
4d4df193 4317 } else {
5f28d2d7
SK		 4318 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
4319 "Done %s.\n", __func__);
4d4df193
HK		 4320 }
4321
4322 return rval;
4323}
73208dfd
AC		 4324
4325int
618a7523 4326qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
73208dfd
AC		 4327{
4328 int rval;
4329 unsigned long flags;
4330 mbx_cmd_t mc;
4331 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4332 struct qla_hw_data *ha = vha->hw;
4333
45235022
QT		 4334 if (!ha->flags.fw_started)
4335 return QLA_SUCCESS;
4336
5f28d2d7
SK		 4337 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
4338 "Entered %s.\n", __func__);
7c3df132 4339
7c6300e3
JC		 4340 if (IS_SHADOW_REG_CAPABLE(ha))
4341 req->options |= BIT_13;
4342
73208dfd 4343 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4344 mcp->mb[1] = req->options;
73208dfd
AC		 4345 mcp->mb[2] = MSW(LSD(req->dma));
4346 mcp->mb[3] = LSW(LSD(req->dma));
4347 mcp->mb[6] = MSW(MSD(req->dma));
4348 mcp->mb[7] = LSW(MSD(req->dma));
4349 mcp->mb[5] = req->length;
4350 if (req->rsp)
4351 mcp->mb[10] = req->rsp->id;
4352 mcp->mb[12] = req->qos;
4353 mcp->mb[11] = req->vp_idx;
4354 mcp->mb[13] = req->rid;
ecc89f25 4355 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
6246b8a1 4356 mcp->mb[15] = 0;
73208dfd 4357
73208dfd
AC		 4358 mcp->mb[4] = req->id;
4359 /* que in ptr index */
4360 mcp->mb[8] = 0;
4361 /* que out ptr index */
7c6300e3 4362 mcp->mb[9] = *req->out_ptr = 0;
73208dfd
AC		 4363 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
4364 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4365 mcp->in_mb = MBX_0;
4366 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4367 mcp->tov = MBX_TOV_SECONDS * 2;
4368
ecc89f25
JC		 4369 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
4370 IS_QLA28XX(ha))
6246b8a1 4371 mcp->in_mb |= MBX_1;
ecc89f25 4372 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
6246b8a1
GM		 4373 mcp->out_mb |= MBX_15;
4374 /* debug q create issue in SR-IOV */
4375 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4376 }
73208dfd
AC		 4377
4378 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4379 if (!(req->options & BIT_0)) {
da9b1d5c 4380 WRT_REG_DWORD(req->req_q_in, 0);
ecc89f25 4381 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
da9b1d5c 4382 WRT_REG_DWORD(req->req_q_out, 0);
73208dfd
AC		 4383 }
4384 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4385
17d98630 4386 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4387 if (rval != QLA_SUCCESS) {
4388 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
4389 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4390 } else {
5f28d2d7
SK		 4391 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
4392 "Done %s.\n", __func__);
7c3df132
SK		 4393 }
4394
73208dfd
AC		 4395 return rval;
4396}
4397
4398int
618a7523 4399qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
73208dfd
AC		 4400{
4401 int rval;
4402 unsigned long flags;
4403 mbx_cmd_t mc;
4404 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4405 struct qla_hw_data *ha = vha->hw;
4406
45235022
QT		 4407 if (!ha->flags.fw_started)
4408 return QLA_SUCCESS;
4409
5f28d2d7
SK		 4410 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
4411 "Entered %s.\n", __func__);
7c3df132 4412
7c6300e3
JC		 4413 if (IS_SHADOW_REG_CAPABLE(ha))
4414 rsp->options |= BIT_13;
4415
73208dfd 4416 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4417 mcp->mb[1] = rsp->options;
73208dfd
AC		 4418 mcp->mb[2] = MSW(LSD(rsp->dma));
4419 mcp->mb[3] = LSW(LSD(rsp->dma));
4420 mcp->mb[6] = MSW(MSD(rsp->dma));
4421 mcp->mb[7] = LSW(MSD(rsp->dma));
4422 mcp->mb[5] = rsp->length;
444786d7 4423 mcp->mb[14] = rsp->msix->entry;
73208dfd 4424 mcp->mb[13] = rsp->rid;
ecc89f25 4425 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
6246b8a1 4426 mcp->mb[15] = 0;
73208dfd 4427
73208dfd
AC		 4428 mcp->mb[4] = rsp->id;
4429 /* que in ptr index */
7c6300e3 4430 mcp->mb[8] = *rsp->in_ptr = 0;
73208dfd
AC		 4431 /* que out ptr index */
4432 mcp->mb[9] = 0;
2afa19a9 4433 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
73208dfd
AC		 4434 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4435 mcp->in_mb = MBX_0;
4436 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4437 mcp->tov = MBX_TOV_SECONDS * 2;
4438
4439 if (IS_QLA81XX(ha)) {
4440 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
4441 mcp->in_mb |= MBX_1;
ecc89f25 4442 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
6246b8a1
GM		 4443 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
4444 mcp->in_mb |= MBX_1;
4445 /* debug q create issue in SR-IOV */
4446 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4447 }
73208dfd
AC		 4448
4449 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4450 if (!(rsp->options & BIT_0)) {
da9b1d5c 4451 WRT_REG_DWORD(rsp->rsp_q_out, 0);
ecc89f25 4452 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
da9b1d5c 4453 WRT_REG_DWORD(rsp->rsp_q_in, 0);
73208dfd
AC		 4454 }
4455
4456 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4457
17d98630 4458 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4459 if (rval != QLA_SUCCESS) {
4460 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
4461 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4462 } else {
5f28d2d7
SK		 4463 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
4464 "Done %s.\n", __func__);
7c3df132
SK		 4465 }
4466
73208dfd
AC		 4467 return rval;
4468}
4469
8a659571
AV		 4470int
4471qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
4472{
4473 int rval;
4474 mbx_cmd_t mc;
4475 mbx_cmd_t *mcp = &mc;
4476
5f28d2d7
SK		 4477 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
4478 "Entered %s.\n", __func__);
8a659571
AV		 4479
4480 mcp->mb[0] = MBC_IDC_ACK;
4481 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4482 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4483 mcp->in_mb = MBX_0;
4484 mcp->tov = MBX_TOV_SECONDS;
4485 mcp->flags = 0;
4486 rval = qla2x00_mailbox_command(vha, mcp);
4487
4488 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4489 ql_dbg(ql_dbg_mbx, vha, 0x10da,
4490 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
8a659571 4491 } else {
5f28d2d7
SK		 4492 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
4493 "Done %s.\n", __func__);
8a659571
AV		 4494 }
4495
4496 return rval;
4497}
1d2874de
JC		 4498
4499int
4500qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
4501{
4502 int rval;
4503 mbx_cmd_t mc;
4504 mbx_cmd_t *mcp = &mc;
4505
5f28d2d7
SK		 4506 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
4507 "Entered %s.\n", __func__);
7c3df132 4508
f73cb695 4509 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
ecc89f25 4510 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
1d2874de
JC		 4511 return QLA_FUNCTION_FAILED;
4512
1d2874de
JC		 4513 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4514 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
4515 mcp->out_mb = MBX_1|MBX_0;
4516 mcp->in_mb = MBX_1|MBX_0;
4517 mcp->tov = MBX_TOV_SECONDS;
4518 mcp->flags = 0;
4519 rval = qla2x00_mailbox_command(vha, mcp);
4520
4521 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4522 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
4523 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4524 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4525 } else {
5f28d2d7
SK		 4526 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
4527 "Done %s.\n", __func__);
1d2874de
JC		 4528 *sector_size = mcp->mb[1];
4529 }
4530
4531 return rval;
4532}
4533
4534int
4535qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
4536{
4537 int rval;
4538 mbx_cmd_t mc;
4539 mbx_cmd_t *mcp = &mc;
4540
f73cb695 4541 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
ecc89f25 4542 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
1d2874de
JC		 4543 return QLA_FUNCTION_FAILED;
4544
5f28d2d7
SK		 4545 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
4546 "Entered %s.\n", __func__);
1d2874de
JC		 4547
4548 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4549 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
4550 FAC_OPT_CMD_WRITE_PROTECT;
4551 mcp->out_mb = MBX_1|MBX_0;
4552 mcp->in_mb = MBX_1|MBX_0;
4553 mcp->tov = MBX_TOV_SECONDS;
4554 mcp->flags = 0;
4555 rval = qla2x00_mailbox_command(vha, mcp);
4556
4557 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4558 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
4559 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4560 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4561 } else {
5f28d2d7
SK		 4562 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
4563 "Done %s.\n", __func__);
1d2874de
JC		 4564 }
4565
4566 return rval;
4567}
4568
4569int
4570qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
4571{
4572 int rval;
4573 mbx_cmd_t mc;
4574 mbx_cmd_t *mcp = &mc;
4575
f73cb695 4576 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
ecc89f25 4577 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
1d2874de
JC		 4578 return QLA_FUNCTION_FAILED;
4579
5f28d2d7
SK		 4580 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4581 "Entered %s.\n", __func__);
1d2874de
JC		 4582
4583 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4584 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
4585 mcp->mb[2] = LSW(start);
4586 mcp->mb[3] = MSW(start);
4587 mcp->mb[4] = LSW(finish);
4588 mcp->mb[5] = MSW(finish);
4589 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4590 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4591 mcp->tov = MBX_TOV_SECONDS;
4592 mcp->flags = 0;
4593 rval = qla2x00_mailbox_command(vha, mcp);
4594
4595 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4596 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4597 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4598 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1d2874de 4599 } else {
5f28d2d7
SK		 4600 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4601 "Done %s.\n", __func__);
1d2874de
JC		 4602 }
4603
4604 return rval;
4605}
6e181be5 4606
3f006ac3
MH		 4607int
4608qla81xx_fac_semaphore_access(scsi_qla_host_t *vha, int lock)
4609{
4610 int rval = QLA_SUCCESS;
4611 mbx_cmd_t mc;
4612 mbx_cmd_t *mcp = &mc;
4613 struct qla_hw_data *ha = vha->hw;
4614
4615 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
4616 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
4617 return rval;
4618
4619 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4620 "Entered %s.\n", __func__);
4621
4622 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4623 mcp->mb[1] = (lock ? FAC_OPT_CMD_LOCK_SEMAPHORE :
4624 FAC_OPT_CMD_UNLOCK_SEMAPHORE);
4625 mcp->out_mb = MBX_1|MBX_0;
4626 mcp->in_mb = MBX_1|MBX_0;
4627 mcp->tov = MBX_TOV_SECONDS;
4628 mcp->flags = 0;
4629 rval = qla2x00_mailbox_command(vha, mcp);
4630
4631 if (rval != QLA_SUCCESS) {
4632 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4633 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4634 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4635 } else {
4636 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4637 "Done %s.\n", __func__);
4638 }
4639
4640 return rval;
4641}
4642
6e181be5
LC		 4643int
4644qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
4645{
4646 int rval = 0;
4647 mbx_cmd_t mc;
4648 mbx_cmd_t *mcp = &mc;
4649
5f28d2d7
SK		 4650 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
4651 "Entered %s.\n", __func__);
6e181be5
LC		 4652
4653 mcp->mb[0] = MBC_RESTART_MPI_FW;
4654 mcp->out_mb = MBX_0;
4655 mcp->in_mb = MBX_0|MBX_1;
4656 mcp->tov = MBX_TOV_SECONDS;
4657 mcp->flags = 0;
4658 rval = qla2x00_mailbox_command(vha, mcp);
4659
4660 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4661 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
4662 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4663 rval, mcp->mb[0], mcp->mb[1]);
6e181be5 4664 } else {
5f28d2d7
SK		 4665 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
4666 "Done %s.\n", __func__);
6e181be5
LC		 4667 }
4668
4669 return rval;
4670}
ad0ecd61 4671
c46e65c7
JC		 4672int
4673qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4674{
4675 int rval;
4676 mbx_cmd_t mc;
4677 mbx_cmd_t *mcp = &mc;
4678 int i;
4679 int len;
4680 uint16_t *str;
4681 struct qla_hw_data *ha = vha->hw;
4682
4683 if (!IS_P3P_TYPE(ha))
4684 return QLA_FUNCTION_FAILED;
4685
4686 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4687 "Entered %s.\n", __func__);
4688
4689 str = (void *)version;
4690 len = strlen(version);
4691
4692 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4693 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4694 mcp->out_mb = MBX_1|MBX_0;
4695 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4696 mcp->mb[i] = cpu_to_le16p(str);
4697 mcp->out_mb |= 1<<i;
4698 }
4699 for (; i < 16; i++) {
4700 mcp->mb[i] = 0;
4701 mcp->out_mb |= 1<<i;
4702 }
4703 mcp->in_mb = MBX_1|MBX_0;
4704 mcp->tov = MBX_TOV_SECONDS;
4705 mcp->flags = 0;
4706 rval = qla2x00_mailbox_command(vha, mcp);
4707
4708 if (rval != QLA_SUCCESS) {
4709 ql_dbg(ql_dbg_mbx, vha, 0x117c,
4710 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4711 } else {
4712 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
4713 "Done %s.\n", __func__);
4714 }
4715
4716 return rval;
4717}
4718
4719int
4720qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4721{
4722 int rval;
4723 mbx_cmd_t mc;
4724 mbx_cmd_t *mcp = &mc;
4725 int len;
4726 uint16_t dwlen;
4727 uint8_t *str;
4728 dma_addr_t str_dma;
4729 struct qla_hw_data *ha = vha->hw;
4730
4731 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4732 IS_P3P_TYPE(ha))
4733 return QLA_FUNCTION_FAILED;
4734
4735 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4736 "Entered %s.\n", __func__);
4737
4738 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4739 if (!str) {
4740 ql_log(ql_log_warn, vha, 0x117f,
4741 "Failed to allocate driver version param.\n");
4742 return QLA_MEMORY_ALLOC_FAILED;
4743 }
4744
4745 memcpy(str, "\x7\x3\x11\x0", 4);
4746 dwlen = str[0];
4747 len = dwlen * 4 - 4;
4748 memset(str + 4, 0, len);
4749 if (len > strlen(version))
4750 len = strlen(version);
4751 memcpy(str + 4, version, len);
4752
4753 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4754 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4755 mcp->mb[2] = MSW(LSD(str_dma));
4756 mcp->mb[3] = LSW(LSD(str_dma));
4757 mcp->mb[6] = MSW(MSD(str_dma));
4758 mcp->mb[7] = LSW(MSD(str_dma));
4759 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4760 mcp->in_mb = MBX_1|MBX_0;
4761 mcp->tov = MBX_TOV_SECONDS;
4762 mcp->flags = 0;
4763 rval = qla2x00_mailbox_command(vha, mcp);
4764
4765 if (rval != QLA_SUCCESS) {
4766 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4767 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4768 } else {
4769 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4770 "Done %s.\n", __func__);
4771 }
4772
4773 dma_pool_free(ha->s_dma_pool, str, str_dma);
4774
4775 return rval;
4776}
4777
edd05de1
DG		 4778int
4779qla24xx_get_port_login_templ(scsi_qla_host_t *vha, dma_addr_t buf_dma,
4780 void *buf, uint16_t bufsiz)
4781{
4782 int rval, i;
4783 mbx_cmd_t mc;
4784 mbx_cmd_t *mcp = &mc;
4785 uint32_t *bp;
4786
4787 if (!IS_FWI2_CAPABLE(vha->hw))
4788 return QLA_FUNCTION_FAILED;
4789
4790 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4791 "Entered %s.\n", __func__);
4792
4793 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4794 mcp->mb[1] = RNID_TYPE_PORT_LOGIN << 8;
4795 mcp->mb[2] = MSW(buf_dma);
4796 mcp->mb[3] = LSW(buf_dma);
4797 mcp->mb[6] = MSW(MSD(buf_dma));
4798 mcp->mb[7] = LSW(MSD(buf_dma));
4799 mcp->mb[8] = bufsiz/4;
4800 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4801 mcp->in_mb = MBX_1|MBX_0;
4802 mcp->tov = MBX_TOV_SECONDS;
4803 mcp->flags = 0;
4804 rval = qla2x00_mailbox_command(vha, mcp);
4805
4806 if (rval != QLA_SUCCESS) {
4807 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4808 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4809 } else {
4810 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4811 "Done %s.\n", __func__);
4812 bp = (uint32_t *) buf;
4813 for (i = 0; i < (bufsiz-4)/4; i++, bp++)
8777e431 4814 *bp = le32_to_cpu(*bp);
edd05de1
DG		 4815 }
4816
4817 return rval;
4818}
4819
fe52f6e1
JC		 4820static int
4821qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4822{
4823 int rval;
4824 mbx_cmd_t mc;
4825 mbx_cmd_t *mcp = &mc;
4826
4827 if (!IS_FWI2_CAPABLE(vha->hw))
4828 return QLA_FUNCTION_FAILED;
4829
4830 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4831 "Entered %s.\n", __func__);
4832
4833 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4834 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
4835 mcp->out_mb = MBX_1|MBX_0;
4836 mcp->in_mb = MBX_1|MBX_0;
4837 mcp->tov = MBX_TOV_SECONDS;
4838 mcp->flags = 0;
4839 rval = qla2x00_mailbox_command(vha, mcp);
4840 *temp = mcp->mb[1];
4841
4842 if (rval != QLA_SUCCESS) {
4843 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4844 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4845 } else {
4846 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4847 "Done %s.\n", __func__);
4848 }
4849
4850 return rval;
4851}
4852
ad0ecd61 4853int
6766df9e
JC		 4854qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4855 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4856{
4857 int rval;
4858 mbx_cmd_t mc;
4859 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4860 struct qla_hw_data *ha = vha->hw;
4861
5f28d2d7
SK		 4862 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
4863 "Entered %s.\n", __func__);
7c3df132 4864
6766df9e
JC		 4865 if (!IS_FWI2_CAPABLE(ha))
4866 return QLA_FUNCTION_FAILED;
ad0ecd61 4867
6766df9e
JC		 4868 if (len == 1)
4869 opt |= BIT_0;
4870
ad0ecd61
JC		 4871 mcp->mb[0] = MBC_READ_SFP;
4872 mcp->mb[1] = dev;
4873 mcp->mb[2] = MSW(sfp_dma);
4874 mcp->mb[3] = LSW(sfp_dma);
4875 mcp->mb[6] = MSW(MSD(sfp_dma));
4876 mcp->mb[7] = LSW(MSD(sfp_dma));
4877 mcp->mb[8] = len;
6766df9e 4878 mcp->mb[9] = off;
ad0ecd61
JC		 4879 mcp->mb[10] = opt;
4880 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1bff6cc8 4881 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4882 mcp->tov = MBX_TOV_SECONDS;
4883 mcp->flags = 0;
4884 rval = qla2x00_mailbox_command(vha, mcp);
4885
4886 if (opt & BIT_0)
6766df9e 4887 *sfp = mcp->mb[1];
ad0ecd61
JC		 4888
4889 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4890 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4891 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2a3192a3 4892 if (mcp->mb[0] == MBS_COMMAND_ERROR && mcp->mb[1] == 0x22) {
e4e3a2ce
QT		 4893 /* sfp is not there */
4894 rval = QLA_INTERFACE_ERROR;
2a3192a3 4895 }
ad0ecd61 4896 } else {
5f28d2d7
SK		 4897 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4898 "Done %s.\n", __func__);
ad0ecd61
JC		 4899 }
4900
4901 return rval;
4902}
4903
4904int
6766df9e
JC		 4905qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4906 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4907{
4908 int rval;
4909 mbx_cmd_t mc;
4910 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4911 struct qla_hw_data *ha = vha->hw;
4912
5f28d2d7
SK		 4913 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
4914 "Entered %s.\n", __func__);
7c3df132 4915
6766df9e
JC		 4916 if (!IS_FWI2_CAPABLE(ha))
4917 return QLA_FUNCTION_FAILED;
ad0ecd61 4918
6766df9e
JC		 4919 if (len == 1)
4920 opt |= BIT_0;
4921
ad0ecd61 4922 if (opt & BIT_0)
6766df9e 4923 len = *sfp;
ad0ecd61
JC		 4924
4925 mcp->mb[0] = MBC_WRITE_SFP;
4926 mcp->mb[1] = dev;
4927 mcp->mb[2] = MSW(sfp_dma);
4928 mcp->mb[3] = LSW(sfp_dma);
4929 mcp->mb[6] = MSW(MSD(sfp_dma));
4930 mcp->mb[7] = LSW(MSD(sfp_dma));
4931 mcp->mb[8] = len;
6766df9e 4932 mcp->mb[9] = off;
ad0ecd61
JC		 4933 mcp->mb[10] = opt;
4934 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6766df9e 4935 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4936 mcp->tov = MBX_TOV_SECONDS;
4937 mcp->flags = 0;
4938 rval = qla2x00_mailbox_command(vha, mcp);
4939
4940 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4941 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
4942 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 4943 } else {
5f28d2d7
SK		 4944 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
4945 "Done %s.\n", __func__);
ad0ecd61
JC		 4946 }
4947
4948 return rval;
4949}
ce0423f4
AV		 4950
4951int
4952qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
4953 uint16_t size_in_bytes, uint16_t *actual_size)
4954{
4955 int rval;
4956 mbx_cmd_t mc;
4957 mbx_cmd_t *mcp = &mc;
4958
5f28d2d7
SK		 4959 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
4960 "Entered %s.\n", __func__);
7c3df132 4961
6246b8a1 4962 if (!IS_CNA_CAPABLE(vha->hw))
ce0423f4
AV		 4963 return QLA_FUNCTION_FAILED;
4964
ce0423f4
AV		 4965 mcp->mb[0] = MBC_GET_XGMAC_STATS;
4966 mcp->mb[2] = MSW(stats_dma);
4967 mcp->mb[3] = LSW(stats_dma);
4968 mcp->mb[6] = MSW(MSD(stats_dma));
4969 mcp->mb[7] = LSW(MSD(stats_dma));
4970 mcp->mb[8] = size_in_bytes >> 2;
4971 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
4972 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4973 mcp->tov = MBX_TOV_SECONDS;
4974 mcp->flags = 0;
4975 rval = qla2x00_mailbox_command(vha, mcp);
4976
4977 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4978 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
4979 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4980 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
ce0423f4 4981 } else {
5f28d2d7
SK		 4982 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
4983 "Done %s.\n", __func__);
7c3df132 4984
ce0423f4
AV		 4985
4986 *actual_size = mcp->mb[2] << 2;
4987 }
4988
4989 return rval;
4990}
11bbc1d8
AV		 4991
4992int
4993qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
4994 uint16_t size)
4995{
4996 int rval;
4997 mbx_cmd_t mc;
4998 mbx_cmd_t *mcp = &mc;
4999
5f28d2d7
SK		 5000 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
5001 "Entered %s.\n", __func__);
7c3df132 5002
6246b8a1 5003 if (!IS_CNA_CAPABLE(vha->hw))
11bbc1d8
AV		 5004 return QLA_FUNCTION_FAILED;
5005
11bbc1d8
AV		 5006 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
5007 mcp->mb[1] = 0;
5008 mcp->mb[2] = MSW(tlv_dma);
5009 mcp->mb[3] = LSW(tlv_dma);
5010 mcp->mb[6] = MSW(MSD(tlv_dma));
5011 mcp->mb[7] = LSW(MSD(tlv_dma));
5012 mcp->mb[8] = size;
5013 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5014 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5015 mcp->tov = MBX_TOV_SECONDS;
5016 mcp->flags = 0;
5017 rval = qla2x00_mailbox_command(vha, mcp);
5018
5019 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5020 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
5021 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
5022 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
11bbc1d8 5023 } else {
5f28d2d7
SK		 5024 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
5025 "Done %s.\n", __func__);
11bbc1d8
AV		 5026 }
5027
5028 return rval;
5029}
18e7555a
AV		 5030
5031int
5032qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
5033{
5034 int rval;
5035 mbx_cmd_t mc;
5036 mbx_cmd_t *mcp = &mc;
5037
5f28d2d7
SK		 5038 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
5039 "Entered %s.\n", __func__);
7c3df132 5040
18e7555a
AV		 5041 if (!IS_FWI2_CAPABLE(vha->hw))
5042 return QLA_FUNCTION_FAILED;
5043
18e7555a
AV		 5044 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
5045 mcp->mb[1] = LSW(risc_addr);
5046 mcp->mb[8] = MSW(risc_addr);
5047 mcp->out_mb = MBX_8|MBX_1|MBX_0;
5048 mcp->in_mb = MBX_3|MBX_2|MBX_0;
5049 mcp->tov = 30;
5050 mcp->flags = 0;
5051 rval = qla2x00_mailbox_command(vha, mcp);
5052 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5053 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
5054 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 5055 } else {
5f28d2d7
SK		 5056 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
5057 "Done %s.\n", __func__);
18e7555a
AV		 5058 *data = mcp->mb[3] << 16 | mcp->mb[2];
5059 }
5060
5061 return rval;
5062}
5063
9a069e19 5064int
a9083016
GM		 5065qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
5066 uint16_t *mresp)
9a069e19
GM		 5067{
5068 int rval;
5069 mbx_cmd_t mc;
5070 mbx_cmd_t *mcp = &mc;
9a069e19 5071
5f28d2d7
SK		 5072 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
5073 "Entered %s.\n", __func__);
9a069e19
GM		 5074
5075 memset(mcp->mb, 0 , sizeof(mcp->mb));
5076 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
5077 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
5078
5079 /* transfer count */
5080 mcp->mb[10] = LSW(mreq->transfer_size);
5081 mcp->mb[11] = MSW(mreq->transfer_size);
5082
5083 /* send data address */
5084 mcp->mb[14] = LSW(mreq->send_dma);
5085 mcp->mb[15] = MSW(mreq->send_dma);
5086 mcp->mb[20] = LSW(MSD(mreq->send_dma));
5087 mcp->mb[21] = MSW(MSD(mreq->send_dma));
5088
25985edc 5089 /* receive data address */
9a069e19
GM		 5090 mcp->mb[16] = LSW(mreq->rcv_dma);
5091 mcp->mb[17] = MSW(mreq->rcv_dma);
5092 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
5093 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
5094
5095 /* Iteration count */
1b98b421
JC		 5096 mcp->mb[18] = LSW(mreq->iteration_count);
5097 mcp->mb[19] = MSW(mreq->iteration_count);
9a069e19
GM		 5098
5099 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
5100 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 5101 if (IS_CNA_CAPABLE(vha->hw))
9a069e19
GM		 5102 mcp->out_mb |= MBX_2;
5103 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
5104
5105 mcp->buf_size = mreq->transfer_size;
5106 mcp->tov = MBX_TOV_SECONDS;
5107 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5108
5109 rval = qla2x00_mailbox_command(vha, mcp);
5110
5111 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5112 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
5113 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
5114 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
5115 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
9a069e19 5116 } else {
5f28d2d7
SK		 5117 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
5118 "Done %s.\n", __func__);
9a069e19
GM		 5119 }
5120
5121 /* Copy mailbox information */
5122 memcpy( mresp, mcp->mb, 64);
9a069e19
GM		 5123 return rval;
5124}
5125
5126int
a9083016
GM		 5127qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
5128 uint16_t *mresp)
9a069e19
GM		 5129{
5130 int rval;
5131 mbx_cmd_t mc;
5132 mbx_cmd_t *mcp = &mc;
5133 struct qla_hw_data *ha = vha->hw;
5134
5f28d2d7
SK		 5135 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
5136 "Entered %s.\n", __func__);
9a069e19
GM		 5137
5138 memset(mcp->mb, 0 , sizeof(mcp->mb));
5139 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
1d634965
JC		 5140 /* BIT_6 specifies 64bit address */
5141 mcp->mb[1] = mreq->options | BIT_15 | BIT_6;
6246b8a1 5142 if (IS_CNA_CAPABLE(ha)) {
a9083016
GM		 5143 mcp->mb[2] = vha->fcoe_fcf_idx;
5144 }
9a069e19
GM		 5145 mcp->mb[16] = LSW(mreq->rcv_dma);
5146 mcp->mb[17] = MSW(mreq->rcv_dma);
5147 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
5148 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
5149
5150 mcp->mb[10] = LSW(mreq->transfer_size);
5151
5152 mcp->mb[14] = LSW(mreq->send_dma);
5153 mcp->mb[15] = MSW(mreq->send_dma);
5154 mcp->mb[20] = LSW(MSD(mreq->send_dma));
5155 mcp->mb[21] = MSW(MSD(mreq->send_dma));
5156
5157 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
5158 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 5159 if (IS_CNA_CAPABLE(ha))
9a069e19
GM		 5160 mcp->out_mb |= MBX_2;
5161
5162 mcp->in_mb = MBX_0;
6246b8a1
GM		 5163 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
5164 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19 5165 mcp->in_mb |= MBX_1;
6246b8a1 5166 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19
GM		 5167 mcp->in_mb |= MBX_3;
5168
5169 mcp->tov = MBX_TOV_SECONDS;
5170 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5171 mcp->buf_size = mreq->transfer_size;
5172
5173 rval = qla2x00_mailbox_command(vha, mcp);
5174
5175 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5176 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
5177 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5178 rval, mcp->mb[0], mcp->mb[1]);
9a069e19 5179 } else {
5f28d2d7
SK		 5180 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
5181 "Done %s.\n", __func__);
9a069e19
GM		 5182 }
5183
5184 /* Copy mailbox information */
6dbdda4d 5185 memcpy(mresp, mcp->mb, 64);
9a069e19
GM		 5186 return rval;
5187}
6dbdda4d 5188
9a069e19 5189int
7c3df132 5190qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
9a069e19
GM		 5191{
5192 int rval;
5193 mbx_cmd_t mc;
5194 mbx_cmd_t *mcp = &mc;
5195
5f28d2d7 5196 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
7c3df132 5197 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
9a069e19
GM		 5198
5199 mcp->mb[0] = MBC_ISP84XX_RESET;
5200 mcp->mb[1] = enable_diagnostic;
5201 mcp->out_mb = MBX_1|MBX_0;
5202 mcp->in_mb = MBX_1|MBX_0;
5203 mcp->tov = MBX_TOV_SECONDS;
5204 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
7c3df132 5205 rval = qla2x00_mailbox_command(vha, mcp);
9a069e19 5206
9a069e19 5207 if (rval != QLA_SUCCESS)
7c3df132 5208 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
9a069e19 5209 else
5f28d2d7
SK		 5210 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
5211 "Done %s.\n", __func__);
9a069e19
GM		 5212
5213 return rval;
5214}
5215
18e7555a
AV		 5216int
5217qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
5218{
5219 int rval;
5220 mbx_cmd_t mc;
5221 mbx_cmd_t *mcp = &mc;
5222
5f28d2d7
SK		 5223 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
5224 "Entered %s.\n", __func__);
7c3df132 5225
18e7555a 5226 if (!IS_FWI2_CAPABLE(vha->hw))
6c452a45 5227 return QLA_FUNCTION_FAILED;
18e7555a 5228
18e7555a
AV		 5229 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
5230 mcp->mb[1] = LSW(risc_addr);
5231 mcp->mb[2] = LSW(data);
5232 mcp->mb[3] = MSW(data);
5233 mcp->mb[8] = MSW(risc_addr);
5234 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
2a3192a3 5235 mcp->in_mb = MBX_1|MBX_0;
18e7555a
AV		 5236 mcp->tov = 30;
5237 mcp->flags = 0;
5238 rval = qla2x00_mailbox_command(vha, mcp);
5239 if (rval != QLA_SUCCESS) {
7c3df132 5240 ql_dbg(ql_dbg_mbx, vha, 0x1101,
2a3192a3
JC		 5241 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5242 rval, mcp->mb[0], mcp->mb[1]);
18e7555a 5243 } else {
5f28d2d7
SK		 5244 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
5245 "Done %s.\n", __func__);
18e7555a
AV		 5246 }
5247
5248 return rval;
5249}
3064ff39 5250
b1d46989
MI		 5251int
5252qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
5253{
5254 int rval;
5255 uint32_t stat, timer;
5256 uint16_t mb0 = 0;
5257 struct qla_hw_data *ha = vha->hw;
5258 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
5259
5260 rval = QLA_SUCCESS;
5261
5f28d2d7
SK		 5262 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
5263 "Entered %s.\n", __func__);
b1d46989
MI		 5264
5265 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
5266
5267 /* Write the MBC data to the registers */
5268 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
5269 WRT_REG_WORD(&reg->mailbox1, mb[0]);
5270 WRT_REG_WORD(&reg->mailbox2, mb[1]);
5271 WRT_REG_WORD(&reg->mailbox3, mb[2]);
5272 WRT_REG_WORD(&reg->mailbox4, mb[3]);
5273
5274 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
5275
5276 /* Poll for MBC interrupt */
5277 for (timer = 6000000; timer; timer--) {
5278 /* Check for pending interrupts. */
5279 stat = RD_REG_DWORD(&reg->host_status);
5280 if (stat & HSRX_RISC_INT) {
5281 stat &= 0xff;
5282
5283 if (stat == 0x1 || stat == 0x2 ||
5284 stat == 0x10 || stat == 0x11) {
5285 set_bit(MBX_INTERRUPT,
5286 &ha->mbx_cmd_flags);
5287 mb0 = RD_REG_WORD(&reg->mailbox0);
5288 WRT_REG_DWORD(&reg->hccr,
5289 HCCRX_CLR_RISC_INT);
5290 RD_REG_DWORD(&reg->hccr);
5291 break;
5292 }
5293 }
5294 udelay(5);
5295 }
5296
5297 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
5298 rval = mb0 & MBS_MASK;
5299 else
5300 rval = QLA_FUNCTION_FAILED;
5301
5302 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5303 ql_dbg(ql_dbg_mbx, vha, 0x1104,
5304 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
b1d46989 5305 } else {
5f28d2d7
SK		 5306 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
5307 "Done %s.\n", __func__);
b1d46989
MI		 5308 }
5309
5310 return rval;
5311}
6246b8a1 5312
4910b524
AG		 5313/* Set the specified data rate */
5314int
5315qla2x00_set_data_rate(scsi_qla_host_t *vha, uint16_t mode)
5316{
5317 int rval;
5318 mbx_cmd_t mc;
5319 mbx_cmd_t *mcp = &mc;
5320 struct qla_hw_data *ha = vha->hw;
5321 uint16_t val;
5322
5323 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
5324 "Entered %s speed:0x%x mode:0x%x.\n", __func__, ha->set_data_rate,
5325 mode);
5326
5327 if (!IS_FWI2_CAPABLE(ha))
5328 return QLA_FUNCTION_FAILED;
5329
5330 memset(mcp, 0, sizeof(*mcp));
5331 switch (ha->set_data_rate) {
5332 case PORT_SPEED_AUTO:
5333 case PORT_SPEED_4GB:
5334 case PORT_SPEED_8GB:
5335 case PORT_SPEED_16GB:
5336 case PORT_SPEED_32GB:
5337 val = ha->set_data_rate;
5338 break;
5339 default:
5340 ql_log(ql_log_warn, vha, 0x1199,
5341 "Unrecognized speed setting:%d. Setting Autoneg\n",
5342 ha->set_data_rate);
5343 val = ha->set_data_rate = PORT_SPEED_AUTO;
5344 break;
5345 }
5346
5347 mcp->mb[0] = MBC_DATA_RATE;
5348 mcp->mb[1] = mode;
5349 mcp->mb[2] = val;
5350
5351 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5352 mcp->in_mb = MBX_2|MBX_1|MBX_0;
ecc89f25 5353 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4910b524
AG		 5354 mcp->in_mb |= MBX_4|MBX_3;
5355 mcp->tov = MBX_TOV_SECONDS;
5356 mcp->flags = 0;
5357 rval = qla2x00_mailbox_command(vha, mcp);
5358 if (rval != QLA_SUCCESS) {
5359 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5360 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5361 } else {
5362 if (mcp->mb[1] != 0x7)
5363 ql_dbg(ql_dbg_mbx, vha, 0x1179,
5364 "Speed set:0x%x\n", mcp->mb[1]);
5365
5366 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5367 "Done %s.\n", __func__);
5368 }
5369
5370 return rval;
5371}
5372
3064ff39
MH		 5373int
5374qla2x00_get_data_rate(scsi_qla_host_t *vha)
5375{
5376 int rval;
5377 mbx_cmd_t mc;
5378 mbx_cmd_t *mcp = &mc;
5379 struct qla_hw_data *ha = vha->hw;
5380
5f28d2d7
SK		 5381 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
5382 "Entered %s.\n", __func__);
7c3df132 5383
3064ff39
MH		 5384 if (!IS_FWI2_CAPABLE(ha))
5385 return QLA_FUNCTION_FAILED;
5386
3064ff39 5387 mcp->mb[0] = MBC_DATA_RATE;
4910b524 5388 mcp->mb[1] = QLA_GET_DATA_RATE;
3064ff39
MH		 5389 mcp->out_mb = MBX_1|MBX_0;
5390 mcp->in_mb = MBX_2|MBX_1|MBX_0;
ecc89f25 5391 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
6246b8a1 5392 mcp->in_mb |= MBX_3;
3064ff39
MH		 5393 mcp->tov = MBX_TOV_SECONDS;
5394 mcp->flags = 0;
5395 rval = qla2x00_mailbox_command(vha, mcp);
5396 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5397 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5398 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3064ff39 5399 } else {
5f28d2d7
SK		 5400 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5401 "Done %s.\n", __func__);
3064ff39
MH		 5402 if (mcp->mb[1] != 0x7)
5403 ha->link_data_rate = mcp->mb[1];
5404 }
5405
5406 return rval;
5407}
09ff701a 5408
23f2ebd1
SR		 5409int
5410qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5411{
5412 int rval;
5413 mbx_cmd_t mc;
5414 mbx_cmd_t *mcp = &mc;
5415 struct qla_hw_data *ha = vha->hw;
5416
5f28d2d7
SK		 5417 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
5418 "Entered %s.\n", __func__);
23f2ebd1 5419
f73cb695 5420 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
ecc89f25 5421 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
23f2ebd1
SR		 5422 return QLA_FUNCTION_FAILED;
5423 mcp->mb[0] = MBC_GET_PORT_CONFIG;
5424 mcp->out_mb = MBX_0;
5425 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5426 mcp->tov = MBX_TOV_SECONDS;
5427 mcp->flags = 0;
5428
5429 rval = qla2x00_mailbox_command(vha, mcp);
5430
5431 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5432 ql_dbg(ql_dbg_mbx, vha, 0x110a,
5433 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1
SR		 5434 } else {
5435 /* Copy all bits to preserve original value */
5436 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
5437
5f28d2d7
SK		 5438 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
5439 "Done %s.\n", __func__);
23f2ebd1
SR		 5440 }
5441 return rval;
5442}
5443
5444int
5445qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5446{
5447 int rval;
5448 mbx_cmd_t mc;
5449 mbx_cmd_t *mcp = &mc;
5450
5f28d2d7
SK		 5451 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
5452 "Entered %s.\n", __func__);
23f2ebd1
SR		 5453
5454 mcp->mb[0] = MBC_SET_PORT_CONFIG;
5455 /* Copy all bits to preserve original setting */
5456 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
5457 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5458 mcp->in_mb = MBX_0;
5459 mcp->tov = MBX_TOV_SECONDS;
5460 mcp->flags = 0;
5461 rval = qla2x00_mailbox_command(vha, mcp);
5462
5463 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5464 ql_dbg(ql_dbg_mbx, vha, 0x110d,
5465 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1 5466 } else
5f28d2d7
SK		 5467 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
5468 "Done %s.\n", __func__);
23f2ebd1
SR		 5469
5470 return rval;
5471}
5472
5473
09ff701a
SR		 5474int
5475qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
5476 uint16_t *mb)
5477{
5478 int rval;
5479 mbx_cmd_t mc;
5480 mbx_cmd_t *mcp = &mc;
5481 struct qla_hw_data *ha = vha->hw;
5482
5f28d2d7
SK		 5483 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
5484 "Entered %s.\n", __func__);
7c3df132 5485
09ff701a
SR		 5486 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
5487 return QLA_FUNCTION_FAILED;
5488
09ff701a
SR		 5489 mcp->mb[0] = MBC_PORT_PARAMS;
5490 mcp->mb[1] = loop_id;
5491 if (ha->flags.fcp_prio_enabled)
5492 mcp->mb[2] = BIT_1;
5493 else
5494 mcp->mb[2] = BIT_2;
5495 mcp->mb[4] = priority & 0xf;
5496 mcp->mb[9] = vha->vp_idx;
5497 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5498 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5499 mcp->tov = 30;
5500 mcp->flags = 0;
5501 rval = qla2x00_mailbox_command(vha, mcp);
5502 if (mb != NULL) {
5503 mb[0] = mcp->mb[0];
5504 mb[1] = mcp->mb[1];
5505 mb[3] = mcp->mb[3];
5506 mb[4] = mcp->mb[4];
5507 }
5508
5509 if (rval != QLA_SUCCESS) {
7c3df132 5510 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
09ff701a 5511 } else {
5f28d2d7
SK		 5512 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
5513 "Done %s.\n", __func__);
09ff701a
SR		 5514 }
5515
5516 return rval;
5517}
a9083016 5518
794a5691 5519int
fe52f6e1 5520qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
794a5691 5521{
fe52f6e1 5522 int rval = QLA_FUNCTION_FAILED;
794a5691 5523 struct qla_hw_data *ha = vha->hw;
fe52f6e1 5524 uint8_t byte;
794a5691 5525
1ae47cf3
JC		 5526 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
5527 ql_dbg(ql_dbg_mbx, vha, 0x1150,
5528 "Thermal not supported by this card.\n");
5529 return rval;
5530 }
5531
5532 if (IS_QLA25XX(ha)) {
5533 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
5534 ha->pdev->subsystem_device == 0x0175) {
5535 rval = qla2x00_read_sfp(vha, 0, &byte,
5536 0x98, 0x1, 1, BIT_13|BIT_0);
5537 *temp = byte;
5538 return rval;
5539 }
5540 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
5541 ha->pdev->subsystem_device == 0x338e) {
5542 rval = qla2x00_read_sfp(vha, 0, &byte,
5543 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
5544 *temp = byte;
5545 return rval;
5546 }
5547 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
5548 "Thermal not supported by this card.\n");
5549 return rval;
794a5691 5550 }
794a5691 5551
1ae47cf3
JC		 5552 if (IS_QLA82XX(ha)) {
5553 *temp = qla82xx_read_temperature(vha);
5554 rval = QLA_SUCCESS;
5555 return rval;
5556 } else if (IS_QLA8044(ha)) {
5557 *temp = qla8044_read_temperature(vha);
5558 rval = QLA_SUCCESS;
5559 return rval;
794a5691 5560 }
794a5691 5561
1ae47cf3 5562 rval = qla2x00_read_asic_temperature(vha, temp);
794a5691
AV		 5563 return rval;
5564}
5565
a9083016
GM		 5566int
5567qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
5568{
5569 int rval;
5570 struct qla_hw_data *ha = vha->hw;
5571 mbx_cmd_t mc;
5572 mbx_cmd_t *mcp = &mc;
5573
5f28d2d7
SK		 5574 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
5575 "Entered %s.\n", __func__);
7c3df132 5576
a9083016
GM		 5577 if (!IS_FWI2_CAPABLE(ha))
5578 return QLA_FUNCTION_FAILED;
5579
a9083016 5580 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5581 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5582 mcp->mb[1] = 1;
5583
5584 mcp->out_mb = MBX_1|MBX_0;
5585 mcp->in_mb = MBX_0;
5586 mcp->tov = 30;
5587 mcp->flags = 0;
5588
5589 rval = qla2x00_mailbox_command(vha, mcp);
5590 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5591 ql_dbg(ql_dbg_mbx, vha, 0x1016,
5592 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5593 } else {
5f28d2d7
SK		 5594 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
5595 "Done %s.\n", __func__);
a9083016
GM		 5596 }
5597
5598 return rval;
5599}
5600
5601int
5602qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
5603{
5604 int rval;
5605 struct qla_hw_data *ha = vha->hw;
5606 mbx_cmd_t mc;
5607 mbx_cmd_t *mcp = &mc;
5608
5f28d2d7
SK		 5609 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
5610 "Entered %s.\n", __func__);
7c3df132 5611
7ec0effd 5612 if (!IS_P3P_TYPE(ha))
a9083016
GM		 5613 return QLA_FUNCTION_FAILED;
5614
a9083016 5615 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5616 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5617 mcp->mb[1] = 0;
5618
5619 mcp->out_mb = MBX_1|MBX_0;
5620 mcp->in_mb = MBX_0;
5621 mcp->tov = 30;
5622 mcp->flags = 0;
5623
5624 rval = qla2x00_mailbox_command(vha, mcp);
5625 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5626 ql_dbg(ql_dbg_mbx, vha, 0x100c,
5627 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5628 } else {
5f28d2d7
SK		 5629 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
5630 "Done %s.\n", __func__);
a9083016
GM		 5631 }
5632
5633 return rval;
5634}
08de2844
GM		 5635
5636int
5637qla82xx_md_get_template_size(scsi_qla_host_t *vha)
5638{
5639 struct qla_hw_data *ha = vha->hw;
5640 mbx_cmd_t mc;
5641 mbx_cmd_t *mcp = &mc;
5642 int rval = QLA_FUNCTION_FAILED;
5643
5f28d2d7
SK		 5644 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
5645 "Entered %s.\n", __func__);
08de2844
GM		 5646
5647 memset(mcp->mb, 0 , sizeof(mcp->mb));
5648 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5649 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5650 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
5651 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
5652
5653 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5654 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
5655 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5656
5657 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5658 mcp->tov = MBX_TOV_SECONDS;
5659 rval = qla2x00_mailbox_command(vha, mcp);
5660
5661 /* Always copy back return mailbox values. */
5662 if (rval != QLA_SUCCESS) {
5663 ql_dbg(ql_dbg_mbx, vha, 0x1120,
5664 "mailbox command FAILED=0x%x, subcode=%x.\n",
5665 (mcp->mb[1] << 16) | mcp->mb[0],
5666 (mcp->mb[3] << 16) | mcp->mb[2]);
5667 } else {
5f28d2d7
SK		 5668 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
5669 "Done %s.\n", __func__);
08de2844
GM		 5670 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
5671 if (!ha->md_template_size) {
5672 ql_dbg(ql_dbg_mbx, vha, 0x1122,
5673 "Null template size obtained.\n");
5674 rval = QLA_FUNCTION_FAILED;
5675 }
5676 }
5677 return rval;
5678}
5679
5680int
5681qla82xx_md_get_template(scsi_qla_host_t *vha)
5682{
5683 struct qla_hw_data *ha = vha->hw;
5684 mbx_cmd_t mc;
5685 mbx_cmd_t *mcp = &mc;
5686 int rval = QLA_FUNCTION_FAILED;
5687
5f28d2d7
SK		 5688 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
5689 "Entered %s.\n", __func__);
08de2844
GM		 5690
5691 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5692 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5693 if (!ha->md_tmplt_hdr) {
5694 ql_log(ql_log_warn, vha, 0x1124,
5695 "Unable to allocate memory for Minidump template.\n");
5696 return rval;
5697 }
5698
5699 memset(mcp->mb, 0 , sizeof(mcp->mb));
5700 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5701 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5702 mcp->mb[2] = LSW(RQST_TMPLT);
5703 mcp->mb[3] = MSW(RQST_TMPLT);
5704 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
5705 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
5706 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
5707 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
5708 mcp->mb[8] = LSW(ha->md_template_size);
5709 mcp->mb[9] = MSW(ha->md_template_size);
5710
5711 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5712 mcp->tov = MBX_TOV_SECONDS;
5713 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5714 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5715 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5716 rval = qla2x00_mailbox_command(vha, mcp);
5717
5718 if (rval != QLA_SUCCESS) {
5719 ql_dbg(ql_dbg_mbx, vha, 0x1125,
5720 "mailbox command FAILED=0x%x, subcode=%x.\n",
5721 ((mcp->mb[1] << 16) | mcp->mb[0]),
5722 ((mcp->mb[3] << 16) | mcp->mb[2]));
5723 } else
5f28d2d7
SK		 5724 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
5725 "Done %s.\n", __func__);
08de2844
GM		 5726 return rval;
5727}
999916dc 5728
7ec0effd
AD		 5729int
5730qla8044_md_get_template(scsi_qla_host_t *vha)
5731{
5732 struct qla_hw_data *ha = vha->hw;
5733 mbx_cmd_t mc;
5734 mbx_cmd_t *mcp = &mc;
5735 int rval = QLA_FUNCTION_FAILED;
5736 int offset = 0, size = MINIDUMP_SIZE_36K;
bd432bb5 5737
7ec0effd
AD		 5738 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5739 "Entered %s.\n", __func__);
5740
5741 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5742 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5743 if (!ha->md_tmplt_hdr) {
5744 ql_log(ql_log_warn, vha, 0xb11b,
5745 "Unable to allocate memory for Minidump template.\n");
5746 return rval;
5747 }
5748
5749 memset(mcp->mb, 0 , sizeof(mcp->mb));
5750 while (offset < ha->md_template_size) {
5751 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5752 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5753 mcp->mb[2] = LSW(RQST_TMPLT);
5754 mcp->mb[3] = MSW(RQST_TMPLT);
5755 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
5756 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
5757 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
5758 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
5759 mcp->mb[8] = LSW(size);
5760 mcp->mb[9] = MSW(size);
5761 mcp->mb[10] = offset & 0x0000FFFF;
5762 mcp->mb[11] = offset & 0xFFFF0000;
5763 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5764 mcp->tov = MBX_TOV_SECONDS;
5765 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5766 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5767 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5768 rval = qla2x00_mailbox_command(vha, mcp);
5769
5770 if (rval != QLA_SUCCESS) {
5771 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
5772 "mailbox command FAILED=0x%x, subcode=%x.\n",
5773 ((mcp->mb[1] << 16) | mcp->mb[0]),
5774 ((mcp->mb[3] << 16) | mcp->mb[2]));
5775 return rval;
5776 } else
5777 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
5778 "Done %s.\n", __func__);
5779 offset = offset + size;
5780 }
5781 return rval;
5782}
5783
6246b8a1
GM		 5784int
5785qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5786{
5787 int rval;
5788 struct qla_hw_data *ha = vha->hw;
5789 mbx_cmd_t mc;
5790 mbx_cmd_t *mcp = &mc;
5791
5792 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5793 return QLA_FUNCTION_FAILED;
5794
5f28d2d7
SK		 5795 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
5796 "Entered %s.\n", __func__);
6246b8a1
GM		 5797
5798 memset(mcp, 0, sizeof(mbx_cmd_t));
5799 mcp->mb[0] = MBC_SET_LED_CONFIG;
5800 mcp->mb[1] = led_cfg[0];
5801 mcp->mb[2] = led_cfg[1];
5802 if (IS_QLA8031(ha)) {
5803 mcp->mb[3] = led_cfg[2];
5804 mcp->mb[4] = led_cfg[3];
5805 mcp->mb[5] = led_cfg[4];
5806 mcp->mb[6] = led_cfg[5];
5807 }
5808
5809 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5810 if (IS_QLA8031(ha))
5811 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5812 mcp->in_mb = MBX_0;
5813 mcp->tov = 30;
5814 mcp->flags = 0;
5815
5816 rval = qla2x00_mailbox_command(vha, mcp);
5817 if (rval != QLA_SUCCESS) {
5818 ql_dbg(ql_dbg_mbx, vha, 0x1134,
5819 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5820 } else {
5f28d2d7
SK		 5821 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
5822 "Done %s.\n", __func__);
6246b8a1
GM		 5823 }
5824
5825 return rval;
5826}
5827
5828int
5829qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5830{
5831 int rval;
5832 struct qla_hw_data *ha = vha->hw;
5833 mbx_cmd_t mc;
5834 mbx_cmd_t *mcp = &mc;
5835
5836 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5837 return QLA_FUNCTION_FAILED;
5838
5f28d2d7
SK		 5839 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
5840 "Entered %s.\n", __func__);
6246b8a1
GM		 5841
5842 memset(mcp, 0, sizeof(mbx_cmd_t));
5843 mcp->mb[0] = MBC_GET_LED_CONFIG;
5844
5845 mcp->out_mb = MBX_0;
5846 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5847 if (IS_QLA8031(ha))
5848 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5849 mcp->tov = 30;
5850 mcp->flags = 0;
5851
5852 rval = qla2x00_mailbox_command(vha, mcp);
5853 if (rval != QLA_SUCCESS) {
5854 ql_dbg(ql_dbg_mbx, vha, 0x1137,
5855 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5856 } else {
5857 led_cfg[0] = mcp->mb[1];
5858 led_cfg[1] = mcp->mb[2];
5859 if (IS_QLA8031(ha)) {
5860 led_cfg[2] = mcp->mb[3];
5861 led_cfg[3] = mcp->mb[4];
5862 led_cfg[4] = mcp->mb[5];
5863 led_cfg[5] = mcp->mb[6];
5864 }
5f28d2d7
SK		 5865 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
5866 "Done %s.\n", __func__);
6246b8a1
GM		 5867 }
5868
5869 return rval;
5870}
5871
999916dc
SK		 5872int
5873qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
5874{
5875 int rval;
5876 struct qla_hw_data *ha = vha->hw;
5877 mbx_cmd_t mc;
5878 mbx_cmd_t *mcp = &mc;
5879
7ec0effd 5880 if (!IS_P3P_TYPE(ha))
999916dc
SK		 5881 return QLA_FUNCTION_FAILED;
5882
5f28d2d7 5883 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
999916dc
SK		 5884 "Entered %s.\n", __func__);
5885
5886 memset(mcp, 0, sizeof(mbx_cmd_t));
5887 mcp->mb[0] = MBC_SET_LED_CONFIG;
5888 if (enable)
5889 mcp->mb[7] = 0xE;
5890 else
5891 mcp->mb[7] = 0xD;
5892
5893 mcp->out_mb = MBX_7|MBX_0;
5894 mcp->in_mb = MBX_0;
6246b8a1 5895 mcp->tov = MBX_TOV_SECONDS;
999916dc
SK		 5896 mcp->flags = 0;
5897
5898 rval = qla2x00_mailbox_command(vha, mcp);
5899 if (rval != QLA_SUCCESS) {
5900 ql_dbg(ql_dbg_mbx, vha, 0x1128,
5901 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5902 } else {
5f28d2d7 5903 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
999916dc
SK		 5904 "Done %s.\n", __func__);
5905 }
5906
5907 return rval;
5908}
6246b8a1
GM		 5909
5910int
7d613ac6 5911qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
6246b8a1
GM		 5912{
5913 int rval;
5914 struct qla_hw_data *ha = vha->hw;
5915 mbx_cmd_t mc;
5916 mbx_cmd_t *mcp = &mc;
5917
ecc89f25 5918 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
6246b8a1
GM		 5919 return QLA_FUNCTION_FAILED;
5920
5f28d2d7
SK		 5921 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
5922 "Entered %s.\n", __func__);
6246b8a1
GM		 5923
5924 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
5925 mcp->mb[1] = LSW(reg);
5926 mcp->mb[2] = MSW(reg);
5927 mcp->mb[3] = LSW(data);
5928 mcp->mb[4] = MSW(data);
5929 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5930
5931 mcp->in_mb = MBX_1|MBX_0;
5932 mcp->tov = MBX_TOV_SECONDS;
5933 mcp->flags = 0;
5934 rval = qla2x00_mailbox_command(vha, mcp);
5935
5936 if (rval != QLA_SUCCESS) {
5937 ql_dbg(ql_dbg_mbx, vha, 0x1131,
5938 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5939 } else {
5f28d2d7 5940 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
6246b8a1
GM		 5941 "Done %s.\n", __func__);
5942 }
af11f64d 5943
6246b8a1
GM		 5944 return rval;
5945}
af11f64d
AV		 5946
5947int
5948qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
5949{
5950 int rval;
5951 struct qla_hw_data *ha = vha->hw;
5952 mbx_cmd_t mc;
5953 mbx_cmd_t *mcp = &mc;
5954
5955 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5f28d2d7 5956 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
af11f64d
AV		 5957 "Implicit LOGO Unsupported.\n");
5958 return QLA_FUNCTION_FAILED;
5959 }
5960
5961
5f28d2d7
SK		 5962 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
5963 "Entering %s.\n", __func__);
af11f64d
AV		 5964
5965 /* Perform Implicit LOGO. */
5966 mcp->mb[0] = MBC_PORT_LOGOUT;
5967 mcp->mb[1] = fcport->loop_id;
5968 mcp->mb[10] = BIT_15;
5969 mcp->out_mb = MBX_10|MBX_1|MBX_0;
5970 mcp->in_mb = MBX_0;
5971 mcp->tov = MBX_TOV_SECONDS;
5972 mcp->flags = 0;
5973 rval = qla2x00_mailbox_command(vha, mcp);
5974 if (rval != QLA_SUCCESS)
5975 ql_dbg(ql_dbg_mbx, vha, 0x113d,
5976 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5977 else
5f28d2d7
SK		 5978 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
5979 "Done %s.\n", __func__);
af11f64d
AV		 5980
5981 return rval;
5982}
5983
7d613ac6
SV		 5984int
5985qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
5986{
5987 int rval;
5988 mbx_cmd_t mc;
5989 mbx_cmd_t *mcp = &mc;
5990 struct qla_hw_data *ha = vha->hw;
5991 unsigned long retry_max_time = jiffies + (2 * HZ);
5992
ecc89f25 5993 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
7d613ac6
SV		 5994 return QLA_FUNCTION_FAILED;
5995
5996 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
5997
5998retry_rd_reg:
5999 mcp->mb[0] = MBC_READ_REMOTE_REG;
6000 mcp->mb[1] = LSW(reg);
6001 mcp->mb[2] = MSW(reg);
6002 mcp->out_mb = MBX_2|MBX_1|MBX_0;
6003 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
6004 mcp->tov = MBX_TOV_SECONDS;
6005 mcp->flags = 0;
6006 rval = qla2x00_mailbox_command(vha, mcp);
6007
6008 if (rval != QLA_SUCCESS) {
6009 ql_dbg(ql_dbg_mbx, vha, 0x114c,
6010 "Failed=%x mb[0]=%x mb[1]=%x.\n",
6011 rval, mcp->mb[0], mcp->mb[1]);
6012 } else {
6013 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
6014 if (*data == QLA8XXX_BAD_VALUE) {
6015 /*
6016 * During soft-reset CAMRAM register reads might
6017 * return 0xbad0bad0. So retry for MAX of 2 sec
6018 * while reading camram registers.
6019 */
6020 if (time_after(jiffies, retry_max_time)) {
6021 ql_dbg(ql_dbg_mbx, vha, 0x1141,
6022 "Failure to read CAMRAM register. "
6023 "data=0x%x.\n", *data);
6024 return QLA_FUNCTION_FAILED;
6025 }
6026 msleep(100);
6027 goto retry_rd_reg;
6028 }
6029 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
6030 }
6031
6032 return rval;
6033}
6034
6035int
6036qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
6037{
6038 int rval;
6039 mbx_cmd_t mc;
6040 mbx_cmd_t *mcp = &mc;
6041 struct qla_hw_data *ha = vha->hw;
6042
ecc89f25 6043 if (!IS_QLA83XX(ha))
7d613ac6
SV		 6044 return QLA_FUNCTION_FAILED;
6045
6046 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
6047
6048 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
6049 mcp->out_mb = MBX_0;
6050 mcp->in_mb = MBX_1|MBX_0;
6051 mcp->tov = MBX_TOV_SECONDS;
6052 mcp->flags = 0;
6053 rval = qla2x00_mailbox_command(vha, mcp);
6054
6055 if (rval != QLA_SUCCESS) {
6056 ql_dbg(ql_dbg_mbx, vha, 0x1144,
6057 "Failed=%x mb[0]=%x mb[1]=%x.\n",
6058 rval, mcp->mb[0], mcp->mb[1]);
6059 ha->isp_ops->fw_dump(vha, 0);
6060 } else {
6061 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
6062 }
6063
6064 return rval;
6065}
6066
6067int
6068qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
6069 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
6070{
6071 int rval;
6072 mbx_cmd_t mc;
6073 mbx_cmd_t *mcp = &mc;
6074 uint8_t subcode = (uint8_t)options;
6075 struct qla_hw_data *ha = vha->hw;
6076
6077 if (!IS_QLA8031(ha))
6078 return QLA_FUNCTION_FAILED;
6079
6080 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
6081
6082 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
6083 mcp->mb[1] = options;
6084 mcp->out_mb = MBX_1|MBX_0;
6085 if (subcode & BIT_2) {
6086 mcp->mb[2] = LSW(start_addr);
6087 mcp->mb[3] = MSW(start_addr);
6088 mcp->mb[4] = LSW(end_addr);
6089 mcp->mb[5] = MSW(end_addr);
6090 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
6091 }
6092 mcp->in_mb = MBX_2|MBX_1|MBX_0;
6093 if (!(subcode & (BIT_2 | BIT_5)))
6094 mcp->in_mb |= MBX_4|MBX_3;
6095 mcp->tov = MBX_TOV_SECONDS;
6096 mcp->flags = 0;
6097 rval = qla2x00_mailbox_command(vha, mcp);
6098
6099 if (rval != QLA_SUCCESS) {
6100 ql_dbg(ql_dbg_mbx, vha, 0x1147,
6101 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
6102 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
6103 mcp->mb[4]);
6104 ha->isp_ops->fw_dump(vha, 0);
6105 } else {
6106 if (subcode & BIT_5)
6107 *sector_size = mcp->mb[1];
6108 else if (subcode & (BIT_6 | BIT_7)) {
6109 ql_dbg(ql_dbg_mbx, vha, 0x1148,
6110 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
6111 } else if (subcode & (BIT_3 | BIT_4)) {
6112 ql_dbg(ql_dbg_mbx, vha, 0x1149,
6113 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
6114 }
6115 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
6116 }
6117
6118 return rval;
6119}
81178772
SK		 6120
6121int
6122qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
6123 uint32_t size)
6124{
6125 int rval;
6126 mbx_cmd_t mc;
6127 mbx_cmd_t *mcp = &mc;
6128
6129 if (!IS_MCTP_CAPABLE(vha->hw))
6130 return QLA_FUNCTION_FAILED;
6131
6132 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
6133 "Entered %s.\n", __func__);
6134
6135 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
6136 mcp->mb[1] = LSW(addr);
6137 mcp->mb[2] = MSW(req_dma);
6138 mcp->mb[3] = LSW(req_dma);
6139 mcp->mb[4] = MSW(size);
6140 mcp->mb[5] = LSW(size);
6141 mcp->mb[6] = MSW(MSD(req_dma));
6142 mcp->mb[7] = LSW(MSD(req_dma));
6143 mcp->mb[8] = MSW(addr);
6144 /* Setting RAM ID to valid */
6145 mcp->mb[10] |= BIT_7;
6146 /* For MCTP RAM ID is 0x40 */
6147 mcp->mb[10] |= 0x40;
6148
6149 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
6150 MBX_0;
6151
6152 mcp->in_mb = MBX_0;
6153 mcp->tov = MBX_TOV_SECONDS;
6154 mcp->flags = 0;
6155 rval = qla2x00_mailbox_command(vha, mcp);
6156
6157 if (rval != QLA_SUCCESS) {
6158 ql_dbg(ql_dbg_mbx, vha, 0x114e,
6159 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6160 } else {
6161 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
6162 "Done %s.\n", __func__);
6163 }
6164
6165 return rval;
6166}
ec891462
JC		 6167
6168int
6169qla26xx_dport_diagnostics(scsi_qla_host_t *vha,
6170 void *dd_buf, uint size, uint options)
6171{
6172 int rval;
6173 mbx_cmd_t mc;
6174 mbx_cmd_t *mcp = &mc;
6175 dma_addr_t dd_dma;
6176
ecc89f25
JC		 6177 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
6178 !IS_QLA28XX(vha->hw))
ec891462
JC		 6179 return QLA_FUNCTION_FAILED;
6180
83548fe2 6181 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f,
ec891462
JC		 6182 "Entered %s.\n", __func__);
6183
ec891462
JC		 6184 dd_dma = dma_map_single(&vha->hw->pdev->dev,
6185 dd_buf, size, DMA_FROM_DEVICE);
0b2ce198 6186 if (dma_mapping_error(&vha->hw->pdev->dev, dd_dma)) {
ec891462
JC		 6187 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n");
6188 return QLA_MEMORY_ALLOC_FAILED;
6189 }
6190
6191 memset(dd_buf, 0, size);
6192
6193 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS;
6194 mcp->mb[1] = options;
6195 mcp->mb[2] = MSW(LSD(dd_dma));
6196 mcp->mb[3] = LSW(LSD(dd_dma));
6197 mcp->mb[6] = MSW(MSD(dd_dma));
6198 mcp->mb[7] = LSW(MSD(dd_dma));
6199 mcp->mb[8] = size;
6200 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6201 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
6202 mcp->buf_size = size;
6203 mcp->flags = MBX_DMA_IN;
6204 mcp->tov = MBX_TOV_SECONDS * 4;
6205 rval = qla2x00_mailbox_command(vha, mcp);
6206
6207 if (rval != QLA_SUCCESS) {
6208 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval);
6209 } else {
6210 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196,
6211 "Done %s.\n", __func__);
6212 }
6213
6214 dma_unmap_single(&vha->hw->pdev->dev, dd_dma,
6215 size, DMA_FROM_DEVICE);
6216
6217 return rval;
6218}
15f30a57 6219
6c18a43e 6220static void qla2x00_async_mb_sp_done(srb_t *sp, int res)
15f30a57 6221{
15f30a57
QT		 6222 sp->u.iocb_cmd.u.mbx.rc = res;
6223
6224 complete(&sp->u.iocb_cmd.u.mbx.comp);
6225 /* don't free sp here. Let the caller do the free */
6226}
6227
6228/*
6229 * This mailbox uses the iocb interface to send MB command.
6230 * This allows non-critial (non chip setup) command to go
6231 * out in parrallel.
6232 */
6233int qla24xx_send_mb_cmd(struct scsi_qla_host *vha, mbx_cmd_t *mcp)
6234{
6235 int rval = QLA_FUNCTION_FAILED;
6236 srb_t *sp;
6237 struct srb_iocb *c;
6238
6239 if (!vha->hw->flags.fw_started)
6240 goto done;
6241
6242 sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL);
6243 if (!sp)
6244 goto done;
6245
6246 sp->type = SRB_MB_IOCB;
6247 sp->name = mb_to_str(mcp->mb[0]);
6248
15f30a57
QT		 6249 c = &sp->u.iocb_cmd;
6250 c->timeout = qla2x00_async_iocb_timeout;
6251 init_completion(&c->u.mbx.comp);
6252
e74e7d95
BH		 6253 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
6254
6255 memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG);
6256
15f30a57
QT		 6257 sp->done = qla2x00_async_mb_sp_done;
6258
6259 rval = qla2x00_start_sp(sp);
6260 if (rval != QLA_SUCCESS) {
83548fe2 6261 ql_dbg(ql_dbg_mbx, vha, 0x1018,
15f30a57
QT		 6262 "%s: %s Failed submission. %x.\n",
6263 __func__, sp->name, rval);
6264 goto done_free_sp;
6265 }
6266
83548fe2 6267 ql_dbg(ql_dbg_mbx, vha, 0x113f, "MB:%s hndl %x submitted\n",
15f30a57
QT		 6268 sp->name, sp->handle);
6269
6270 wait_for_completion(&c->u.mbx.comp);
6271 memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG);
6272
6273 rval = c->u.mbx.rc;
6274 switch (rval) {
6275 case QLA_FUNCTION_TIMEOUT:
83548fe2 6276 ql_dbg(ql_dbg_mbx, vha, 0x1140, "%s: %s Timeout. %x.\n",
15f30a57
QT		 6277 __func__, sp->name, rval);
6278 break;
6279 case QLA_SUCCESS:
83548fe2 6280 ql_dbg(ql_dbg_mbx, vha, 0x119d, "%s: %s done.\n",
15f30a57
QT		 6281 __func__, sp->name);
6282 sp->free(sp);
6283 break;
6284 default:
83548fe2 6285 ql_dbg(ql_dbg_mbx, vha, 0x119e, "%s: %s Failed. %x.\n",
15f30a57
QT		 6286 __func__, sp->name, rval);
6287 sp->free(sp);
6288 break;
6289 }
6290
6291 return rval;
6292
6293done_free_sp:
6294 sp->free(sp);
6295done:
6296 return rval;
6297}
6298
6299/*
6300 * qla24xx_gpdb_wait
6301 * NOTE: Do not call this routine from DPC thread
6302 */
6303int qla24xx_gpdb_wait(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
6304{
6305 int rval = QLA_FUNCTION_FAILED;
6306 dma_addr_t pd_dma;
6307 struct port_database_24xx *pd;
6308 struct qla_hw_data *ha = vha->hw;
6309 mbx_cmd_t mc;
6310
6311 if (!vha->hw->flags.fw_started)
6312 goto done;
6313
08eb7f45 6314 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
15f30a57 6315 if (pd == NULL) {
83548fe2
QT		 6316 ql_log(ql_log_warn, vha, 0xd047,
6317 "Failed to allocate port database structure.\n");
15f30a57
QT		 6318 goto done_free_sp;
6319 }
15f30a57
QT		 6320
6321 memset(&mc, 0, sizeof(mc));
6322 mc.mb[0] = MBC_GET_PORT_DATABASE;
6323 mc.mb[1] = cpu_to_le16(fcport->loop_id);
6324 mc.mb[2] = MSW(pd_dma);
6325 mc.mb[3] = LSW(pd_dma);
6326 mc.mb[6] = MSW(MSD(pd_dma));
6327 mc.mb[7] = LSW(MSD(pd_dma));
6328 mc.mb[9] = cpu_to_le16(vha->vp_idx);
6329 mc.mb[10] = cpu_to_le16((uint16_t)opt);
6330
6331 rval = qla24xx_send_mb_cmd(vha, &mc);
6332 if (rval != QLA_SUCCESS) {
83548fe2 6333 ql_dbg(ql_dbg_mbx, vha, 0x1193,
15f30a57
QT		 6334 "%s: %8phC fail\n", __func__, fcport->port_name);
6335 goto done_free_sp;
6336 }
6337
6338 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
6339
83548fe2 6340 ql_dbg(ql_dbg_mbx, vha, 0x1197, "%s: %8phC done\n",
15f30a57
QT		 6341 __func__, fcport->port_name);
6342
6343done_free_sp:
6344 if (pd)
6345 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
6346done:
6347 return rval;
6348}
6349
6350int __qla24xx_parse_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport,
6351 struct port_database_24xx *pd)
6352{
6353 int rval = QLA_SUCCESS;
6354 uint64_t zero = 0;
a5d42f4c
DG		 6355 u8 current_login_state, last_login_state;
6356
6357 if (fcport->fc4f_nvme) {
6358 current_login_state = pd->current_login_state >> 4;
6359 last_login_state = pd->last_login_state >> 4;
6360 } else {
6361 current_login_state = pd->current_login_state & 0xf;
6362 last_login_state = pd->last_login_state & 0xf;
6363 }
15f30a57
QT		 6364
6365 /* Check for logged in state. */
23c64559 6366 if (current_login_state != PDS_PRLI_COMPLETE) {
83548fe2
QT		 6367 ql_dbg(ql_dbg_mbx, vha, 0x119a,
6368 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
a5d42f4c 6369 current_login_state, last_login_state, fcport->loop_id);
15f30a57
QT		 6370 rval = QLA_FUNCTION_FAILED;
6371 goto gpd_error_out;
6372 }
6373
6374 if (fcport->loop_id == FC_NO_LOOP_ID ||
6375 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
6376 memcmp(fcport->port_name, pd->port_name, 8))) {
6377 /* We lost the device mid way. */
6378 rval = QLA_NOT_LOGGED_IN;
6379 goto gpd_error_out;
6380 }
6381
6382 /* Names are little-endian. */
6383 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
6384 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
6385
6386 /* Get port_id of device. */
6387 fcport->d_id.b.domain = pd->port_id[0];
6388 fcport->d_id.b.area = pd->port_id[1];
6389 fcport->d_id.b.al_pa = pd->port_id[2];
6390 fcport->d_id.b.rsvd_1 = 0;
6391
a5d42f4c 6392 if (fcport->fc4f_nvme) {
a6a6d058
HR		 6393 fcport->port_type = 0;
6394 if ((pd->prli_svc_param_word_3[0] & BIT_5) == 0)
6395 fcport->port_type |= FCT_NVME_INITIATOR;
6396 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6397 fcport->port_type |= FCT_NVME_TARGET;
6398 if ((pd->prli_svc_param_word_3[0] & BIT_3) == 0)
6399 fcport->port_type |= FCT_NVME_DISCOVERY;
a5d42f4c
DG		 6400 } else {
6401 /* If not target must be initiator or unknown type. */
6402 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6403 fcport->port_type = FCT_INITIATOR;
6404 else
6405 fcport->port_type = FCT_TARGET;
6406 }
15f30a57
QT		 6407 /* Passback COS information. */
6408 fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
6409 FC_COS_CLASS2 : FC_COS_CLASS3;
6410
6411 if (pd->prli_svc_param_word_3[0] & BIT_7) {
6412 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
6413 fcport->conf_compl_supported = 1;
6414 }
6415
6416gpd_error_out:
6417 return rval;
6418}
6419
6420/*
6421 * qla24xx_gidlist__wait
6422 * NOTE: don't call this routine from DPC thread.
6423 */
6424int qla24xx_gidlist_wait(struct scsi_qla_host *vha,
6425 void *id_list, dma_addr_t id_list_dma, uint16_t *entries)
6426{
6427 int rval = QLA_FUNCTION_FAILED;
6428 mbx_cmd_t mc;
6429
6430 if (!vha->hw->flags.fw_started)
6431 goto done;
6432
6433 memset(&mc, 0, sizeof(mc));
6434 mc.mb[0] = MBC_GET_ID_LIST;
6435 mc.mb[2] = MSW(id_list_dma);
6436 mc.mb[3] = LSW(id_list_dma);
6437 mc.mb[6] = MSW(MSD(id_list_dma));
6438 mc.mb[7] = LSW(MSD(id_list_dma));
6439 mc.mb[8] = 0;
6440 mc.mb[9] = cpu_to_le16(vha->vp_idx);
6441
6442 rval = qla24xx_send_mb_cmd(vha, &mc);
6443 if (rval != QLA_SUCCESS) {
83548fe2
QT		 6444 ql_dbg(ql_dbg_mbx, vha, 0x119b,
6445 "%s: fail\n", __func__);
15f30a57
QT		 6446 } else {
6447 *entries = mc.mb[1];
83548fe2
QT		 6448 ql_dbg(ql_dbg_mbx, vha, 0x119c,
6449 "%s: done\n", __func__);
15f30a57
QT		 6450 }
6451done:
6452 return rval;
6453}
deeae7a6
DG		 6454
6455int qla27xx_set_zio_threshold(scsi_qla_host_t *vha, uint16_t value)
6456{
6457 int rval;
6458 mbx_cmd_t mc;
6459 mbx_cmd_t *mcp = &mc;
6460
6461 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1200,
6462 "Entered %s\n", __func__);
6463
6464 memset(mcp->mb, 0 , sizeof(mcp->mb));
6465 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6466 mcp->mb[1] = cpu_to_le16(1);
6467 mcp->mb[2] = cpu_to_le16(value);
6468 mcp->out_mb = MBX_2 | MBX_1 | MBX_0;
6469 mcp->in_mb = MBX_2 | MBX_0;
6470 mcp->tov = MBX_TOV_SECONDS;
6471 mcp->flags = 0;
6472
6473 rval = qla2x00_mailbox_command(vha, mcp);
6474
6475 ql_dbg(ql_dbg_mbx, vha, 0x1201, "%s %x\n",
6476 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6477
6478 return rval;
6479}
6480
6481int qla27xx_get_zio_threshold(scsi_qla_host_t *vha, uint16_t *value)
6482{
6483 int rval;
6484 mbx_cmd_t mc;
6485 mbx_cmd_t *mcp = &mc;
6486
6487 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1203,
6488 "Entered %s\n", __func__);
6489
6490 memset(mcp->mb, 0, sizeof(mcp->mb));
6491 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6492 mcp->mb[1] = cpu_to_le16(0);
6493 mcp->out_mb = MBX_1 | MBX_0;
6494 mcp->in_mb = MBX_2 | MBX_0;
6495 mcp->tov = MBX_TOV_SECONDS;
6496 mcp->flags = 0;
6497
6498 rval = qla2x00_mailbox_command(vha, mcp);
6499 if (rval == QLA_SUCCESS)
6500 *value = mc.mb[2];
6501
6502 ql_dbg(ql_dbg_mbx, vha, 0x1205, "%s %x\n",
6503 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6504
6505 return rval;
6506}
e4e3a2ce
QT		 6507
6508int
6509qla2x00_read_sfp_dev(struct scsi_qla_host *vha, char *buf, int count)
6510{
6511 struct qla_hw_data *ha = vha->hw;
6512 uint16_t iter, addr, offset;
6513 dma_addr_t phys_addr;
6514 int rval, c;
6515 u8 *sfp_data;
6516
6517 memset(ha->sfp_data, 0, SFP_DEV_SIZE);
6518 addr = 0xa0;
6519 phys_addr = ha->sfp_data_dma;
6520 sfp_data = ha->sfp_data;
6521 offset = c = 0;
6522
6523 for (iter = 0; iter < SFP_DEV_SIZE / SFP_BLOCK_SIZE; iter++) {
6524 if (iter == 4) {
6525 /* Skip to next device address. */
6526 addr = 0xa2;
6527 offset = 0;
6528 }
6529
6530 rval = qla2x00_read_sfp(vha, phys_addr, sfp_data,
6531 addr, offset, SFP_BLOCK_SIZE, BIT_1);
6532 if (rval != QLA_SUCCESS) {
6533 ql_log(ql_log_warn, vha, 0x706d,
6534 "Unable to read SFP data (%x/%x/%x).\n", rval,
6535 addr, offset);
6536
6537 return rval;
6538 }
6539
6540 if (buf && (c < count)) {
6541 u16 sz;
6542
6543 if ((count - c) >= SFP_BLOCK_SIZE)
6544 sz = SFP_BLOCK_SIZE;
6545 else
6546 sz = count - c;
6547
6548 memcpy(buf, sfp_data, sz);
6549 buf += SFP_BLOCK_SIZE;
6550 c += sz;
6551 }
6552 phys_addr += SFP_BLOCK_SIZE;
6553 sfp_data += SFP_BLOCK_SIZE;
6554 offset += SFP_BLOCK_SIZE;
6555 }
6556
6557 return rval;
6558}
94d83e36
QT		 6559
6560int qla24xx_res_count_wait(struct scsi_qla_host *vha,
6561 uint16_t *out_mb, int out_mb_sz)
6562{
6563 int rval = QLA_FUNCTION_FAILED;
6564 mbx_cmd_t mc;
6565
6566 if (!vha->hw->flags.fw_started)
6567 goto done;
6568
6569 memset(&mc, 0, sizeof(mc));
6570 mc.mb[0] = MBC_GET_RESOURCE_COUNTS;
6571
6572 rval = qla24xx_send_mb_cmd(vha, &mc);
6573 if (rval != QLA_SUCCESS) {
6574 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6575 "%s: fail\n", __func__);
6576 } else {
6577 if (out_mb_sz <= SIZEOF_IOCB_MB_REG)
6578 memcpy(out_mb, mc.mb, out_mb_sz);
6579 else
6580 memcpy(out_mb, mc.mb, SIZEOF_IOCB_MB_REG);
6581
6582 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6583 "%s: done\n", __func__);
6584 }
6585done:
6586 return rval;
6587}
3f006ac3
MH		 6588
6589int qla28xx_secure_flash_update(scsi_qla_host_t *vha, uint16_t opts,
6590 uint16_t region, uint32_t len, dma_addr_t sfub_dma_addr,
6591 uint32_t sfub_len)
6592{
6593 int rval;
6594 mbx_cmd_t mc;
6595 mbx_cmd_t *mcp = &mc;
6596
6597 mcp->mb[0] = MBC_SECURE_FLASH_UPDATE;
6598 mcp->mb[1] = opts;
6599 mcp->mb[2] = region;
6600 mcp->mb[3] = MSW(len);
6601 mcp->mb[4] = LSW(len);
6602 mcp->mb[5] = MSW(sfub_dma_addr);
6603 mcp->mb[6] = LSW(sfub_dma_addr);
6604 mcp->mb[7] = MSW(MSD(sfub_dma_addr));
6605 mcp->mb[8] = LSW(MSD(sfub_dma_addr));
6606 mcp->mb[9] = sfub_len;
6607 mcp->out_mb =
6608 MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6609 mcp->in_mb = MBX_2|MBX_1|MBX_0;
6610 mcp->tov = MBX_TOV_SECONDS;
6611 mcp->flags = 0;
6612 rval = qla2x00_mailbox_command(vha, mcp);
6613
6614 if (rval != QLA_SUCCESS) {
6615 ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s(%ld): failed rval 0x%x, %x %x %x",
6616 __func__, vha->host_no, rval, mcp->mb[0], mcp->mb[1],
6617 mcp->mb[2]);
6618 }
6619
6620 return rval;
6621}
6622
6623int qla2xxx_write_remote_register(scsi_qla_host_t *vha, uint32_t addr,
6624 uint32_t data)
6625{
6626 int rval;
6627 mbx_cmd_t mc;
6628 mbx_cmd_t *mcp = &mc;
6629
6630 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
6631 "Entered %s.\n", __func__);
6632
6633 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
6634 mcp->mb[1] = LSW(addr);
6635 mcp->mb[2] = MSW(addr);
6636 mcp->mb[3] = LSW(data);
6637 mcp->mb[4] = MSW(data);
6638 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6639 mcp->in_mb = MBX_1|MBX_0;
6640 mcp->tov = MBX_TOV_SECONDS;
6641 mcp->flags = 0;
6642 rval = qla2x00_mailbox_command(vha, mcp);
6643
6644 if (rval != QLA_SUCCESS) {
6645 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
6646 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6647 } else {
6648 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
6649 "Done %s.\n", __func__);
6650 }
6651
6652 return rval;
6653}
6654
6655int qla2xxx_read_remote_register(scsi_qla_host_t *vha, uint32_t addr,
6656 uint32_t *data)
6657{
6658 int rval;
6659 mbx_cmd_t mc;
6660 mbx_cmd_t *mcp = &mc;
6661
6662 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
6663 "Entered %s.\n", __func__);
6664
6665 mcp->mb[0] = MBC_READ_REMOTE_REG;
6666 mcp->mb[1] = LSW(addr);
6667 mcp->mb[2] = MSW(addr);
6668 mcp->out_mb = MBX_2|MBX_1|MBX_0;
6669 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6670 mcp->tov = MBX_TOV_SECONDS;
6671 mcp->flags = 0;
6672 rval = qla2x00_mailbox_command(vha, mcp);
6673
6674 *data = (uint32_t)((((uint32_t)mcp->mb[4]) << 16) | mcp->mb[3]);
6675
6676 if (rval != QLA_SUCCESS) {
6677 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
6678 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6679 } else {
6680 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
6681 "Done %s.\n", __func__);
6682 }
6683
6684 return rval;
6685}
Linux 6.x block layer and io_uring tree(s)