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9a58a333 SD |
1 | /* |
2 | * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism | |
3 | * | |
7c2e3c74 | 4 | * (C) Copyright 2008-2010,2015 Intel Corporation |
9a58a333 SD |
5 | * Author: Sreedhara DS (sreedhara.ds@intel.com) |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | * | |
c8440336 | 12 | * SCU running in ARC processor communicates with other entity running in IA |
9a58a333 SD |
13 | * core through IPC mechanism which in turn messaging between IA core ad SCU. |
14 | * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and | |
15 | * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with | |
16 | * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC) | |
17 | * along with other APIs. | |
18 | */ | |
19 | #include <linux/delay.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/init.h> | |
edbaa603 | 22 | #include <linux/device.h> |
9a58a333 SD |
23 | #include <linux/pm.h> |
24 | #include <linux/pci.h> | |
25 | #include <linux/interrupt.h> | |
209009b2 | 26 | #include <linux/sfi.h> |
7c52d551 | 27 | #include <linux/module.h> |
05454c26 | 28 | #include <asm/intel-mid.h> |
9a58a333 SD |
29 | #include <asm/intel_scu_ipc.h> |
30 | ||
31 | /* IPC defines the following message types */ | |
32 | #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */ | |
33 | #define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */ | |
34 | #define IPCMSG_FW_UPDATE 0xFE /* Firmware update */ | |
35 | #define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */ | |
36 | #define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */ | |
37 | ||
38 | /* Command id associated with message IPCMSG_PCNTRL */ | |
39 | #define IPC_CMD_PCNTRL_W 0 /* Register write */ | |
40 | #define IPC_CMD_PCNTRL_R 1 /* Register read */ | |
41 | #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */ | |
42 | ||
9a58a333 SD |
43 | /* |
44 | * IPC register summary | |
45 | * | |
32d0e4a3 | 46 | * IPC register blocks are memory mapped at fixed address of PCI BAR 0. |
9a58a333 | 47 | * To read or write information to the SCU, driver writes to IPC-1 memory |
32d0e4a3 | 48 | * mapped registers. The following is the IPC mechanism |
9a58a333 SD |
49 | * |
50 | * 1. IA core cDMI interface claims this transaction and converts it to a | |
51 | * Transaction Layer Packet (TLP) message which is sent across the cDMI. | |
52 | * | |
53 | * 2. South Complex cDMI block receives this message and writes it to | |
54 | * the IPC-1 register block, causing an interrupt to the SCU | |
55 | * | |
56 | * 3. SCU firmware decodes this interrupt and IPC message and the appropriate | |
57 | * message handler is called within firmware. | |
58 | */ | |
59 | ||
51cd525d AV |
60 | #define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */ |
61 | #define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */ | |
ed12f295 | 62 | #define IPC_IOC 0x100 /* IPC command register IOC bit */ |
e97a1c98 | 63 | |
b4b0b4a9 DC |
64 | #define PCI_DEVICE_ID_LINCROFT 0x082a |
65 | #define PCI_DEVICE_ID_PENWELL 0x080e | |
66 | #define PCI_DEVICE_ID_CLOVERVIEW 0x08ea | |
67 | #define PCI_DEVICE_ID_TANGIER 0x11a0 | |
68 | ||
7c2e3c74 | 69 | /* intel scu ipc driver data */ |
e97a1c98 | 70 | struct intel_scu_ipc_pdata_t { |
e97a1c98 | 71 | u32 i2c_base; |
e97a1c98 | 72 | u32 i2c_len; |
ed12f295 | 73 | u8 irq_mode; |
e97a1c98 KS |
74 | }; |
75 | ||
694e523c | 76 | static struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = { |
694e523c | 77 | .i2c_base = 0xff12b000, |
694e523c DC |
78 | .i2c_len = 0x10, |
79 | .irq_mode = 0, | |
80 | }; | |
81 | ||
82 | /* Penwell and Cloverview */ | |
83 | static struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = { | |
694e523c | 84 | .i2c_base = 0xff12b000, |
694e523c DC |
85 | .i2c_len = 0x10, |
86 | .irq_mode = 1, | |
87 | }; | |
88 | ||
89 | static struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = { | |
694e523c | 90 | .i2c_base = 0xff00d000, |
694e523c DC |
91 | .i2c_len = 0x10, |
92 | .irq_mode = 0, | |
e97a1c98 | 93 | }; |
9a58a333 SD |
94 | |
95 | static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id); | |
96 | static void ipc_remove(struct pci_dev *pdev); | |
97 | ||
98 | struct intel_scu_ipc_dev { | |
99 | struct pci_dev *pdev; | |
100 | void __iomem *ipc_base; | |
101 | void __iomem *i2c_base; | |
ed12f295 KS |
102 | struct completion cmd_complete; |
103 | u8 irq_mode; | |
9a58a333 SD |
104 | }; |
105 | ||
106 | static struct intel_scu_ipc_dev ipcdev; /* Only one for now */ | |
107 | ||
9a58a333 SD |
108 | /* |
109 | * IPC Read Buffer (Read Only): | |
110 | * 16 byte buffer for receiving data from SCU, if IPC command | |
111 | * processing results in response data | |
112 | */ | |
113 | #define IPC_READ_BUFFER 0x90 | |
114 | ||
115 | #define IPC_I2C_CNTRL_ADDR 0 | |
116 | #define I2C_DATA_ADDR 0x04 | |
117 | ||
118 | static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */ | |
119 | ||
120 | /* | |
121 | * Command Register (Write Only): | |
122 | * A write to this register results in an interrupt to the SCU core processor | |
123 | * Format: | |
124 | * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)| | |
125 | */ | |
126 | static inline void ipc_command(u32 cmd) /* Send ipc command */ | |
127 | { | |
ed12f295 KS |
128 | if (ipcdev.irq_mode) { |
129 | reinit_completion(&ipcdev.cmd_complete); | |
130 | writel(cmd | IPC_IOC, ipcdev.ipc_base); | |
131 | } | |
9a58a333 SD |
132 | writel(cmd, ipcdev.ipc_base); |
133 | } | |
134 | ||
135 | /* | |
136 | * IPC Write Buffer (Write Only): | |
137 | * 16-byte buffer for sending data associated with IPC command to | |
138 | * SCU. Size of the data is specified in the IPC_COMMAND_REG register | |
139 | */ | |
140 | static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */ | |
141 | { | |
142 | writel(data, ipcdev.ipc_base + 0x80 + offset); | |
143 | } | |
144 | ||
9a58a333 SD |
145 | /* |
146 | * Status Register (Read Only): | |
147 | * Driver will read this register to get the ready/busy status of the IPC | |
148 | * block and error status of the IPC command that was just processed by SCU | |
149 | * Format: | |
150 | * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)| | |
151 | */ | |
9a58a333 SD |
152 | static inline u8 ipc_read_status(void) |
153 | { | |
154 | return __raw_readl(ipcdev.ipc_base + 0x04); | |
155 | } | |
156 | ||
157 | static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */ | |
158 | { | |
159 | return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
160 | } | |
161 | ||
e3359fd5 | 162 | static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */ |
9a58a333 SD |
163 | { |
164 | return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
165 | } | |
166 | ||
7c2e3c74 AS |
167 | /* Wait till scu status is busy */ |
168 | static inline int busy_loop(void) | |
9a58a333 | 169 | { |
f0295a36 AS |
170 | u32 status = ipc_read_status(); |
171 | u32 loop_count = 100000; | |
9a58a333 | 172 | |
f0295a36 AS |
173 | /* break if scu doesn't reset busy bit after huge retry */ |
174 | while ((status & BIT(0)) && --loop_count) { | |
9a58a333 SD |
175 | udelay(1); /* scu processing time is in few u secods */ |
176 | status = ipc_read_status(); | |
9a58a333 | 177 | } |
f0295a36 AS |
178 | |
179 | if (status & BIT(0)) { | |
180 | dev_err(&ipcdev.pdev->dev, "IPC timed out"); | |
181 | return -ETIMEDOUT; | |
182 | } | |
183 | ||
184 | if (status & BIT(1)) | |
77e01d6d HL |
185 | return -EIO; |
186 | ||
187 | return 0; | |
9a58a333 SD |
188 | } |
189 | ||
ed12f295 KS |
190 | /* Wait till ipc ioc interrupt is received or timeout in 3 HZ */ |
191 | static inline int ipc_wait_for_interrupt(void) | |
192 | { | |
193 | int status; | |
194 | ||
195 | if (!wait_for_completion_timeout(&ipcdev.cmd_complete, 3 * HZ)) { | |
196 | struct device *dev = &ipcdev.pdev->dev; | |
197 | dev_err(dev, "IPC timed out\n"); | |
198 | return -ETIMEDOUT; | |
199 | } | |
200 | ||
201 | status = ipc_read_status(); | |
f0295a36 | 202 | if (status & BIT(1)) |
ed12f295 KS |
203 | return -EIO; |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
7c2e3c74 | 208 | static int intel_scu_ipc_check_status(void) |
ed12f295 KS |
209 | { |
210 | return ipcdev.irq_mode ? ipc_wait_for_interrupt() : busy_loop(); | |
211 | } | |
212 | ||
9a58a333 SD |
213 | /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */ |
214 | static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id) | |
215 | { | |
4707375f | 216 | int nc; |
9a58a333 | 217 | u32 offset = 0; |
ecb5646c | 218 | int err; |
8642d7f8 | 219 | u8 cbuf[IPC_WWBUF_SIZE]; |
9a58a333 SD |
220 | u32 *wbuf = (u32 *)&cbuf; |
221 | ||
ed6f2b4d AV |
222 | memset(cbuf, 0, sizeof(cbuf)); |
223 | ||
8642d7f8 CJ |
224 | mutex_lock(&ipclock); |
225 | ||
9a58a333 SD |
226 | if (ipcdev.pdev == NULL) { |
227 | mutex_unlock(&ipclock); | |
228 | return -ENODEV; | |
229 | } | |
230 | ||
4707375f AC |
231 | for (nc = 0; nc < count; nc++, offset += 2) { |
232 | cbuf[offset] = addr[nc]; | |
233 | cbuf[offset + 1] = addr[nc] >> 8; | |
234 | } | |
9a58a333 | 235 | |
4707375f AC |
236 | if (id == IPC_CMD_PCNTRL_R) { |
237 | for (nc = 0, offset = 0; nc < count; nc++, offset += 4) | |
238 | ipc_data_writel(wbuf[nc], offset); | |
7c2e3c74 | 239 | ipc_command((count * 2) << 16 | id << 12 | 0 << 8 | op); |
4707375f AC |
240 | } else if (id == IPC_CMD_PCNTRL_W) { |
241 | for (nc = 0; nc < count; nc++, offset += 1) | |
242 | cbuf[offset] = data[nc]; | |
243 | for (nc = 0, offset = 0; nc < count; nc++, offset += 4) | |
244 | ipc_data_writel(wbuf[nc], offset); | |
7c2e3c74 | 245 | ipc_command((count * 3) << 16 | id << 12 | 0 << 8 | op); |
4707375f AC |
246 | } else if (id == IPC_CMD_PCNTRL_M) { |
247 | cbuf[offset] = data[0]; | |
248 | cbuf[offset + 1] = data[1]; | |
249 | ipc_data_writel(wbuf[0], 0); /* Write wbuff */ | |
7c2e3c74 | 250 | ipc_command(4 << 16 | id << 12 | 0 << 8 | op); |
e3359fd5 | 251 | } |
9a58a333 | 252 | |
ed12f295 | 253 | err = intel_scu_ipc_check_status(); |
c7094d1d | 254 | if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */ |
9a58a333 | 255 | /* Workaround: values are read as 0 without memcpy_fromio */ |
e3359fd5 | 256 | memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16); |
4707375f AC |
257 | for (nc = 0; nc < count; nc++) |
258 | data[nc] = ipc_data_readb(nc); | |
9a58a333 SD |
259 | } |
260 | mutex_unlock(&ipclock); | |
261 | return err; | |
262 | } | |
263 | ||
264 | /** | |
265 | * intel_scu_ipc_ioread8 - read a word via the SCU | |
266 | * @addr: register on SCU | |
267 | * @data: return pointer for read byte | |
268 | * | |
269 | * Read a single register. Returns 0 on success or an error code. All | |
270 | * locking between SCU accesses is handled for the caller. | |
271 | * | |
272 | * This function may sleep. | |
273 | */ | |
274 | int intel_scu_ipc_ioread8(u16 addr, u8 *data) | |
275 | { | |
276 | return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
277 | } | |
278 | EXPORT_SYMBOL(intel_scu_ipc_ioread8); | |
279 | ||
280 | /** | |
281 | * intel_scu_ipc_ioread16 - read a word via the SCU | |
282 | * @addr: register on SCU | |
283 | * @data: return pointer for read word | |
284 | * | |
285 | * Read a register pair. Returns 0 on success or an error code. All | |
286 | * locking between SCU accesses is handled for the caller. | |
287 | * | |
288 | * This function may sleep. | |
289 | */ | |
290 | int intel_scu_ipc_ioread16(u16 addr, u16 *data) | |
291 | { | |
7c2e3c74 | 292 | u16 x[2] = {addr, addr + 1}; |
9a58a333 SD |
293 | return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); |
294 | } | |
295 | EXPORT_SYMBOL(intel_scu_ipc_ioread16); | |
296 | ||
297 | /** | |
298 | * intel_scu_ipc_ioread32 - read a dword via the SCU | |
299 | * @addr: register on SCU | |
300 | * @data: return pointer for read dword | |
301 | * | |
302 | * Read four registers. Returns 0 on success or an error code. All | |
303 | * locking between SCU accesses is handled for the caller. | |
304 | * | |
305 | * This function may sleep. | |
306 | */ | |
307 | int intel_scu_ipc_ioread32(u16 addr, u32 *data) | |
308 | { | |
309 | u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; | |
310 | return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
311 | } | |
312 | EXPORT_SYMBOL(intel_scu_ipc_ioread32); | |
313 | ||
314 | /** | |
315 | * intel_scu_ipc_iowrite8 - write a byte via the SCU | |
316 | * @addr: register on SCU | |
317 | * @data: byte to write | |
318 | * | |
319 | * Write a single register. Returns 0 on success or an error code. All | |
320 | * locking between SCU accesses is handled for the caller. | |
321 | * | |
322 | * This function may sleep. | |
323 | */ | |
324 | int intel_scu_ipc_iowrite8(u16 addr, u8 data) | |
325 | { | |
326 | return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
327 | } | |
328 | EXPORT_SYMBOL(intel_scu_ipc_iowrite8); | |
329 | ||
330 | /** | |
331 | * intel_scu_ipc_iowrite16 - write a word via the SCU | |
332 | * @addr: register on SCU | |
333 | * @data: word to write | |
334 | * | |
335 | * Write two registers. Returns 0 on success or an error code. All | |
336 | * locking between SCU accesses is handled for the caller. | |
337 | * | |
338 | * This function may sleep. | |
339 | */ | |
340 | int intel_scu_ipc_iowrite16(u16 addr, u16 data) | |
341 | { | |
7c2e3c74 | 342 | u16 x[2] = {addr, addr + 1}; |
9a58a333 SD |
343 | return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); |
344 | } | |
345 | EXPORT_SYMBOL(intel_scu_ipc_iowrite16); | |
346 | ||
347 | /** | |
348 | * intel_scu_ipc_iowrite32 - write a dword via the SCU | |
349 | * @addr: register on SCU | |
350 | * @data: dword to write | |
351 | * | |
352 | * Write four registers. Returns 0 on success or an error code. All | |
353 | * locking between SCU accesses is handled for the caller. | |
354 | * | |
355 | * This function may sleep. | |
356 | */ | |
357 | int intel_scu_ipc_iowrite32(u16 addr, u32 data) | |
358 | { | |
359 | u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; | |
360 | return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
361 | } | |
362 | EXPORT_SYMBOL(intel_scu_ipc_iowrite32); | |
363 | ||
364 | /** | |
365 | * intel_scu_ipc_readvv - read a set of registers | |
366 | * @addr: register list | |
367 | * @data: bytes to return | |
368 | * @len: length of array | |
369 | * | |
370 | * Read registers. Returns 0 on success or an error code. All | |
371 | * locking between SCU accesses is handled for the caller. | |
372 | * | |
373 | * The largest array length permitted by the hardware is 5 items. | |
374 | * | |
375 | * This function may sleep. | |
376 | */ | |
377 | int intel_scu_ipc_readv(u16 *addr, u8 *data, int len) | |
378 | { | |
379 | return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
380 | } | |
381 | EXPORT_SYMBOL(intel_scu_ipc_readv); | |
382 | ||
383 | /** | |
384 | * intel_scu_ipc_writev - write a set of registers | |
385 | * @addr: register list | |
386 | * @data: bytes to write | |
387 | * @len: length of array | |
388 | * | |
389 | * Write registers. Returns 0 on success or an error code. All | |
390 | * locking between SCU accesses is handled for the caller. | |
391 | * | |
392 | * The largest array length permitted by the hardware is 5 items. | |
393 | * | |
394 | * This function may sleep. | |
395 | * | |
396 | */ | |
397 | int intel_scu_ipc_writev(u16 *addr, u8 *data, int len) | |
398 | { | |
399 | return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
400 | } | |
401 | EXPORT_SYMBOL(intel_scu_ipc_writev); | |
402 | ||
9a58a333 SD |
403 | /** |
404 | * intel_scu_ipc_update_register - r/m/w a register | |
405 | * @addr: register address | |
406 | * @bits: bits to update | |
407 | * @mask: mask of bits to update | |
408 | * | |
409 | * Read-modify-write power control unit register. The first data argument | |
410 | * must be register value and second is mask value | |
411 | * mask is a bitmap that indicates which bits to update. | |
412 | * 0 = masked. Don't modify this bit, 1 = modify this bit. | |
413 | * returns 0 on success or an error code. | |
414 | * | |
415 | * This function may sleep. Locking between SCU accesses is handled | |
416 | * for the caller. | |
417 | */ | |
418 | int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask) | |
419 | { | |
420 | u8 data[2] = { bits, mask }; | |
421 | return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M); | |
422 | } | |
423 | EXPORT_SYMBOL(intel_scu_ipc_update_register); | |
424 | ||
9a58a333 SD |
425 | /** |
426 | * intel_scu_ipc_simple_command - send a simple command | |
427 | * @cmd: command | |
428 | * @sub: sub type | |
429 | * | |
430 | * Issue a simple command to the SCU. Do not use this interface if | |
431 | * you must then access data as any data values may be overwritten | |
432 | * by another SCU access by the time this function returns. | |
433 | * | |
434 | * This function may sleep. Locking for SCU accesses is handled for | |
435 | * the caller. | |
436 | */ | |
437 | int intel_scu_ipc_simple_command(int cmd, int sub) | |
438 | { | |
ecb5646c | 439 | int err; |
9a58a333 SD |
440 | |
441 | mutex_lock(&ipclock); | |
442 | if (ipcdev.pdev == NULL) { | |
443 | mutex_unlock(&ipclock); | |
444 | return -ENODEV; | |
445 | } | |
b4fd4f89 | 446 | ipc_command(sub << 12 | cmd); |
ed12f295 | 447 | err = intel_scu_ipc_check_status(); |
9a58a333 SD |
448 | mutex_unlock(&ipclock); |
449 | return err; | |
450 | } | |
451 | EXPORT_SYMBOL(intel_scu_ipc_simple_command); | |
452 | ||
453 | /** | |
454 | * intel_scu_ipc_command - command with data | |
455 | * @cmd: command | |
456 | * @sub: sub type | |
457 | * @in: input data | |
b4fd4f89 | 458 | * @inlen: input length in dwords |
9a58a333 | 459 | * @out: output data |
b4fd4f89 | 460 | * @outlein: output length in dwords |
9a58a333 SD |
461 | * |
462 | * Issue a command to the SCU which involves data transfers. Do the | |
463 | * data copies under the lock but leave it for the caller to interpret | |
464 | */ | |
9a58a333 | 465 | int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen, |
7c2e3c74 | 466 | u32 *out, int outlen) |
9a58a333 | 467 | { |
ecb5646c | 468 | int i, err; |
9a58a333 SD |
469 | |
470 | mutex_lock(&ipclock); | |
471 | if (ipcdev.pdev == NULL) { | |
472 | mutex_unlock(&ipclock); | |
473 | return -ENODEV; | |
474 | } | |
475 | ||
476 | for (i = 0; i < inlen; i++) | |
477 | ipc_data_writel(*in++, 4 * i); | |
478 | ||
5aa06930 | 479 | ipc_command((inlen << 16) | (sub << 12) | cmd); |
ed12f295 | 480 | err = intel_scu_ipc_check_status(); |
9a58a333 | 481 | |
c7094d1d KS |
482 | if (!err) { |
483 | for (i = 0; i < outlen; i++) | |
484 | *out++ = ipc_data_readl(4 * i); | |
485 | } | |
9a58a333 SD |
486 | |
487 | mutex_unlock(&ipclock); | |
488 | return err; | |
489 | } | |
490 | EXPORT_SYMBOL(intel_scu_ipc_command); | |
491 | ||
7c2e3c74 | 492 | /* I2C commands */ |
9a58a333 SD |
493 | #define IPC_I2C_WRITE 1 /* I2C Write command */ |
494 | #define IPC_I2C_READ 2 /* I2C Read command */ | |
495 | ||
496 | /** | |
497 | * intel_scu_ipc_i2c_cntrl - I2C read/write operations | |
498 | * @addr: I2C address + command bits | |
499 | * @data: data to read/write | |
500 | * | |
501 | * Perform an an I2C read/write operation via the SCU. All locking is | |
502 | * handled for the caller. This function may sleep. | |
503 | * | |
504 | * Returns an error code or 0 on success. | |
505 | * | |
506 | * This has to be in the IPC driver for the locking. | |
507 | */ | |
508 | int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data) | |
509 | { | |
510 | u32 cmd = 0; | |
511 | ||
512 | mutex_lock(&ipclock); | |
b4fd4f89 SD |
513 | if (ipcdev.pdev == NULL) { |
514 | mutex_unlock(&ipclock); | |
515 | return -ENODEV; | |
516 | } | |
9a58a333 SD |
517 | cmd = (addr >> 24) & 0xFF; |
518 | if (cmd == IPC_I2C_READ) { | |
519 | writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); | |
520 | /* Write not getting updated without delay */ | |
521 | mdelay(1); | |
522 | *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR); | |
523 | } else if (cmd == IPC_I2C_WRITE) { | |
32e2f63b | 524 | writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR); |
9a58a333 SD |
525 | mdelay(1); |
526 | writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); | |
527 | } else { | |
528 | dev_err(&ipcdev.pdev->dev, | |
529 | "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd); | |
530 | ||
531 | mutex_unlock(&ipclock); | |
5369c02d | 532 | return -EIO; |
9a58a333 SD |
533 | } |
534 | mutex_unlock(&ipclock); | |
535 | return 0; | |
536 | } | |
537 | EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl); | |
538 | ||
9a58a333 SD |
539 | /* |
540 | * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1 | |
541 | * When ioc bit is set to 1, caller api must wait for interrupt handler called | |
542 | * which in turn unlocks the caller api. Currently this is not used | |
543 | * | |
544 | * This is edge triggered so we need take no action to clear anything | |
545 | */ | |
546 | static irqreturn_t ioc(int irq, void *dev_id) | |
547 | { | |
ed12f295 KS |
548 | if (ipcdev.irq_mode) |
549 | complete(&ipcdev.cmd_complete); | |
550 | ||
9a58a333 SD |
551 | return IRQ_HANDLED; |
552 | } | |
553 | ||
554 | /** | |
555 | * ipc_probe - probe an Intel SCU IPC | |
556 | * @dev: the PCI device matching | |
557 | * @id: entry in the match table | |
558 | * | |
559 | * Enable and install an intel SCU IPC. This appears in the PCI space | |
560 | * but uses some hard coded addresses as well. | |
561 | */ | |
562 | static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
563 | { | |
694e523c | 564 | int err; |
e97a1c98 | 565 | struct intel_scu_ipc_pdata_t *pdata; |
32d0e4a3 | 566 | resource_size_t base; |
9a58a333 SD |
567 | |
568 | if (ipcdev.pdev) /* We support only one SCU */ | |
569 | return -EBUSY; | |
570 | ||
694e523c | 571 | pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data; |
e97a1c98 | 572 | |
9a58a333 | 573 | ipcdev.pdev = pci_dev_get(dev); |
ed12f295 | 574 | ipcdev.irq_mode = pdata->irq_mode; |
9a58a333 SD |
575 | |
576 | err = pci_enable_device(dev); | |
577 | if (err) | |
578 | return err; | |
579 | ||
580 | err = pci_request_regions(dev, "intel_scu_ipc"); | |
581 | if (err) | |
582 | return err; | |
583 | ||
32d0e4a3 AS |
584 | base = pci_resource_start(dev, 0); |
585 | if (!base) | |
9a58a333 SD |
586 | return -ENOMEM; |
587 | ||
ed12f295 KS |
588 | init_completion(&ipcdev.cmd_complete); |
589 | ||
9a58a333 SD |
590 | if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev)) |
591 | return -EBUSY; | |
592 | ||
32d0e4a3 | 593 | ipcdev.ipc_base = ioremap_nocache(base, pci_resource_len(dev, 0)); |
9a58a333 SD |
594 | if (!ipcdev.ipc_base) |
595 | return -ENOMEM; | |
596 | ||
e97a1c98 | 597 | ipcdev.i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len); |
9a58a333 SD |
598 | if (!ipcdev.i2c_base) { |
599 | iounmap(ipcdev.ipc_base); | |
600 | return -ENOMEM; | |
601 | } | |
1da4b1c6 FT |
602 | |
603 | intel_scu_devices_create(); | |
604 | ||
9a58a333 SD |
605 | return 0; |
606 | } | |
607 | ||
608 | /** | |
609 | * ipc_remove - remove a bound IPC device | |
610 | * @pdev: PCI device | |
611 | * | |
612 | * In practice the SCU is not removable but this function is also | |
613 | * called for each device on a module unload or cleanup which is the | |
614 | * path that will get used. | |
615 | * | |
616 | * Free up the mappings and release the PCI resources | |
617 | */ | |
618 | static void ipc_remove(struct pci_dev *pdev) | |
619 | { | |
620 | free_irq(pdev->irq, &ipcdev); | |
621 | pci_release_regions(pdev); | |
622 | pci_dev_put(ipcdev.pdev); | |
623 | iounmap(ipcdev.ipc_base); | |
624 | iounmap(ipcdev.i2c_base); | |
625 | ipcdev.pdev = NULL; | |
1da4b1c6 | 626 | intel_scu_devices_destroy(); |
9a58a333 SD |
627 | } |
628 | ||
9baa3c34 | 629 | static const struct pci_device_id pci_ids[] = { |
694e523c | 630 | { |
b4b0b4a9 | 631 | PCI_VDEVICE(INTEL, PCI_DEVICE_ID_LINCROFT), |
694e523c DC |
632 | (kernel_ulong_t)&intel_scu_ipc_lincroft_pdata, |
633 | }, { | |
b4b0b4a9 | 634 | PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), |
694e523c DC |
635 | (kernel_ulong_t)&intel_scu_ipc_penwell_pdata, |
636 | }, { | |
b4b0b4a9 | 637 | PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CLOVERVIEW), |
694e523c DC |
638 | (kernel_ulong_t)&intel_scu_ipc_penwell_pdata, |
639 | }, { | |
b4b0b4a9 | 640 | PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), |
694e523c DC |
641 | (kernel_ulong_t)&intel_scu_ipc_tangier_pdata, |
642 | }, { | |
643 | 0, | |
644 | } | |
9a58a333 SD |
645 | }; |
646 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
647 | ||
648 | static struct pci_driver ipc_driver = { | |
649 | .name = "intel_scu_ipc", | |
650 | .id_table = pci_ids, | |
651 | .probe = ipc_probe, | |
652 | .remove = ipc_remove, | |
653 | }; | |
654 | ||
9a58a333 SD |
655 | static int __init intel_scu_ipc_init(void) |
656 | { | |
7c2e3c74 AS |
657 | int platform; /* Platform type */ |
658 | ||
712b6aa8 | 659 | platform = intel_mid_identify_cpu(); |
9dd3adeb AC |
660 | if (platform == 0) |
661 | return -ENODEV; | |
9a58a333 SD |
662 | return pci_register_driver(&ipc_driver); |
663 | } | |
664 | ||
665 | static void __exit intel_scu_ipc_exit(void) | |
666 | { | |
667 | pci_unregister_driver(&ipc_driver); | |
668 | } | |
669 | ||
670 | MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>"); | |
671 | MODULE_DESCRIPTION("Intel SCU IPC driver"); | |
672 | MODULE_LICENSE("GPL"); | |
673 | ||
674 | module_init(intel_scu_ipc_init); | |
675 | module_exit(intel_scu_ipc_exit); |