[linux-2.6-block.git] / drivers / phy / phy-rcar-gen3-usb2.c

/*
 * Renesas R-Car Gen3 for USB2.0 PHY driver
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 *
 * This is based on the phy-rcar-gen2 driver:
 * Copyright (C) 2014 Renesas Solutions Corp.
 * Copyright (C) 2014 Cogent Embedded, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/extcon.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>

/******* USB2.0 Host registers (original offset is +0x200) *******/
#define USB2_INT_ENABLE		0x000
#define USB2_USBCTR		0x00c
#define USB2_SPD_RSM_TIMSET	0x10c
#define USB2_OC_TIMSET		0x110
#define USB2_COMMCTRL		0x600
#define USB2_OBINTSTA		0x604
#define USB2_OBINTEN		0x608
#define USB2_VBCTRL		0x60c
#define USB2_LINECTRL1		0x610
#define USB2_ADPCTRL		0x630

/* INT_ENABLE */
#define USB2_INT_ENABLE_UCOM_INTEN	BIT(3)
#define USB2_INT_ENABLE_USBH_INTB_EN	BIT(2)
#define USB2_INT_ENABLE_USBH_INTA_EN	BIT(1)
#define USB2_INT_ENABLE_INIT		(USB2_INT_ENABLE_UCOM_INTEN | \
					 USB2_INT_ENABLE_USBH_INTB_EN | \
					 USB2_INT_ENABLE_USBH_INTA_EN)

/* USBCTR */
#define USB2_USBCTR_DIRPD	BIT(2)
#define USB2_USBCTR_PLL_RST	BIT(1)

/* SPD_RSM_TIMSET */
#define USB2_SPD_RSM_TIMSET_INIT	0x014e029b

/* OC_TIMSET */
#define USB2_OC_TIMSET_INIT		0x000209ab

/* COMMCTRL */
#define USB2_COMMCTRL_OTG_PERI		BIT(31)	/* 1 = Peripheral mode */

/* OBINTSTA and OBINTEN */
#define USB2_OBINT_SESSVLDCHG		BIT(12)
#define USB2_OBINT_IDDIGCHG		BIT(11)
#define USB2_OBINT_BITS			(USB2_OBINT_SESSVLDCHG | \
					 USB2_OBINT_IDDIGCHG)

/* VBCTRL */
#define USB2_VBCTRL_DRVVBUSSEL		BIT(8)

/* LINECTRL1 */
#define USB2_LINECTRL1_DPRPD_EN		BIT(19)
#define USB2_LINECTRL1_DP_RPD		BIT(18)
#define USB2_LINECTRL1_DMRPD_EN		BIT(17)
#define USB2_LINECTRL1_DM_RPD		BIT(16)

/* ADPCTRL */
#define USB2_ADPCTRL_OTGSESSVLD		BIT(20)
#define USB2_ADPCTRL_IDDIG		BIT(19)
#define USB2_ADPCTRL_IDPULLUP		BIT(5)	/* 1 = ID sampling is enabled */
#define USB2_ADPCTRL_DRVVBUS		BIT(4)

struct rcar_gen3_chan {
	void __iomem *base;
	struct extcon_dev *extcon;
	struct phy *phy;
	struct regulator *vbus;
	bool has_otg;
};

static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
{
	void __iomem *usb2_base = ch->base;
	u32 val = readl(usb2_base + USB2_COMMCTRL);

	dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, host);
	if (host)
		val &= ~USB2_COMMCTRL_OTG_PERI;
	else
		val |= USB2_COMMCTRL_OTG_PERI;
	writel(val, usb2_base + USB2_COMMCTRL);
}

static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
{
	void __iomem *usb2_base = ch->base;
	u32 val = readl(usb2_base + USB2_LINECTRL1);

	dev_vdbg(&ch->phy->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm);
	val &= ~(USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
	if (dp)
		val |= USB2_LINECTRL1_DP_RPD;
	if (dm)
		val |= USB2_LINECTRL1_DM_RPD;
	writel(val, usb2_base + USB2_LINECTRL1);
}

static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
{
	void __iomem *usb2_base = ch->base;
	u32 val = readl(usb2_base + USB2_ADPCTRL);

	dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, vbus);
	if (vbus)
		val |= USB2_ADPCTRL_DRVVBUS;
	else
		val &= ~USB2_ADPCTRL_DRVVBUS;
	writel(val, usb2_base + USB2_ADPCTRL);
}

static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch)
{
	rcar_gen3_set_linectrl(ch, 1, 1);
	rcar_gen3_set_host_mode(ch, 1);
	rcar_gen3_enable_vbus_ctrl(ch, 1);

	extcon_set_cable_state_(ch->extcon, EXTCON_USB_HOST, true);
	extcon_set_cable_state_(ch->extcon, EXTCON_USB, false);
}

static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch)
{
	rcar_gen3_set_linectrl(ch, 0, 1);
	rcar_gen3_set_host_mode(ch, 0);
	rcar_gen3_enable_vbus_ctrl(ch, 0);

	extcon_set_cable_state_(ch->extcon, EXTCON_USB_HOST, false);
	extcon_set_cable_state_(ch->extcon, EXTCON_USB, true);
}

static bool rcar_gen3_check_vbus(struct rcar_gen3_chan *ch)
{
	return !!(readl(ch->base + USB2_ADPCTRL) &
		  USB2_ADPCTRL_OTGSESSVLD);
}

static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
{
	return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
}

static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch)
{
	bool is_host = true;

	/* B-device? */
	if (rcar_gen3_check_id(ch) && rcar_gen3_check_vbus(ch))
		is_host = false;

	if (is_host)
		rcar_gen3_init_for_host(ch);
	else
		rcar_gen3_init_for_peri(ch);
}

static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
{
	void __iomem *usb2_base = ch->base;
	u32 val;

	val = readl(usb2_base + USB2_VBCTRL);
	writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
	writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
	val = readl(usb2_base + USB2_OBINTEN);
	writel(val | USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
	val = readl(usb2_base + USB2_ADPCTRL);
	writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
	val = readl(usb2_base + USB2_LINECTRL1);
	rcar_gen3_set_linectrl(ch, 0, 0);
	writel(val | USB2_LINECTRL1_DPRPD_EN | USB2_LINECTRL1_DMRPD_EN,
	       usb2_base + USB2_LINECTRL1);

	rcar_gen3_device_recognition(ch);
}

static int rcar_gen3_phy_usb2_init(struct phy *p)
{
	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	void __iomem *usb2_base = channel->base;

	/* Initialize USB2 part */
	writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
	writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
	writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);

	/* Initialize otg part */
	if (channel->has_otg)
		rcar_gen3_init_otg(channel);

	return 0;
}

static int rcar_gen3_phy_usb2_exit(struct phy *p)
{
	struct rcar_gen3_chan *channel = phy_get_drvdata(p);

	writel(0, channel->base + USB2_INT_ENABLE);

	return 0;
}

static int rcar_gen3_phy_usb2_power_on(struct phy *p)
{
	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	void __iomem *usb2_base = channel->base;
	u32 val;
	int ret;

	if (channel->vbus) {
		ret = regulator_enable(channel->vbus);
		if (ret)
			return ret;
	}

	val = readl(usb2_base + USB2_USBCTR);
	val |= USB2_USBCTR_PLL_RST;
	writel(val, usb2_base + USB2_USBCTR);
	val &= ~USB2_USBCTR_PLL_RST;
	writel(val, usb2_base + USB2_USBCTR);

	return 0;
}

static int rcar_gen3_phy_usb2_power_off(struct phy *p)
{
	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	int ret = 0;

	if (channel->vbus)
		ret = regulator_disable(channel->vbus);

	return ret;
}

static struct phy_ops rcar_gen3_phy_usb2_ops = {
	.init		= rcar_gen3_phy_usb2_init,
	.exit		= rcar_gen3_phy_usb2_exit,
	.power_on	= rcar_gen3_phy_usb2_power_on,
	.power_off	= rcar_gen3_phy_usb2_power_off,
	.owner		= THIS_MODULE,
};

static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
{
	struct rcar_gen3_chan *ch = _ch;
	void __iomem *usb2_base = ch->base;
	u32 status = readl(usb2_base + USB2_OBINTSTA);
	irqreturn_t ret = IRQ_NONE;

	if (status & USB2_OBINT_BITS) {
		dev_vdbg(&ch->phy->dev, "%s: %08x\n", __func__, status);
		writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
		rcar_gen3_device_recognition(ch);
		ret = IRQ_HANDLED;
	}

	return ret;
}

static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
	{ .compatible = "renesas,usb2-phy-r8a7795" },
	{ .compatible = "renesas,rcar-gen3-usb2-phy" },
	{ }
};
MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);

static const unsigned int rcar_gen3_phy_cable[] = {
	EXTCON_USB,
	EXTCON_USB_HOST,
	EXTCON_NONE,
};

static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct rcar_gen3_chan *channel;
	struct phy_provider *provider;
	struct resource *res;
	int irq;

	if (!dev->of_node) {
		dev_err(dev, "This driver needs device tree\n");
		return -EINVAL;
	}

	channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL);
	if (!channel)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	channel->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(channel->base))
		return PTR_ERR(channel->base);

	/* call request_irq for OTG */
	irq = platform_get_irq(pdev, 0);
	if (irq >= 0) {
		int ret;

		irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
				       IRQF_SHARED, dev_name(dev), channel);
		if (irq < 0)
			dev_err(dev, "No irq handler (%d)\n", irq);
		channel->has_otg = true;
		channel->extcon = devm_extcon_dev_allocate(dev,
							rcar_gen3_phy_cable);
		if (IS_ERR(channel->extcon))
			return PTR_ERR(channel->extcon);

		ret = devm_extcon_dev_register(dev, channel->extcon);
		if (ret < 0) {
			dev_err(dev, "Failed to register extcon\n");
			return ret;
		}
	}

	/* devm_phy_create() will call pm_runtime_enable(dev); */
	channel->phy = devm_phy_create(dev, NULL, &rcar_gen3_phy_usb2_ops);
	if (IS_ERR(channel->phy)) {
		dev_err(dev, "Failed to create USB2 PHY\n");
		return PTR_ERR(channel->phy);
	}

	channel->vbus = devm_regulator_get_optional(dev, "vbus");
	if (IS_ERR(channel->vbus)) {
		if (PTR_ERR(channel->vbus) == -EPROBE_DEFER)
			return PTR_ERR(channel->vbus);
		channel->vbus = NULL;
	}

	phy_set_drvdata(channel->phy, channel);

	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	if (IS_ERR(provider))
		dev_err(dev, "Failed to register PHY provider\n");

	return PTR_ERR_OR_ZERO(provider);
}

static struct platform_driver rcar_gen3_phy_usb2_driver = {
	.driver = {
		.name		= "phy_rcar_gen3_usb2",
		.of_match_table	= rcar_gen3_phy_usb2_match_table,
	},
	.probe	= rcar_gen3_phy_usb2_probe,
};
module_platform_driver(rcar_gen3_phy_usb2_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY");
MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
Commit	Line	Data
f3b5a8d9 YS	1	/*
	2	* Renesas R-Car Gen3 for USB2.0 PHY driver
	3	*
	4	* Copyright (C) 2015 Renesas Electronics Corporation
	5	*
	6	* This is based on the phy-rcar-gen2 driver:
	7	* Copyright (C) 2014 Renesas Solutions Corp.
	8	* Copyright (C) 2014 Cogent Embedded, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
2b38543c	15	#include <linux/extcon.h>
9f391c57	16	#include <linux/interrupt.h>
f3b5a8d9 YS	17	#include <linux/io.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_address.h>
	21	#include <linux/phy/phy.h>
	22	#include <linux/platform_device.h>
6dcfd7c3	23	#include <linux/regulator/consumer.h>
f3b5a8d9 YS	24
	25	/***** USB2.0 Host registers (original offset is +0x200) *****/
	26	#define USB2_INT_ENABLE 0x000
	27	#define USB2_USBCTR 0x00c
	28	#define USB2_SPD_RSM_TIMSET 0x10c
	29	#define USB2_OC_TIMSET 0x110
1114e2d3	30	#define USB2_COMMCTRL 0x600
9f391c57 YS	31	#define USB2_OBINTSTA 0x604
9f391c57 YS	32	#define USB2_OBINTEN 0x608
1114e2d3 YS	33	#define USB2_VBCTRL 0x60c
	34	#define USB2_LINECTRL1 0x610
	35	#define USB2_ADPCTRL 0x630
f3b5a8d9 YS	36
f3b5a8d9 YS	37	/* INT_ENABLE */
9f391c57	38	#define USB2_INT_ENABLE_UCOM_INTEN BIT(3)
f3b5a8d9 YS	39	#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2)
f3b5a8d9 YS	40	#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1)
9f391c57 YS	41	#define USB2_INT_ENABLE_INIT (USB2_INT_ENABLE_UCOM_INTEN \| \
9f391c57 YS	42	USB2_INT_ENABLE_USBH_INTB_EN \| \
f3b5a8d9 YS	43	USB2_INT_ENABLE_USBH_INTA_EN)
	44
	45	/* USBCTR */
	46	#define USB2_USBCTR_DIRPD BIT(2)
	47	#define USB2_USBCTR_PLL_RST BIT(1)
	48
	49	/* SPD_RSM_TIMSET */
	50	#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
	51
	52	/* OC_TIMSET */
	53	#define USB2_OC_TIMSET_INIT 0x000209ab
	54
1114e2d3 YS	55	/* COMMCTRL */
	56	#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
	57
9f391c57 YS	58	/* OBINTSTA and OBINTEN */
	59	#define USB2_OBINT_SESSVLDCHG BIT(12)
	60	#define USB2_OBINT_IDDIGCHG BIT(11)
	61	#define USB2_OBINT_BITS (USB2_OBINT_SESSVLDCHG \| \
	62	USB2_OBINT_IDDIGCHG)
	63
1114e2d3 YS	64	/* VBCTRL */
	65	#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
	66
	67	/* LINECTRL1 */
	68	#define USB2_LINECTRL1_DPRPD_EN BIT(19)
	69	#define USB2_LINECTRL1_DP_RPD BIT(18)
	70	#define USB2_LINECTRL1_DMRPD_EN BIT(17)
	71	#define USB2_LINECTRL1_DM_RPD BIT(16)
	72
	73	/* ADPCTRL */
	74	#define USB2_ADPCTRL_OTGSESSVLD BIT(20)
	75	#define USB2_ADPCTRL_IDDIG BIT(19)
	76	#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
	77	#define USB2_ADPCTRL_DRVVBUS BIT(4)
	78
f3b5a8d9	79	struct rcar_gen3_chan {
801a69c7	80	void __iomem *base;
2b38543c	81	struct extcon_dev *extcon;
f3b5a8d9	82	struct phy *phy;
6dcfd7c3	83	struct regulator *vbus;
b9564016	84	bool has_otg;
f3b5a8d9 YS	85	};
f3b5a8d9 YS	86
1114e2d3 YS	87	static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
1114e2d3 YS	88	{
801a69c7	89	void __iomem *usb2_base = ch->base;
1114e2d3 YS	90	u32 val = readl(usb2_base + USB2_COMMCTRL);
	91
	92	dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, host);
	93	if (host)
	94	val &= ~USB2_COMMCTRL_OTG_PERI;
	95	else
	96	val \|= USB2_COMMCTRL_OTG_PERI;
	97	writel(val, usb2_base + USB2_COMMCTRL);
	98	}
	99
	100	static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
	101	{
801a69c7	102	void __iomem *usb2_base = ch->base;
1114e2d3 YS	103	u32 val = readl(usb2_base + USB2_LINECTRL1);
	104
	105	dev_vdbg(&ch->phy->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm);
	106	val &= ~(USB2_LINECTRL1_DP_RPD \| USB2_LINECTRL1_DM_RPD);
	107	if (dp)
	108	val \|= USB2_LINECTRL1_DP_RPD;
	109	if (dm)
	110	val \|= USB2_LINECTRL1_DM_RPD;
	111	writel(val, usb2_base + USB2_LINECTRL1);
	112	}
	113
	114	static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
	115	{
801a69c7	116	void __iomem *usb2_base = ch->base;
1114e2d3 YS	117	u32 val = readl(usb2_base + USB2_ADPCTRL);
	118
	119	dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, vbus);
	120	if (vbus)
	121	val \|= USB2_ADPCTRL_DRVVBUS;
	122	else
	123	val &= ~USB2_ADPCTRL_DRVVBUS;
	124	writel(val, usb2_base + USB2_ADPCTRL);
	125	}
	126
	127	static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch)
	128	{
	129	rcar_gen3_set_linectrl(ch, 1, 1);
	130	rcar_gen3_set_host_mode(ch, 1);
	131	rcar_gen3_enable_vbus_ctrl(ch, 1);
2b38543c YS	132
	133	extcon_set_cable_state_(ch->extcon, EXTCON_USB_HOST, true);
	134	extcon_set_cable_state_(ch->extcon, EXTCON_USB, false);
1114e2d3 YS	135	}
	136
	137	static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch)
	138	{
	139	rcar_gen3_set_linectrl(ch, 0, 1);
	140	rcar_gen3_set_host_mode(ch, 0);
	141	rcar_gen3_enable_vbus_ctrl(ch, 0);
2b38543c YS	142
	143	extcon_set_cable_state_(ch->extcon, EXTCON_USB_HOST, false);
	144	extcon_set_cable_state_(ch->extcon, EXTCON_USB, true);
1114e2d3 YS	145	}
	146
	147	static bool rcar_gen3_check_vbus(struct rcar_gen3_chan *ch)
	148	{
801a69c7	149	return !!(readl(ch->base + USB2_ADPCTRL) &
1114e2d3 YS	150	USB2_ADPCTRL_OTGSESSVLD);
	151	}
	152
	153	static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
	154	{
801a69c7	155	return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
1114e2d3 YS	156	}
	157
	158	static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch)
	159	{
	160	bool is_host = true;
	161
	162	/* B-device? */
	163	if (rcar_gen3_check_id(ch) && rcar_gen3_check_vbus(ch))
	164	is_host = false;
	165
	166	if (is_host)
	167	rcar_gen3_init_for_host(ch);
	168	else
	169	rcar_gen3_init_for_peri(ch);
	170	}
	171
	172	static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
	173	{
801a69c7	174	void __iomem *usb2_base = ch->base;
1114e2d3 YS	175	u32 val;
	176
	177	val = readl(usb2_base + USB2_VBCTRL);
	178	writel(val \| USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
9f391c57 YS	179	writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
	180	val = readl(usb2_base + USB2_OBINTEN);
	181	writel(val \| USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
1114e2d3 YS	182	val = readl(usb2_base + USB2_ADPCTRL);
	183	writel(val \| USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
	184	val = readl(usb2_base + USB2_LINECTRL1);
	185	rcar_gen3_set_linectrl(ch, 0, 0);
	186	writel(val \| USB2_LINECTRL1_DPRPD_EN \| USB2_LINECTRL1_DMRPD_EN,
	187	usb2_base + USB2_LINECTRL1);
	188
	189	rcar_gen3_device_recognition(ch);
	190	}
	191
f3b5a8d9 YS	192	static int rcar_gen3_phy_usb2_init(struct phy *p)
	193	{
	194	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
801a69c7	195	void __iomem *usb2_base = channel->base;
f3b5a8d9 YS	196
	197	/* Initialize USB2 part */
	198	writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
	199	writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
	200	writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
	201
b9564016 YS	202	/* Initialize otg part */
b9564016 YS	203	if (channel->has_otg)
1114e2d3	204	rcar_gen3_init_otg(channel);
f3b5a8d9 YS	205
	206	return 0;
	207	}
	208
	209	static int rcar_gen3_phy_usb2_exit(struct phy *p)
	210	{
	211	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	212
801a69c7	213	writel(0, channel->base + USB2_INT_ENABLE);
f3b5a8d9 YS	214
	215	return 0;
	216	}
	217
	218	static int rcar_gen3_phy_usb2_power_on(struct phy *p)
	219	{
	220	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
801a69c7	221	void __iomem *usb2_base = channel->base;
f3b5a8d9	222	u32 val;
6dcfd7c3 YS	223	int ret;
	224
	225	if (channel->vbus) {
	226	ret = regulator_enable(channel->vbus);
	227	if (ret)
	228	return ret;
	229	}
f3b5a8d9 YS	230
	231	val = readl(usb2_base + USB2_USBCTR);
	232	val \|= USB2_USBCTR_PLL_RST;
	233	writel(val, usb2_base + USB2_USBCTR);
	234	val &= ~USB2_USBCTR_PLL_RST;
	235	writel(val, usb2_base + USB2_USBCTR);
	236
f3b5a8d9 YS	237	return 0;
	238	}
	239
6dcfd7c3 YS	240	static int rcar_gen3_phy_usb2_power_off(struct phy *p)
	241	{
	242	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	243	int ret = 0;
	244
	245	if (channel->vbus)
	246	ret = regulator_disable(channel->vbus);
	247
	248	return ret;
	249	}
	250
f3b5a8d9 YS	251	static struct phy_ops rcar_gen3_phy_usb2_ops = {
	252	.init = rcar_gen3_phy_usb2_init,
	253	.exit = rcar_gen3_phy_usb2_exit,
	254	.power_on = rcar_gen3_phy_usb2_power_on,
6dcfd7c3	255	.power_off = rcar_gen3_phy_usb2_power_off,
f3b5a8d9 YS	256	.owner = THIS_MODULE,
	257	};
	258
9f391c57 YS	259	static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
	260	{
	261	struct rcar_gen3_chan *ch = _ch;
801a69c7	262	void __iomem *usb2_base = ch->base;
9f391c57 YS	263	u32 status = readl(usb2_base + USB2_OBINTSTA);
	264	irqreturn_t ret = IRQ_NONE;
	265
	266	if (status & USB2_OBINT_BITS) {
	267	dev_vdbg(&ch->phy->dev, "%s: %08x\n", __func__, status);
	268	writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
	269	rcar_gen3_device_recognition(ch);
	270	ret = IRQ_HANDLED;
	271	}
	272
	273	return ret;
	274	}
	275
f3b5a8d9 YS	276	static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
f3b5a8d9 YS	277	{ .compatible = "renesas,usb2-phy-r8a7795" },
cde7bc36	278	{ .compatible = "renesas,rcar-gen3-usb2-phy" },
f3b5a8d9 YS	279	{ }
	280	};
	281	MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);
	282
2b38543c YS	283	static const unsigned int rcar_gen3_phy_cable[] = {
	284	EXTCON_USB,
	285	EXTCON_USB_HOST,
	286	EXTCON_NONE,
	287	};
	288
f3b5a8d9 YS	289	static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
	290	{
	291	struct device *dev = &pdev->dev;
	292	struct rcar_gen3_chan *channel;
	293	struct phy_provider *provider;
	294	struct resource *res;
b9564016	295	int irq;
f3b5a8d9 YS	296
	297	if (!dev->of_node) {
	298	dev_err(dev, "This driver needs device tree\n");
	299	return -EINVAL;
	300	}
	301
	302	channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL);
	303	if (!channel)
	304	return -ENOMEM;
	305
b9564016	306	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
801a69c7 YS	307	channel->base = devm_ioremap_resource(dev, res);
	308	if (IS_ERR(channel->base))
	309	return PTR_ERR(channel->base);
f3b5a8d9	310
b9564016 YS	311	/* call request_irq for OTG */
	312	irq = platform_get_irq(pdev, 0);
	313	if (irq >= 0) {
2b38543c YS	314	int ret;
2b38543c YS	315
b9564016 YS	316	irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
b9564016 YS	317	IRQF_SHARED, dev_name(dev), channel);
9f391c57 YS	318	if (irq < 0)
9f391c57 YS	319	dev_err(dev, "No irq handler (%d)\n", irq);
b9564016	320	channel->has_otg = true;
2b38543c YS	321	channel->extcon = devm_extcon_dev_allocate(dev,
	322	rcar_gen3_phy_cable);
	323	if (IS_ERR(channel->extcon))
	324	return PTR_ERR(channel->extcon);
	325
	326	ret = devm_extcon_dev_register(dev, channel->extcon);
	327	if (ret < 0) {
	328	dev_err(dev, "Failed to register extcon\n");
	329	return ret;
	330	}
f3b5a8d9 YS	331	}
	332
	333	/* devm_phy_create() will call pm_runtime_enable(dev); */
	334	channel->phy = devm_phy_create(dev, NULL, &rcar_gen3_phy_usb2_ops);
	335	if (IS_ERR(channel->phy)) {
	336	dev_err(dev, "Failed to create USB2 PHY\n");
	337	return PTR_ERR(channel->phy);
	338	}
	339
6dcfd7c3 YS	340	channel->vbus = devm_regulator_get_optional(dev, "vbus");
	341	if (IS_ERR(channel->vbus)) {
	342	if (PTR_ERR(channel->vbus) == -EPROBE_DEFER)
	343	return PTR_ERR(channel->vbus);
	344	channel->vbus = NULL;
	345	}
	346
f3b5a8d9 YS	347	phy_set_drvdata(channel->phy, channel);
	348
	349	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	350	if (IS_ERR(provider))
	351	dev_err(dev, "Failed to register PHY provider\n");
	352
	353	return PTR_ERR_OR_ZERO(provider);
	354	}
	355
	356	static struct platform_driver rcar_gen3_phy_usb2_driver = {
	357	.driver = {
	358	.name = "phy_rcar_gen3_usb2",
	359	.of_match_table = rcar_gen3_phy_usb2_match_table,
	360	},
	361	.probe = rcar_gen3_phy_usb2_probe,
	362	};
	363	module_platform_driver(rcar_gen3_phy_usb2_driver);
	364
	365	MODULE_LICENSE("GPL v2");
	366	MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY");
	367	MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");