projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 39e794bf YG |
1 | /* |
| 2 | * Copyright (c) 2013-2015, Linux Foundation. All rights reserved. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 and | |
| 6 | * only version 2 as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope that it will be useful, | |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 11 | * GNU General Public License for more details. | |
| 12 | * | |
| 13 | */ | |
| 14 | ||
| 15 | #ifndef UFS_QCOM_PHY_QMP_20NM_H_ | |
| 16 | #define UFS_QCOM_PHY_QMP_20NM_H_ | |
| 17 | ||
| 18 | #include "phy-qcom-ufs-i.h" | |
| 19 | ||
| 20 | /* QCOM UFS PHY control registers */ | |
| 21 | ||
| 22 | #define COM_OFF(x) (0x000 + x) | |
| 23 | #define PHY_OFF(x) (0xC00 + x) | |
| 24 | #define TX_OFF(n, x) (0x400 + (0x400 * n) + x) | |
| 25 | #define RX_OFF(n, x) (0x600 + (0x400 * n) + x) | |
| 26 | ||
| 27 | /* UFS PHY PLL block registers */ | |
| 28 | #define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x0) | |
| 29 | #define QSERDES_COM_PLL_VCOTAIL_EN COM_OFF(0x04) | |
| 30 | #define QSERDES_COM_PLL_CNTRL COM_OFF(0x14) | |
| 31 | #define QSERDES_COM_PLL_IP_SETI COM_OFF(0x24) | |
| 32 | #define QSERDES_COM_CORE_CLK_IN_SYNC_SEL COM_OFF(0x28) | |
| 33 | #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x30) | |
| 34 | #define QSERDES_COM_PLL_CP_SETI COM_OFF(0x34) | |
| 35 | #define QSERDES_COM_PLL_IP_SETP COM_OFF(0x38) | |
| 36 | #define QSERDES_COM_PLL_CP_SETP COM_OFF(0x3C) | |
| 37 | #define QSERDES_COM_SYSCLK_EN_SEL_TXBAND COM_OFF(0x48) | |
| 38 | #define QSERDES_COM_RESETSM_CNTRL COM_OFF(0x4C) | |
| 39 | #define QSERDES_COM_RESETSM_CNTRL2 COM_OFF(0x50) | |
| 40 | #define QSERDES_COM_PLLLOCK_CMP1 COM_OFF(0x90) | |
| 41 | #define QSERDES_COM_PLLLOCK_CMP2 COM_OFF(0x94) | |
| 42 | #define QSERDES_COM_PLLLOCK_CMP3 COM_OFF(0x98) | |
| 43 | #define QSERDES_COM_PLLLOCK_CMP_EN COM_OFF(0x9C) | |
| 44 | #define QSERDES_COM_BGTC COM_OFF(0xA0) | |
| 45 | #define QSERDES_COM_DEC_START1 COM_OFF(0xAC) | |
| 46 | #define QSERDES_COM_PLL_AMP_OS COM_OFF(0xB0) | |
| 47 | #define QSERDES_COM_RES_CODE_UP_OFFSET COM_OFF(0xD8) | |
| 48 | #define QSERDES_COM_RES_CODE_DN_OFFSET COM_OFF(0xDC) | |
| 49 | #define QSERDES_COM_DIV_FRAC_START1 COM_OFF(0x100) | |
| 50 | #define QSERDES_COM_DIV_FRAC_START2 COM_OFF(0x104) | |
| 51 | #define QSERDES_COM_DIV_FRAC_START3 COM_OFF(0x108) | |
| 52 | #define QSERDES_COM_DEC_START2 COM_OFF(0x10C) | |
| 53 | #define QSERDES_COM_PLL_RXTXEPCLK_EN COM_OFF(0x110) | |
| 54 | #define QSERDES_COM_PLL_CRCTRL COM_OFF(0x114) | |
| 55 | #define QSERDES_COM_PLL_CLKEPDIV COM_OFF(0x118) | |
| 56 | ||
| 57 | /* TX LANE n (0, 1) registers */ | |
| 58 | #define QSERDES_TX_EMP_POST1_LVL(n) TX_OFF(n, 0x08) | |
| 59 | #define QSERDES_TX_DRV_LVL(n) TX_OFF(n, 0x0C) | |
| 60 | #define QSERDES_TX_LANE_MODE(n) TX_OFF(n, 0x54) | |
| 61 | ||
| 62 | /* RX LANE n (0, 1) registers */ | |
| 63 | #define QSERDES_RX_CDR_CONTROL1(n) RX_OFF(n, 0x0) | |
| 64 | #define QSERDES_RX_CDR_CONTROL_HALF(n) RX_OFF(n, 0x8) | |
| 65 | #define QSERDES_RX_RX_EQ_GAIN1_LSB(n) RX_OFF(n, 0xA8) | |
| 66 | #define QSERDES_RX_RX_EQ_GAIN1_MSB(n) RX_OFF(n, 0xAC) | |
| 67 | #define QSERDES_RX_RX_EQ_GAIN2_LSB(n) RX_OFF(n, 0xB0) | |
| 68 | #define QSERDES_RX_RX_EQ_GAIN2_MSB(n) RX_OFF(n, 0xB4) | |
| 69 | #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(n) RX_OFF(n, 0xBC) | |
| 70 | #define QSERDES_RX_CDR_CONTROL_QUARTER(n) RX_OFF(n, 0xC) | |
| 71 | #define QSERDES_RX_SIGDET_CNTRL(n) RX_OFF(n, 0x100) | |
| 72 | ||
| 73 | /* UFS PHY registers */ | |
| 74 | #define UFS_PHY_PHY_START PHY_OFF(0x00) | |
| 75 | #define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x4) | |
| 76 | #define UFS_PHY_TX_LANE_ENABLE PHY_OFF(0x44) | |
| 77 | #define UFS_PHY_PWM_G1_CLK_DIVIDER PHY_OFF(0x08) | |
| 78 | #define UFS_PHY_PWM_G2_CLK_DIVIDER PHY_OFF(0x0C) | |
| 79 | #define UFS_PHY_PWM_G3_CLK_DIVIDER PHY_OFF(0x10) | |
| 80 | #define UFS_PHY_PWM_G4_CLK_DIVIDER PHY_OFF(0x14) | |
| 81 | #define UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER PHY_OFF(0x34) | |
| 82 | #define UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER PHY_OFF(0x38) | |
| 83 | #define UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER PHY_OFF(0x3C) | |
| 84 | #define UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER PHY_OFF(0x40) | |
| 85 | #define UFS_PHY_OMC_STATUS_RDVAL PHY_OFF(0x68) | |
| 86 | #define UFS_PHY_LINE_RESET_TIME PHY_OFF(0x28) | |
| 87 | #define UFS_PHY_LINE_RESET_GRANULARITY PHY_OFF(0x2C) | |
| 88 | #define UFS_PHY_TSYNC_RSYNC_CNTL PHY_OFF(0x48) | |
| 89 | #define UFS_PHY_PLL_CNTL PHY_OFF(0x50) | |
| 90 | #define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x54) | |
| 91 | #define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x5C) | |
| 92 | #define UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL PHY_OFF(0x58) | |
| 93 | #define UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL PHY_OFF(0x60) | |
| 94 | #define UFS_PHY_CFG_CHANGE_CNT_VAL PHY_OFF(0x64) | |
| 95 | #define UFS_PHY_RX_SYNC_WAIT_TIME PHY_OFF(0x6C) | |
| 96 | #define UFS_PHY_TX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xB4) | |
| 97 | #define UFS_PHY_RX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xE0) | |
| 98 | #define UFS_PHY_TX_MIN_STALL_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xB8) | |
| 99 | #define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xE4) | |
| 100 | #define UFS_PHY_TX_MIN_SAVE_CONFIG_TIME_CAPABILITY PHY_OFF(0xBC) | |
| 101 | #define UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY PHY_OFF(0xE8) | |
| 102 | #define UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY PHY_OFF(0xFC) | |
| 103 | #define UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY PHY_OFF(0x100) | |
| 104 | #define UFS_PHY_RX_SIGDET_CTRL3 PHY_OFF(0x14c) | |
| 105 | #define UFS_PHY_RMMI_ATTR_CTRL PHY_OFF(0x160) | |
| 106 | #define UFS_PHY_RMMI_RX_CFGUPDT_L1 (1 << 7) | |
| 107 | #define UFS_PHY_RMMI_TX_CFGUPDT_L1 (1 << 6) | |
| 108 | #define UFS_PHY_RMMI_CFGWR_L1 (1 << 5) | |
| 109 | #define UFS_PHY_RMMI_CFGRD_L1 (1 << 4) | |
| 110 | #define UFS_PHY_RMMI_RX_CFGUPDT_L0 (1 << 3) | |
| 111 | #define UFS_PHY_RMMI_TX_CFGUPDT_L0 (1 << 2) | |
| 112 | #define UFS_PHY_RMMI_CFGWR_L0 (1 << 1) | |
| 113 | #define UFS_PHY_RMMI_CFGRD_L0 (1 << 0) | |
| 114 | #define UFS_PHY_RMMI_ATTRID PHY_OFF(0x164) | |
| 115 | #define UFS_PHY_RMMI_ATTRWRVAL PHY_OFF(0x168) | |
| 116 | #define UFS_PHY_RMMI_ATTRRDVAL_L0_STATUS PHY_OFF(0x16C) | |
| 117 | #define UFS_PHY_RMMI_ATTRRDVAL_L1_STATUS PHY_OFF(0x170) | |
| 118 | #define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x174) | |
| 119 | ||
| 120 | #define UFS_PHY_TX_LANE_ENABLE_MASK 0x3 | |
| 121 | ||
| 122 | /* | |
| 123 | * This structure represents the 20nm specific phy. | |
| 124 | * common_cfg MUST remain the first field in this structure | |
| 125 | * in case extra fields are added. This way, when calling | |
| 126 | * get_ufs_qcom_phy() of generic phy, we can extract the | |
| 127 | * common phy structure (struct ufs_qcom_phy) out of it | |
| 128 | * regardless of the relevant specific phy. | |
| 129 | */ | |
| 130 | struct ufs_qcom_phy_qmp_20nm { | |
| 131 | struct ufs_qcom_phy common_cfg; | |
| 132 | }; | |
| 133 | ||
| 134 | static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_2_0[] = { | |
| 135 | UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01), | |
| 136 | UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL3, 0x0D), | |
| 137 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1), | |
| 138 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc), | |
| 139 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08), | |
| 140 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03), | |
| 141 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10), | |
| 142 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82), | |
| 143 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03), | |
| 144 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80), | |
| 145 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80), | |
| 146 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40), | |
| 147 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff), | |
| 148 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19), | |
| 149 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00), | |
| 150 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03), | |
| 151 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90), | |
| 152 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03), | |
| 153 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2), | |
| 154 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c), | |
| 155 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12), | |
| 156 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2), | |
| 157 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c), | |
| 158 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12), | |
| 159 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff), | |
| 160 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff), | |
| 161 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff), | |
| 162 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00), | |
| 163 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff), | |
| 164 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff), | |
| 165 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff), | |
| 166 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00), | |
| 167 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f), | |
| 168 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b), | |
| 169 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f), | |
| 170 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01), | |
| 171 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(0), 0x2F), | |
| 172 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(0), 0x20), | |
| 173 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(1), 0x2F), | |
| 174 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(1), 0x20), | |
| 175 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68), | |
| 176 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68), | |
| 177 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc), | |
| 178 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc), | |
| 179 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3), | |
| 180 | }; | |
| 181 | ||
| 182 | static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_3_0[] = { | |
| 183 | UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01), | |
| 184 | UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL3, 0x0D), | |
| 185 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1), | |
| 186 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc), | |
| 187 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08), | |
| 188 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03), | |
| 189 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10), | |
| 190 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82), | |
| 191 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03), | |
| 192 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80), | |
| 193 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80), | |
| 194 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40), | |
| 195 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff), | |
| 196 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19), | |
| 197 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00), | |
| 198 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03), | |
| 199 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90), | |
| 200 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03), | |
| 201 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2), | |
| 202 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c), | |
| 203 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12), | |
| 204 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2), | |
| 205 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c), | |
| 206 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12), | |
| 207 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff), | |
| 208 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff), | |
| 209 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff), | |
| 210 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00), | |
| 211 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff), | |
| 212 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff), | |
| 213 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff), | |
| 214 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00), | |
| 215 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x2b), | |
| 216 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x38), | |
| 217 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x3c), | |
| 218 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_UP_OFFSET, 0x02), | |
| 219 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_DN_OFFSET, 0x02), | |
| 220 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01), | |
| 221 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x40), | |
| 222 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68), | |
| 223 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68), | |
| 224 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc), | |
| 225 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc), | |
| 226 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3), | |
| 227 | }; | |
| 228 | ||
| 229 | static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { | |
| 230 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98), | |
| 231 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65), | |
| 232 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1e), | |
| 233 | }; | |
| 234 | ||
| 235 | #endif |