[linux-2.6-block.git] / drivers / pci / controller / dwc / pcie-artpec6.c

// SPDX-License-Identifier: GPL-2.0
/*
 * PCIe host controller driver for Axis ARTPEC-6 SoC
 *
 * Author: Niklas Cassel <niklas.cassel@axis.com>
 *
 * Based on work done by Phil Edworthy <phil@edworthys.org>
 */

#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/resource.h>
#include <linux/signal.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include "pcie-designware.h"

#define to_artpec6_pcie(x)	dev_get_drvdata((x)->dev)

enum artpec_pcie_variants {
	ARTPEC6,
	ARTPEC7,
};

struct artpec6_pcie {
	struct dw_pcie		*pci;
	struct regmap		*regmap;	/* DT axis,syscon-pcie */
	void __iomem		*phy_base;	/* DT phy */
	enum artpec_pcie_variants variant;
	enum dw_pcie_device_mode mode;
};

struct artpec_pcie_of_data {
	enum artpec_pcie_variants variant;
	enum dw_pcie_device_mode mode;
};

static const struct of_device_id artpec6_pcie_of_match[];

/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET			0x700

#define ACK_F_ASPM_CTRL_OFF		(PL_OFFSET + 0xc)
#define ACK_N_FTS_MASK			GENMASK(15, 8)
#define ACK_N_FTS(x)			(((x) << 8) & ACK_N_FTS_MASK)

#define FAST_TRAINING_SEQ_MASK		GENMASK(7, 0)
#define FAST_TRAINING_SEQ(x)		(((x) << 0) & FAST_TRAINING_SEQ_MASK)

/* ARTPEC-6 specific registers */
#define PCIECFG				0x18
#define  PCIECFG_DBG_OEN		BIT(24)
#define  PCIECFG_CORE_RESET_REQ		BIT(21)
#define  PCIECFG_LTSSM_ENABLE		BIT(20)
#define  PCIECFG_DEVICE_TYPE_MASK	GENMASK(19, 16)
#define  PCIECFG_CLKREQ_B		BIT(11)
#define  PCIECFG_REFCLK_ENABLE		BIT(10)
#define  PCIECFG_PLL_ENABLE		BIT(9)
#define  PCIECFG_PCLK_ENABLE		BIT(8)
#define  PCIECFG_RISRCREN		BIT(4)
#define  PCIECFG_MODE_TX_DRV_EN		BIT(3)
#define  PCIECFG_CISRREN		BIT(2)
#define  PCIECFG_MACRO_ENABLE		BIT(0)
/* ARTPEC-7 specific fields */
#define  PCIECFG_REFCLKSEL		BIT(23)
#define  PCIECFG_NOC_RESET		BIT(3)

#define PCIESTAT			0x1c
/* ARTPEC-7 specific fields */
#define  PCIESTAT_EXTREFCLK		BIT(3)

#define NOCCFG				0x40
#define  NOCCFG_ENABLE_CLK_PCIE		BIT(4)
#define  NOCCFG_POWER_PCIE_IDLEACK	BIT(3)
#define  NOCCFG_POWER_PCIE_IDLE		BIT(2)
#define  NOCCFG_POWER_PCIE_IDLEREQ	BIT(1)

#define PHY_STATUS			0x118
#define  PHY_COSPLLLOCK			BIT(0)

#define PHY_TX_ASIC_OUT			0x4040
#define  PHY_TX_ASIC_OUT_TX_ACK		BIT(0)

#define PHY_RX_ASIC_OUT			0x405c
#define  PHY_RX_ASIC_OUT_ACK		BIT(0)

static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
{
	u32 val;

	regmap_read(artpec6_pcie->regmap, offset, &val);
	return val;
}

static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
{
	regmap_write(artpec6_pcie->regmap, offset, val);
}

static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
{
	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
	struct pcie_port *pp = &pci->pp;
	struct dw_pcie_ep *ep = &pci->ep;

	switch (artpec6_pcie->mode) {
	case DW_PCIE_RC_TYPE:
		return pci_addr - pp->cfg0_base;
	case DW_PCIE_EP_TYPE:
		return pci_addr - ep->phys_base;
	default:
		dev_err(pci->dev, "UNKNOWN device type\n");
	}
	return pci_addr;
}

static int artpec6_pcie_establish_link(struct dw_pcie *pci)
{
	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
	u32 val;

	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	val |= PCIECFG_LTSSM_ENABLE;
	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);

	return 0;
}

static void artpec6_pcie_stop_link(struct dw_pcie *pci)
{
	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
	u32 val;

	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	val &= ~PCIECFG_LTSSM_ENABLE;
	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
}

static const struct dw_pcie_ops dw_pcie_ops = {
	.cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
	.start_link = artpec6_pcie_establish_link,
	.stop_link = artpec6_pcie_stop_link,
};

static void artpec6_pcie_wait_for_phy_a6(struct artpec6_pcie *artpec6_pcie)
{
	struct dw_pcie *pci = artpec6_pcie->pci;
	struct device *dev = pci->dev;
	u32 val;
	unsigned int retries;

	retries = 50;
	do {
		usleep_range(1000, 2000);
		val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
		retries--;
	} while (retries &&
		(val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
	if (!retries)
		dev_err(dev, "PCIe clock manager did not leave idle state\n");

	retries = 50;
	do {
		usleep_range(1000, 2000);
		val = readl(artpec6_pcie->phy_base + PHY_STATUS);
		retries--;
	} while (retries && !(val & PHY_COSPLLLOCK));
	if (!retries)
		dev_err(dev, "PHY PLL did not lock\n");
}

static void artpec6_pcie_wait_for_phy_a7(struct artpec6_pcie *artpec6_pcie)
{
	struct dw_pcie *pci = artpec6_pcie->pci;
	struct device *dev = pci->dev;
	u32 val;
	u16 phy_status_tx, phy_status_rx;
	unsigned int retries;

	retries = 50;
	do {
		usleep_range(1000, 2000);
		val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
		retries--;
	} while (retries &&
		(val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
	if (!retries)
		dev_err(dev, "PCIe clock manager did not leave idle state\n");

	retries = 50;
	do {
		usleep_range(1000, 2000);
		phy_status_tx = readw(artpec6_pcie->phy_base + PHY_TX_ASIC_OUT);
		phy_status_rx = readw(artpec6_pcie->phy_base + PHY_RX_ASIC_OUT);
		retries--;
	} while (retries && ((phy_status_tx & PHY_TX_ASIC_OUT_TX_ACK) ||
				(phy_status_rx & PHY_RX_ASIC_OUT_ACK)));
	if (!retries)
		dev_err(dev, "PHY did not enter Pn state\n");
}

static void artpec6_pcie_wait_for_phy(struct artpec6_pcie *artpec6_pcie)
{
	switch (artpec6_pcie->variant) {
	case ARTPEC6:
		artpec6_pcie_wait_for_phy_a6(artpec6_pcie);
		break;
	case ARTPEC7:
		artpec6_pcie_wait_for_phy_a7(artpec6_pcie);
		break;
	}
}

static void artpec6_pcie_init_phy_a6(struct artpec6_pcie *artpec6_pcie)
{
	u32 val;

	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	val |=  PCIECFG_RISRCREN |	/* Receiver term. 50 Ohm */
		PCIECFG_MODE_TX_DRV_EN |
		PCIECFG_CISRREN |	/* Reference clock term. 100 Ohm */
		PCIECFG_MACRO_ENABLE;
	val |= PCIECFG_REFCLK_ENABLE;
	val &= ~PCIECFG_DBG_OEN;
	val &= ~PCIECFG_CLKREQ_B;
	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
	usleep_range(5000, 6000);

	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
	val |= NOCCFG_ENABLE_CLK_PCIE;
	artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
	usleep_range(20, 30);

	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE;
	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
	usleep_range(6000, 7000);

	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
	val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
	artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
}

static void artpec6_pcie_init_phy_a7(struct artpec6_pcie *artpec6_pcie)
{
	struct dw_pcie *pci = artpec6_pcie->pci;
	u32 val;
	bool extrefclk;

	/* Check if external reference clock is connected */
	val = artpec6_pcie_readl(artpec6_pcie, PCIESTAT);
	extrefclk = !!(val & PCIESTAT_EXTREFCLK);
	dev_dbg(pci->dev, "Using reference clock: %s\n",
		extrefclk ? "external" : "internal");

	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	val |=  PCIECFG_RISRCREN |	/* Receiver term. 50 Ohm */
		PCIECFG_PCLK_ENABLE;
	if (extrefclk)
		val |= PCIECFG_REFCLKSEL;
	else
		val &= ~PCIECFG_REFCLKSEL;
	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
	usleep_range(10, 20);

	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
	val |= NOCCFG_ENABLE_CLK_PCIE;
	artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
	usleep_range(20, 30);

	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
	val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
	artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
}

static void artpec6_pcie_init_phy(struct artpec6_pcie *artpec6_pcie)
{
	switch (artpec6_pcie->variant) {
	case ARTPEC6:
		artpec6_pcie_init_phy_a6(artpec6_pcie);
		break;
	case ARTPEC7:
		artpec6_pcie_init_phy_a7(artpec6_pcie);
		break;
	}
}

static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
{
	struct dw_pcie *pci = artpec6_pcie->pci;
	u32 val;

	if (artpec6_pcie->variant != ARTPEC7)
		return;

	/*
	 * Increase the N_FTS (Number of Fast Training Sequences)
	 * to be transmitted when transitioning from L0s to L0.
	 */
	val = dw_pcie_readl_dbi(pci, ACK_F_ASPM_CTRL_OFF);
	val &= ~ACK_N_FTS_MASK;
	val |= ACK_N_FTS(180);
	dw_pcie_writel_dbi(pci, ACK_F_ASPM_CTRL_OFF, val);

	/*
	 * Set the Number of Fast Training Sequences that the core
	 * advertises as its N_FTS during Gen2 or Gen3 link training.
	 */
	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
	val &= ~FAST_TRAINING_SEQ_MASK;
	val |= FAST_TRAINING_SEQ(180);
	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
}

static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
{
	u32 val;

	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	switch (artpec6_pcie->variant) {
	case ARTPEC6:
		val |= PCIECFG_CORE_RESET_REQ;
		break;
	case ARTPEC7:
		val &= ~PCIECFG_NOC_RESET;
		break;
	}
	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
}

static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie)
{
	u32 val;

	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	switch (artpec6_pcie->variant) {
	case ARTPEC6:
		val &= ~PCIECFG_CORE_RESET_REQ;
		break;
	case ARTPEC7:
		val |= PCIECFG_NOC_RESET;
		break;
	}
	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
	usleep_range(100, 200);
}

static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
{
	struct dw_pcie *pci = artpec6_pcie->pci;
	struct pcie_port *pp = &pci->pp;

	if (IS_ENABLED(CONFIG_PCI_MSI))
		dw_pcie_msi_init(pp);
}

static int artpec6_pcie_host_init(struct pcie_port *pp)
{
	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);

	artpec6_pcie_assert_core_reset(artpec6_pcie);
	artpec6_pcie_init_phy(artpec6_pcie);
	artpec6_pcie_deassert_core_reset(artpec6_pcie);
	artpec6_pcie_wait_for_phy(artpec6_pcie);
	artpec6_pcie_set_nfts(artpec6_pcie);
	dw_pcie_setup_rc(pp);
	artpec6_pcie_establish_link(pci);
	dw_pcie_wait_for_link(pci);
	artpec6_pcie_enable_interrupts(artpec6_pcie);

	return 0;
}

static const struct dw_pcie_host_ops artpec6_pcie_host_ops = {
	.host_init = artpec6_pcie_host_init,
};

static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
				 struct platform_device *pdev)
{
	struct dw_pcie *pci = artpec6_pcie->pci;
	struct pcie_port *pp = &pci->pp;
	struct device *dev = pci->dev;
	int ret;

	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		pp->msi_irq = platform_get_irq_byname(pdev, "msi");
		if (pp->msi_irq < 0) {
			dev_err(dev, "failed to get MSI irq\n");
			return pp->msi_irq;
		}
	}

	pp->ops = &artpec6_pcie_host_ops;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
{
	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
	enum pci_barno bar;

	artpec6_pcie_assert_core_reset(artpec6_pcie);
	artpec6_pcie_init_phy(artpec6_pcie);
	artpec6_pcie_deassert_core_reset(artpec6_pcie);
	artpec6_pcie_wait_for_phy(artpec6_pcie);
	artpec6_pcie_set_nfts(artpec6_pcie);

	for (bar = BAR_0; bar <= BAR_5; bar++)
		dw_pcie_ep_reset_bar(pci, bar);
}

static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
				  enum pci_epc_irq_type type, u16 interrupt_num)
{
	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);

	switch (type) {
	case PCI_EPC_IRQ_LEGACY:
		dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
		return -EINVAL;
	case PCI_EPC_IRQ_MSI:
		return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
	default:
		dev_err(pci->dev, "UNKNOWN IRQ type\n");
	}

	return 0;
}

static const struct dw_pcie_ep_ops pcie_ep_ops = {
	.ep_init = artpec6_pcie_ep_init,
	.raise_irq = artpec6_pcie_raise_irq,
};

static int artpec6_add_pcie_ep(struct artpec6_pcie *artpec6_pcie,
			       struct platform_device *pdev)
{
	int ret;
	struct dw_pcie_ep *ep;
	struct resource *res;
	struct device *dev = &pdev->dev;
	struct dw_pcie *pci = artpec6_pcie->pci;

	ep = &pci->ep;
	ep->ops = &pcie_ep_ops;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
	pci->dbi_base2 = devm_ioremap_resource(dev, res);
	if (IS_ERR(pci->dbi_base2))
		return PTR_ERR(pci->dbi_base2);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
	if (!res)
		return -EINVAL;

	ep->phys_base = res->start;
	ep->addr_size = resource_size(res);

	ret = dw_pcie_ep_init(ep);
	if (ret) {
		dev_err(dev, "failed to initialize endpoint\n");
		return ret;
	}

	return 0;
}

static int artpec6_pcie_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct dw_pcie *pci;
	struct artpec6_pcie *artpec6_pcie;
	struct resource *dbi_base;
	struct resource *phy_base;
	int ret;
	const struct of_device_id *match;
	const struct artpec_pcie_of_data *data;
	enum artpec_pcie_variants variant;
	enum dw_pcie_device_mode mode;

	match = of_match_device(artpec6_pcie_of_match, dev);
	if (!match)
		return -EINVAL;

	data = (struct artpec_pcie_of_data *)match->data;
	variant = (enum artpec_pcie_variants)data->variant;
	mode = (enum dw_pcie_device_mode)data->mode;

	artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
	if (!artpec6_pcie)
		return -ENOMEM;

	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
	if (!pci)
		return -ENOMEM;

	pci->dev = dev;
	pci->ops = &dw_pcie_ops;

	artpec6_pcie->pci = pci;
	artpec6_pcie->variant = variant;
	artpec6_pcie->mode = mode;

	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
	pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
	if (IS_ERR(pci->dbi_base))
		return PTR_ERR(pci->dbi_base);

	phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
	artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
	if (IS_ERR(artpec6_pcie->phy_base))
		return PTR_ERR(artpec6_pcie->phy_base);

	artpec6_pcie->regmap =
		syscon_regmap_lookup_by_phandle(dev->of_node,
						"axis,syscon-pcie");
	if (IS_ERR(artpec6_pcie->regmap))
		return PTR_ERR(artpec6_pcie->regmap);

	platform_set_drvdata(pdev, artpec6_pcie);

	switch (artpec6_pcie->mode) {
	case DW_PCIE_RC_TYPE:
		if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_HOST))
			return -ENODEV;

		ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
		if (ret < 0)
			return ret;
		break;
	case DW_PCIE_EP_TYPE: {
		u32 val;

		if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_EP))
			return -ENODEV;

		val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
		val &= ~PCIECFG_DEVICE_TYPE_MASK;
		artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
		ret = artpec6_add_pcie_ep(artpec6_pcie, pdev);
		if (ret < 0)
			return ret;
		break;
	}
	default:
		dev_err(dev, "INVALID device type %d\n", artpec6_pcie->mode);
	}

	return 0;
}

static const struct artpec_pcie_of_data artpec6_pcie_rc_of_data = {
	.variant = ARTPEC6,
	.mode = DW_PCIE_RC_TYPE,
};

static const struct artpec_pcie_of_data artpec6_pcie_ep_of_data = {
	.variant = ARTPEC6,
	.mode = DW_PCIE_EP_TYPE,
};

static const struct artpec_pcie_of_data artpec7_pcie_rc_of_data = {
	.variant = ARTPEC7,
	.mode = DW_PCIE_RC_TYPE,
};

static const struct artpec_pcie_of_data artpec7_pcie_ep_of_data = {
	.variant = ARTPEC7,
	.mode = DW_PCIE_EP_TYPE,
};

static const struct of_device_id artpec6_pcie_of_match[] = {
	{
		.compatible = "axis,artpec6-pcie",
		.data = &artpec6_pcie_rc_of_data,
	},
	{
		.compatible = "axis,artpec6-pcie-ep",
		.data = &artpec6_pcie_ep_of_data,
	},
	{
		.compatible = "axis,artpec7-pcie",
		.data = &artpec7_pcie_rc_of_data,
	},
	{
		.compatible = "axis,artpec7-pcie-ep",
		.data = &artpec7_pcie_ep_of_data,
	},
	{},
};

static struct platform_driver artpec6_pcie_driver = {
	.probe = artpec6_pcie_probe,
	.driver = {
		.name	= "artpec6-pcie",
		.of_match_table = artpec6_pcie_of_match,
		.suppress_bind_attrs = true,
	},
};
builtin_platform_driver(artpec6_pcie_driver);
Commit	Line	Data
8cfab3cf	1	// SPDX-License-Identifier: GPL-2.0
a3cbfae1 NC	2	/*
	3	* PCIe host controller driver for Axis ARTPEC-6 SoC
	4	*
58bdaa1d PG	5	* Author: Niklas Cassel <niklas.cassel@axis.com>
58bdaa1d PG	6	*
a3cbfae1	7	* Based on work done by Phil Edworthy <phil@edworthys.org>
a3cbfae1 NC	8	*/
	9
	10	#include <linux/delay.h>
	11	#include <linux/kernel.h>
58bdaa1d	12	#include <linux/init.h>
b5074ef6	13	#include <linux/of_device.h>
a3cbfae1 NC	14	#include <linux/pci.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/resource.h>
	17	#include <linux/signal.h>
	18	#include <linux/types.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/mfd/syscon.h>
	21	#include <linux/regmap.h>
	22
	23	#include "pcie-designware.h"
	24
442ec4c0	25	#define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
a3cbfae1	26
dc734ee0 NC	27	enum artpec_pcie_variants {
	28	ARTPEC6,
	29	ARTPEC7,
	30	};
	31
a3cbfae1	32	struct artpec6_pcie {
442ec4c0	33	struct dw_pcie *pci;
7c62efcf BH	34	struct regmap regmap; / DT axis,syscon-pcie */
7c62efcf BH	35	void __iomem phy_base; / DT phy */
dc734ee0	36	enum artpec_pcie_variants variant;
b5074ef6	37	enum dw_pcie_device_mode mode;
a3cbfae1 NC	38	};
a3cbfae1 NC	39
b5074ef6	40	struct artpec_pcie_of_data {
dc734ee0	41	enum artpec_pcie_variants variant;
b5074ef6	42	enum dw_pcie_device_mode mode;
a3cbfae1 NC	43	};
a3cbfae1 NC	44
b5074ef6 NC	45	static const struct of_device_id artpec6_pcie_of_match[];
b5074ef6 NC	46
a3cbfae1 NC	47	/* PCIe Port Logic registers (memory-mapped) */
a3cbfae1 NC	48	#define PL_OFFSET 0x700
a3cbfae1	49
dc734ee0 NC	50	#define ACK_F_ASPM_CTRL_OFF (PL_OFFSET + 0xc)
	51	#define ACK_N_FTS_MASK GENMASK(15, 8)
	52	#define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK)
	53
	54	#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0)
	55	#define FAST_TRAINING_SEQ(x) (((x) << 0) & FAST_TRAINING_SEQ_MASK)
a3cbfae1 NC	56
	57	/* ARTPEC-6 specific registers */
	58	#define PCIECFG 0x18
bc5d7dfa NC	59	#define PCIECFG_DBG_OEN BIT(24)
	60	#define PCIECFG_CORE_RESET_REQ BIT(21)
	61	#define PCIECFG_LTSSM_ENABLE BIT(20)
b5074ef6	62	#define PCIECFG_DEVICE_TYPE_MASK GENMASK(19, 16)
bc5d7dfa NC	63	#define PCIECFG_CLKREQ_B BIT(11)
	64	#define PCIECFG_REFCLK_ENABLE BIT(10)
	65	#define PCIECFG_PLL_ENABLE BIT(9)
	66	#define PCIECFG_PCLK_ENABLE BIT(8)
	67	#define PCIECFG_RISRCREN BIT(4)
	68	#define PCIECFG_MODE_TX_DRV_EN BIT(3)
	69	#define PCIECFG_CISRREN BIT(2)
	70	#define PCIECFG_MACRO_ENABLE BIT(0)
dc734ee0 NC	71	/* ARTPEC-7 specific fields */
	72	#define PCIECFG_REFCLKSEL BIT(23)
	73	#define PCIECFG_NOC_RESET BIT(3)
	74
	75	#define PCIESTAT 0x1c
	76	/* ARTPEC-7 specific fields */
	77	#define PCIESTAT_EXTREFCLK BIT(3)
a3cbfae1 NC	78
a3cbfae1 NC	79	#define NOCCFG 0x40
bc5d7dfa NC	80	#define NOCCFG_ENABLE_CLK_PCIE BIT(4)
	81	#define NOCCFG_POWER_PCIE_IDLEACK BIT(3)
	82	#define NOCCFG_POWER_PCIE_IDLE BIT(2)
	83	#define NOCCFG_POWER_PCIE_IDLEREQ BIT(1)
a3cbfae1 NC	84
a3cbfae1 NC	85	#define PHY_STATUS 0x118
bc5d7dfa	86	#define PHY_COSPLLLOCK BIT(0)
a3cbfae1	87
dc734ee0 NC	88	#define PHY_TX_ASIC_OUT 0x4040
	89	#define PHY_TX_ASIC_OUT_TX_ACK BIT(0)
	90
	91	#define PHY_RX_ASIC_OUT 0x405c
	92	#define PHY_RX_ASIC_OUT_ACK BIT(0)
a3cbfae1	93
26fbcc5a BH	94	static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
	95	{
	96	u32 val;
	97
	98	regmap_read(artpec6_pcie->regmap, offset, &val);
	99	return val;
	100	}
	101
	102	static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
	103	{
	104	regmap_write(artpec6_pcie->regmap, offset, val);
	105	}
	106
b6900aeb	107	static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
62c5549f	108	{
b6900aeb NC	109	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
	110	struct pcie_port *pp = &pci->pp;
	111	struct dw_pcie_ep *ep = &pci->ep;
	112
	113	switch (artpec6_pcie->mode) {
	114	case DW_PCIE_RC_TYPE:
	115	return pci_addr - pp->cfg0_base;
	116	case DW_PCIE_EP_TYPE:
	117	return pci_addr - ep->phys_base;
	118	default:
	119	dev_err(pci->dev, "UNKNOWN device type\n");
	120	}
	121	return pci_addr;
62c5549f KVA	122	}
62c5549f KVA	123
87c9a730	124	static int artpec6_pcie_establish_link(struct dw_pcie *pci)
a3cbfae1	125	{
87c9a730	126	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
a3cbfae1	127	u32 val;
a3cbfae1	128
26fbcc5a	129	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
87c9a730	130	val \|= PCIECFG_LTSSM_ENABLE;
26fbcc5a	131	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
a3cbfae1	132
87c9a730 NC	133	return 0;
	134	}
	135
b5074ef6 NC	136	static void artpec6_pcie_stop_link(struct dw_pcie *pci)
	137	{
	138	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
a3cbfae1	139	u32 val;
a3cbfae1	140
26fbcc5a	141	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
b5074ef6	142	val &= ~PCIECFG_LTSSM_ENABLE;
26fbcc5a	143	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
b5074ef6 NC	144	}
	145
	146	static const struct dw_pcie_ops dw_pcie_ops = {
	147	.cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
	148	.start_link = artpec6_pcie_establish_link,
	149	.stop_link = artpec6_pcie_stop_link,
	150	};
	151
dc734ee0	152	static void artpec6_pcie_wait_for_phy_a6(struct artpec6_pcie *artpec6_pcie)
87c9a730	153	{
4fdd5b5b NC	154	struct dw_pcie *pci = artpec6_pcie->pci;
4fdd5b5b NC	155	struct device *dev = pci->dev;
87c9a730 NC	156	u32 val;
	157	unsigned int retries;
	158
4fdd5b5b NC	159	retries = 50;
	160	do {
	161	usleep_range(1000, 2000);
	162	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
	163	retries--;
	164	} while (retries &&
	165	(val & (NOCCFG_POWER_PCIE_IDLEACK \| NOCCFG_POWER_PCIE_IDLE)));
	166	if (!retries)
	167	dev_err(dev, "PCIe clock manager did not leave idle state\n");
	168
	169	retries = 50;
	170	do {
	171	usleep_range(1000, 2000);
	172	val = readl(artpec6_pcie->phy_base + PHY_STATUS);
	173	retries--;
	174	} while (retries && !(val & PHY_COSPLLLOCK));
	175	if (!retries)
	176	dev_err(dev, "PHY PLL did not lock\n");
	177	}
	178
dc734ee0 NC	179	static void artpec6_pcie_wait_for_phy_a7(struct artpec6_pcie *artpec6_pcie)
	180	{
	181	struct dw_pcie *pci = artpec6_pcie->pci;
	182	struct device *dev = pci->dev;
	183	u32 val;
	184	u16 phy_status_tx, phy_status_rx;
	185	unsigned int retries;
	186
	187	retries = 50;
	188	do {
	189	usleep_range(1000, 2000);
	190	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
	191	retries--;
	192	} while (retries &&
	193	(val & (NOCCFG_POWER_PCIE_IDLEACK \| NOCCFG_POWER_PCIE_IDLE)));
	194	if (!retries)
	195	dev_err(dev, "PCIe clock manager did not leave idle state\n");
	196
	197	retries = 50;
	198	do {
	199	usleep_range(1000, 2000);
	200	phy_status_tx = readw(artpec6_pcie->phy_base + PHY_TX_ASIC_OUT);
	201	phy_status_rx = readw(artpec6_pcie->phy_base + PHY_RX_ASIC_OUT);
	202	retries--;
	203	} while (retries && ((phy_status_tx & PHY_TX_ASIC_OUT_TX_ACK) \|\|
	204	(phy_status_rx & PHY_RX_ASIC_OUT_ACK)));
	205	if (!retries)
	206	dev_err(dev, "PHY did not enter Pn state\n");
	207	}
	208
	209	static void artpec6_pcie_wait_for_phy(struct artpec6_pcie *artpec6_pcie)
	210	{
	211	switch (artpec6_pcie->variant) {
	212	case ARTPEC6:
	213	artpec6_pcie_wait_for_phy_a6(artpec6_pcie);
	214	break;
	215	case ARTPEC7:
	216	artpec6_pcie_wait_for_phy_a7(artpec6_pcie);
	217	break;
	218	}
	219	}
	220
	221	static void artpec6_pcie_init_phy_a6(struct artpec6_pcie *artpec6_pcie)
4fdd5b5b NC	222	{
4fdd5b5b NC	223	u32 val;
a3cbfae1	224
26fbcc5a	225	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
a3cbfae1 NC	226	val \|= PCIECFG_RISRCREN \| /* Receiver term. 50 Ohm */
	227	PCIECFG_MODE_TX_DRV_EN \|
	228	PCIECFG_CISRREN \| /* Reference clock term. 100 Ohm */
	229	PCIECFG_MACRO_ENABLE;
	230	val \|= PCIECFG_REFCLK_ENABLE;
	231	val &= ~PCIECFG_DBG_OEN;
	232	val &= ~PCIECFG_CLKREQ_B;
26fbcc5a	233	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
a3cbfae1 NC	234	usleep_range(5000, 6000);
a3cbfae1 NC	235
26fbcc5a	236	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
a3cbfae1	237	val \|= NOCCFG_ENABLE_CLK_PCIE;
26fbcc5a	238	artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
a3cbfae1 NC	239	usleep_range(20, 30);
a3cbfae1 NC	240
26fbcc5a	241	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
a3cbfae1	242	val \|= PCIECFG_PCLK_ENABLE \| PCIECFG_PLL_ENABLE;
26fbcc5a	243	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
a3cbfae1 NC	244	usleep_range(6000, 7000);
a3cbfae1 NC	245
26fbcc5a	246	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
a3cbfae1	247	val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
26fbcc5a	248	artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
87c9a730	249	}
a3cbfae1	250
dc734ee0 NC	251	static void artpec6_pcie_init_phy_a7(struct artpec6_pcie *artpec6_pcie)
	252	{
	253	struct dw_pcie *pci = artpec6_pcie->pci;
	254	u32 val;
	255	bool extrefclk;
a3cbfae1	256
dc734ee0 NC	257	/* Check if external reference clock is connected */
	258	val = artpec6_pcie_readl(artpec6_pcie, PCIESTAT);
	259	extrefclk = !!(val & PCIESTAT_EXTREFCLK);
	260	dev_dbg(pci->dev, "Using reference clock: %s\n",
	261	extrefclk ? "external" : "internal");
a3cbfae1	262
26fbcc5a	263	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
dc734ee0 NC	264	val \|= PCIECFG_RISRCREN \| /* Receiver term. 50 Ohm */
	265	PCIECFG_PCLK_ENABLE;
	266	if (extrefclk)
	267	val \|= PCIECFG_REFCLKSEL;
	268	else
	269	val &= ~PCIECFG_REFCLKSEL;
26fbcc5a	270	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
dc734ee0	271	usleep_range(10, 20);
a3cbfae1	272
dc734ee0 NC	273	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
	274	val \|= NOCCFG_ENABLE_CLK_PCIE;
	275	artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
	276	usleep_range(20, 30);
	277
	278	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
	279	val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
	280	artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
	281	}
	282
	283	static void artpec6_pcie_init_phy(struct artpec6_pcie *artpec6_pcie)
	284	{
	285	switch (artpec6_pcie->variant) {
	286	case ARTPEC6:
	287	artpec6_pcie_init_phy_a6(artpec6_pcie);
	288	break;
	289	case ARTPEC7:
	290	artpec6_pcie_init_phy_a7(artpec6_pcie);
	291	break;
	292	}
	293	}
	294
	295	static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
	296	{
	297	struct dw_pcie *pci = artpec6_pcie->pci;
	298	u32 val;
	299
	300	if (artpec6_pcie->variant != ARTPEC7)
	301	return;
	302
	303	/*
	304	* Increase the N_FTS (Number of Fast Training Sequences)
	305	* to be transmitted when transitioning from L0s to L0.
	306	*/
	307	val = dw_pcie_readl_dbi(pci, ACK_F_ASPM_CTRL_OFF);
	308	val &= ~ACK_N_FTS_MASK;
	309	val \|= ACK_N_FTS(180);
	310	dw_pcie_writel_dbi(pci, ACK_F_ASPM_CTRL_OFF, val);
	311
	312	/*
	313	* Set the Number of Fast Training Sequences that the core
	314	* advertises as its N_FTS during Gen2 or Gen3 link training.
	315	*/
	316	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
	317	val &= ~FAST_TRAINING_SEQ_MASK;
	318	val \|= FAST_TRAINING_SEQ(180);
	319	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
	320	}
	321
87c9a730 NC	322	static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
	323	{
	324	u32 val;
a3cbfae1	325
26fbcc5a	326	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
dc734ee0 NC	327	switch (artpec6_pcie->variant) {
	328	case ARTPEC6:
	329	val \|= PCIECFG_CORE_RESET_REQ;
	330	break;
	331	case ARTPEC7:
	332	val &= ~PCIECFG_NOC_RESET;
	333	break;
	334	}
26fbcc5a	335	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
87c9a730	336	}
a3cbfae1	337
87c9a730 NC	338	static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie)
	339	{
	340	u32 val;
a3cbfae1	341
26fbcc5a	342	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
dc734ee0 NC	343	switch (artpec6_pcie->variant) {
	344	case ARTPEC6:
	345	val &= ~PCIECFG_CORE_RESET_REQ;
	346	break;
	347	case ARTPEC7:
	348	val \|= PCIECFG_NOC_RESET;
	349	break;
	350	}
26fbcc5a	351	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
87c9a730	352	usleep_range(100, 200);
a3cbfae1 NC	353	}
a3cbfae1 NC	354
b6f5f434	355	static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
a3cbfae1	356	{
442ec4c0 KVA	357	struct dw_pcie *pci = artpec6_pcie->pci;
442ec4c0 KVA	358	struct pcie_port *pp = &pci->pp;
b6f5f434	359
a3cbfae1 NC	360	if (IS_ENABLED(CONFIG_PCI_MSI))
	361	dw_pcie_msi_init(pp);
	362	}
	363
4a301766	364	static int artpec6_pcie_host_init(struct pcie_port *pp)
a3cbfae1	365	{
442ec4c0 KVA	366	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
442ec4c0 KVA	367	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
b6f5f434	368
87c9a730 NC	369	artpec6_pcie_assert_core_reset(artpec6_pcie);
	370	artpec6_pcie_init_phy(artpec6_pcie);
	371	artpec6_pcie_deassert_core_reset(artpec6_pcie);
4fdd5b5b	372	artpec6_pcie_wait_for_phy(artpec6_pcie);
dc734ee0	373	artpec6_pcie_set_nfts(artpec6_pcie);
87c9a730 NC	374	dw_pcie_setup_rc(pp);
	375	artpec6_pcie_establish_link(pci);
	376	dw_pcie_wait_for_link(pci);
b6f5f434	377	artpec6_pcie_enable_interrupts(artpec6_pcie);
4a301766 BA	378
4a301766 BA	379	return 0;
a3cbfae1 NC	380	}
a3cbfae1 NC	381
4ab2e7c0	382	static const struct dw_pcie_host_ops artpec6_pcie_host_ops = {
a3cbfae1 NC	383	.host_init = artpec6_pcie_host_init,
	384	};
	385
b6f5f434	386	static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
b58ddf17	387	struct platform_device *pdev)
a3cbfae1	388	{
442ec4c0 KVA	389	struct dw_pcie *pci = artpec6_pcie->pci;
	390	struct pcie_port *pp = &pci->pp;
	391	struct device *dev = pci->dev;
a3cbfae1 NC	392	int ret;
	393
	394	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	395	pp->msi_irq = platform_get_irq_byname(pdev, "msi");
16df7cdb	396	if (pp->msi_irq < 0) {
e6f3115f	397	dev_err(dev, "failed to get MSI irq\n");
16df7cdb	398	return pp->msi_irq;
a3cbfae1	399	}
a3cbfae1 NC	400	}
a3cbfae1 NC	401
a3cbfae1 NC	402	pp->ops = &artpec6_pcie_host_ops;
	403
	404	ret = dw_pcie_host_init(pp);
	405	if (ret) {
e6f3115f	406	dev_err(dev, "failed to initialize host\n");
a3cbfae1 NC	407	return ret;
	408	}
	409
	410	return 0;
	411	}
	412
b5074ef6 NC	413	static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
	414	{
	415	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
	416	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
	417	enum pci_barno bar;
	418
	419	artpec6_pcie_assert_core_reset(artpec6_pcie);
	420	artpec6_pcie_init_phy(artpec6_pcie);
	421	artpec6_pcie_deassert_core_reset(artpec6_pcie);
4fdd5b5b	422	artpec6_pcie_wait_for_phy(artpec6_pcie);
dc734ee0	423	artpec6_pcie_set_nfts(artpec6_pcie);
b5074ef6 NC	424
	425	for (bar = BAR_0; bar <= BAR_5; bar++)
	426	dw_pcie_ep_reset_bar(pci, bar);
	427	}
	428
16093362	429	static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
d3c70a98	430	enum pci_epc_irq_type type, u16 interrupt_num)
b5074ef6 NC	431	{
	432	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
	433
	434	switch (type) {
	435	case PCI_EPC_IRQ_LEGACY:
	436	dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
	437	return -EINVAL;
	438	case PCI_EPC_IRQ_MSI:
16093362	439	return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
b5074ef6 NC	440	default:
	441	dev_err(pci->dev, "UNKNOWN IRQ type\n");
	442	}
	443
	444	return 0;
	445	}
	446
626961dd	447	static const struct dw_pcie_ep_ops pcie_ep_ops = {
b5074ef6 NC	448	.ep_init = artpec6_pcie_ep_init,
b5074ef6 NC	449	.raise_irq = artpec6_pcie_raise_irq,
794a8604 NC	450	};
794a8604 NC	451
b5074ef6 NC	452	static int artpec6_add_pcie_ep(struct artpec6_pcie *artpec6_pcie,
	453	struct platform_device *pdev)
	454	{
	455	int ret;
	456	struct dw_pcie_ep *ep;
	457	struct resource *res;
	458	struct device *dev = &pdev->dev;
	459	struct dw_pcie *pci = artpec6_pcie->pci;
	460
	461	ep = &pci->ep;
	462	ep->ops = &pcie_ep_ops;
	463
	464	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
71dcce64 GP	465	pci->dbi_base2 = devm_ioremap_resource(dev, res);
	466	if (IS_ERR(pci->dbi_base2))
	467	return PTR_ERR(pci->dbi_base2);
b5074ef6 NC	468
	469	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
	470	if (!res)
	471	return -EINVAL;
	472
	473	ep->phys_base = res->start;
	474	ep->addr_size = resource_size(res);
	475
	476	ret = dw_pcie_ep_init(ep);
	477	if (ret) {
	478	dev_err(dev, "failed to initialize endpoint\n");
	479	return ret;
	480	}
	481
	482	return 0;
	483	}
	484
a3cbfae1 NC	485	static int artpec6_pcie_probe(struct platform_device *pdev)
a3cbfae1 NC	486	{
e6f3115f	487	struct device *dev = &pdev->dev;
442ec4c0	488	struct dw_pcie *pci;
a3cbfae1	489	struct artpec6_pcie *artpec6_pcie;
a3cbfae1 NC	490	struct resource *dbi_base;
	491	struct resource *phy_base;
	492	int ret;
b5074ef6 NC	493	const struct of_device_id *match;
b5074ef6 NC	494	const struct artpec_pcie_of_data *data;
dc734ee0	495	enum artpec_pcie_variants variant;
b5074ef6 NC	496	enum dw_pcie_device_mode mode;
	497
	498	match = of_match_device(artpec6_pcie_of_match, dev);
	499	if (!match)
	500	return -EINVAL;
	501
	502	data = (struct artpec_pcie_of_data *)match->data;
dc734ee0	503	variant = (enum artpec_pcie_variants)data->variant;
b5074ef6	504	mode = (enum dw_pcie_device_mode)data->mode;
a3cbfae1	505
e6f3115f	506	artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
a3cbfae1 NC	507	if (!artpec6_pcie)
	508	return -ENOMEM;
	509
442ec4c0 KVA	510	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
	511	if (!pci)
	512	return -ENOMEM;
	513
	514	pci->dev = dev;
794a8604	515	pci->ops = &dw_pcie_ops;
a3cbfae1	516
c0464062	517	artpec6_pcie->pci = pci;
dc734ee0	518	artpec6_pcie->variant = variant;
b5074ef6	519	artpec6_pcie->mode = mode;
c0464062	520
a3cbfae1	521	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
442ec4c0 KVA	522	pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
	523	if (IS_ERR(pci->dbi_base))
	524	return PTR_ERR(pci->dbi_base);
a3cbfae1 NC	525
a3cbfae1 NC	526	phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
e6f3115f	527	artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
a3cbfae1 NC	528	if (IS_ERR(artpec6_pcie->phy_base))
	529	return PTR_ERR(artpec6_pcie->phy_base);
	530
	531	artpec6_pcie->regmap =
e6f3115f	532	syscon_regmap_lookup_by_phandle(dev->of_node,
a3cbfae1 NC	533	"axis,syscon-pcie");
	534	if (IS_ERR(artpec6_pcie->regmap))
	535	return PTR_ERR(artpec6_pcie->regmap);
	536
9bcf0a6f KVA	537	platform_set_drvdata(pdev, artpec6_pcie);
9bcf0a6f KVA	538
b5074ef6 NC	539	switch (artpec6_pcie->mode) {
	540	case DW_PCIE_RC_TYPE:
	541	if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_HOST))
	542	return -ENODEV;
	543
	544	ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
	545	if (ret < 0)
	546	return ret;
	547	break;
	548	case DW_PCIE_EP_TYPE: {
	549	u32 val;
	550
	551	if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_EP))
	552	return -ENODEV;
	553
	554	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	555	val &= ~PCIECFG_DEVICE_TYPE_MASK;
	556	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
	557	ret = artpec6_add_pcie_ep(artpec6_pcie, pdev);
	558	if (ret < 0)
	559	return ret;
	560	break;
	561	}
	562	default:
	563	dev_err(dev, "INVALID device type %d\n", artpec6_pcie->mode);
	564	}
a3cbfae1	565
a3cbfae1 NC	566	return 0;
	567	}
	568
b5074ef6	569	static const struct artpec_pcie_of_data artpec6_pcie_rc_of_data = {
dc734ee0	570	.variant = ARTPEC6,
b5074ef6 NC	571	.mode = DW_PCIE_RC_TYPE,
	572	};
	573
	574	static const struct artpec_pcie_of_data artpec6_pcie_ep_of_data = {
dc734ee0 NC	575	.variant = ARTPEC6,
	576	.mode = DW_PCIE_EP_TYPE,
	577	};
	578
	579	static const struct artpec_pcie_of_data artpec7_pcie_rc_of_data = {
	580	.variant = ARTPEC7,
	581	.mode = DW_PCIE_RC_TYPE,
	582	};
	583
	584	static const struct artpec_pcie_of_data artpec7_pcie_ep_of_data = {
	585	.variant = ARTPEC7,
b5074ef6 NC	586	.mode = DW_PCIE_EP_TYPE,
	587	};
	588
a3cbfae1	589	static const struct of_device_id artpec6_pcie_of_match[] = {
b5074ef6 NC	590	{
	591	.compatible = "axis,artpec6-pcie",
	592	.data = &artpec6_pcie_rc_of_data,
	593	},
	594	{
	595	.compatible = "axis,artpec6-pcie-ep",
	596	.data = &artpec6_pcie_ep_of_data,
	597	},
dc734ee0 NC	598	{
	599	.compatible = "axis,artpec7-pcie",
	600	.data = &artpec7_pcie_rc_of_data,
	601	},
	602	{
	603	.compatible = "axis,artpec7-pcie-ep",
	604	.data = &artpec7_pcie_ep_of_data,
	605	},
a3cbfae1 NC	606	{},
a3cbfae1 NC	607	};
a3cbfae1 NC	608
	609	static struct platform_driver artpec6_pcie_driver = {
	610	.probe = artpec6_pcie_probe,
	611	.driver = {
	612	.name = "artpec6-pcie",
	613	.of_match_table = artpec6_pcie_of_match,
a5f40e80	614	.suppress_bind_attrs = true,
a3cbfae1 NC	615	},
a3cbfae1 NC	616	};
58bdaa1d	617	builtin_platform_driver(artpec6_pcie_driver);