r8152: move the setting for the default speed
[linux-2.6-block.git] / drivers / net / usb / r8152.c
CommitLineData
ac718b69 1/*
c7de7dec 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
ac718b69 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
ac718b69 10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
ac718b69 13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
ebc2ec48 21#include <linux/list.h>
5bd23881 22#include <linux/ip.h>
23#include <linux/ipv6.h>
6128d1bb 24#include <net/ip6_checksum.h>
4c4a6b1b 25#include <uapi/linux/mdio.h>
26#include <linux/mdio.h>
d9a28c5b 27#include <linux/usb/cdc.h>
5ee3c60c 28#include <linux/suspend.h>
ac718b69 29
d0942473 30/* Information for net-next */
31#define NETNEXT_VERSION "08"
32
33/* Information for net */
5ee3c60c 34#define NET_VERSION "3"
d0942473 35
36#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
ac718b69 37#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
44d942a9 38#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
ac718b69 39#define MODULENAME "r8152"
40
41#define R8152_PHY_ID 32
42
43#define PLA_IDR 0xc000
44#define PLA_RCR 0xc010
45#define PLA_RMS 0xc016
46#define PLA_RXFIFO_CTRL0 0xc0a0
47#define PLA_RXFIFO_CTRL1 0xc0a4
48#define PLA_RXFIFO_CTRL2 0xc0a8
65bab84c 49#define PLA_DMY_REG0 0xc0b0
ac718b69 50#define PLA_FMC 0xc0b4
51#define PLA_CFG_WOL 0xc0b6
43779f8d 52#define PLA_TEREDO_CFG 0xc0bc
ac718b69 53#define PLA_MAR 0xcd00
43779f8d 54#define PLA_BACKUP 0xd000
ac718b69 55#define PAL_BDC_CR 0xd1a0
43779f8d 56#define PLA_TEREDO_TIMER 0xd2cc
57#define PLA_REALWOW_TIMER 0xd2e8
ac718b69 58#define PLA_LEDSEL 0xdd90
59#define PLA_LED_FEATURE 0xdd92
60#define PLA_PHYAR 0xde00
43779f8d 61#define PLA_BOOT_CTRL 0xe004
ac718b69 62#define PLA_GPHY_INTR_IMR 0xe022
63#define PLA_EEE_CR 0xe040
64#define PLA_EEEP_CR 0xe080
65#define PLA_MAC_PWR_CTRL 0xe0c0
43779f8d 66#define PLA_MAC_PWR_CTRL2 0xe0ca
67#define PLA_MAC_PWR_CTRL3 0xe0cc
68#define PLA_MAC_PWR_CTRL4 0xe0ce
69#define PLA_WDT6_CTRL 0xe428
ac718b69 70#define PLA_TCR0 0xe610
71#define PLA_TCR1 0xe612
69b4b7a4 72#define PLA_MTPS 0xe615
ac718b69 73#define PLA_TXFIFO_CTRL 0xe618
4f1d4d54 74#define PLA_RSTTALLY 0xe800
ac718b69 75#define PLA_CR 0xe813
76#define PLA_CRWECR 0xe81c
21ff2e89 77#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
78#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
ac718b69 79#define PLA_CONFIG5 0xe822
80#define PLA_PHY_PWR 0xe84c
81#define PLA_OOB_CTRL 0xe84f
82#define PLA_CPCR 0xe854
83#define PLA_MISC_0 0xe858
84#define PLA_MISC_1 0xe85a
85#define PLA_OCP_GPHY_BASE 0xe86c
4f1d4d54 86#define PLA_TALLYCNT 0xe890
ac718b69 87#define PLA_SFF_STS_7 0xe8de
88#define PLA_PHYSTATUS 0xe908
89#define PLA_BP_BA 0xfc26
90#define PLA_BP_0 0xfc28
91#define PLA_BP_1 0xfc2a
92#define PLA_BP_2 0xfc2c
93#define PLA_BP_3 0xfc2e
94#define PLA_BP_4 0xfc30
95#define PLA_BP_5 0xfc32
96#define PLA_BP_6 0xfc34
97#define PLA_BP_7 0xfc36
43779f8d 98#define PLA_BP_EN 0xfc38
ac718b69 99
65bab84c 100#define USB_USB2PHY 0xb41e
101#define USB_SSPHYLINK2 0xb428
43779f8d 102#define USB_U2P3_CTRL 0xb460
65bab84c 103#define USB_CSR_DUMMY1 0xb464
104#define USB_CSR_DUMMY2 0xb466
ac718b69 105#define USB_DEV_STAT 0xb808
65bab84c 106#define USB_CONNECT_TIMER 0xcbf8
107#define USB_BURST_SIZE 0xcfc0
ac718b69 108#define USB_USB_CTRL 0xd406
109#define USB_PHY_CTRL 0xd408
110#define USB_TX_AGG 0xd40a
111#define USB_RX_BUF_TH 0xd40c
112#define USB_USB_TIMER 0xd428
464ec10a 113#define USB_RX_EARLY_TIMEOUT 0xd42c
114#define USB_RX_EARLY_SIZE 0xd42e
ac718b69 115#define USB_PM_CTRL_STATUS 0xd432
116#define USB_TX_DMA 0xd434
43779f8d 117#define USB_TOLERANCE 0xd490
118#define USB_LPM_CTRL 0xd41a
ac718b69 119#define USB_UPS_CTRL 0xd800
43779f8d 120#define USB_MISC_0 0xd81a
121#define USB_POWER_CUT 0xd80a
122#define USB_AFE_CTRL2 0xd824
123#define USB_WDT11_CTRL 0xe43c
ac718b69 124#define USB_BP_BA 0xfc26
125#define USB_BP_0 0xfc28
126#define USB_BP_1 0xfc2a
127#define USB_BP_2 0xfc2c
128#define USB_BP_3 0xfc2e
129#define USB_BP_4 0xfc30
130#define USB_BP_5 0xfc32
131#define USB_BP_6 0xfc34
132#define USB_BP_7 0xfc36
43779f8d 133#define USB_BP_EN 0xfc38
ac718b69 134
135/* OCP Registers */
136#define OCP_ALDPS_CONFIG 0x2010
137#define OCP_EEE_CONFIG1 0x2080
138#define OCP_EEE_CONFIG2 0x2092
139#define OCP_EEE_CONFIG3 0x2094
ac244d3e 140#define OCP_BASE_MII 0xa400
ac718b69 141#define OCP_EEE_AR 0xa41a
142#define OCP_EEE_DATA 0xa41c
43779f8d 143#define OCP_PHY_STATUS 0xa420
144#define OCP_POWER_CFG 0xa430
145#define OCP_EEE_CFG 0xa432
146#define OCP_SRAM_ADDR 0xa436
147#define OCP_SRAM_DATA 0xa438
148#define OCP_DOWN_SPEED 0xa442
df35d283 149#define OCP_EEE_ABLE 0xa5c4
4c4a6b1b 150#define OCP_EEE_ADV 0xa5d0
df35d283 151#define OCP_EEE_LPABLE 0xa5d2
2dd49e0f 152#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
43779f8d 153#define OCP_ADC_CFG 0xbc06
154
155/* SRAM Register */
156#define SRAM_LPF_CFG 0x8012
157#define SRAM_10M_AMP1 0x8080
158#define SRAM_10M_AMP2 0x8082
159#define SRAM_IMPEDANCE 0x8084
ac718b69 160
161/* PLA_RCR */
162#define RCR_AAP 0x00000001
163#define RCR_APM 0x00000002
164#define RCR_AM 0x00000004
165#define RCR_AB 0x00000008
166#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
167
168/* PLA_RXFIFO_CTRL0 */
169#define RXFIFO_THR1_NORMAL 0x00080002
170#define RXFIFO_THR1_OOB 0x01800003
171
172/* PLA_RXFIFO_CTRL1 */
173#define RXFIFO_THR2_FULL 0x00000060
174#define RXFIFO_THR2_HIGH 0x00000038
175#define RXFIFO_THR2_OOB 0x0000004a
43779f8d 176#define RXFIFO_THR2_NORMAL 0x00a0
ac718b69 177
178/* PLA_RXFIFO_CTRL2 */
179#define RXFIFO_THR3_FULL 0x00000078
180#define RXFIFO_THR3_HIGH 0x00000048
181#define RXFIFO_THR3_OOB 0x0000005a
43779f8d 182#define RXFIFO_THR3_NORMAL 0x0110
ac718b69 183
184/* PLA_TXFIFO_CTRL */
185#define TXFIFO_THR_NORMAL 0x00400008
43779f8d 186#define TXFIFO_THR_NORMAL2 0x01000008
ac718b69 187
65bab84c 188/* PLA_DMY_REG0 */
189#define ECM_ALDPS 0x0002
190
ac718b69 191/* PLA_FMC */
192#define FMC_FCR_MCU_EN 0x0001
193
194/* PLA_EEEP_CR */
195#define EEEP_CR_EEEP_TX 0x0002
196
43779f8d 197/* PLA_WDT6_CTRL */
198#define WDT6_SET_MODE 0x0010
199
ac718b69 200/* PLA_TCR0 */
201#define TCR0_TX_EMPTY 0x0800
202#define TCR0_AUTO_FIFO 0x0080
203
204/* PLA_TCR1 */
205#define VERSION_MASK 0x7cf0
206
69b4b7a4 207/* PLA_MTPS */
208#define MTPS_JUMBO (12 * 1024 / 64)
209#define MTPS_DEFAULT (6 * 1024 / 64)
210
4f1d4d54 211/* PLA_RSTTALLY */
212#define TALLY_RESET 0x0001
213
ac718b69 214/* PLA_CR */
215#define CR_RST 0x10
216#define CR_RE 0x08
217#define CR_TE 0x04
218
219/* PLA_CRWECR */
220#define CRWECR_NORAML 0x00
221#define CRWECR_CONFIG 0xc0
222
223/* PLA_OOB_CTRL */
224#define NOW_IS_OOB 0x80
225#define TXFIFO_EMPTY 0x20
226#define RXFIFO_EMPTY 0x10
227#define LINK_LIST_READY 0x02
228#define DIS_MCU_CLROOB 0x01
229#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
230
231/* PLA_MISC_1 */
232#define RXDY_GATED_EN 0x0008
233
234/* PLA_SFF_STS_7 */
235#define RE_INIT_LL 0x8000
236#define MCU_BORW_EN 0x4000
237
238/* PLA_CPCR */
239#define CPCR_RX_VLAN 0x0040
240
241/* PLA_CFG_WOL */
242#define MAGIC_EN 0x0001
243
43779f8d 244/* PLA_TEREDO_CFG */
245#define TEREDO_SEL 0x8000
246#define TEREDO_WAKE_MASK 0x7f00
247#define TEREDO_RS_EVENT_MASK 0x00fe
248#define OOB_TEREDO_EN 0x0001
249
ac718b69 250/* PAL_BDC_CR */
251#define ALDPS_PROXY_MODE 0x0001
252
21ff2e89 253/* PLA_CONFIG34 */
254#define LINK_ON_WAKE_EN 0x0010
255#define LINK_OFF_WAKE_EN 0x0008
256
ac718b69 257/* PLA_CONFIG5 */
21ff2e89 258#define BWF_EN 0x0040
259#define MWF_EN 0x0020
260#define UWF_EN 0x0010
ac718b69 261#define LAN_WAKE_EN 0x0002
262
263/* PLA_LED_FEATURE */
264#define LED_MODE_MASK 0x0700
265
266/* PLA_PHY_PWR */
267#define TX_10M_IDLE_EN 0x0080
268#define PFM_PWM_SWITCH 0x0040
269
270/* PLA_MAC_PWR_CTRL */
271#define D3_CLK_GATED_EN 0x00004000
272#define MCU_CLK_RATIO 0x07010f07
273#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
43779f8d 274#define ALDPS_SPDWN_RATIO 0x0f87
275
276/* PLA_MAC_PWR_CTRL2 */
277#define EEE_SPDWN_RATIO 0x8007
278
279/* PLA_MAC_PWR_CTRL3 */
280#define PKT_AVAIL_SPDWN_EN 0x0100
281#define SUSPEND_SPDWN_EN 0x0004
282#define U1U2_SPDWN_EN 0x0002
283#define L1_SPDWN_EN 0x0001
284
285/* PLA_MAC_PWR_CTRL4 */
286#define PWRSAVE_SPDWN_EN 0x1000
287#define RXDV_SPDWN_EN 0x0800
288#define TX10MIDLE_EN 0x0100
289#define TP100_SPDWN_EN 0x0020
290#define TP500_SPDWN_EN 0x0010
291#define TP1000_SPDWN_EN 0x0008
292#define EEE_SPDWN_EN 0x0001
ac718b69 293
294/* PLA_GPHY_INTR_IMR */
295#define GPHY_STS_MSK 0x0001
296#define SPEED_DOWN_MSK 0x0002
297#define SPDWN_RXDV_MSK 0x0004
298#define SPDWN_LINKCHG_MSK 0x0008
299
300/* PLA_PHYAR */
301#define PHYAR_FLAG 0x80000000
302
303/* PLA_EEE_CR */
304#define EEE_RX_EN 0x0001
305#define EEE_TX_EN 0x0002
306
43779f8d 307/* PLA_BOOT_CTRL */
308#define AUTOLOAD_DONE 0x0002
309
65bab84c 310/* USB_USB2PHY */
311#define USB2PHY_SUSPEND 0x0001
312#define USB2PHY_L1 0x0002
313
314/* USB_SSPHYLINK2 */
315#define pwd_dn_scale_mask 0x3ffe
316#define pwd_dn_scale(x) ((x) << 1)
317
318/* USB_CSR_DUMMY1 */
319#define DYNAMIC_BURST 0x0001
320
321/* USB_CSR_DUMMY2 */
322#define EP4_FULL_FC 0x0001
323
ac718b69 324/* USB_DEV_STAT */
325#define STAT_SPEED_MASK 0x0006
326#define STAT_SPEED_HIGH 0x0000
a3cc465d 327#define STAT_SPEED_FULL 0x0002
ac718b69 328
329/* USB_TX_AGG */
330#define TX_AGG_MAX_THRESHOLD 0x03
331
332/* USB_RX_BUF_TH */
43779f8d 333#define RX_THR_SUPPER 0x0c350180
8e1f51bd 334#define RX_THR_HIGH 0x7a120180
43779f8d 335#define RX_THR_SLOW 0xffff0180
ac718b69 336
337/* USB_TX_DMA */
338#define TEST_MODE_DISABLE 0x00000001
339#define TX_SIZE_ADJUST1 0x00000100
340
341/* USB_UPS_CTRL */
342#define POWER_CUT 0x0100
343
344/* USB_PM_CTRL_STATUS */
8e1f51bd 345#define RESUME_INDICATE 0x0001
ac718b69 346
347/* USB_USB_CTRL */
348#define RX_AGG_DISABLE 0x0010
e90fba8d 349#define RX_ZERO_EN 0x0080
ac718b69 350
43779f8d 351/* USB_U2P3_CTRL */
352#define U2P3_ENABLE 0x0001
353
354/* USB_POWER_CUT */
355#define PWR_EN 0x0001
356#define PHASE2_EN 0x0008
357
358/* USB_MISC_0 */
359#define PCUT_STATUS 0x0001
360
464ec10a 361/* USB_RX_EARLY_TIMEOUT */
362#define COALESCE_SUPER 85000U
363#define COALESCE_HIGH 250000U
364#define COALESCE_SLOW 524280U
43779f8d 365
366/* USB_WDT11_CTRL */
367#define TIMER11_EN 0x0001
368
369/* USB_LPM_CTRL */
65bab84c 370/* bit 4 ~ 5: fifo empty boundary */
371#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
372/* bit 2 ~ 3: LMP timer */
43779f8d 373#define LPM_TIMER_MASK 0x0c
374#define LPM_TIMER_500MS 0x04 /* 500 ms */
375#define LPM_TIMER_500US 0x0c /* 500 us */
65bab84c 376#define ROK_EXIT_LPM 0x02
43779f8d 377
378/* USB_AFE_CTRL2 */
379#define SEN_VAL_MASK 0xf800
380#define SEN_VAL_NORMAL 0xa000
381#define SEL_RXIDLE 0x0100
382
ac718b69 383/* OCP_ALDPS_CONFIG */
384#define ENPWRSAVE 0x8000
385#define ENPDNPS 0x0200
386#define LINKENA 0x0100
387#define DIS_SDSAVE 0x0010
388
43779f8d 389/* OCP_PHY_STATUS */
390#define PHY_STAT_MASK 0x0007
391#define PHY_STAT_LAN_ON 3
392#define PHY_STAT_PWRDN 5
393
394/* OCP_POWER_CFG */
395#define EEE_CLKDIV_EN 0x8000
396#define EN_ALDPS 0x0004
397#define EN_10M_PLLOFF 0x0001
398
ac718b69 399/* OCP_EEE_CONFIG1 */
400#define RG_TXLPI_MSK_HFDUP 0x8000
401#define RG_MATCLR_EN 0x4000
402#define EEE_10_CAP 0x2000
403#define EEE_NWAY_EN 0x1000
404#define TX_QUIET_EN 0x0200
405#define RX_QUIET_EN 0x0100
d24f6134 406#define sd_rise_time_mask 0x0070
4c4a6b1b 407#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
ac718b69 408#define RG_RXLPI_MSK_HFDUP 0x0008
409#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
410
411/* OCP_EEE_CONFIG2 */
412#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
413#define RG_DACQUIET_EN 0x0400
414#define RG_LDVQUIET_EN 0x0200
415#define RG_CKRSEL 0x0020
416#define RG_EEEPRG_EN 0x0010
417
418/* OCP_EEE_CONFIG3 */
d24f6134 419#define fast_snr_mask 0xff80
4c4a6b1b 420#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
ac718b69 421#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
422#define MSK_PH 0x0006 /* bit 0 ~ 3 */
423
424/* OCP_EEE_AR */
425/* bit[15:14] function */
426#define FUN_ADDR 0x0000
427#define FUN_DATA 0x4000
428/* bit[4:0] device addr */
ac718b69 429
43779f8d 430/* OCP_EEE_CFG */
431#define CTAP_SHORT_EN 0x0040
432#define EEE10_EN 0x0010
433
434/* OCP_DOWN_SPEED */
435#define EN_10M_BGOFF 0x0080
436
2dd49e0f 437/* OCP_PHY_STATE */
438#define TXDIS_STATE 0x01
439#define ABD_STATE 0x02
440
43779f8d 441/* OCP_ADC_CFG */
442#define CKADSEL_L 0x0100
443#define ADC_EN 0x0080
444#define EN_EMI_L 0x0040
445
446/* SRAM_LPF_CFG */
447#define LPF_AUTO_TUNE 0x8000
448
449/* SRAM_10M_AMP1 */
450#define GDAC_IB_UPALL 0x0008
451
452/* SRAM_10M_AMP2 */
453#define AMP_DN 0x0200
454
455/* SRAM_IMPEDANCE */
456#define RX_DRIVING_MASK 0x6000
457
ac718b69 458enum rtl_register_content {
43779f8d 459 _1000bps = 0x10,
ac718b69 460 _100bps = 0x08,
461 _10bps = 0x04,
462 LINK_STATUS = 0x02,
463 FULL_DUP = 0x01,
464};
465
1764bcd9 466#define RTL8152_MAX_TX 4
ebc2ec48 467#define RTL8152_MAX_RX 10
40a82917 468#define INTBUFSIZE 2
8e1f51bd 469#define CRC_SIZE 4
470#define TX_ALIGN 4
471#define RX_ALIGN 8
40a82917 472
473#define INTR_LINK 0x0004
ebc2ec48 474
ac718b69 475#define RTL8152_REQT_READ 0xc0
476#define RTL8152_REQT_WRITE 0x40
477#define RTL8152_REQ_GET_REGS 0x05
478#define RTL8152_REQ_SET_REGS 0x05
479
480#define BYTE_EN_DWORD 0xff
481#define BYTE_EN_WORD 0x33
482#define BYTE_EN_BYTE 0x11
483#define BYTE_EN_SIX_BYTES 0x3f
484#define BYTE_EN_START_MASK 0x0f
485#define BYTE_EN_END_MASK 0xf0
486
69b4b7a4 487#define RTL8153_MAX_PACKET 9216 /* 9K */
488#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
ac718b69 489#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
69b4b7a4 490#define RTL8153_RMS RTL8153_MAX_PACKET
b8125404 491#define RTL8152_TX_TIMEOUT (5 * HZ)
d823ab68 492#define RTL8152_NAPI_WEIGHT 64
ac718b69 493
494/* rtl8152 flags */
495enum rtl8152_flags {
496 RTL8152_UNPLUG = 0,
ac718b69 497 RTL8152_SET_RX_MODE,
40a82917 498 WORK_ENABLE,
499 RTL8152_LINK_CHG,
9a4be1bd 500 SELECTIVE_SUSPEND,
aa66a5f1 501 PHY_RESET,
d823ab68 502 SCHEDULE_NAPI,
ac718b69 503};
504
505/* Define these values to match your device */
506#define VENDOR_ID_REALTEK 0x0bda
43779f8d 507#define VENDOR_ID_SAMSUNG 0x04e8
347eec34 508#define VENDOR_ID_LENOVO 0x17ef
d065c3c1 509#define VENDOR_ID_NVIDIA 0x0955
ac718b69 510
511#define MCU_TYPE_PLA 0x0100
512#define MCU_TYPE_USB 0x0000
513
4f1d4d54 514struct tally_counter {
515 __le64 tx_packets;
516 __le64 rx_packets;
517 __le64 tx_errors;
518 __le32 rx_errors;
519 __le16 rx_missed;
520 __le16 align_errors;
521 __le32 tx_one_collision;
522 __le32 tx_multi_collision;
523 __le64 rx_unicast;
524 __le64 rx_broadcast;
525 __le32 rx_multicast;
526 __le16 tx_aborted;
f37119c5 527 __le16 tx_underrun;
4f1d4d54 528};
529
ac718b69 530struct rx_desc {
500b6d7e 531 __le32 opts1;
ac718b69 532#define RX_LEN_MASK 0x7fff
565cab0a 533
500b6d7e 534 __le32 opts2;
f5aaaa6d 535#define RD_UDP_CS BIT(23)
536#define RD_TCP_CS BIT(22)
537#define RD_IPV6_CS BIT(20)
538#define RD_IPV4_CS BIT(19)
565cab0a 539
500b6d7e 540 __le32 opts3;
f5aaaa6d 541#define IPF BIT(23) /* IP checksum fail */
542#define UDPF BIT(22) /* UDP checksum fail */
543#define TCPF BIT(21) /* TCP checksum fail */
544#define RX_VLAN_TAG BIT(16)
565cab0a 545
500b6d7e 546 __le32 opts4;
547 __le32 opts5;
548 __le32 opts6;
ac718b69 549};
550
551struct tx_desc {
500b6d7e 552 __le32 opts1;
f5aaaa6d 553#define TX_FS BIT(31) /* First segment of a packet */
554#define TX_LS BIT(30) /* Final segment of a packet */
555#define GTSENDV4 BIT(28)
556#define GTSENDV6 BIT(27)
60c89071 557#define GTTCPHO_SHIFT 18
6128d1bb 558#define GTTCPHO_MAX 0x7fU
60c89071 559#define TX_LEN_MAX 0x3ffffU
5bd23881 560
500b6d7e 561 __le32 opts2;
f5aaaa6d 562#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
563#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
564#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
565#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
60c89071 566#define MSS_SHIFT 17
567#define MSS_MAX 0x7ffU
568#define TCPHO_SHIFT 17
6128d1bb 569#define TCPHO_MAX 0x7ffU
f5aaaa6d 570#define TX_VLAN_TAG BIT(16)
ac718b69 571};
572
dff4e8ad 573struct r8152;
574
ebc2ec48 575struct rx_agg {
576 struct list_head list;
577 struct urb *urb;
dff4e8ad 578 struct r8152 *context;
ebc2ec48 579 void *buffer;
580 void *head;
581};
582
583struct tx_agg {
584 struct list_head list;
585 struct urb *urb;
dff4e8ad 586 struct r8152 *context;
ebc2ec48 587 void *buffer;
588 void *head;
589 u32 skb_num;
590 u32 skb_len;
591};
592
ac718b69 593struct r8152 {
594 unsigned long flags;
595 struct usb_device *udev;
d823ab68 596 struct napi_struct napi;
40a82917 597 struct usb_interface *intf;
ac718b69 598 struct net_device *netdev;
40a82917 599 struct urb *intr_urb;
ebc2ec48 600 struct tx_agg tx_info[RTL8152_MAX_TX];
601 struct rx_agg rx_info[RTL8152_MAX_RX];
602 struct list_head rx_done, tx_free;
d823ab68 603 struct sk_buff_head tx_queue, rx_queue;
ebc2ec48 604 spinlock_t rx_lock, tx_lock;
a028a9e0 605 struct delayed_work schedule, hw_phy_work;
ac718b69 606 struct mii_if_info mii;
b5403273 607 struct mutex control; /* use for hw setting */
5ee3c60c 608#ifdef CONFIG_PM_SLEEP
609 struct notifier_block pm_notifier;
610#endif
c81229c9 611
612 struct rtl_ops {
613 void (*init)(struct r8152 *);
614 int (*enable)(struct r8152 *);
615 void (*disable)(struct r8152 *);
7e9da481 616 void (*up)(struct r8152 *);
c81229c9 617 void (*down)(struct r8152 *);
618 void (*unload)(struct r8152 *);
df35d283 619 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
620 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
2dd49e0f 621 bool (*in_nway)(struct r8152 *);
a028a9e0 622 void (*hw_phy_cfg)(struct r8152 *);
c81229c9 623 } rtl_ops;
624
40a82917 625 int intr_interval;
21ff2e89 626 u32 saved_wolopts;
ac718b69 627 u32 msg_enable;
dd1b119c 628 u32 tx_qlen;
464ec10a 629 u32 coalesce;
ac718b69 630 u16 ocp_base;
40a82917 631 u8 *intr_buff;
ac718b69 632 u8 version;
ac718b69 633};
634
635enum rtl_version {
636 RTL_VER_UNKNOWN = 0,
637 RTL_VER_01,
43779f8d 638 RTL_VER_02,
639 RTL_VER_03,
640 RTL_VER_04,
641 RTL_VER_05,
fb02eb4a 642 RTL_VER_06,
43779f8d 643 RTL_VER_MAX
ac718b69 644};
645
60c89071 646enum tx_csum_stat {
647 TX_CSUM_SUCCESS = 0,
648 TX_CSUM_TSO,
649 TX_CSUM_NONE
650};
651
ac718b69 652/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
653 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
654 */
655static const int multicast_filter_limit = 32;
52aec126 656static unsigned int agg_buf_sz = 16384;
ac718b69 657
52aec126 658#define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
60c89071 659 VLAN_ETH_HLEN - VLAN_HLEN)
660
ac718b69 661static
662int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
663{
31787f53 664 int ret;
665 void *tmp;
666
667 tmp = kmalloc(size, GFP_KERNEL);
668 if (!tmp)
669 return -ENOMEM;
670
671 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
b209af99 672 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
673 value, index, tmp, size, 500);
31787f53 674
675 memcpy(data, tmp, size);
676 kfree(tmp);
677
678 return ret;
ac718b69 679}
680
681static
682int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
683{
31787f53 684 int ret;
685 void *tmp;
686
c4438f03 687 tmp = kmemdup(data, size, GFP_KERNEL);
31787f53 688 if (!tmp)
689 return -ENOMEM;
690
31787f53 691 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
b209af99 692 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
693 value, index, tmp, size, 500);
31787f53 694
695 kfree(tmp);
db8515ef 696
31787f53 697 return ret;
ac718b69 698}
699
700static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
b209af99 701 void *data, u16 type)
ac718b69 702{
45f4a19f 703 u16 limit = 64;
704 int ret = 0;
ac718b69 705
706 if (test_bit(RTL8152_UNPLUG, &tp->flags))
707 return -ENODEV;
708
709 /* both size and indix must be 4 bytes align */
710 if ((size & 3) || !size || (index & 3) || !data)
711 return -EPERM;
712
713 if ((u32)index + (u32)size > 0xffff)
714 return -EPERM;
715
716 while (size) {
717 if (size > limit) {
718 ret = get_registers(tp, index, type, limit, data);
719 if (ret < 0)
720 break;
721
722 index += limit;
723 data += limit;
724 size -= limit;
725 } else {
726 ret = get_registers(tp, index, type, size, data);
727 if (ret < 0)
728 break;
729
730 index += size;
731 data += size;
732 size = 0;
733 break;
734 }
735 }
736
67610496 737 if (ret == -ENODEV)
738 set_bit(RTL8152_UNPLUG, &tp->flags);
739
ac718b69 740 return ret;
741}
742
743static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
b209af99 744 u16 size, void *data, u16 type)
ac718b69 745{
45f4a19f 746 int ret;
747 u16 byteen_start, byteen_end, byen;
748 u16 limit = 512;
ac718b69 749
750 if (test_bit(RTL8152_UNPLUG, &tp->flags))
751 return -ENODEV;
752
753 /* both size and indix must be 4 bytes align */
754 if ((size & 3) || !size || (index & 3) || !data)
755 return -EPERM;
756
757 if ((u32)index + (u32)size > 0xffff)
758 return -EPERM;
759
760 byteen_start = byteen & BYTE_EN_START_MASK;
761 byteen_end = byteen & BYTE_EN_END_MASK;
762
763 byen = byteen_start | (byteen_start << 4);
764 ret = set_registers(tp, index, type | byen, 4, data);
765 if (ret < 0)
766 goto error1;
767
768 index += 4;
769 data += 4;
770 size -= 4;
771
772 if (size) {
773 size -= 4;
774
775 while (size) {
776 if (size > limit) {
777 ret = set_registers(tp, index,
b209af99 778 type | BYTE_EN_DWORD,
779 limit, data);
ac718b69 780 if (ret < 0)
781 goto error1;
782
783 index += limit;
784 data += limit;
785 size -= limit;
786 } else {
787 ret = set_registers(tp, index,
b209af99 788 type | BYTE_EN_DWORD,
789 size, data);
ac718b69 790 if (ret < 0)
791 goto error1;
792
793 index += size;
794 data += size;
795 size = 0;
796 break;
797 }
798 }
799
800 byen = byteen_end | (byteen_end >> 4);
801 ret = set_registers(tp, index, type | byen, 4, data);
802 if (ret < 0)
803 goto error1;
804 }
805
806error1:
67610496 807 if (ret == -ENODEV)
808 set_bit(RTL8152_UNPLUG, &tp->flags);
809
ac718b69 810 return ret;
811}
812
813static inline
814int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
815{
816 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
817}
818
819static inline
820int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
821{
822 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
823}
824
825static inline
826int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
827{
828 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
829}
830
831static inline
832int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
833{
834 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
835}
836
837static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
838{
c8826de8 839 __le32 data;
ac718b69 840
c8826de8 841 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 842
843 return __le32_to_cpu(data);
844}
845
846static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
847{
c8826de8 848 __le32 tmp = __cpu_to_le32(data);
849
850 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 851}
852
853static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
854{
855 u32 data;
c8826de8 856 __le32 tmp;
ac718b69 857 u8 shift = index & 2;
858
859 index &= ~3;
860
c8826de8 861 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 862
c8826de8 863 data = __le32_to_cpu(tmp);
ac718b69 864 data >>= (shift * 8);
865 data &= 0xffff;
866
867 return (u16)data;
868}
869
870static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
871{
c8826de8 872 u32 mask = 0xffff;
873 __le32 tmp;
ac718b69 874 u16 byen = BYTE_EN_WORD;
875 u8 shift = index & 2;
876
877 data &= mask;
878
879 if (index & 2) {
880 byen <<= shift;
881 mask <<= (shift * 8);
882 data <<= (shift * 8);
883 index &= ~3;
884 }
885
c8826de8 886 tmp = __cpu_to_le32(data);
ac718b69 887
c8826de8 888 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 889}
890
891static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
892{
893 u32 data;
c8826de8 894 __le32 tmp;
ac718b69 895 u8 shift = index & 3;
896
897 index &= ~3;
898
c8826de8 899 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 900
c8826de8 901 data = __le32_to_cpu(tmp);
ac718b69 902 data >>= (shift * 8);
903 data &= 0xff;
904
905 return (u8)data;
906}
907
908static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
909{
c8826de8 910 u32 mask = 0xff;
911 __le32 tmp;
ac718b69 912 u16 byen = BYTE_EN_BYTE;
913 u8 shift = index & 3;
914
915 data &= mask;
916
917 if (index & 3) {
918 byen <<= shift;
919 mask <<= (shift * 8);
920 data <<= (shift * 8);
921 index &= ~3;
922 }
923
c8826de8 924 tmp = __cpu_to_le32(data);
ac718b69 925
c8826de8 926 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 927}
928
ac244d3e 929static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 930{
931 u16 ocp_base, ocp_index;
932
933 ocp_base = addr & 0xf000;
934 if (ocp_base != tp->ocp_base) {
935 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
936 tp->ocp_base = ocp_base;
937 }
938
939 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 940 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 941}
942
ac244d3e 943static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 944{
ac244d3e 945 u16 ocp_base, ocp_index;
ac718b69 946
ac244d3e 947 ocp_base = addr & 0xf000;
948 if (ocp_base != tp->ocp_base) {
949 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
950 tp->ocp_base = ocp_base;
ac718b69 951 }
ac244d3e 952
953 ocp_index = (addr & 0x0fff) | 0xb000;
954 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 955}
956
ac244d3e 957static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 958{
ac244d3e 959 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
960}
ac718b69 961
ac244d3e 962static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
963{
964 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 965}
966
43779f8d 967static void sram_write(struct r8152 *tp, u16 addr, u16 data)
968{
969 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
970 ocp_reg_write(tp, OCP_SRAM_DATA, data);
971}
972
ac718b69 973static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
974{
975 struct r8152 *tp = netdev_priv(netdev);
9a4be1bd 976 int ret;
ac718b69 977
6871438c 978 if (test_bit(RTL8152_UNPLUG, &tp->flags))
979 return -ENODEV;
980
ac718b69 981 if (phy_id != R8152_PHY_ID)
982 return -EINVAL;
983
9a4be1bd 984 ret = r8152_mdio_read(tp, reg);
985
9a4be1bd 986 return ret;
ac718b69 987}
988
989static
990void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
991{
992 struct r8152 *tp = netdev_priv(netdev);
993
6871438c 994 if (test_bit(RTL8152_UNPLUG, &tp->flags))
995 return;
996
ac718b69 997 if (phy_id != R8152_PHY_ID)
998 return;
999
1000 r8152_mdio_write(tp, reg, val);
1001}
1002
b209af99 1003static int
1004r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
ebc2ec48 1005
8ba789ab 1006static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1007{
1008 struct r8152 *tp = netdev_priv(netdev);
1009 struct sockaddr *addr = p;
ea6a7112 1010 int ret = -EADDRNOTAVAIL;
8ba789ab 1011
1012 if (!is_valid_ether_addr(addr->sa_data))
ea6a7112 1013 goto out1;
1014
1015 ret = usb_autopm_get_interface(tp->intf);
1016 if (ret < 0)
1017 goto out1;
8ba789ab 1018
b5403273 1019 mutex_lock(&tp->control);
1020
8ba789ab 1021 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1022
1023 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1024 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1025 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1026
b5403273 1027 mutex_unlock(&tp->control);
1028
ea6a7112 1029 usb_autopm_put_interface(tp->intf);
1030out1:
1031 return ret;
8ba789ab 1032}
1033
179bb6d7 1034static int set_ethernet_addr(struct r8152 *tp)
ac718b69 1035{
1036 struct net_device *dev = tp->netdev;
179bb6d7 1037 struct sockaddr sa;
8a91c824 1038 int ret;
ac718b69 1039
8a91c824 1040 if (tp->version == RTL_VER_01)
179bb6d7 1041 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
8a91c824 1042 else
179bb6d7 1043 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
8a91c824 1044
1045 if (ret < 0) {
179bb6d7 1046 netif_err(tp, probe, dev, "Get ether addr fail\n");
1047 } else if (!is_valid_ether_addr(sa.sa_data)) {
1048 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1049 sa.sa_data);
1050 eth_hw_addr_random(dev);
1051 ether_addr_copy(sa.sa_data, dev->dev_addr);
1052 ret = rtl8152_set_mac_address(dev, &sa);
1053 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1054 sa.sa_data);
8a91c824 1055 } else {
179bb6d7 1056 if (tp->version == RTL_VER_01)
1057 ether_addr_copy(dev->dev_addr, sa.sa_data);
1058 else
1059 ret = rtl8152_set_mac_address(dev, &sa);
ac718b69 1060 }
179bb6d7 1061
1062 return ret;
ac718b69 1063}
1064
ac718b69 1065static void read_bulk_callback(struct urb *urb)
1066{
ac718b69 1067 struct net_device *netdev;
ac718b69 1068 int status = urb->status;
ebc2ec48 1069 struct rx_agg *agg;
1070 struct r8152 *tp;
ac718b69 1071
ebc2ec48 1072 agg = urb->context;
1073 if (!agg)
1074 return;
1075
1076 tp = agg->context;
ac718b69 1077 if (!tp)
1078 return;
ebc2ec48 1079
ac718b69 1080 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1081 return;
ebc2ec48 1082
1083 if (!test_bit(WORK_ENABLE, &tp->flags))
1084 return;
1085
ac718b69 1086 netdev = tp->netdev;
7559fb2f 1087
1088 /* When link down, the driver would cancel all bulks. */
1089 /* This avoid the re-submitting bulk */
ebc2ec48 1090 if (!netif_carrier_ok(netdev))
ac718b69 1091 return;
1092
9a4be1bd 1093 usb_mark_last_busy(tp->udev);
1094
ac718b69 1095 switch (status) {
1096 case 0:
ebc2ec48 1097 if (urb->actual_length < ETH_ZLEN)
1098 break;
1099
2685d410 1100 spin_lock(&tp->rx_lock);
ebc2ec48 1101 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1102 spin_unlock(&tp->rx_lock);
d823ab68 1103 napi_schedule(&tp->napi);
ebc2ec48 1104 return;
ac718b69 1105 case -ESHUTDOWN:
1106 set_bit(RTL8152_UNPLUG, &tp->flags);
1107 netif_device_detach(tp->netdev);
ebc2ec48 1108 return;
ac718b69 1109 case -ENOENT:
1110 return; /* the urb is in unlink state */
1111 case -ETIME:
4a8deae2
HW
1112 if (net_ratelimit())
1113 netdev_warn(netdev, "maybe reset is needed?\n");
ebc2ec48 1114 break;
ac718b69 1115 default:
4a8deae2
HW
1116 if (net_ratelimit())
1117 netdev_warn(netdev, "Rx status %d\n", status);
ebc2ec48 1118 break;
ac718b69 1119 }
1120
a0fccd48 1121 r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 1122}
1123
ebc2ec48 1124static void write_bulk_callback(struct urb *urb)
ac718b69 1125{
ebc2ec48 1126 struct net_device_stats *stats;
d104eafa 1127 struct net_device *netdev;
ebc2ec48 1128 struct tx_agg *agg;
ac718b69 1129 struct r8152 *tp;
ebc2ec48 1130 int status = urb->status;
ac718b69 1131
ebc2ec48 1132 agg = urb->context;
1133 if (!agg)
ac718b69 1134 return;
1135
ebc2ec48 1136 tp = agg->context;
1137 if (!tp)
1138 return;
1139
d104eafa 1140 netdev = tp->netdev;
05e0f1aa 1141 stats = &netdev->stats;
ebc2ec48 1142 if (status) {
4a8deae2 1143 if (net_ratelimit())
d104eafa 1144 netdev_warn(netdev, "Tx status %d\n", status);
ebc2ec48 1145 stats->tx_errors += agg->skb_num;
ac718b69 1146 } else {
ebc2ec48 1147 stats->tx_packets += agg->skb_num;
1148 stats->tx_bytes += agg->skb_len;
ac718b69 1149 }
1150
2685d410 1151 spin_lock(&tp->tx_lock);
ebc2ec48 1152 list_add_tail(&agg->list, &tp->tx_free);
2685d410 1153 spin_unlock(&tp->tx_lock);
ebc2ec48 1154
9a4be1bd 1155 usb_autopm_put_interface_async(tp->intf);
1156
d104eafa 1157 if (!netif_carrier_ok(netdev))
ebc2ec48 1158 return;
1159
1160 if (!test_bit(WORK_ENABLE, &tp->flags))
1161 return;
1162
1163 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1164 return;
1165
1166 if (!skb_queue_empty(&tp->tx_queue))
d823ab68 1167 napi_schedule(&tp->napi);
ac718b69 1168}
1169
40a82917 1170static void intr_callback(struct urb *urb)
1171{
1172 struct r8152 *tp;
500b6d7e 1173 __le16 *d;
40a82917 1174 int status = urb->status;
1175 int res;
1176
1177 tp = urb->context;
1178 if (!tp)
1179 return;
1180
1181 if (!test_bit(WORK_ENABLE, &tp->flags))
1182 return;
1183
1184 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1185 return;
1186
1187 switch (status) {
1188 case 0: /* success */
1189 break;
1190 case -ECONNRESET: /* unlink */
1191 case -ESHUTDOWN:
1192 netif_device_detach(tp->netdev);
1193 case -ENOENT:
d59c876d 1194 case -EPROTO:
1195 netif_info(tp, intr, tp->netdev,
1196 "Stop submitting intr, status %d\n", status);
40a82917 1197 return;
1198 case -EOVERFLOW:
1199 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1200 goto resubmit;
1201 /* -EPIPE: should clear the halt */
1202 default:
1203 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1204 goto resubmit;
1205 }
1206
1207 d = urb->transfer_buffer;
1208 if (INTR_LINK & __le16_to_cpu(d[0])) {
51d979fa 1209 if (!netif_carrier_ok(tp->netdev)) {
40a82917 1210 set_bit(RTL8152_LINK_CHG, &tp->flags);
1211 schedule_delayed_work(&tp->schedule, 0);
1212 }
1213 } else {
51d979fa 1214 if (netif_carrier_ok(tp->netdev)) {
40a82917 1215 set_bit(RTL8152_LINK_CHG, &tp->flags);
1216 schedule_delayed_work(&tp->schedule, 0);
1217 }
1218 }
1219
1220resubmit:
1221 res = usb_submit_urb(urb, GFP_ATOMIC);
67610496 1222 if (res == -ENODEV) {
1223 set_bit(RTL8152_UNPLUG, &tp->flags);
40a82917 1224 netif_device_detach(tp->netdev);
67610496 1225 } else if (res) {
40a82917 1226 netif_err(tp, intr, tp->netdev,
4a8deae2 1227 "can't resubmit intr, status %d\n", res);
67610496 1228 }
40a82917 1229}
1230
ebc2ec48 1231static inline void *rx_agg_align(void *data)
1232{
8e1f51bd 1233 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 1234}
1235
1236static inline void *tx_agg_align(void *data)
1237{
8e1f51bd 1238 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 1239}
1240
1241static void free_all_mem(struct r8152 *tp)
1242{
1243 int i;
1244
1245 for (i = 0; i < RTL8152_MAX_RX; i++) {
9629e3c0 1246 usb_free_urb(tp->rx_info[i].urb);
1247 tp->rx_info[i].urb = NULL;
ebc2ec48 1248
9629e3c0 1249 kfree(tp->rx_info[i].buffer);
1250 tp->rx_info[i].buffer = NULL;
1251 tp->rx_info[i].head = NULL;
ebc2ec48 1252 }
1253
1254 for (i = 0; i < RTL8152_MAX_TX; i++) {
9629e3c0 1255 usb_free_urb(tp->tx_info[i].urb);
1256 tp->tx_info[i].urb = NULL;
ebc2ec48 1257
9629e3c0 1258 kfree(tp->tx_info[i].buffer);
1259 tp->tx_info[i].buffer = NULL;
1260 tp->tx_info[i].head = NULL;
ebc2ec48 1261 }
40a82917 1262
9629e3c0 1263 usb_free_urb(tp->intr_urb);
1264 tp->intr_urb = NULL;
40a82917 1265
9629e3c0 1266 kfree(tp->intr_buff);
1267 tp->intr_buff = NULL;
ebc2ec48 1268}
1269
1270static int alloc_all_mem(struct r8152 *tp)
1271{
1272 struct net_device *netdev = tp->netdev;
40a82917 1273 struct usb_interface *intf = tp->intf;
1274 struct usb_host_interface *alt = intf->cur_altsetting;
1275 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 1276 struct urb *urb;
1277 int node, i;
1278 u8 *buf;
1279
1280 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1281
1282 spin_lock_init(&tp->rx_lock);
1283 spin_lock_init(&tp->tx_lock);
ebc2ec48 1284 INIT_LIST_HEAD(&tp->tx_free);
1285 skb_queue_head_init(&tp->tx_queue);
d823ab68 1286 skb_queue_head_init(&tp->rx_queue);
ebc2ec48 1287
1288 for (i = 0; i < RTL8152_MAX_RX; i++) {
52aec126 1289 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1290 if (!buf)
1291 goto err1;
1292
1293 if (buf != rx_agg_align(buf)) {
1294 kfree(buf);
52aec126 1295 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
8e1f51bd 1296 node);
ebc2ec48 1297 if (!buf)
1298 goto err1;
1299 }
1300
1301 urb = usb_alloc_urb(0, GFP_KERNEL);
1302 if (!urb) {
1303 kfree(buf);
1304 goto err1;
1305 }
1306
1307 INIT_LIST_HEAD(&tp->rx_info[i].list);
1308 tp->rx_info[i].context = tp;
1309 tp->rx_info[i].urb = urb;
1310 tp->rx_info[i].buffer = buf;
1311 tp->rx_info[i].head = rx_agg_align(buf);
1312 }
1313
1314 for (i = 0; i < RTL8152_MAX_TX; i++) {
52aec126 1315 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1316 if (!buf)
1317 goto err1;
1318
1319 if (buf != tx_agg_align(buf)) {
1320 kfree(buf);
52aec126 1321 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
8e1f51bd 1322 node);
ebc2ec48 1323 if (!buf)
1324 goto err1;
1325 }
1326
1327 urb = usb_alloc_urb(0, GFP_KERNEL);
1328 if (!urb) {
1329 kfree(buf);
1330 goto err1;
1331 }
1332
1333 INIT_LIST_HEAD(&tp->tx_info[i].list);
1334 tp->tx_info[i].context = tp;
1335 tp->tx_info[i].urb = urb;
1336 tp->tx_info[i].buffer = buf;
1337 tp->tx_info[i].head = tx_agg_align(buf);
1338
1339 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1340 }
1341
40a82917 1342 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1343 if (!tp->intr_urb)
1344 goto err1;
1345
1346 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1347 if (!tp->intr_buff)
1348 goto err1;
1349
1350 tp->intr_interval = (int)ep_intr->desc.bInterval;
1351 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
b209af99 1352 tp->intr_buff, INTBUFSIZE, intr_callback,
1353 tp, tp->intr_interval);
40a82917 1354
ebc2ec48 1355 return 0;
1356
1357err1:
1358 free_all_mem(tp);
1359 return -ENOMEM;
1360}
1361
0de98f6c 1362static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1363{
1364 struct tx_agg *agg = NULL;
1365 unsigned long flags;
1366
21949ab7 1367 if (list_empty(&tp->tx_free))
1368 return NULL;
1369
0de98f6c 1370 spin_lock_irqsave(&tp->tx_lock, flags);
1371 if (!list_empty(&tp->tx_free)) {
1372 struct list_head *cursor;
1373
1374 cursor = tp->tx_free.next;
1375 list_del_init(cursor);
1376 agg = list_entry(cursor, struct tx_agg, list);
1377 }
1378 spin_unlock_irqrestore(&tp->tx_lock, flags);
1379
1380 return agg;
1381}
1382
b209af99 1383/* r8152_csum_workaround()
6128d1bb 1384 * The hw limites the value the transport offset. When the offset is out of the
1385 * range, calculate the checksum by sw.
1386 */
1387static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1388 struct sk_buff_head *list)
1389{
1390 if (skb_shinfo(skb)->gso_size) {
1391 netdev_features_t features = tp->netdev->features;
1392 struct sk_buff_head seg_list;
1393 struct sk_buff *segs, *nskb;
1394
a91d45f1 1395 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6128d1bb 1396 segs = skb_gso_segment(skb, features);
1397 if (IS_ERR(segs) || !segs)
1398 goto drop;
1399
1400 __skb_queue_head_init(&seg_list);
1401
1402 do {
1403 nskb = segs;
1404 segs = segs->next;
1405 nskb->next = NULL;
1406 __skb_queue_tail(&seg_list, nskb);
1407 } while (segs);
1408
1409 skb_queue_splice(&seg_list, list);
1410 dev_kfree_skb(skb);
1411 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1412 if (skb_checksum_help(skb) < 0)
1413 goto drop;
1414
1415 __skb_queue_head(list, skb);
1416 } else {
1417 struct net_device_stats *stats;
1418
1419drop:
1420 stats = &tp->netdev->stats;
1421 stats->tx_dropped++;
1422 dev_kfree_skb(skb);
1423 }
1424}
1425
b209af99 1426/* msdn_giant_send_check()
6128d1bb 1427 * According to the document of microsoft, the TCP Pseudo Header excludes the
1428 * packet length for IPv6 TCP large packets.
1429 */
1430static int msdn_giant_send_check(struct sk_buff *skb)
1431{
1432 const struct ipv6hdr *ipv6h;
1433 struct tcphdr *th;
fcb308d5 1434 int ret;
1435
1436 ret = skb_cow_head(skb, 0);
1437 if (ret)
1438 return ret;
6128d1bb 1439
1440 ipv6h = ipv6_hdr(skb);
1441 th = tcp_hdr(skb);
1442
1443 th->check = 0;
1444 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1445
fcb308d5 1446 return ret;
6128d1bb 1447}
1448
c5554298 1449static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1450{
df8a39de 1451 if (skb_vlan_tag_present(skb)) {
c5554298 1452 u32 opts2;
1453
df8a39de 1454 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
c5554298 1455 desc->opts2 |= cpu_to_le32(opts2);
1456 }
1457}
1458
1459static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1460{
1461 u32 opts2 = le32_to_cpu(desc->opts2);
1462
1463 if (opts2 & RX_VLAN_TAG)
1464 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1465 swab16(opts2 & 0xffff));
1466}
1467
60c89071 1468static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1469 struct sk_buff *skb, u32 len, u32 transport_offset)
1470{
1471 u32 mss = skb_shinfo(skb)->gso_size;
1472 u32 opts1, opts2 = 0;
1473 int ret = TX_CSUM_SUCCESS;
1474
1475 WARN_ON_ONCE(len > TX_LEN_MAX);
1476
1477 opts1 = len | TX_FS | TX_LS;
1478
1479 if (mss) {
6128d1bb 1480 if (transport_offset > GTTCPHO_MAX) {
1481 netif_warn(tp, tx_err, tp->netdev,
1482 "Invalid transport offset 0x%x for TSO\n",
1483 transport_offset);
1484 ret = TX_CSUM_TSO;
1485 goto unavailable;
1486 }
1487
6e74d174 1488 switch (vlan_get_protocol(skb)) {
60c89071 1489 case htons(ETH_P_IP):
1490 opts1 |= GTSENDV4;
1491 break;
1492
6128d1bb 1493 case htons(ETH_P_IPV6):
fcb308d5 1494 if (msdn_giant_send_check(skb)) {
1495 ret = TX_CSUM_TSO;
1496 goto unavailable;
1497 }
6128d1bb 1498 opts1 |= GTSENDV6;
6128d1bb 1499 break;
1500
60c89071 1501 default:
1502 WARN_ON_ONCE(1);
1503 break;
1504 }
1505
1506 opts1 |= transport_offset << GTTCPHO_SHIFT;
1507 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1508 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1509 u8 ip_protocol;
5bd23881 1510
6128d1bb 1511 if (transport_offset > TCPHO_MAX) {
1512 netif_warn(tp, tx_err, tp->netdev,
1513 "Invalid transport offset 0x%x\n",
1514 transport_offset);
1515 ret = TX_CSUM_NONE;
1516 goto unavailable;
1517 }
1518
6e74d174 1519 switch (vlan_get_protocol(skb)) {
5bd23881 1520 case htons(ETH_P_IP):
1521 opts2 |= IPV4_CS;
1522 ip_protocol = ip_hdr(skb)->protocol;
1523 break;
1524
1525 case htons(ETH_P_IPV6):
1526 opts2 |= IPV6_CS;
1527 ip_protocol = ipv6_hdr(skb)->nexthdr;
1528 break;
1529
1530 default:
1531 ip_protocol = IPPROTO_RAW;
1532 break;
1533 }
1534
60c89071 1535 if (ip_protocol == IPPROTO_TCP)
5bd23881 1536 opts2 |= TCP_CS;
60c89071 1537 else if (ip_protocol == IPPROTO_UDP)
5bd23881 1538 opts2 |= UDP_CS;
60c89071 1539 else
5bd23881 1540 WARN_ON_ONCE(1);
5bd23881 1541
60c89071 1542 opts2 |= transport_offset << TCPHO_SHIFT;
5bd23881 1543 }
60c89071 1544
1545 desc->opts2 = cpu_to_le32(opts2);
1546 desc->opts1 = cpu_to_le32(opts1);
1547
6128d1bb 1548unavailable:
60c89071 1549 return ret;
5bd23881 1550}
1551
b1379d9a 1552static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1553{
d84130a1 1554 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
9a4be1bd 1555 int remain, ret;
b1379d9a 1556 u8 *tx_data;
1557
d84130a1 1558 __skb_queue_head_init(&skb_head);
0c3121fc 1559 spin_lock(&tx_queue->lock);
d84130a1 1560 skb_queue_splice_init(tx_queue, &skb_head);
0c3121fc 1561 spin_unlock(&tx_queue->lock);
d84130a1 1562
b1379d9a 1563 tx_data = agg->head;
b209af99 1564 agg->skb_num = 0;
1565 agg->skb_len = 0;
52aec126 1566 remain = agg_buf_sz;
b1379d9a 1567
7937f9e5 1568 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1569 struct tx_desc *tx_desc;
1570 struct sk_buff *skb;
1571 unsigned int len;
60c89071 1572 u32 offset;
b1379d9a 1573
d84130a1 1574 skb = __skb_dequeue(&skb_head);
b1379d9a 1575 if (!skb)
1576 break;
1577
60c89071 1578 len = skb->len + sizeof(*tx_desc);
1579
1580 if (len > remain) {
d84130a1 1581 __skb_queue_head(&skb_head, skb);
b1379d9a 1582 break;
1583 }
1584
7937f9e5 1585 tx_data = tx_agg_align(tx_data);
b1379d9a 1586 tx_desc = (struct tx_desc *)tx_data;
60c89071 1587
1588 offset = (u32)skb_transport_offset(skb);
1589
6128d1bb 1590 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1591 r8152_csum_workaround(tp, skb, &skb_head);
1592 continue;
1593 }
60c89071 1594
c5554298 1595 rtl_tx_vlan_tag(tx_desc, skb);
1596
b1379d9a 1597 tx_data += sizeof(*tx_desc);
1598
60c89071 1599 len = skb->len;
1600 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1601 struct net_device_stats *stats = &tp->netdev->stats;
1602
1603 stats->tx_dropped++;
1604 dev_kfree_skb_any(skb);
1605 tx_data -= sizeof(*tx_desc);
1606 continue;
1607 }
1608
1609 tx_data += len;
b1379d9a 1610 agg->skb_len += len;
60c89071 1611 agg->skb_num++;
1612
b1379d9a 1613 dev_kfree_skb_any(skb);
1614
52aec126 1615 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1616 }
1617
d84130a1 1618 if (!skb_queue_empty(&skb_head)) {
0c3121fc 1619 spin_lock(&tx_queue->lock);
d84130a1 1620 skb_queue_splice(&skb_head, tx_queue);
0c3121fc 1621 spin_unlock(&tx_queue->lock);
d84130a1 1622 }
1623
0c3121fc 1624 netif_tx_lock(tp->netdev);
dd1b119c 1625
1626 if (netif_queue_stopped(tp->netdev) &&
1627 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1628 netif_wake_queue(tp->netdev);
1629
0c3121fc 1630 netif_tx_unlock(tp->netdev);
9a4be1bd 1631
0c3121fc 1632 ret = usb_autopm_get_interface_async(tp->intf);
9a4be1bd 1633 if (ret < 0)
1634 goto out_tx_fill;
dd1b119c 1635
b1379d9a 1636 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1637 agg->head, (int)(tx_data - (u8 *)agg->head),
1638 (usb_complete_t)write_bulk_callback, agg);
1639
0c3121fc 1640 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
9a4be1bd 1641 if (ret < 0)
0c3121fc 1642 usb_autopm_put_interface_async(tp->intf);
9a4be1bd 1643
1644out_tx_fill:
1645 return ret;
b1379d9a 1646}
1647
565cab0a 1648static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1649{
1650 u8 checksum = CHECKSUM_NONE;
1651 u32 opts2, opts3;
1652
1653 if (tp->version == RTL_VER_01)
1654 goto return_result;
1655
1656 opts2 = le32_to_cpu(rx_desc->opts2);
1657 opts3 = le32_to_cpu(rx_desc->opts3);
1658
1659 if (opts2 & RD_IPV4_CS) {
1660 if (opts3 & IPF)
1661 checksum = CHECKSUM_NONE;
1662 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1663 checksum = CHECKSUM_NONE;
1664 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1665 checksum = CHECKSUM_NONE;
1666 else
1667 checksum = CHECKSUM_UNNECESSARY;
6128d1bb 1668 } else if (RD_IPV6_CS) {
1669 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1670 checksum = CHECKSUM_UNNECESSARY;
1671 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1672 checksum = CHECKSUM_UNNECESSARY;
565cab0a 1673 }
1674
1675return_result:
1676 return checksum;
1677}
1678
d823ab68 1679static int rx_bottom(struct r8152 *tp, int budget)
ebc2ec48 1680{
a5a4f468 1681 unsigned long flags;
d84130a1 1682 struct list_head *cursor, *next, rx_queue;
e1a2ca92 1683 int ret = 0, work_done = 0;
d823ab68 1684
1685 if (!skb_queue_empty(&tp->rx_queue)) {
1686 while (work_done < budget) {
1687 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1688 struct net_device *netdev = tp->netdev;
1689 struct net_device_stats *stats = &netdev->stats;
1690 unsigned int pkt_len;
1691
1692 if (!skb)
1693 break;
1694
1695 pkt_len = skb->len;
1696 napi_gro_receive(&tp->napi, skb);
1697 work_done++;
1698 stats->rx_packets++;
1699 stats->rx_bytes += pkt_len;
1700 }
1701 }
ebc2ec48 1702
d84130a1 1703 if (list_empty(&tp->rx_done))
d823ab68 1704 goto out1;
d84130a1 1705
1706 INIT_LIST_HEAD(&rx_queue);
a5a4f468 1707 spin_lock_irqsave(&tp->rx_lock, flags);
d84130a1 1708 list_splice_init(&tp->rx_done, &rx_queue);
1709 spin_unlock_irqrestore(&tp->rx_lock, flags);
1710
1711 list_for_each_safe(cursor, next, &rx_queue) {
43a4478d 1712 struct rx_desc *rx_desc;
1713 struct rx_agg *agg;
43a4478d 1714 int len_used = 0;
1715 struct urb *urb;
1716 u8 *rx_data;
43a4478d 1717
ebc2ec48 1718 list_del_init(cursor);
ebc2ec48 1719
1720 agg = list_entry(cursor, struct rx_agg, list);
1721 urb = agg->urb;
0de98f6c 1722 if (urb->actual_length < ETH_ZLEN)
1723 goto submit;
ebc2ec48 1724
ebc2ec48 1725 rx_desc = agg->head;
1726 rx_data = agg->head;
7937f9e5 1727 len_used += sizeof(struct rx_desc);
ebc2ec48 1728
7937f9e5 1729 while (urb->actual_length > len_used) {
43a4478d 1730 struct net_device *netdev = tp->netdev;
05e0f1aa 1731 struct net_device_stats *stats = &netdev->stats;
7937f9e5 1732 unsigned int pkt_len;
43a4478d 1733 struct sk_buff *skb;
1734
7937f9e5 1735 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1736 if (pkt_len < ETH_ZLEN)
1737 break;
1738
7937f9e5 1739 len_used += pkt_len;
1740 if (urb->actual_length < len_used)
1741 break;
1742
8e1f51bd 1743 pkt_len -= CRC_SIZE;
ebc2ec48 1744 rx_data += sizeof(struct rx_desc);
1745
c8d83963 1746 skb = napi_alloc_skb(&tp->napi, pkt_len);
ebc2ec48 1747 if (!skb) {
1748 stats->rx_dropped++;
5e2f7485 1749 goto find_next_rx;
ebc2ec48 1750 }
565cab0a 1751
1752 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
ebc2ec48 1753 memcpy(skb->data, rx_data, pkt_len);
1754 skb_put(skb, pkt_len);
1755 skb->protocol = eth_type_trans(skb, netdev);
c5554298 1756 rtl_rx_vlan_tag(rx_desc, skb);
d823ab68 1757 if (work_done < budget) {
1758 napi_gro_receive(&tp->napi, skb);
1759 work_done++;
1760 stats->rx_packets++;
1761 stats->rx_bytes += pkt_len;
1762 } else {
1763 __skb_queue_tail(&tp->rx_queue, skb);
1764 }
ebc2ec48 1765
5e2f7485 1766find_next_rx:
8e1f51bd 1767 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1768 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1769 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1770 len_used += sizeof(struct rx_desc);
ebc2ec48 1771 }
1772
0de98f6c 1773submit:
e1a2ca92 1774 if (!ret) {
1775 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1776 } else {
1777 urb->actual_length = 0;
1778 list_add_tail(&agg->list, next);
1779 }
1780 }
1781
1782 if (!list_empty(&rx_queue)) {
1783 spin_lock_irqsave(&tp->rx_lock, flags);
1784 list_splice_tail(&rx_queue, &tp->rx_done);
1785 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1786 }
d823ab68 1787
1788out1:
1789 return work_done;
ebc2ec48 1790}
1791
1792static void tx_bottom(struct r8152 *tp)
1793{
ebc2ec48 1794 int res;
1795
b1379d9a 1796 do {
1797 struct tx_agg *agg;
ebc2ec48 1798
b1379d9a 1799 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1800 break;
1801
b1379d9a 1802 agg = r8152_get_tx_agg(tp);
1803 if (!agg)
ebc2ec48 1804 break;
ebc2ec48 1805
b1379d9a 1806 res = r8152_tx_agg_fill(tp, agg);
1807 if (res) {
05e0f1aa 1808 struct net_device *netdev = tp->netdev;
ebc2ec48 1809
b1379d9a 1810 if (res == -ENODEV) {
67610496 1811 set_bit(RTL8152_UNPLUG, &tp->flags);
b1379d9a 1812 netif_device_detach(netdev);
1813 } else {
05e0f1aa 1814 struct net_device_stats *stats = &netdev->stats;
1815 unsigned long flags;
1816
b1379d9a 1817 netif_warn(tp, tx_err, netdev,
1818 "failed tx_urb %d\n", res);
1819 stats->tx_dropped += agg->skb_num;
db8515ef 1820
b1379d9a 1821 spin_lock_irqsave(&tp->tx_lock, flags);
1822 list_add_tail(&agg->list, &tp->tx_free);
1823 spin_unlock_irqrestore(&tp->tx_lock, flags);
1824 }
ebc2ec48 1825 }
b1379d9a 1826 } while (res == 0);
ebc2ec48 1827}
1828
d823ab68 1829static void bottom_half(struct r8152 *tp)
ac718b69 1830{
ebc2ec48 1831 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1832 return;
1833
1834 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1835 return;
ebc2ec48 1836
7559fb2f 1837 /* When link down, the driver would cancel all bulks. */
1838 /* This avoid the re-submitting bulk */
ebc2ec48 1839 if (!netif_carrier_ok(tp->netdev))
ac718b69 1840 return;
ebc2ec48 1841
d823ab68 1842 clear_bit(SCHEDULE_NAPI, &tp->flags);
9451a11c 1843
0c3121fc 1844 tx_bottom(tp);
ebc2ec48 1845}
1846
d823ab68 1847static int r8152_poll(struct napi_struct *napi, int budget)
1848{
1849 struct r8152 *tp = container_of(napi, struct r8152, napi);
1850 int work_done;
1851
1852 work_done = rx_bottom(tp, budget);
1853 bottom_half(tp);
1854
1855 if (work_done < budget) {
1856 napi_complete(napi);
1857 if (!list_empty(&tp->rx_done))
1858 napi_schedule(napi);
1859 }
1860
1861 return work_done;
1862}
1863
ebc2ec48 1864static
1865int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1866{
a0fccd48 1867 int ret;
1868
ef827a5b 1869 /* The rx would be stopped, so skip submitting */
1870 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1871 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1872 return 0;
1873
ebc2ec48 1874 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
52aec126 1875 agg->head, agg_buf_sz,
b209af99 1876 (usb_complete_t)read_bulk_callback, agg);
ebc2ec48 1877
a0fccd48 1878 ret = usb_submit_urb(agg->urb, mem_flags);
1879 if (ret == -ENODEV) {
1880 set_bit(RTL8152_UNPLUG, &tp->flags);
1881 netif_device_detach(tp->netdev);
1882 } else if (ret) {
1883 struct urb *urb = agg->urb;
1884 unsigned long flags;
1885
1886 urb->actual_length = 0;
1887 spin_lock_irqsave(&tp->rx_lock, flags);
1888 list_add_tail(&agg->list, &tp->rx_done);
1889 spin_unlock_irqrestore(&tp->rx_lock, flags);
d823ab68 1890
1891 netif_err(tp, rx_err, tp->netdev,
1892 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1893
1894 napi_schedule(&tp->napi);
a0fccd48 1895 }
1896
1897 return ret;
ac718b69 1898}
1899
00a5e360 1900static void rtl_drop_queued_tx(struct r8152 *tp)
1901{
1902 struct net_device_stats *stats = &tp->netdev->stats;
d84130a1 1903 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
00a5e360 1904 struct sk_buff *skb;
1905
d84130a1 1906 if (skb_queue_empty(tx_queue))
1907 return;
1908
1909 __skb_queue_head_init(&skb_head);
2685d410 1910 spin_lock_bh(&tx_queue->lock);
d84130a1 1911 skb_queue_splice_init(tx_queue, &skb_head);
2685d410 1912 spin_unlock_bh(&tx_queue->lock);
d84130a1 1913
1914 while ((skb = __skb_dequeue(&skb_head))) {
00a5e360 1915 dev_kfree_skb(skb);
1916 stats->tx_dropped++;
1917 }
1918}
1919
ac718b69 1920static void rtl8152_tx_timeout(struct net_device *netdev)
1921{
1922 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1923
4a8deae2 1924 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
37608f3e 1925
1926 usb_queue_reset_device(tp->intf);
ac718b69 1927}
1928
1929static void rtl8152_set_rx_mode(struct net_device *netdev)
1930{
1931 struct r8152 *tp = netdev_priv(netdev);
1932
51d979fa 1933 if (netif_carrier_ok(netdev)) {
ac718b69 1934 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1935 schedule_delayed_work(&tp->schedule, 0);
1936 }
ac718b69 1937}
1938
1939static void _rtl8152_set_rx_mode(struct net_device *netdev)
1940{
1941 struct r8152 *tp = netdev_priv(netdev);
31787f53 1942 u32 mc_filter[2]; /* Multicast hash filter */
1943 __le32 tmp[2];
ac718b69 1944 u32 ocp_data;
1945
ac718b69 1946 netif_stop_queue(netdev);
1947 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1948 ocp_data &= ~RCR_ACPT_ALL;
1949 ocp_data |= RCR_AB | RCR_APM;
1950
1951 if (netdev->flags & IFF_PROMISC) {
1952 /* Unconditionally log net taps. */
1953 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1954 ocp_data |= RCR_AM | RCR_AAP;
b209af99 1955 mc_filter[1] = 0xffffffff;
1956 mc_filter[0] = 0xffffffff;
ac718b69 1957 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1958 (netdev->flags & IFF_ALLMULTI)) {
1959 /* Too many to filter perfectly -- accept all multicasts. */
1960 ocp_data |= RCR_AM;
b209af99 1961 mc_filter[1] = 0xffffffff;
1962 mc_filter[0] = 0xffffffff;
ac718b69 1963 } else {
1964 struct netdev_hw_addr *ha;
1965
b209af99 1966 mc_filter[1] = 0;
1967 mc_filter[0] = 0;
ac718b69 1968 netdev_for_each_mc_addr(ha, netdev) {
1969 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
b209af99 1970
ac718b69 1971 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1972 ocp_data |= RCR_AM;
1973 }
1974 }
1975
31787f53 1976 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1977 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1978
31787f53 1979 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1980 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1981 netif_wake_queue(netdev);
ac718b69 1982}
1983
a5e31255 1984static netdev_features_t
1985rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
1986 netdev_features_t features)
1987{
1988 u32 mss = skb_shinfo(skb)->gso_size;
1989 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
1990 int offset = skb_transport_offset(skb);
1991
1992 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
a188222b 1993 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
a5e31255 1994 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
1995 features &= ~NETIF_F_GSO_MASK;
1996
1997 return features;
1998}
1999
ac718b69 2000static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
b209af99 2001 struct net_device *netdev)
ac718b69 2002{
2003 struct r8152 *tp = netdev_priv(netdev);
ac718b69 2004
ebc2ec48 2005 skb_tx_timestamp(skb);
ac718b69 2006
61598788 2007 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 2008
0c3121fc 2009 if (!list_empty(&tp->tx_free)) {
2010 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
d823ab68 2011 set_bit(SCHEDULE_NAPI, &tp->flags);
0c3121fc 2012 schedule_delayed_work(&tp->schedule, 0);
2013 } else {
2014 usb_mark_last_busy(tp->udev);
d823ab68 2015 napi_schedule(&tp->napi);
0c3121fc 2016 }
b209af99 2017 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
dd1b119c 2018 netif_stop_queue(netdev);
b209af99 2019 }
dd1b119c 2020
ac718b69 2021 return NETDEV_TX_OK;
2022}
2023
2024static void r8152b_reset_packet_filter(struct r8152 *tp)
2025{
2026 u32 ocp_data;
2027
2028 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2029 ocp_data &= ~FMC_FCR_MCU_EN;
2030 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2031 ocp_data |= FMC_FCR_MCU_EN;
2032 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2033}
2034
2035static void rtl8152_nic_reset(struct r8152 *tp)
2036{
2037 int i;
2038
2039 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2040
2041 for (i = 0; i < 1000; i++) {
2042 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2043 break;
b209af99 2044 usleep_range(100, 400);
ac718b69 2045 }
2046}
2047
dd1b119c 2048static void set_tx_qlen(struct r8152 *tp)
2049{
2050 struct net_device *netdev = tp->netdev;
2051
52aec126 2052 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2053 sizeof(struct tx_desc));
dd1b119c 2054}
2055
ac718b69 2056static inline u8 rtl8152_get_speed(struct r8152 *tp)
2057{
2058 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2059}
2060
507605a8 2061static void rtl_set_eee_plus(struct r8152 *tp)
ac718b69 2062{
ebc2ec48 2063 u32 ocp_data;
ac718b69 2064 u8 speed;
2065
2066 speed = rtl8152_get_speed(tp);
ebc2ec48 2067 if (speed & _10bps) {
ac718b69 2068 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 2069 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 2070 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2071 } else {
2072 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 2073 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 2074 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2075 }
507605a8 2076}
2077
00a5e360 2078static void rxdy_gated_en(struct r8152 *tp, bool enable)
2079{
2080 u32 ocp_data;
2081
2082 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2083 if (enable)
2084 ocp_data |= RXDY_GATED_EN;
2085 else
2086 ocp_data &= ~RXDY_GATED_EN;
2087 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2088}
2089
445f7f4d 2090static int rtl_start_rx(struct r8152 *tp)
2091{
2092 int i, ret = 0;
2093
2094 INIT_LIST_HEAD(&tp->rx_done);
2095 for (i = 0; i < RTL8152_MAX_RX; i++) {
2096 INIT_LIST_HEAD(&tp->rx_info[i].list);
2097 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2098 if (ret)
2099 break;
2100 }
2101
7bcf4f60 2102 if (ret && ++i < RTL8152_MAX_RX) {
2103 struct list_head rx_queue;
2104 unsigned long flags;
2105
2106 INIT_LIST_HEAD(&rx_queue);
2107
2108 do {
2109 struct rx_agg *agg = &tp->rx_info[i++];
2110 struct urb *urb = agg->urb;
2111
2112 urb->actual_length = 0;
2113 list_add_tail(&agg->list, &rx_queue);
2114 } while (i < RTL8152_MAX_RX);
2115
2116 spin_lock_irqsave(&tp->rx_lock, flags);
2117 list_splice_tail(&rx_queue, &tp->rx_done);
2118 spin_unlock_irqrestore(&tp->rx_lock, flags);
2119 }
2120
445f7f4d 2121 return ret;
2122}
2123
2124static int rtl_stop_rx(struct r8152 *tp)
2125{
2126 int i;
2127
2128 for (i = 0; i < RTL8152_MAX_RX; i++)
2129 usb_kill_urb(tp->rx_info[i].urb);
2130
d823ab68 2131 while (!skb_queue_empty(&tp->rx_queue))
2132 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2133
445f7f4d 2134 return 0;
2135}
2136
507605a8 2137static int rtl_enable(struct r8152 *tp)
2138{
2139 u32 ocp_data;
ac718b69 2140
2141 r8152b_reset_packet_filter(tp);
2142
2143 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2144 ocp_data |= CR_RE | CR_TE;
2145 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2146
00a5e360 2147 rxdy_gated_en(tp, false);
ac718b69 2148
aa2e0926 2149 return 0;
ac718b69 2150}
2151
507605a8 2152static int rtl8152_enable(struct r8152 *tp)
2153{
6871438c 2154 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2155 return -ENODEV;
2156
507605a8 2157 set_tx_qlen(tp);
2158 rtl_set_eee_plus(tp);
2159
2160 return rtl_enable(tp);
2161}
2162
464ec10a 2163static void r8153_set_rx_early_timeout(struct r8152 *tp)
43779f8d 2164{
464ec10a 2165 u32 ocp_data = tp->coalesce / 8;
43779f8d 2166
464ec10a 2167 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
2168}
2169
2170static void r8153_set_rx_early_size(struct r8152 *tp)
2171{
2172 u32 mtu = tp->netdev->mtu;
2173 u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4;
2174
2175 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
43779f8d 2176}
2177
2178static int rtl8153_enable(struct r8152 *tp)
2179{
6871438c 2180 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2181 return -ENODEV;
2182
b214396f 2183 usb_disable_lpm(tp->udev);
43779f8d 2184 set_tx_qlen(tp);
2185 rtl_set_eee_plus(tp);
464ec10a 2186 r8153_set_rx_early_timeout(tp);
2187 r8153_set_rx_early_size(tp);
43779f8d 2188
2189 return rtl_enable(tp);
2190}
2191
d70b1137 2192static void rtl_disable(struct r8152 *tp)
ac718b69 2193{
ebc2ec48 2194 u32 ocp_data;
2195 int i;
ac718b69 2196
6871438c 2197 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2198 rtl_drop_queued_tx(tp);
2199 return;
2200 }
2201
ac718b69 2202 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2203 ocp_data &= ~RCR_ACPT_ALL;
2204 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2205
00a5e360 2206 rtl_drop_queued_tx(tp);
ebc2ec48 2207
2208 for (i = 0; i < RTL8152_MAX_TX; i++)
2209 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 2210
00a5e360 2211 rxdy_gated_en(tp, true);
ac718b69 2212
2213 for (i = 0; i < 1000; i++) {
2214 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2215 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2216 break;
8ddfa077 2217 usleep_range(1000, 2000);
ac718b69 2218 }
2219
2220 for (i = 0; i < 1000; i++) {
2221 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2222 break;
8ddfa077 2223 usleep_range(1000, 2000);
ac718b69 2224 }
2225
445f7f4d 2226 rtl_stop_rx(tp);
ac718b69 2227
2228 rtl8152_nic_reset(tp);
2229}
2230
00a5e360 2231static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2232{
2233 u32 ocp_data;
2234
2235 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2236 if (enable)
2237 ocp_data |= POWER_CUT;
2238 else
2239 ocp_data &= ~POWER_CUT;
2240 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2241
2242 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2243 ocp_data &= ~RESUME_INDICATE;
2244 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
00a5e360 2245}
2246
c5554298 2247static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2248{
2249 u32 ocp_data;
2250
2251 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2252 if (enable)
2253 ocp_data |= CPCR_RX_VLAN;
2254 else
2255 ocp_data &= ~CPCR_RX_VLAN;
2256 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2257}
2258
2259static int rtl8152_set_features(struct net_device *dev,
2260 netdev_features_t features)
2261{
2262 netdev_features_t changed = features ^ dev->features;
2263 struct r8152 *tp = netdev_priv(dev);
405f8a0e 2264 int ret;
2265
2266 ret = usb_autopm_get_interface(tp->intf);
2267 if (ret < 0)
2268 goto out;
c5554298 2269
b5403273 2270 mutex_lock(&tp->control);
2271
c5554298 2272 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2273 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2274 rtl_rx_vlan_en(tp, true);
2275 else
2276 rtl_rx_vlan_en(tp, false);
2277 }
2278
b5403273 2279 mutex_unlock(&tp->control);
2280
405f8a0e 2281 usb_autopm_put_interface(tp->intf);
2282
2283out:
2284 return ret;
c5554298 2285}
2286
21ff2e89 2287#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2288
2289static u32 __rtl_get_wol(struct r8152 *tp)
2290{
2291 u32 ocp_data;
2292 u32 wolopts = 0;
2293
2294 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2295 if (!(ocp_data & LAN_WAKE_EN))
2296 return 0;
2297
2298 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2299 if (ocp_data & LINK_ON_WAKE_EN)
2300 wolopts |= WAKE_PHY;
2301
2302 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2303 if (ocp_data & UWF_EN)
2304 wolopts |= WAKE_UCAST;
2305 if (ocp_data & BWF_EN)
2306 wolopts |= WAKE_BCAST;
2307 if (ocp_data & MWF_EN)
2308 wolopts |= WAKE_MCAST;
2309
2310 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2311 if (ocp_data & MAGIC_EN)
2312 wolopts |= WAKE_MAGIC;
2313
2314 return wolopts;
2315}
2316
2317static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2318{
2319 u32 ocp_data;
2320
2321 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2322
2323 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2324 ocp_data &= ~LINK_ON_WAKE_EN;
2325 if (wolopts & WAKE_PHY)
2326 ocp_data |= LINK_ON_WAKE_EN;
2327 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2328
2329 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2330 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2331 if (wolopts & WAKE_UCAST)
2332 ocp_data |= UWF_EN;
2333 if (wolopts & WAKE_BCAST)
2334 ocp_data |= BWF_EN;
2335 if (wolopts & WAKE_MCAST)
2336 ocp_data |= MWF_EN;
2337 if (wolopts & WAKE_ANY)
2338 ocp_data |= LAN_WAKE_EN;
2339 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2340
2341 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2342
2343 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2344 ocp_data &= ~MAGIC_EN;
2345 if (wolopts & WAKE_MAGIC)
2346 ocp_data |= MAGIC_EN;
2347 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2348
2349 if (wolopts & WAKE_ANY)
2350 device_set_wakeup_enable(&tp->udev->dev, true);
2351 else
2352 device_set_wakeup_enable(&tp->udev->dev, false);
2353}
2354
b214396f 2355static void r8153_u1u2en(struct r8152 *tp, bool enable)
2356{
2357 u8 u1u2[8];
2358
2359 if (enable)
2360 memset(u1u2, 0xff, sizeof(u1u2));
2361 else
2362 memset(u1u2, 0x00, sizeof(u1u2));
2363
2364 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2365}
2366
2367static void r8153_u2p3en(struct r8152 *tp, bool enable)
2368{
2369 u32 ocp_data;
2370
2371 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2372 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
2373 ocp_data |= U2P3_ENABLE;
2374 else
2375 ocp_data &= ~U2P3_ENABLE;
2376 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2377}
2378
2379static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2380{
2381 u32 ocp_data;
2382
2383 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2384 if (enable)
2385 ocp_data |= PWR_EN | PHASE2_EN;
2386 else
2387 ocp_data &= ~(PWR_EN | PHASE2_EN);
2388 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2389
2390 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2391 ocp_data &= ~PCUT_STATUS;
2392 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2393}
2394
7daed8dc 2395static bool rtl_can_wakeup(struct r8152 *tp)
2396{
2397 struct usb_device *udev = tp->udev;
2398
2399 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2400}
2401
9a4be1bd 2402static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2403{
2404 if (enable) {
2405 u32 ocp_data;
2406
b214396f 2407 r8153_u1u2en(tp, false);
2408 r8153_u2p3en(tp, false);
2409
9a4be1bd 2410 __rtl_set_wol(tp, WAKE_ANY);
2411
2412 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2413
2414 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2415 ocp_data |= LINK_OFF_WAKE_EN;
2416 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2417
2418 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2419 } else {
2420 __rtl_set_wol(tp, tp->saved_wolopts);
b214396f 2421 r8153_u2p3en(tp, true);
2422 r8153_u1u2en(tp, true);
9a4be1bd 2423 }
2424}
2425
aa66a5f1 2426static void rtl_phy_reset(struct r8152 *tp)
2427{
2428 u16 data;
2429 int i;
2430
aa66a5f1 2431 data = r8152_mdio_read(tp, MII_BMCR);
2432
2433 /* don't reset again before the previous one complete */
2434 if (data & BMCR_RESET)
2435 return;
2436
2437 data |= BMCR_RESET;
2438 r8152_mdio_write(tp, MII_BMCR, data);
2439
2440 for (i = 0; i < 50; i++) {
2441 msleep(20);
2442 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2443 break;
2444 }
2445}
2446
4349968a 2447static void r8153_teredo_off(struct r8152 *tp)
2448{
2449 u32 ocp_data;
2450
2451 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2452 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2453 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2454
2455 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2456 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2457 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2458}
2459
cda9fb01 2460static void r8152_aldps_en(struct r8152 *tp, bool enable)
4349968a 2461{
cda9fb01 2462 if (enable) {
2463 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2464 LINKENA | DIS_SDSAVE);
2465 } else {
2466 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2467 DIS_SDSAVE);
2468 msleep(20);
2469 }
4349968a 2470}
2471
d70b1137 2472static void rtl8152_disable(struct r8152 *tp)
2473{
cda9fb01 2474 r8152_aldps_en(tp, false);
d70b1137 2475 rtl_disable(tp);
cda9fb01 2476 r8152_aldps_en(tp, true);
d70b1137 2477}
2478
4349968a 2479static void r8152b_hw_phy_cfg(struct r8152 *tp)
2480{
f0cbe0ac 2481 u16 data;
2482
2483 data = r8152_mdio_read(tp, MII_BMCR);
2484 if (data & BMCR_PDOWN) {
2485 data &= ~BMCR_PDOWN;
2486 r8152_mdio_write(tp, MII_BMCR, data);
2487 }
2488
aa66a5f1 2489 set_bit(PHY_RESET, &tp->flags);
4349968a 2490}
2491
ac718b69 2492static void r8152b_exit_oob(struct r8152 *tp)
2493{
db8515ef 2494 u32 ocp_data;
2495 int i;
ac718b69 2496
2497 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2498 ocp_data &= ~RCR_ACPT_ALL;
2499 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2500
00a5e360 2501 rxdy_gated_en(tp, true);
da9bd117 2502 r8153_teredo_off(tp);
ac718b69 2503 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2504 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2505
2506 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2507 ocp_data &= ~NOW_IS_OOB;
2508 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2509
2510 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2511 ocp_data &= ~MCU_BORW_EN;
2512 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2513
2514 for (i = 0; i < 1000; i++) {
2515 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2516 if (ocp_data & LINK_LIST_READY)
2517 break;
8ddfa077 2518 usleep_range(1000, 2000);
ac718b69 2519 }
2520
2521 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2522 ocp_data |= RE_INIT_LL;
2523 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2524
2525 for (i = 0; i < 1000; i++) {
2526 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2527 if (ocp_data & LINK_LIST_READY)
2528 break;
8ddfa077 2529 usleep_range(1000, 2000);
ac718b69 2530 }
2531
2532 rtl8152_nic_reset(tp);
2533
2534 /* rx share fifo credit full threshold */
2535 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2536
a3cc465d 2537 if (tp->udev->speed == USB_SPEED_FULL ||
2538 tp->udev->speed == USB_SPEED_LOW) {
ac718b69 2539 /* rx share fifo credit near full threshold */
2540 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2541 RXFIFO_THR2_FULL);
2542 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2543 RXFIFO_THR3_FULL);
2544 } else {
2545 /* rx share fifo credit near full threshold */
2546 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2547 RXFIFO_THR2_HIGH);
2548 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2549 RXFIFO_THR3_HIGH);
2550 }
2551
2552 /* TX share fifo free credit full threshold */
2553 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2554
2555 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 2556 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 2557 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2558 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2559
c5554298 2560 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
ac718b69 2561
2562 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2563
2564 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2565 ocp_data |= TCR0_AUTO_FIFO;
2566 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2567}
2568
2569static void r8152b_enter_oob(struct r8152 *tp)
2570{
45f4a19f 2571 u32 ocp_data;
2572 int i;
ac718b69 2573
2574 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2575 ocp_data &= ~NOW_IS_OOB;
2576 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2577
2578 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2579 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2580 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2581
d70b1137 2582 rtl_disable(tp);
ac718b69 2583
2584 for (i = 0; i < 1000; i++) {
2585 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2586 if (ocp_data & LINK_LIST_READY)
2587 break;
8ddfa077 2588 usleep_range(1000, 2000);
ac718b69 2589 }
2590
2591 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2592 ocp_data |= RE_INIT_LL;
2593 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2594
2595 for (i = 0; i < 1000; i++) {
2596 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2597 if (ocp_data & LINK_LIST_READY)
2598 break;
8ddfa077 2599 usleep_range(1000, 2000);
ac718b69 2600 }
2601
2602 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2603
c5554298 2604 rtl_rx_vlan_en(tp, true);
ac718b69 2605
2606 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2607 ocp_data |= ALDPS_PROXY_MODE;
2608 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2609
2610 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2611 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2612 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2613
00a5e360 2614 rxdy_gated_en(tp, false);
ac718b69 2615
2616 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2617 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2618 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2619}
2620
43779f8d 2621static void r8153_hw_phy_cfg(struct r8152 *tp)
2622{
2623 u32 ocp_data;
2624 u16 data;
2625
fb02eb4a 2626 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
2627 tp->version == RTL_VER_05)
2628 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2629
f0cbe0ac 2630 data = r8152_mdio_read(tp, MII_BMCR);
2631 if (data & BMCR_PDOWN) {
2632 data &= ~BMCR_PDOWN;
2633 r8152_mdio_write(tp, MII_BMCR, data);
2634 }
43779f8d 2635
2636 if (tp->version == RTL_VER_03) {
2637 data = ocp_reg_read(tp, OCP_EEE_CFG);
2638 data &= ~CTAP_SHORT_EN;
2639 ocp_reg_write(tp, OCP_EEE_CFG, data);
2640 }
2641
2642 data = ocp_reg_read(tp, OCP_POWER_CFG);
2643 data |= EEE_CLKDIV_EN;
2644 ocp_reg_write(tp, OCP_POWER_CFG, data);
2645
2646 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2647 data |= EN_10M_BGOFF;
2648 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2649 data = ocp_reg_read(tp, OCP_POWER_CFG);
2650 data |= EN_10M_PLLOFF;
2651 ocp_reg_write(tp, OCP_POWER_CFG, data);
b4d99def 2652 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
43779f8d 2653
2654 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2655 ocp_data |= PFM_PWM_SWITCH;
2656 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2657
b4d99def 2658 /* Enable LPF corner auto tune */
2659 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
43779f8d 2660
b4d99def 2661 /* Adjust 10M Amplitude */
2662 sram_write(tp, SRAM_10M_AMP1, 0x00af);
2663 sram_write(tp, SRAM_10M_AMP2, 0x0208);
aa66a5f1 2664
2665 set_bit(PHY_RESET, &tp->flags);
43779f8d 2666}
2667
43779f8d 2668static void r8153_first_init(struct r8152 *tp)
2669{
2670 u32 ocp_data;
2671 int i;
2672
00a5e360 2673 rxdy_gated_en(tp, true);
43779f8d 2674 r8153_teredo_off(tp);
2675
2676 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2677 ocp_data &= ~RCR_ACPT_ALL;
2678 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2679
43779f8d 2680 rtl8152_nic_reset(tp);
2681
2682 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2683 ocp_data &= ~NOW_IS_OOB;
2684 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2685
2686 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2687 ocp_data &= ~MCU_BORW_EN;
2688 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2689
2690 for (i = 0; i < 1000; i++) {
2691 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2692 if (ocp_data & LINK_LIST_READY)
2693 break;
8ddfa077 2694 usleep_range(1000, 2000);
43779f8d 2695 }
2696
2697 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2698 ocp_data |= RE_INIT_LL;
2699 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2700
2701 for (i = 0; i < 1000; i++) {
2702 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2703 if (ocp_data & LINK_LIST_READY)
2704 break;
8ddfa077 2705 usleep_range(1000, 2000);
43779f8d 2706 }
2707
c5554298 2708 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
43779f8d 2709
69b4b7a4 2710 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2711 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
43779f8d 2712
2713 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2714 ocp_data |= TCR0_AUTO_FIFO;
2715 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2716
2717 rtl8152_nic_reset(tp);
2718
2719 /* rx share fifo credit full threshold */
2720 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2721 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2722 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2723 /* TX share fifo free credit full threshold */
2724 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2725
9629e3c0 2726 /* rx aggregation */
43779f8d 2727 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
e90fba8d 2728 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
43779f8d 2729 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2730}
2731
2732static void r8153_enter_oob(struct r8152 *tp)
2733{
2734 u32 ocp_data;
2735 int i;
2736
2737 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2738 ocp_data &= ~NOW_IS_OOB;
2739 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2740
d70b1137 2741 rtl_disable(tp);
43779f8d 2742
2743 for (i = 0; i < 1000; i++) {
2744 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2745 if (ocp_data & LINK_LIST_READY)
2746 break;
8ddfa077 2747 usleep_range(1000, 2000);
43779f8d 2748 }
2749
2750 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2751 ocp_data |= RE_INIT_LL;
2752 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2753
2754 for (i = 0; i < 1000; i++) {
2755 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2756 if (ocp_data & LINK_LIST_READY)
2757 break;
8ddfa077 2758 usleep_range(1000, 2000);
43779f8d 2759 }
2760
69b4b7a4 2761 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
43779f8d 2762
43779f8d 2763 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2764 ocp_data &= ~TEREDO_WAKE_MASK;
2765 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2766
c5554298 2767 rtl_rx_vlan_en(tp, true);
43779f8d 2768
2769 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2770 ocp_data |= ALDPS_PROXY_MODE;
2771 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2772
2773 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2774 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2775 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2776
00a5e360 2777 rxdy_gated_en(tp, false);
43779f8d 2778
2779 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2780 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2781 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2782}
2783
cda9fb01 2784static void r8153_aldps_en(struct r8152 *tp, bool enable)
43779f8d 2785{
2786 u16 data;
2787
2788 data = ocp_reg_read(tp, OCP_POWER_CFG);
cda9fb01 2789 if (enable) {
2790 data |= EN_ALDPS;
2791 ocp_reg_write(tp, OCP_POWER_CFG, data);
2792 } else {
2793 data &= ~EN_ALDPS;
2794 ocp_reg_write(tp, OCP_POWER_CFG, data);
2795 msleep(20);
2796 }
43779f8d 2797}
2798
d70b1137 2799static void rtl8153_disable(struct r8152 *tp)
2800{
cda9fb01 2801 r8153_aldps_en(tp, false);
d70b1137 2802 rtl_disable(tp);
cda9fb01 2803 r8153_aldps_en(tp, true);
b214396f 2804 usb_enable_lpm(tp->udev);
d70b1137 2805}
2806
ac718b69 2807static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2808{
43779f8d 2809 u16 bmcr, anar, gbcr;
ac718b69 2810 int ret = 0;
2811
2812 cancel_delayed_work_sync(&tp->schedule);
2813 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2814 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2815 ADVERTISE_100HALF | ADVERTISE_100FULL);
43779f8d 2816 if (tp->mii.supports_gmii) {
2817 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2818 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2819 } else {
2820 gbcr = 0;
2821 }
ac718b69 2822
2823 if (autoneg == AUTONEG_DISABLE) {
2824 if (speed == SPEED_10) {
2825 bmcr = 0;
2826 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2827 } else if (speed == SPEED_100) {
2828 bmcr = BMCR_SPEED100;
2829 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
43779f8d 2830 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2831 bmcr = BMCR_SPEED1000;
2832 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
ac718b69 2833 } else {
2834 ret = -EINVAL;
2835 goto out;
2836 }
2837
2838 if (duplex == DUPLEX_FULL)
2839 bmcr |= BMCR_FULLDPLX;
2840 } else {
2841 if (speed == SPEED_10) {
2842 if (duplex == DUPLEX_FULL)
2843 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2844 else
2845 anar |= ADVERTISE_10HALF;
2846 } else if (speed == SPEED_100) {
2847 if (duplex == DUPLEX_FULL) {
2848 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2849 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2850 } else {
2851 anar |= ADVERTISE_10HALF;
2852 anar |= ADVERTISE_100HALF;
2853 }
43779f8d 2854 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2855 if (duplex == DUPLEX_FULL) {
2856 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2857 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2858 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2859 } else {
2860 anar |= ADVERTISE_10HALF;
2861 anar |= ADVERTISE_100HALF;
2862 gbcr |= ADVERTISE_1000HALF;
2863 }
ac718b69 2864 } else {
2865 ret = -EINVAL;
2866 goto out;
2867 }
2868
2869 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2870 }
2871
aa66a5f1 2872 if (test_bit(PHY_RESET, &tp->flags))
2873 bmcr |= BMCR_RESET;
2874
43779f8d 2875 if (tp->mii.supports_gmii)
2876 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2877
ac718b69 2878 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2879 r8152_mdio_write(tp, MII_BMCR, bmcr);
2880
216a8349 2881 if (test_and_clear_bit(PHY_RESET, &tp->flags)) {
aa66a5f1 2882 int i;
2883
aa66a5f1 2884 for (i = 0; i < 50; i++) {
2885 msleep(20);
2886 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2887 break;
2888 }
2889 }
2890
ac718b69 2891out:
ac718b69 2892 return ret;
2893}
2894
d70b1137 2895static void rtl8152_up(struct r8152 *tp)
2896{
2897 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2898 return;
2899
cda9fb01 2900 r8152_aldps_en(tp, false);
d70b1137 2901 r8152b_exit_oob(tp);
cda9fb01 2902 r8152_aldps_en(tp, true);
d70b1137 2903}
2904
ac718b69 2905static void rtl8152_down(struct r8152 *tp)
2906{
6871438c 2907 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2908 rtl_drop_queued_tx(tp);
2909 return;
2910 }
2911
00a5e360 2912 r8152_power_cut_en(tp, false);
cda9fb01 2913 r8152_aldps_en(tp, false);
ac718b69 2914 r8152b_enter_oob(tp);
cda9fb01 2915 r8152_aldps_en(tp, true);
ac718b69 2916}
2917
d70b1137 2918static void rtl8153_up(struct r8152 *tp)
2919{
2920 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2921 return;
2922
b214396f 2923 r8153_u1u2en(tp, false);
cda9fb01 2924 r8153_aldps_en(tp, false);
d70b1137 2925 r8153_first_init(tp);
cda9fb01 2926 r8153_aldps_en(tp, true);
b214396f 2927 r8153_u2p3en(tp, true);
2928 r8153_u1u2en(tp, true);
2929 usb_enable_lpm(tp->udev);
d70b1137 2930}
2931
43779f8d 2932static void rtl8153_down(struct r8152 *tp)
2933{
6871438c 2934 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2935 rtl_drop_queued_tx(tp);
2936 return;
2937 }
2938
b9702723 2939 r8153_u1u2en(tp, false);
b214396f 2940 r8153_u2p3en(tp, false);
b9702723 2941 r8153_power_cut_en(tp, false);
cda9fb01 2942 r8153_aldps_en(tp, false);
43779f8d 2943 r8153_enter_oob(tp);
cda9fb01 2944 r8153_aldps_en(tp, true);
43779f8d 2945}
2946
2dd49e0f 2947static bool rtl8152_in_nway(struct r8152 *tp)
2948{
2949 u16 nway_state;
2950
2951 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
2952 tp->ocp_base = 0x2000;
2953 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
2954 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
2955
2956 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
2957 if (nway_state & 0xc000)
2958 return false;
2959 else
2960 return true;
2961}
2962
2963static bool rtl8153_in_nway(struct r8152 *tp)
2964{
2965 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
2966
2967 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
2968 return false;
2969 else
2970 return true;
2971}
2972
ac718b69 2973static void set_carrier(struct r8152 *tp)
2974{
2975 struct net_device *netdev = tp->netdev;
2976 u8 speed;
2977
2978 speed = rtl8152_get_speed(tp);
2979
2980 if (speed & LINK_STATUS) {
51d979fa 2981 if (!netif_carrier_ok(netdev)) {
c81229c9 2982 tp->rtl_ops.enable(tp);
ac718b69 2983 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
41cec84c 2984 napi_disable(&tp->napi);
ac718b69 2985 netif_carrier_on(netdev);
aa2e0926 2986 rtl_start_rx(tp);
41cec84c 2987 napi_enable(&tp->napi);
ac718b69 2988 }
2989 } else {
51d979fa 2990 if (netif_carrier_ok(netdev)) {
ac718b69 2991 netif_carrier_off(netdev);
d823ab68 2992 napi_disable(&tp->napi);
c81229c9 2993 tp->rtl_ops.disable(tp);
d823ab68 2994 napi_enable(&tp->napi);
ac718b69 2995 }
2996 }
ac718b69 2997}
2998
2999static void rtl_work_func_t(struct work_struct *work)
3000{
3001 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3002
a1f83fee 3003 /* If the device is unplugged or !netif_running(), the workqueue
3004 * doesn't need to wake the device, and could return directly.
3005 */
3006 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3007 return;
3008
9a4be1bd 3009 if (usb_autopm_get_interface(tp->intf) < 0)
3010 return;
3011
ac718b69 3012 if (!test_bit(WORK_ENABLE, &tp->flags))
3013 goto out1;
3014
b5403273 3015 if (!mutex_trylock(&tp->control)) {
3016 schedule_delayed_work(&tp->schedule, 0);
3017 goto out1;
3018 }
3019
216a8349 3020 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
40a82917 3021 set_carrier(tp);
ac718b69 3022
216a8349 3023 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
ac718b69 3024 _rtl8152_set_rx_mode(tp->netdev);
3025
d823ab68 3026 /* don't schedule napi before linking */
216a8349 3027 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3028 netif_carrier_ok(tp->netdev))
d823ab68 3029 napi_schedule(&tp->napi);
aa66a5f1 3030
216a8349 3031 if (test_and_clear_bit(PHY_RESET, &tp->flags))
aa66a5f1 3032 rtl_phy_reset(tp);
3033
b5403273 3034 mutex_unlock(&tp->control);
3035
ac718b69 3036out1:
9a4be1bd 3037 usb_autopm_put_interface(tp->intf);
ac718b69 3038}
3039
a028a9e0 3040static void rtl_hw_phy_work_func_t(struct work_struct *work)
3041{
3042 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3043
3044 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3045 return;
3046
3047 if (usb_autopm_get_interface(tp->intf) < 0)
3048 return;
3049
3050 mutex_lock(&tp->control);
3051
3052 tp->rtl_ops.hw_phy_cfg(tp);
3053
9d21c0d8 3054 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3055 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3056 DUPLEX_FULL);
3057
a028a9e0 3058 mutex_unlock(&tp->control);
3059
3060 usb_autopm_put_interface(tp->intf);
3061}
3062
5ee3c60c 3063#ifdef CONFIG_PM_SLEEP
3064static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3065 void *data)
3066{
3067 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3068
3069 switch (action) {
3070 case PM_HIBERNATION_PREPARE:
3071 case PM_SUSPEND_PREPARE:
3072 usb_autopm_get_interface(tp->intf);
3073 break;
3074
3075 case PM_POST_HIBERNATION:
3076 case PM_POST_SUSPEND:
3077 usb_autopm_put_interface(tp->intf);
3078 break;
3079
3080 case PM_POST_RESTORE:
3081 case PM_RESTORE_PREPARE:
3082 default:
3083 break;
3084 }
3085
3086 return NOTIFY_DONE;
3087}
3088#endif
3089
ac718b69 3090static int rtl8152_open(struct net_device *netdev)
3091{
3092 struct r8152 *tp = netdev_priv(netdev);
3093 int res = 0;
3094
7e9da481 3095 res = alloc_all_mem(tp);
3096 if (res)
3097 goto out;
3098
51d979fa 3099 netif_carrier_off(netdev);
f4c7476b 3100
9a4be1bd 3101 res = usb_autopm_get_interface(tp->intf);
3102 if (res < 0) {
3103 free_all_mem(tp);
3104 goto out;
3105 }
3106
b5403273 3107 mutex_lock(&tp->control);
3108
7e9da481 3109 tp->rtl_ops.up(tp);
3110
3d55f44f 3111 netif_carrier_off(netdev);
3112 netif_start_queue(netdev);
3113 set_bit(WORK_ENABLE, &tp->flags);
db8515ef 3114
40a82917 3115 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3116 if (res) {
3117 if (res == -ENODEV)
3118 netif_device_detach(tp->netdev);
4a8deae2
HW
3119 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3120 res);
7e9da481 3121 free_all_mem(tp);
93ffbeab 3122 } else {
d823ab68 3123 napi_enable(&tp->napi);
ac718b69 3124 }
3125
b5403273 3126 mutex_unlock(&tp->control);
3127
9a4be1bd 3128 usb_autopm_put_interface(tp->intf);
5ee3c60c 3129#ifdef CONFIG_PM_SLEEP
3130 tp->pm_notifier.notifier_call = rtl_notifier;
3131 register_pm_notifier(&tp->pm_notifier);
3132#endif
ac718b69 3133
7e9da481 3134out:
ac718b69 3135 return res;
3136}
3137
3138static int rtl8152_close(struct net_device *netdev)
3139{
3140 struct r8152 *tp = netdev_priv(netdev);
3141 int res = 0;
3142
5ee3c60c 3143#ifdef CONFIG_PM_SLEEP
3144 unregister_pm_notifier(&tp->pm_notifier);
3145#endif
d823ab68 3146 napi_disable(&tp->napi);
ac718b69 3147 clear_bit(WORK_ENABLE, &tp->flags);
3d55f44f 3148 usb_kill_urb(tp->intr_urb);
ac718b69 3149 cancel_delayed_work_sync(&tp->schedule);
3150 netif_stop_queue(netdev);
9a4be1bd 3151
3152 res = usb_autopm_get_interface(tp->intf);
53543db5 3153 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
9a4be1bd 3154 rtl_drop_queued_tx(tp);
d823ab68 3155 rtl_stop_rx(tp);
9a4be1bd 3156 } else {
b5403273 3157 mutex_lock(&tp->control);
3158
9a4be1bd 3159 tp->rtl_ops.down(tp);
b5403273 3160
3161 mutex_unlock(&tp->control);
3162
9a4be1bd 3163 usb_autopm_put_interface(tp->intf);
3164 }
ac718b69 3165
7e9da481 3166 free_all_mem(tp);
3167
ac718b69 3168 return res;
3169}
3170
d24f6134 3171static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3172{
3173 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3174 ocp_reg_write(tp, OCP_EEE_DATA, reg);
3175 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3176}
3177
3178static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3179{
3180 u16 data;
3181
3182 r8152_mmd_indirect(tp, dev, reg);
3183 data = ocp_reg_read(tp, OCP_EEE_DATA);
3184 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3185
3186 return data;
3187}
3188
3189static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
ac718b69 3190{
d24f6134 3191 r8152_mmd_indirect(tp, dev, reg);
3192 ocp_reg_write(tp, OCP_EEE_DATA, data);
3193 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3194}
3195
3196static void r8152_eee_en(struct r8152 *tp, bool enable)
3197{
3198 u16 config1, config2, config3;
45f4a19f 3199 u32 ocp_data;
ac718b69 3200
3201 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3202 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3203 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3204 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3205
3206 if (enable) {
3207 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3208 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3209 config1 |= sd_rise_time(1);
3210 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3211 config3 |= fast_snr(42);
3212 } else {
3213 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3214 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3215 RX_QUIET_EN);
3216 config1 |= sd_rise_time(7);
3217 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3218 config3 |= fast_snr(511);
3219 }
3220
ac718b69 3221 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3222 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3223 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3224 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
ac718b69 3225}
3226
d24f6134 3227static void r8152b_enable_eee(struct r8152 *tp)
3228{
3229 r8152_eee_en(tp, true);
3230 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3231}
3232
3233static void r8153_eee_en(struct r8152 *tp, bool enable)
43779f8d 3234{
3235 u32 ocp_data;
d24f6134 3236 u16 config;
43779f8d 3237
3238 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3239 config = ocp_reg_read(tp, OCP_EEE_CFG);
3240
3241 if (enable) {
3242 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3243 config |= EEE10_EN;
3244 } else {
3245 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3246 config &= ~EEE10_EN;
3247 }
3248
43779f8d 3249 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3250 ocp_reg_write(tp, OCP_EEE_CFG, config);
3251}
3252
3253static void r8153_enable_eee(struct r8152 *tp)
3254{
3255 r8153_eee_en(tp, true);
3256 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
43779f8d 3257}
3258
ac718b69 3259static void r8152b_enable_fc(struct r8152 *tp)
3260{
3261 u16 anar;
3262
3263 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3264 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3265 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3266}
3267
4f1d4d54 3268static void rtl_tally_reset(struct r8152 *tp)
3269{
3270 u32 ocp_data;
3271
3272 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3273 ocp_data |= TALLY_RESET;
3274 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3275}
3276
ac718b69 3277static void r8152b_init(struct r8152 *tp)
3278{
ebc2ec48 3279 u32 ocp_data;
ac718b69 3280
6871438c 3281 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3282 return;
3283
cda9fb01 3284 r8152_aldps_en(tp, false);
d70b1137 3285
ac718b69 3286 if (tp->version == RTL_VER_01) {
3287 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3288 ocp_data &= ~LED_MODE_MASK;
3289 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3290 }
3291
00a5e360 3292 r8152_power_cut_en(tp, false);
ac718b69 3293
ac718b69 3294 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3295 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3296 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3297 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3298 ocp_data &= ~MCU_CLK_RATIO_MASK;
3299 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3300 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3301 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3302 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3303 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3304
3305 r8152b_enable_eee(tp);
cda9fb01 3306 r8152_aldps_en(tp, true);
ac718b69 3307 r8152b_enable_fc(tp);
4f1d4d54 3308 rtl_tally_reset(tp);
ac718b69 3309
ebc2ec48 3310 /* enable rx aggregation */
ac718b69 3311 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
e90fba8d 3312 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
ac718b69 3313 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3314}
3315
43779f8d 3316static void r8153_init(struct r8152 *tp)
3317{
3318 u32 ocp_data;
3319 int i;
3320
6871438c 3321 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3322 return;
3323
cda9fb01 3324 r8153_aldps_en(tp, false);
b9702723 3325 r8153_u1u2en(tp, false);
43779f8d 3326
3327 for (i = 0; i < 500; i++) {
3328 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3329 AUTOLOAD_DONE)
3330 break;
3331 msleep(20);
3332 }
3333
3334 for (i = 0; i < 500; i++) {
3335 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3336 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3337 break;
3338 msleep(20);
3339 }
3340
b214396f 3341 usb_disable_lpm(tp->udev);
b9702723 3342 r8153_u2p3en(tp, false);
43779f8d 3343
65bab84c 3344 if (tp->version == RTL_VER_04) {
3345 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
3346 ocp_data &= ~pwd_dn_scale_mask;
3347 ocp_data |= pwd_dn_scale(96);
3348 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
3349
3350 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
3351 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
3352 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
3353 } else if (tp->version == RTL_VER_05) {
3354 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
3355 ocp_data &= ~ECM_ALDPS;
3356 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
3357
fb02eb4a 3358 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3359 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3360 ocp_data &= ~DYNAMIC_BURST;
3361 else
3362 ocp_data |= DYNAMIC_BURST;
3363 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3364 } else if (tp->version == RTL_VER_06) {
65bab84c 3365 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3366 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3367 ocp_data &= ~DYNAMIC_BURST;
3368 else
3369 ocp_data |= DYNAMIC_BURST;
3370 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3371 }
3372
3373 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
3374 ocp_data |= EP4_FULL_FC;
3375 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
3376
43779f8d 3377 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3378 ocp_data &= ~TIMER11_EN;
3379 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3380
43779f8d 3381 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3382 ocp_data &= ~LED_MODE_MASK;
3383 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3384
65bab84c 3385 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
2b84af94 3386 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
43779f8d 3387 ocp_data |= LPM_TIMER_500MS;
34203e25 3388 else
3389 ocp_data |= LPM_TIMER_500US;
43779f8d 3390 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3391
3392 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3393 ocp_data &= ~SEN_VAL_MASK;
3394 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3395 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3396
65bab84c 3397 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
3398
b9702723 3399 r8153_power_cut_en(tp, false);
3400 r8153_u1u2en(tp, true);
43779f8d 3401
43779f8d 3402 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3403 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3404 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3405 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3406 U1U2_SPDWN_EN | L1_SPDWN_EN);
3407 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3408 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3409 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3410 EEE_SPDWN_EN);
3411
3412 r8153_enable_eee(tp);
cda9fb01 3413 r8153_aldps_en(tp, true);
43779f8d 3414 r8152b_enable_fc(tp);
4f1d4d54 3415 rtl_tally_reset(tp);
b214396f 3416 r8153_u2p3en(tp, true);
43779f8d 3417}
3418
e501139a 3419static int rtl8152_pre_reset(struct usb_interface *intf)
3420{
3421 struct r8152 *tp = usb_get_intfdata(intf);
3422 struct net_device *netdev;
3423
3424 if (!tp)
3425 return 0;
3426
3427 netdev = tp->netdev;
3428 if (!netif_running(netdev))
3429 return 0;
3430
3431 napi_disable(&tp->napi);
3432 clear_bit(WORK_ENABLE, &tp->flags);
3433 usb_kill_urb(tp->intr_urb);
3434 cancel_delayed_work_sync(&tp->schedule);
3435 if (netif_carrier_ok(netdev)) {
3436 netif_stop_queue(netdev);
3437 mutex_lock(&tp->control);
3438 tp->rtl_ops.disable(tp);
3439 mutex_unlock(&tp->control);
3440 }
3441
3442 return 0;
3443}
3444
3445static int rtl8152_post_reset(struct usb_interface *intf)
3446{
3447 struct r8152 *tp = usb_get_intfdata(intf);
3448 struct net_device *netdev;
3449
3450 if (!tp)
3451 return 0;
3452
3453 netdev = tp->netdev;
3454 if (!netif_running(netdev))
3455 return 0;
3456
3457 set_bit(WORK_ENABLE, &tp->flags);
3458 if (netif_carrier_ok(netdev)) {
3459 mutex_lock(&tp->control);
3460 tp->rtl_ops.enable(tp);
3461 rtl8152_set_rx_mode(netdev);
3462 mutex_unlock(&tp->control);
3463 netif_wake_queue(netdev);
3464 }
3465
3466 napi_enable(&tp->napi);
3467
3468 return 0;
43779f8d 3469}
3470
2dd49e0f 3471static bool delay_autosuspend(struct r8152 *tp)
3472{
3473 bool sw_linking = !!netif_carrier_ok(tp->netdev);
3474 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
3475
3476 /* This means a linking change occurs and the driver doesn't detect it,
3477 * yet. If the driver has disabled tx/rx and hw is linking on, the
3478 * device wouldn't wake up by receiving any packet.
3479 */
3480 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
3481 return true;
3482
3483 /* If the linking down is occurred by nway, the device may miss the
3484 * linking change event. And it wouldn't wake when linking on.
3485 */
3486 if (!sw_linking && tp->rtl_ops.in_nway(tp))
3487 return true;
3488 else
3489 return false;
3490}
3491
ac718b69 3492static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3493{
3494 struct r8152 *tp = usb_get_intfdata(intf);
6cc69f2a 3495 struct net_device *netdev = tp->netdev;
3496 int ret = 0;
ac718b69 3497
b5403273 3498 mutex_lock(&tp->control);
3499
6cc69f2a 3500 if (PMSG_IS_AUTO(message)) {
2dd49e0f 3501 if (netif_running(netdev) && delay_autosuspend(tp)) {
6cc69f2a 3502 ret = -EBUSY;
3503 goto out1;
3504 }
3505
9a4be1bd 3506 set_bit(SELECTIVE_SUSPEND, &tp->flags);
6cc69f2a 3507 } else {
3508 netif_device_detach(netdev);
3509 }
ac718b69 3510
e3bd1a81 3511 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
ac718b69 3512 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 3513 usb_kill_urb(tp->intr_urb);
d823ab68 3514 napi_disable(&tp->napi);
9a4be1bd 3515 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
445f7f4d 3516 rtl_stop_rx(tp);
9a4be1bd 3517 rtl_runtime_suspend_enable(tp, true);
3518 } else {
6cc69f2a 3519 cancel_delayed_work_sync(&tp->schedule);
9a4be1bd 3520 tp->rtl_ops.down(tp);
9a4be1bd 3521 }
d823ab68 3522 napi_enable(&tp->napi);
ac718b69 3523 }
6cc69f2a 3524out1:
b5403273 3525 mutex_unlock(&tp->control);
3526
6cc69f2a 3527 return ret;
ac718b69 3528}
3529
3530static int rtl8152_resume(struct usb_interface *intf)
3531{
3532 struct r8152 *tp = usb_get_intfdata(intf);
3533
b5403273 3534 mutex_lock(&tp->control);
3535
9a4be1bd 3536 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3537 tp->rtl_ops.init(tp);
a028a9e0 3538 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
9a4be1bd 3539 netif_device_attach(tp->netdev);
3540 }
3541
90186af4 3542 if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) {
9a4be1bd 3543 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3544 rtl_runtime_suspend_enable(tp, false);
3545 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
41cec84c 3546 napi_disable(&tp->napi);
445f7f4d 3547 set_bit(WORK_ENABLE, &tp->flags);
51d979fa 3548 if (netif_carrier_ok(tp->netdev))
445f7f4d 3549 rtl_start_rx(tp);
41cec84c 3550 napi_enable(&tp->napi);
9a4be1bd 3551 } else {
3552 tp->rtl_ops.up(tp);
445f7f4d 3553 netif_carrier_off(tp->netdev);
3554 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3555 }
40a82917 3556 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
923e1ee3 3557 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
90186af4
PW
3558 if (tp->netdev->flags & IFF_UP)
3559 rtl_runtime_suspend_enable(tp, false);
923e1ee3 3560 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
ac718b69 3561 }
3562
b5403273 3563 mutex_unlock(&tp->control);
3564
ac718b69 3565 return 0;
3566}
3567
7ec2541a 3568static int rtl8152_reset_resume(struct usb_interface *intf)
3569{
3570 struct r8152 *tp = usb_get_intfdata(intf);
3571
3572 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3573 return rtl8152_resume(intf);
3574}
3575
21ff2e89 3576static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3577{
3578 struct r8152 *tp = netdev_priv(dev);
3579
9a4be1bd 3580 if (usb_autopm_get_interface(tp->intf) < 0)
3581 return;
3582
7daed8dc 3583 if (!rtl_can_wakeup(tp)) {
3584 wol->supported = 0;
3585 wol->wolopts = 0;
3586 } else {
3587 mutex_lock(&tp->control);
3588 wol->supported = WAKE_ANY;
3589 wol->wolopts = __rtl_get_wol(tp);
3590 mutex_unlock(&tp->control);
3591 }
b5403273 3592
9a4be1bd 3593 usb_autopm_put_interface(tp->intf);
21ff2e89 3594}
3595
3596static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3597{
3598 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3599 int ret;
3600
7daed8dc 3601 if (!rtl_can_wakeup(tp))
3602 return -EOPNOTSUPP;
3603
9a4be1bd 3604 ret = usb_autopm_get_interface(tp->intf);
3605 if (ret < 0)
3606 goto out_set_wol;
21ff2e89 3607
b5403273 3608 mutex_lock(&tp->control);
3609
21ff2e89 3610 __rtl_set_wol(tp, wol->wolopts);
3611 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3612
b5403273 3613 mutex_unlock(&tp->control);
3614
9a4be1bd 3615 usb_autopm_put_interface(tp->intf);
3616
3617out_set_wol:
3618 return ret;
21ff2e89 3619}
3620
a5ec27c1 3621static u32 rtl8152_get_msglevel(struct net_device *dev)
3622{
3623 struct r8152 *tp = netdev_priv(dev);
3624
3625 return tp->msg_enable;
3626}
3627
3628static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3629{
3630 struct r8152 *tp = netdev_priv(dev);
3631
3632 tp->msg_enable = value;
3633}
3634
ac718b69 3635static void rtl8152_get_drvinfo(struct net_device *netdev,
3636 struct ethtool_drvinfo *info)
3637{
3638 struct r8152 *tp = netdev_priv(netdev);
3639
b0b46c77 3640 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3641 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
ac718b69 3642 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3643}
3644
3645static
3646int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3647{
3648 struct r8152 *tp = netdev_priv(netdev);
8d4a4d72 3649 int ret;
ac718b69 3650
3651 if (!tp->mii.mdio_read)
3652 return -EOPNOTSUPP;
3653
8d4a4d72 3654 ret = usb_autopm_get_interface(tp->intf);
3655 if (ret < 0)
3656 goto out;
3657
b5403273 3658 mutex_lock(&tp->control);
3659
8d4a4d72 3660 ret = mii_ethtool_gset(&tp->mii, cmd);
3661
b5403273 3662 mutex_unlock(&tp->control);
3663
8d4a4d72 3664 usb_autopm_put_interface(tp->intf);
3665
3666out:
3667 return ret;
ac718b69 3668}
3669
3670static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3671{
3672 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3673 int ret;
3674
3675 ret = usb_autopm_get_interface(tp->intf);
3676 if (ret < 0)
3677 goto out;
ac718b69 3678
b5403273 3679 mutex_lock(&tp->control);
3680
9a4be1bd 3681 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3682
b5403273 3683 mutex_unlock(&tp->control);
3684
9a4be1bd 3685 usb_autopm_put_interface(tp->intf);
3686
3687out:
3688 return ret;
ac718b69 3689}
3690
4f1d4d54 3691static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3692 "tx_packets",
3693 "rx_packets",
3694 "tx_errors",
3695 "rx_errors",
3696 "rx_missed",
3697 "align_errors",
3698 "tx_single_collisions",
3699 "tx_multi_collisions",
3700 "rx_unicast",
3701 "rx_broadcast",
3702 "rx_multicast",
3703 "tx_aborted",
3704 "tx_underrun",
3705};
3706
3707static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3708{
3709 switch (sset) {
3710 case ETH_SS_STATS:
3711 return ARRAY_SIZE(rtl8152_gstrings);
3712 default:
3713 return -EOPNOTSUPP;
3714 }
3715}
3716
3717static void rtl8152_get_ethtool_stats(struct net_device *dev,
3718 struct ethtool_stats *stats, u64 *data)
3719{
3720 struct r8152 *tp = netdev_priv(dev);
3721 struct tally_counter tally;
3722
0b030244 3723 if (usb_autopm_get_interface(tp->intf) < 0)
3724 return;
3725
4f1d4d54 3726 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3727
0b030244 3728 usb_autopm_put_interface(tp->intf);
3729
4f1d4d54 3730 data[0] = le64_to_cpu(tally.tx_packets);
3731 data[1] = le64_to_cpu(tally.rx_packets);
3732 data[2] = le64_to_cpu(tally.tx_errors);
3733 data[3] = le32_to_cpu(tally.rx_errors);
3734 data[4] = le16_to_cpu(tally.rx_missed);
3735 data[5] = le16_to_cpu(tally.align_errors);
3736 data[6] = le32_to_cpu(tally.tx_one_collision);
3737 data[7] = le32_to_cpu(tally.tx_multi_collision);
3738 data[8] = le64_to_cpu(tally.rx_unicast);
3739 data[9] = le64_to_cpu(tally.rx_broadcast);
3740 data[10] = le32_to_cpu(tally.rx_multicast);
3741 data[11] = le16_to_cpu(tally.tx_aborted);
f37119c5 3742 data[12] = le16_to_cpu(tally.tx_underrun);
4f1d4d54 3743}
3744
3745static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3746{
3747 switch (stringset) {
3748 case ETH_SS_STATS:
3749 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3750 break;
3751 }
3752}
3753
df35d283 3754static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3755{
3756 u32 ocp_data, lp, adv, supported = 0;
3757 u16 val;
3758
3759 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3760 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3761
3762 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3763 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3764
3765 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3766 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3767
3768 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3769 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3770
3771 eee->eee_enabled = !!ocp_data;
3772 eee->eee_active = !!(supported & adv & lp);
3773 eee->supported = supported;
3774 eee->advertised = adv;
3775 eee->lp_advertised = lp;
3776
3777 return 0;
3778}
3779
3780static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3781{
3782 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3783
3784 r8152_eee_en(tp, eee->eee_enabled);
3785
3786 if (!eee->eee_enabled)
3787 val = 0;
3788
3789 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3790
3791 return 0;
3792}
3793
3794static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3795{
3796 u32 ocp_data, lp, adv, supported = 0;
3797 u16 val;
3798
3799 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3800 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3801
3802 val = ocp_reg_read(tp, OCP_EEE_ADV);
3803 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3804
3805 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3806 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3807
3808 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3809 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3810
3811 eee->eee_enabled = !!ocp_data;
3812 eee->eee_active = !!(supported & adv & lp);
3813 eee->supported = supported;
3814 eee->advertised = adv;
3815 eee->lp_advertised = lp;
3816
3817 return 0;
3818}
3819
3820static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3821{
3822 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3823
3824 r8153_eee_en(tp, eee->eee_enabled);
3825
3826 if (!eee->eee_enabled)
3827 val = 0;
3828
3829 ocp_reg_write(tp, OCP_EEE_ADV, val);
3830
3831 return 0;
3832}
3833
3834static int
3835rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3836{
3837 struct r8152 *tp = netdev_priv(net);
3838 int ret;
3839
3840 ret = usb_autopm_get_interface(tp->intf);
3841 if (ret < 0)
3842 goto out;
3843
b5403273 3844 mutex_lock(&tp->control);
3845
df35d283 3846 ret = tp->rtl_ops.eee_get(tp, edata);
3847
b5403273 3848 mutex_unlock(&tp->control);
3849
df35d283 3850 usb_autopm_put_interface(tp->intf);
3851
3852out:
3853 return ret;
3854}
3855
3856static int
3857rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3858{
3859 struct r8152 *tp = netdev_priv(net);
3860 int ret;
3861
3862 ret = usb_autopm_get_interface(tp->intf);
3863 if (ret < 0)
3864 goto out;
3865
b5403273 3866 mutex_lock(&tp->control);
3867
df35d283 3868 ret = tp->rtl_ops.eee_set(tp, edata);
9d31a7b9 3869 if (!ret)
3870 ret = mii_nway_restart(&tp->mii);
df35d283 3871
b5403273 3872 mutex_unlock(&tp->control);
3873
df35d283 3874 usb_autopm_put_interface(tp->intf);
3875
3876out:
3877 return ret;
3878}
3879
8884f507 3880static int rtl8152_nway_reset(struct net_device *dev)
3881{
3882 struct r8152 *tp = netdev_priv(dev);
3883 int ret;
3884
3885 ret = usb_autopm_get_interface(tp->intf);
3886 if (ret < 0)
3887 goto out;
3888
3889 mutex_lock(&tp->control);
3890
3891 ret = mii_nway_restart(&tp->mii);
3892
3893 mutex_unlock(&tp->control);
3894
3895 usb_autopm_put_interface(tp->intf);
3896
3897out:
3898 return ret;
3899}
3900
efb3dd88 3901static int rtl8152_get_coalesce(struct net_device *netdev,
3902 struct ethtool_coalesce *coalesce)
3903{
3904 struct r8152 *tp = netdev_priv(netdev);
3905
3906 switch (tp->version) {
3907 case RTL_VER_01:
3908 case RTL_VER_02:
3909 return -EOPNOTSUPP;
3910 default:
3911 break;
3912 }
3913
3914 coalesce->rx_coalesce_usecs = tp->coalesce;
3915
3916 return 0;
3917}
3918
3919static int rtl8152_set_coalesce(struct net_device *netdev,
3920 struct ethtool_coalesce *coalesce)
3921{
3922 struct r8152 *tp = netdev_priv(netdev);
3923 int ret;
3924
3925 switch (tp->version) {
3926 case RTL_VER_01:
3927 case RTL_VER_02:
3928 return -EOPNOTSUPP;
3929 default:
3930 break;
3931 }
3932
3933 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
3934 return -EINVAL;
3935
3936 ret = usb_autopm_get_interface(tp->intf);
3937 if (ret < 0)
3938 return ret;
3939
3940 mutex_lock(&tp->control);
3941
3942 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
3943 tp->coalesce = coalesce->rx_coalesce_usecs;
3944
3945 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
3946 r8153_set_rx_early_timeout(tp);
3947 }
3948
3949 mutex_unlock(&tp->control);
3950
3951 usb_autopm_put_interface(tp->intf);
3952
3953 return ret;
3954}
3955
ac718b69 3956static struct ethtool_ops ops = {
3957 .get_drvinfo = rtl8152_get_drvinfo,
3958 .get_settings = rtl8152_get_settings,
3959 .set_settings = rtl8152_set_settings,
3960 .get_link = ethtool_op_get_link,
8884f507 3961 .nway_reset = rtl8152_nway_reset,
a5ec27c1 3962 .get_msglevel = rtl8152_get_msglevel,
3963 .set_msglevel = rtl8152_set_msglevel,
21ff2e89 3964 .get_wol = rtl8152_get_wol,
3965 .set_wol = rtl8152_set_wol,
4f1d4d54 3966 .get_strings = rtl8152_get_strings,
3967 .get_sset_count = rtl8152_get_sset_count,
3968 .get_ethtool_stats = rtl8152_get_ethtool_stats,
efb3dd88 3969 .get_coalesce = rtl8152_get_coalesce,
3970 .set_coalesce = rtl8152_set_coalesce,
df35d283 3971 .get_eee = rtl_ethtool_get_eee,
3972 .set_eee = rtl_ethtool_set_eee,
ac718b69 3973};
3974
3975static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3976{
3977 struct r8152 *tp = netdev_priv(netdev);
3978 struct mii_ioctl_data *data = if_mii(rq);
9a4be1bd 3979 int res;
3980
6871438c 3981 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3982 return -ENODEV;
3983
9a4be1bd 3984 res = usb_autopm_get_interface(tp->intf);
3985 if (res < 0)
3986 goto out;
ac718b69 3987
3988 switch (cmd) {
3989 case SIOCGMIIPHY:
3990 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3991 break;
3992
3993 case SIOCGMIIREG:
b5403273 3994 mutex_lock(&tp->control);
ac718b69 3995 data->val_out = r8152_mdio_read(tp, data->reg_num);
b5403273 3996 mutex_unlock(&tp->control);
ac718b69 3997 break;
3998
3999 case SIOCSMIIREG:
4000 if (!capable(CAP_NET_ADMIN)) {
4001 res = -EPERM;
4002 break;
4003 }
b5403273 4004 mutex_lock(&tp->control);
ac718b69 4005 r8152_mdio_write(tp, data->reg_num, data->val_in);
b5403273 4006 mutex_unlock(&tp->control);
ac718b69 4007 break;
4008
4009 default:
4010 res = -EOPNOTSUPP;
4011 }
4012
9a4be1bd 4013 usb_autopm_put_interface(tp->intf);
4014
4015out:
ac718b69 4016 return res;
4017}
4018
69b4b7a4 4019static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4020{
4021 struct r8152 *tp = netdev_priv(dev);
396e2e23 4022 int ret;
69b4b7a4 4023
4024 switch (tp->version) {
4025 case RTL_VER_01:
4026 case RTL_VER_02:
4027 return eth_change_mtu(dev, new_mtu);
4028 default:
4029 break;
4030 }
4031
4032 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
4033 return -EINVAL;
4034
396e2e23 4035 ret = usb_autopm_get_interface(tp->intf);
4036 if (ret < 0)
4037 return ret;
4038
4039 mutex_lock(&tp->control);
4040
69b4b7a4 4041 dev->mtu = new_mtu;
4042
396e2e23 4043 if (netif_running(dev) && netif_carrier_ok(dev))
4044 r8153_set_rx_early_size(tp);
4045
4046 mutex_unlock(&tp->control);
4047
4048 usb_autopm_put_interface(tp->intf);
4049
4050 return ret;
69b4b7a4 4051}
4052
ac718b69 4053static const struct net_device_ops rtl8152_netdev_ops = {
4054 .ndo_open = rtl8152_open,
4055 .ndo_stop = rtl8152_close,
4056 .ndo_do_ioctl = rtl8152_ioctl,
4057 .ndo_start_xmit = rtl8152_start_xmit,
4058 .ndo_tx_timeout = rtl8152_tx_timeout,
c5554298 4059 .ndo_set_features = rtl8152_set_features,
ac718b69 4060 .ndo_set_rx_mode = rtl8152_set_rx_mode,
4061 .ndo_set_mac_address = rtl8152_set_mac_address,
69b4b7a4 4062 .ndo_change_mtu = rtl8152_change_mtu,
ac718b69 4063 .ndo_validate_addr = eth_validate_addr,
a5e31255 4064 .ndo_features_check = rtl8152_features_check,
ac718b69 4065};
4066
4067static void r8152b_get_version(struct r8152 *tp)
4068{
4069 u32 ocp_data;
4070 u16 version;
4071
4072 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
4073 version = (u16)(ocp_data & VERSION_MASK);
4074
4075 switch (version) {
4076 case 0x4c00:
4077 tp->version = RTL_VER_01;
4078 break;
4079 case 0x4c10:
4080 tp->version = RTL_VER_02;
4081 break;
43779f8d 4082 case 0x5c00:
4083 tp->version = RTL_VER_03;
4084 tp->mii.supports_gmii = 1;
4085 break;
4086 case 0x5c10:
4087 tp->version = RTL_VER_04;
4088 tp->mii.supports_gmii = 1;
4089 break;
4090 case 0x5c20:
4091 tp->version = RTL_VER_05;
4092 tp->mii.supports_gmii = 1;
4093 break;
fb02eb4a 4094 case 0x5c30:
4095 tp->version = RTL_VER_06;
4096 tp->mii.supports_gmii = 1;
4097 break;
ac718b69 4098 default:
4099 netif_info(tp, probe, tp->netdev,
4100 "Unknown version 0x%04x\n", version);
4101 break;
4102 }
4103}
4104
e3fe0b1a 4105static void rtl8152_unload(struct r8152 *tp)
4106{
6871438c 4107 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4108 return;
4109
00a5e360 4110 if (tp->version != RTL_VER_01)
4111 r8152_power_cut_en(tp, true);
e3fe0b1a 4112}
4113
43779f8d 4114static void rtl8153_unload(struct r8152 *tp)
4115{
6871438c 4116 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4117 return;
4118
49be1723 4119 r8153_power_cut_en(tp, false);
43779f8d 4120}
4121
55b65475 4122static int rtl_ops_init(struct r8152 *tp)
c81229c9 4123{
4124 struct rtl_ops *ops = &tp->rtl_ops;
55b65475 4125 int ret = 0;
4126
4127 switch (tp->version) {
4128 case RTL_VER_01:
4129 case RTL_VER_02:
4130 ops->init = r8152b_init;
4131 ops->enable = rtl8152_enable;
4132 ops->disable = rtl8152_disable;
4133 ops->up = rtl8152_up;
4134 ops->down = rtl8152_down;
4135 ops->unload = rtl8152_unload;
4136 ops->eee_get = r8152_get_eee;
4137 ops->eee_set = r8152_set_eee;
2dd49e0f 4138 ops->in_nway = rtl8152_in_nway;
a028a9e0 4139 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
43779f8d 4140 break;
4141
55b65475 4142 case RTL_VER_03:
4143 case RTL_VER_04:
4144 case RTL_VER_05:
fb02eb4a 4145 case RTL_VER_06:
55b65475 4146 ops->init = r8153_init;
4147 ops->enable = rtl8153_enable;
4148 ops->disable = rtl8153_disable;
4149 ops->up = rtl8153_up;
4150 ops->down = rtl8153_down;
4151 ops->unload = rtl8153_unload;
4152 ops->eee_get = r8153_get_eee;
4153 ops->eee_set = r8153_set_eee;
2dd49e0f 4154 ops->in_nway = rtl8153_in_nway;
a028a9e0 4155 ops->hw_phy_cfg = r8153_hw_phy_cfg;
c81229c9 4156 break;
4157
4158 default:
55b65475 4159 ret = -ENODEV;
4160 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
c81229c9 4161 break;
4162 }
4163
4164 return ret;
4165}
4166
ac718b69 4167static int rtl8152_probe(struct usb_interface *intf,
4168 const struct usb_device_id *id)
4169{
4170 struct usb_device *udev = interface_to_usbdev(intf);
4171 struct r8152 *tp;
4172 struct net_device *netdev;
ebc2ec48 4173 int ret;
ac718b69 4174
10c32717 4175 if (udev->actconfig->desc.bConfigurationValue != 1) {
4176 usb_driver_set_configuration(udev, 1);
4177 return -ENODEV;
4178 }
4179
4180 usb_reset_device(udev);
ac718b69 4181 netdev = alloc_etherdev(sizeof(struct r8152));
4182 if (!netdev) {
4a8deae2 4183 dev_err(&intf->dev, "Out of memory\n");
ac718b69 4184 return -ENOMEM;
4185 }
4186
ebc2ec48 4187 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 4188 tp = netdev_priv(netdev);
4189 tp->msg_enable = 0x7FFF;
4190
e3ad412a 4191 tp->udev = udev;
4192 tp->netdev = netdev;
4193 tp->intf = intf;
4194
82cf94cb 4195 r8152b_get_version(tp);
55b65475 4196 ret = rtl_ops_init(tp);
31ca1dec 4197 if (ret)
4198 goto out;
c81229c9 4199
b5403273 4200 mutex_init(&tp->control);
ac718b69 4201 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
a028a9e0 4202 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
ac718b69 4203
ac718b69 4204 netdev->netdev_ops = &rtl8152_netdev_ops;
4205 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 4206
60c89071 4207 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 4208 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
c5554298 4209 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
4210 NETIF_F_HW_VLAN_CTAG_TX;
60c89071 4211 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 4212 NETIF_F_TSO | NETIF_F_FRAGLIST |
c5554298 4213 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
ccc39faf 4214 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
c5554298 4215 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4216 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
4217 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
db8515ef 4218
7ad24ea4 4219 netdev->ethtool_ops = &ops;
60c89071 4220 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
ac718b69 4221
4222 tp->mii.dev = netdev;
4223 tp->mii.mdio_read = read_mii_word;
4224 tp->mii.mdio_write = write_mii_word;
4225 tp->mii.phy_id_mask = 0x3f;
4226 tp->mii.reg_num_mask = 0x1f;
4227 tp->mii.phy_id = R8152_PHY_ID;
ac718b69 4228
464ec10a 4229 switch (udev->speed) {
4230 case USB_SPEED_SUPER:
2b84af94 4231 case USB_SPEED_SUPER_PLUS:
464ec10a 4232 tp->coalesce = COALESCE_SUPER;
4233 break;
4234 case USB_SPEED_HIGH:
4235 tp->coalesce = COALESCE_HIGH;
4236 break;
4237 default:
4238 tp->coalesce = COALESCE_SLOW;
4239 break;
4240 }
4241
9a4be1bd 4242 intf->needs_remote_wakeup = 1;
4243
c81229c9 4244 tp->rtl_ops.init(tp);
a028a9e0 4245 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
ac718b69 4246 set_ethernet_addr(tp);
4247
ac718b69 4248 usb_set_intfdata(intf, tp);
d823ab68 4249 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
ac718b69 4250
ebc2ec48 4251 ret = register_netdev(netdev);
4252 if (ret != 0) {
4a8deae2 4253 netif_err(tp, probe, netdev, "couldn't register the device\n");
ebc2ec48 4254 goto out1;
ac718b69 4255 }
4256
7daed8dc 4257 if (!rtl_can_wakeup(tp))
4258 __rtl_set_wol(tp, 0);
4259
21ff2e89 4260 tp->saved_wolopts = __rtl_get_wol(tp);
4261 if (tp->saved_wolopts)
4262 device_set_wakeup_enable(&udev->dev, true);
4263 else
4264 device_set_wakeup_enable(&udev->dev, false);
4265
4a8deae2 4266 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
ac718b69 4267
4268 return 0;
4269
ac718b69 4270out1:
d823ab68 4271 netif_napi_del(&tp->napi);
ebc2ec48 4272 usb_set_intfdata(intf, NULL);
ac718b69 4273out:
4274 free_netdev(netdev);
ebc2ec48 4275 return ret;
ac718b69 4276}
4277
ac718b69 4278static void rtl8152_disconnect(struct usb_interface *intf)
4279{
4280 struct r8152 *tp = usb_get_intfdata(intf);
4281
4282 usb_set_intfdata(intf, NULL);
4283 if (tp) {
f561de33 4284 struct usb_device *udev = tp->udev;
4285
4286 if (udev->state == USB_STATE_NOTATTACHED)
4287 set_bit(RTL8152_UNPLUG, &tp->flags);
4288
d823ab68 4289 netif_napi_del(&tp->napi);
ac718b69 4290 unregister_netdev(tp->netdev);
a028a9e0 4291 cancel_delayed_work_sync(&tp->hw_phy_work);
c81229c9 4292 tp->rtl_ops.unload(tp);
ac718b69 4293 free_netdev(tp->netdev);
4294 }
4295}
4296
d9a28c5b 4297#define REALTEK_USB_DEVICE(vend, prod) \
4298 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
4299 USB_DEVICE_ID_MATCH_INT_CLASS, \
4300 .idVendor = (vend), \
4301 .idProduct = (prod), \
4302 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
4303}, \
4304{ \
4305 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
4306 USB_DEVICE_ID_MATCH_DEVICE, \
4307 .idVendor = (vend), \
4308 .idProduct = (prod), \
4309 .bInterfaceClass = USB_CLASS_COMM, \
4310 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
4311 .bInterfaceProtocol = USB_CDC_PROTO_NONE
4312
ac718b69 4313/* table of devices that work with this driver */
4314static struct usb_device_id rtl8152_table[] = {
d9a28c5b 4315 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
4316 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
4317 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
347eec34 4318 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
1006da19 4319 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
d065c3c1 4320 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
ac718b69 4321 {}
4322};
4323
4324MODULE_DEVICE_TABLE(usb, rtl8152_table);
4325
4326static struct usb_driver rtl8152_driver = {
4327 .name = MODULENAME,
ebc2ec48 4328 .id_table = rtl8152_table,
ac718b69 4329 .probe = rtl8152_probe,
4330 .disconnect = rtl8152_disconnect,
ac718b69 4331 .suspend = rtl8152_suspend,
ebc2ec48 4332 .resume = rtl8152_resume,
7ec2541a 4333 .reset_resume = rtl8152_reset_resume,
e501139a 4334 .pre_reset = rtl8152_pre_reset,
4335 .post_reset = rtl8152_post_reset,
9a4be1bd 4336 .supports_autosuspend = 1,
a634782f 4337 .disable_hub_initiated_lpm = 1,
ac718b69 4338};
4339
b4236daa 4340module_usb_driver(rtl8152_driver);
ac718b69 4341
4342MODULE_AUTHOR(DRIVER_AUTHOR);
4343MODULE_DESCRIPTION(DRIVER_DESC);
4344MODULE_LICENSE("GPL");