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Merge branch 'bkl/procfs' of git://git.kernel.org/pub/scm/linux/kernel/git/frederic...
[linux-2.6-block.git] / drivers / net / sfc / siena.c
CommitLineData
afd4aea0
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
5a0e3ad6 15#include <linux/slab.h>
afd4aea0
BH		 16#include "net_driver.h"
17#include "bitfield.h"
18#include "efx.h"
19#include "nic.h"
20#include "mac.h"
21#include "spi.h"
22#include "regs.h"
23#include "io.h"
24#include "phy.h"
25#include "workarounds.h"
26#include "mcdi.h"
27#include "mcdi_pcol.h"
28
29/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
30
31static void siena_init_wol(struct efx_nic *efx);
32
33
34static void siena_push_irq_moderation(struct efx_channel *channel)
35{
36 efx_dword_t timer_cmd;
37
38 if (channel->irq_moderation)
39 EFX_POPULATE_DWORD_2(timer_cmd,
40 FRF_CZ_TC_TIMER_MODE,
41 FFE_CZ_TIMER_MODE_INT_HLDOFF,
42 FRF_CZ_TC_TIMER_VAL,
43 channel->irq_moderation - 1);
44 else
45 EFX_POPULATE_DWORD_2(timer_cmd,
46 FRF_CZ_TC_TIMER_MODE,
47 FFE_CZ_TIMER_MODE_DIS,
48 FRF_CZ_TC_TIMER_VAL, 0);
49 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
50 channel->channel);
51}
52
53static void siena_push_multicast_hash(struct efx_nic *efx)
54{
55 WARN_ON(!mutex_is_locked(&efx->mac_lock));
56
57 efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
58 efx->multicast_hash.byte, sizeof(efx->multicast_hash),
59 NULL, 0, NULL);
60}
61
62static int siena_mdio_write(struct net_device *net_dev,
63 int prtad, int devad, u16 addr, u16 value)
64{
65 struct efx_nic *efx = netdev_priv(net_dev);
66 uint32_t status;
67 int rc;
68
69 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
70 addr, value, &status);
71 if (rc)
72 return rc;
73 if (status != MC_CMD_MDIO_STATUS_GOOD)
74 return -EIO;
75
76 return 0;
77}
78
79static int siena_mdio_read(struct net_device *net_dev,
80 int prtad, int devad, u16 addr)
81{
82 struct efx_nic *efx = netdev_priv(net_dev);
83 uint16_t value;
84 uint32_t status;
85 int rc;
86
87 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
88 addr, &value, &status);
89 if (rc)
90 return rc;
91 if (status != MC_CMD_MDIO_STATUS_GOOD)
92 return -EIO;
93
94 return (int)value;
95}
96
97/* This call is responsible for hooking in the MAC and PHY operations */
98static int siena_probe_port(struct efx_nic *efx)
99{
100 int rc;
101
102 /* Hook in PHY operations table */
103 efx->phy_op = &efx_mcdi_phy_ops;
104
105 /* Set up MDIO structure for PHY */
106 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
107 efx->mdio.mdio_read = siena_mdio_read;
108 efx->mdio.mdio_write = siena_mdio_write;
109
7a6b8f6f 110 /* Fill out MDIO structure, loopback modes, and initial link state */
afd4aea0
BH		 111 rc = efx->phy_op->probe(efx);
112 if (rc != 0)
113 return rc;
114
afd4aea0
BH		 115 /* Allocate buffer for stats */
116 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
117 MC_CMD_MAC_NSTATS * sizeof(u64));
118 if (rc)
119 return rc;
120 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
121 (u64)efx->stats_buffer.dma_addr,
122 efx->stats_buffer.addr,
123 (u64)virt_to_phys(efx->stats_buffer.addr));
124
125 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
126
127 return 0;
128}
129
130void siena_remove_port(struct efx_nic *efx)
131{
ff3b00a0 132 efx->phy_op->remove(efx);
afd4aea0
BH		 133 efx_nic_free_buffer(efx, &efx->stats_buffer);
134}
135
136static const struct efx_nic_register_test siena_register_tests[] = {
137 { FR_AZ_ADR_REGION,
4cddca54 138 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
afd4aea0
BH		 139 { FR_CZ_USR_EV_CFG,
140 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
141 { FR_AZ_RX_CFG,
142 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
143 { FR_AZ_TX_CFG,
144 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
145 { FR_AZ_TX_RESERVED,
146 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
147 { FR_AZ_SRM_TX_DC_CFG,
148 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
149 { FR_AZ_RX_DC_CFG,
150 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
151 { FR_AZ_RX_DC_PF_WM,
152 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
153 { FR_BZ_DP_CTRL,
154 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
155 { FR_BZ_RX_RSS_TKEY,
156 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
157 { FR_CZ_RX_RSS_IPV6_REG1,
158 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
159 { FR_CZ_RX_RSS_IPV6_REG2,
160 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
161 { FR_CZ_RX_RSS_IPV6_REG3,
162 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
163};
164
165static int siena_test_registers(struct efx_nic *efx)
166{
167 return efx_nic_test_registers(efx, siena_register_tests,
168 ARRAY_SIZE(siena_register_tests));
169}
170
171/**************************************************************************
172 *
173 * Device reset
174 *
175 **************************************************************************
176 */
177
178static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
179{
8b2103ad
SH		 180 int rc;
181
182 /* Recover from a failed assertion pre-reset */
183 rc = efx_mcdi_handle_assertion(efx);
184 if (rc)
185 return rc;
afd4aea0
BH		 186
187 if (method == RESET_TYPE_WORLD)
188 return efx_mcdi_reset_mc(efx);
189 else
190 return efx_mcdi_reset_port(efx);
191}
192
193static int siena_probe_nvconfig(struct efx_nic *efx)
194{
195 int rc;
196
197 rc = efx_mcdi_get_board_cfg(efx, efx->mac_address, NULL);
198 if (rc)
199 return rc;
200
201 return 0;
202}
203
204static int siena_probe_nic(struct efx_nic *efx)
205{
206 struct siena_nic_data *nic_data;
207 bool already_attached = 0;
208 int rc;
209
210 /* Allocate storage for hardware specific data */
211 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
212 if (!nic_data)
213 return -ENOMEM;
214 efx->nic_data = nic_data;
215
216 if (efx_nic_fpga_ver(efx) != 0) {
217 EFX_ERR(efx, "Siena FPGA not supported\n");
218 rc = -ENODEV;
219 goto fail1;
220 }
221
222 efx_mcdi_init(efx);
223
224 /* Recover from a failed assertion before probing */
225 rc = efx_mcdi_handle_assertion(efx);
226 if (rc)
227 goto fail1;
228
229 rc = efx_mcdi_fwver(efx, &nic_data->fw_version, &nic_data->fw_build);
230 if (rc) {
231 EFX_ERR(efx, "Failed to read MCPU firmware version - "
232 "rc %d\n", rc);
233 goto fail1; /* MCPU absent? */
234 }
235
236 /* Let the BMC know that the driver is now in charge of link and
237 * filter settings. We must do this before we reset the NIC */
238 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
239 if (rc) {
240 EFX_ERR(efx, "Unable to register driver with MCPU\n");
241 goto fail2;
242 }
243 if (already_attached)
244 /* Not a fatal error */
245 EFX_ERR(efx, "Host already registered with MCPU\n");
246
247 /* Now we can reset the NIC */
248 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
249 if (rc) {
250 EFX_ERR(efx, "failed to reset NIC\n");
251 goto fail3;
252 }
253
254 siena_init_wol(efx);
255
256 /* Allocate memory for INT_KER */
257 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
258 if (rc)
259 goto fail4;
260 BUG_ON(efx->irq_status.dma_addr & 0x0f);
261
262 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
263 (unsigned long long)efx->irq_status.dma_addr,
264 efx->irq_status.addr,
265 (unsigned long long)virt_to_phys(efx->irq_status.addr));
266
267 /* Read in the non-volatile configuration */
268 rc = siena_probe_nvconfig(efx);
269 if (rc == -EINVAL) {
270 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
271 efx->phy_type = PHY_TYPE_NONE;
272 efx->mdio.prtad = MDIO_PRTAD_NONE;
273 } else if (rc) {
274 goto fail5;
275 }
276
277 return 0;
278
279fail5:
280 efx_nic_free_buffer(efx, &efx->irq_status);
281fail4:
282fail3:
283 efx_mcdi_drv_attach(efx, false, NULL);
284fail2:
285fail1:
286 kfree(efx->nic_data);
287 return rc;
288}
289
290/* This call performs hardware-specific global initialisation, such as
291 * defining the descriptor cache sizes and number of RSS channels.
292 * It does not set up any buffers, descriptor rings or event queues.
293 */
294static int siena_init_nic(struct efx_nic *efx)
295{
296 efx_oword_t temp;
297 int rc;
298
299 /* Recover from a failed assertion post-reset */
300 rc = efx_mcdi_handle_assertion(efx);
301 if (rc)
302 return rc;
303
304 /* Squash TX of packets of 16 bytes or less */
305 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
306 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
307 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
308
309 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
310 * descriptors (which is bad).
311 */
312 efx_reado(efx, &temp, FR_AZ_TX_CFG);
313 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
314 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
315 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
316
317 efx_reado(efx, &temp, FR_AZ_RX_CFG);
318 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
319 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
320 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
321
322 if (efx_nic_rx_xoff_thresh >= 0 || efx_nic_rx_xon_thresh >= 0)
323 /* No MCDI operation has been defined to set thresholds */
324 EFX_ERR(efx, "ignoring RX flow control thresholds\n");
325
326 /* Enable event logging */
327 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
328 if (rc)
329 return rc;
330
331 /* Set destination of both TX and RX Flush events */
332 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
333 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
334
335 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
336 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
337
338 efx_nic_init_common(efx);
339 return 0;
340}
341
342static void siena_remove_nic(struct efx_nic *efx)
343{
344 efx_nic_free_buffer(efx, &efx->irq_status);
345
346 siena_reset_hw(efx, RESET_TYPE_ALL);
347
348 /* Relinquish the device back to the BMC */
349 if (efx_nic_has_mc(efx))
350 efx_mcdi_drv_attach(efx, false, NULL);
351
352 /* Tear down the private nic state */
353 kfree(efx->nic_data);
354 efx->nic_data = NULL;
355}
356
357#define STATS_GENERATION_INVALID ((u64)(-1))
358
359static int siena_try_update_nic_stats(struct efx_nic *efx)
360{
361 u64 *dma_stats;
362 struct efx_mac_stats *mac_stats;
363 u64 generation_start;
364 u64 generation_end;
365
366 mac_stats = &efx->mac_stats;
367 dma_stats = (u64 *)efx->stats_buffer.addr;
368
369 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
370 if (generation_end == STATS_GENERATION_INVALID)
371 return 0;
372 rmb();
373
374#define MAC_STAT(M, D) \
375 mac_stats->M = dma_stats[MC_CMD_MAC_ ## D]
376
377 MAC_STAT(tx_bytes, TX_BYTES);
378 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
379 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
380 mac_stats->tx_bad_bytes);
381 MAC_STAT(tx_packets, TX_PKTS);
382 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
383 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
384 MAC_STAT(tx_control, TX_CONTROL_PKTS);
385 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
386 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
387 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
388 MAC_STAT(tx_lt64, TX_LT64_PKTS);
389 MAC_STAT(tx_64, TX_64_PKTS);
390 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
391 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
392 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
393 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
394 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
395 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
396 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
397 mac_stats->tx_collision = 0;
398 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
399 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
400 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
401 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
402 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
403 mac_stats->tx_collision = (mac_stats->tx_single_collision +
404 mac_stats->tx_multiple_collision +
405 mac_stats->tx_excessive_collision +
406 mac_stats->tx_late_collision);
407 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
408 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
409 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
410 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
411 MAC_STAT(rx_bytes, RX_BYTES);
412 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
413 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
414 mac_stats->rx_bad_bytes);
415 MAC_STAT(rx_packets, RX_PKTS);
416 MAC_STAT(rx_good, RX_GOOD_PKTS);
417 mac_stats->rx_bad = mac_stats->rx_packets - mac_stats->rx_good;
418 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
419 MAC_STAT(rx_control, RX_CONTROL_PKTS);
420 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
421 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
422 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
423 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
424 MAC_STAT(rx_64, RX_64_PKTS);
425 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
426 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
427 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
428 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
429 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
430 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
431 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
432 mac_stats->rx_bad_lt64 = 0;
433 mac_stats->rx_bad_64_to_15xx = 0;
434 mac_stats->rx_bad_15xx_to_jumbo = 0;
435 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
436 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
437 mac_stats->rx_missed = 0;
438 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
439 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
440 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
441 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
442 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
443 mac_stats->rx_good_lt64 = 0;
444
445 efx->n_rx_nodesc_drop_cnt = dma_stats[MC_CMD_MAC_RX_NODESC_DROPS];
446
447#undef MAC_STAT
448
449 rmb();
450 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
451 if (generation_end != generation_start)
452 return -EAGAIN;
453
454 return 0;
455}
456
457static void siena_update_nic_stats(struct efx_nic *efx)
458{
aabc5649
BH		 459 int retry;
460
461 /* If we're unlucky enough to read statistics wduring the DMA, wait
462 * up to 10ms for it to finish (typically takes <500us) */
463 for (retry = 0; retry < 100; ++retry) {
464 if (siena_try_update_nic_stats(efx) == 0)
465 return;
466 udelay(100);
467 }
468
469 /* Use the old values instead */
afd4aea0
BH		 470}
471
472static void siena_start_nic_stats(struct efx_nic *efx)
473{
474 u64 *dma_stats = (u64 *)efx->stats_buffer.addr;
475
476 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
477
478 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
479 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
480}
481
482static void siena_stop_nic_stats(struct efx_nic *efx)
483{
484 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
485}
486
487void siena_print_fwver(struct efx_nic *efx, char *buf, size_t len)
488{
489 struct siena_nic_data *nic_data = efx->nic_data;
490 snprintf(buf, len, "%u.%u.%u.%u",
491 (unsigned int)(nic_data->fw_version >> 48),
492 (unsigned int)(nic_data->fw_version >> 32 & 0xffff),
493 (unsigned int)(nic_data->fw_version >> 16 & 0xffff),
494 (unsigned int)(nic_data->fw_version & 0xffff));
495}
496
497/**************************************************************************
498 *
499 * Wake on LAN
500 *
501 **************************************************************************
502 */
503
504static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
505{
506 struct siena_nic_data *nic_data = efx->nic_data;
507
508 wol->supported = WAKE_MAGIC;
509 if (nic_data->wol_filter_id != -1)
510 wol->wolopts = WAKE_MAGIC;
511 else
512 wol->wolopts = 0;
513 memset(&wol->sopass, 0, sizeof(wol->sopass));
514}
515
516
517static int siena_set_wol(struct efx_nic *efx, u32 type)
518{
519 struct siena_nic_data *nic_data = efx->nic_data;
520 int rc;
521
522 if (type & ~WAKE_MAGIC)
523 return -EINVAL;
524
525 if (type & WAKE_MAGIC) {
526 if (nic_data->wol_filter_id != -1)
527 efx_mcdi_wol_filter_remove(efx,
528 nic_data->wol_filter_id);
529 rc = efx_mcdi_wol_filter_set_magic(efx, efx->mac_address,
530 &nic_data->wol_filter_id);
531 if (rc)
532 goto fail;
533
534 pci_wake_from_d3(efx->pci_dev, true);
535 } else {
536 rc = efx_mcdi_wol_filter_reset(efx);
537 nic_data->wol_filter_id = -1;
538 pci_wake_from_d3(efx->pci_dev, false);
539 if (rc)
540 goto fail;
541 }
542
543 return 0;
544 fail:
545 EFX_ERR(efx, "%s failed: type=%d rc=%d\n", __func__, type, rc);
546 return rc;
547}
548
549
550static void siena_init_wol(struct efx_nic *efx)
551{
552 struct siena_nic_data *nic_data = efx->nic_data;
553 int rc;
554
555 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
556
557 if (rc != 0) {
558 /* If it failed, attempt to get into a synchronised
559 * state with MC by resetting any set WoL filters */
560 efx_mcdi_wol_filter_reset(efx);
561 nic_data->wol_filter_id = -1;
562 } else if (nic_data->wol_filter_id != -1) {
563 pci_wake_from_d3(efx->pci_dev, true);
564 }
565}
566
567
568/**************************************************************************
569 *
570 * Revision-dependent attributes used by efx.c and nic.c
571 *
572 **************************************************************************
573 */
574
575struct efx_nic_type siena_a0_nic_type = {
576 .probe = siena_probe_nic,
577 .remove = siena_remove_nic,
578 .init = siena_init_nic,
579 .fini = efx_port_dummy_op_void,
580 .monitor = NULL,
581 .reset = siena_reset_hw,
582 .probe_port = siena_probe_port,
583 .remove_port = siena_remove_port,
584 .prepare_flush = efx_port_dummy_op_void,
585 .update_stats = siena_update_nic_stats,
586 .start_stats = siena_start_nic_stats,
587 .stop_stats = siena_stop_nic_stats,
588 .set_id_led = efx_mcdi_set_id_led,
589 .push_irq_moderation = siena_push_irq_moderation,
590 .push_multicast_hash = siena_push_multicast_hash,
591 .reconfigure_port = efx_mcdi_phy_reconfigure,
592 .get_wol = siena_get_wol,
593 .set_wol = siena_set_wol,
594 .resume_wol = siena_init_wol,
595 .test_registers = siena_test_registers,
2e803407 596 .test_nvram = efx_mcdi_nvram_test_all,
afd4aea0
BH		 597 .default_mac_ops = &efx_mcdi_mac_operations,
598
599 .revision = EFX_REV_SIENA_A0,
600 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
601 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
602 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
603 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
604 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
605 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
606 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
607 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
608 .rx_buffer_padding = 0,
609 .max_interrupt_mode = EFX_INT_MODE_MSIX,
610 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
611 * interrupt handler only supports 32
612 * channels */
613 .tx_dc_base = 0x88000,
614 .rx_dc_base = 0x68000,
615 .offload_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM,
616 .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT,
617};
Linux 6.x block layer and io_uring tree(s)