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Merge branch 'bkl/procfs' of git://git.kernel.org/pub/scm/linux/kernel/git/frederic...
[linux-2.6-block.git] / drivers / net / sfc / efx.c
CommitLineData
8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
906bb26c 4 * Copyright 2005-2009 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
20#include <linux/crc32.h>
21#include <linux/ethtool.h>
aa6ef27e 22#include <linux/topology.h>
5a0e3ad6 23#include <linux/gfp.h>
8ceee660 24#include "net_driver.h"
8ceee660
BH		 25#include "efx.h"
26#include "mdio_10g.h"
744093c9 27#include "nic.h"
8ceee660 28
8880f4ec
BH		 29#include "mcdi.h"
30
c459302d
BH		 31/**************************************************************************
32 *
33 * Type name strings
34 *
35 **************************************************************************
36 */
37
38/* Loopback mode names (see LOOPBACK_MODE()) */
39const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
40const char *efx_loopback_mode_names[] = {
41 [LOOPBACK_NONE] = "NONE",
e58f69f4 42 [LOOPBACK_DATA] = "DATAPATH",
c459302d
BH		 43 [LOOPBACK_GMAC] = "GMAC",
44 [LOOPBACK_XGMII] = "XGMII",
45 [LOOPBACK_XGXS] = "XGXS",
46 [LOOPBACK_XAUI] = "XAUI",
e58f69f4
BH		 47 [LOOPBACK_GMII] = "GMII",
48 [LOOPBACK_SGMII] = "SGMII",
49 [LOOPBACK_XGBR] = "XGBR",
50 [LOOPBACK_XFI] = "XFI",
51 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
52 [LOOPBACK_GMII_FAR] = "GMII_FAR",
53 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
54 [LOOPBACK_XFI_FAR] = "XFI_FAR",
c459302d
BH		 55 [LOOPBACK_GPHY] = "GPHY",
56 [LOOPBACK_PHYXS] = "PHYXS",
57 [LOOPBACK_PCS] = "PCS",
58 [LOOPBACK_PMAPMD] = "PMA/PMD",
e58f69f4
BH		 59 [LOOPBACK_XPORT] = "XPORT",
60 [LOOPBACK_XGMII_WS] = "XGMII_WS",
61 [LOOPBACK_XAUI_WS] = "XAUI_WS",
62 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
63 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
64 [LOOPBACK_GMII_WS] = "GMII_WS",
65 [LOOPBACK_XFI_WS] = "XFI_WS",
66 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
67 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
c459302d
BH		 68};
69
70/* Interrupt mode names (see INT_MODE())) */
71const unsigned int efx_interrupt_mode_max = EFX_INT_MODE_MAX;
72const char *efx_interrupt_mode_names[] = {
73 [EFX_INT_MODE_MSIX] = "MSI-X",
74 [EFX_INT_MODE_MSI] = "MSI",
75 [EFX_INT_MODE_LEGACY] = "legacy",
76};
77
78const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
79const char *efx_reset_type_names[] = {
80 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
81 [RESET_TYPE_ALL] = "ALL",
82 [RESET_TYPE_WORLD] = "WORLD",
83 [RESET_TYPE_DISABLE] = "DISABLE",
84 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
85 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
86 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
87 [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH",
88 [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH",
89 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
8880f4ec 90 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
c459302d
BH		 91};
92
8ceee660
BH		 93#define EFX_MAX_MTU (9 * 1024)
94
95/* RX slow fill workqueue. If memory allocation fails in the fast path,
96 * a work item is pushed onto this work queue to retry the allocation later,
97 * to avoid the NIC being starved of RX buffers. Since this is a per cpu
98 * workqueue, there is nothing to be gained in making it per NIC
99 */
100static struct workqueue_struct *refill_workqueue;
101
1ab00629
SH		 102/* Reset workqueue. If any NIC has a hardware failure then a reset will be
103 * queued onto this work queue. This is not a per-nic work queue, because
104 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
105 */
106static struct workqueue_struct *reset_workqueue;
107
8ceee660
BH		 108/**************************************************************************
109 *
110 * Configurable values
111 *
112 *************************************************************************/
113
8ceee660
BH		 114/*
115 * Use separate channels for TX and RX events
116 *
28b581ab
NT		 117 * Set this to 1 to use separate channels for TX and RX. It allows us
118 * to control interrupt affinity separately for TX and RX.
8ceee660 119 *
28b581ab 120 * This is only used in MSI-X interrupt mode
8ceee660 121 */
28b581ab
NT		 122static unsigned int separate_tx_channels;
123module_param(separate_tx_channels, uint, 0644);
124MODULE_PARM_DESC(separate_tx_channels,
125 "Use separate channels for TX and RX");
8ceee660
BH		 126
127/* This is the weight assigned to each of the (per-channel) virtual
128 * NAPI devices.
129 */
130static int napi_weight = 64;
131
132/* This is the time (in jiffies) between invocations of the hardware
133 * monitor, which checks for known hardware bugs and resets the
134 * hardware and driver as necessary.
135 */
136unsigned int efx_monitor_interval = 1 * HZ;
137
8ceee660
BH		 138/* This controls whether or not the driver will initialise devices
139 * with invalid MAC addresses stored in the EEPROM or flash. If true,
140 * such devices will be initialised with a random locally-generated
141 * MAC address. This allows for loading the sfc_mtd driver to
142 * reprogram the flash, even if the flash contents (including the MAC
143 * address) have previously been erased.
144 */
145static unsigned int allow_bad_hwaddr;
146
147/* Initial interrupt moderation settings. They can be modified after
148 * module load with ethtool.
149 *
150 * The default for RX should strike a balance between increasing the
151 * round-trip latency and reducing overhead.
152 */
153static unsigned int rx_irq_mod_usec = 60;
154
155/* Initial interrupt moderation settings. They can be modified after
156 * module load with ethtool.
157 *
158 * This default is chosen to ensure that a 10G link does not go idle
159 * while a TX queue is stopped after it has become full. A queue is
160 * restarted when it drops below half full. The time this takes (assuming
161 * worst case 3 descriptors per packet and 1024 descriptors) is
162 * 512 / 3 * 1.2 = 205 usec.
163 */
164static unsigned int tx_irq_mod_usec = 150;
165
166/* This is the first interrupt mode to try out of:
167 * 0 => MSI-X
168 * 1 => MSI
169 * 2 => legacy
170 */
171static unsigned int interrupt_mode;
172
173/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
174 * i.e. the number of CPUs among which we may distribute simultaneous
175 * interrupt handling.
176 *
177 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
178 * The default (0) means to assign an interrupt to each package (level II cache)
179 */
180static unsigned int rss_cpus;
181module_param(rss_cpus, uint, 0444);
182MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
183
84ae48fe
BH		 184static int phy_flash_cfg;
185module_param(phy_flash_cfg, int, 0644);
186MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
187
6fb70fd1
BH		 188static unsigned irq_adapt_low_thresh = 10000;
189module_param(irq_adapt_low_thresh, uint, 0644);
190MODULE_PARM_DESC(irq_adapt_low_thresh,
191 "Threshold score for reducing IRQ moderation");
192
193static unsigned irq_adapt_high_thresh = 20000;
194module_param(irq_adapt_high_thresh, uint, 0644);
195MODULE_PARM_DESC(irq_adapt_high_thresh,
196 "Threshold score for increasing IRQ moderation");
197
8ceee660
BH		 198/**************************************************************************
199 *
200 * Utility functions and prototypes
201 *
202 *************************************************************************/
203static void efx_remove_channel(struct efx_channel *channel);
204static void efx_remove_port(struct efx_nic *efx);
205static void efx_fini_napi(struct efx_nic *efx);
206static void efx_fini_channels(struct efx_nic *efx);
207
208#define EFX_ASSERT_RESET_SERIALISED(efx) \
209 do { \
332c1ce9
BH		 210 if ((efx->state == STATE_RUNNING) || \
211 (efx->state == STATE_DISABLED)) \
8ceee660
BH		 212 ASSERT_RTNL(); \
213 } while (0)
214
215/**************************************************************************
216 *
217 * Event queue processing
218 *
219 *************************************************************************/
220
221/* Process channel's event queue
222 *
223 * This function is responsible for processing the event queue of a
224 * single channel. The caller must guarantee that this function will
225 * never be concurrently called more than once on the same channel,
226 * though different channels may be being processed concurrently.
227 */
4d566063 228static int efx_process_channel(struct efx_channel *channel, int rx_quota)
8ceee660 229{
42cbe2d7
BH		 230 struct efx_nic *efx = channel->efx;
231 int rx_packets;
8ceee660 232
42cbe2d7 233 if (unlikely(efx->reset_pending != RESET_TYPE_NONE ||
8ceee660 234 !channel->enabled))
42cbe2d7 235 return 0;
8ceee660 236
152b6a62 237 rx_packets = efx_nic_process_eventq(channel, rx_quota);
42cbe2d7
BH		 238 if (rx_packets == 0)
239 return 0;
8ceee660
BH		 240
241 /* Deliver last RX packet. */
242 if (channel->rx_pkt) {
243 __efx_rx_packet(channel, channel->rx_pkt,
244 channel->rx_pkt_csummed);
245 channel->rx_pkt = NULL;
246 }
247
8ceee660
BH		 248 efx_rx_strategy(channel);
249
42cbe2d7 250 efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]);
8ceee660 251
42cbe2d7 252 return rx_packets;
8ceee660
BH		 253}
254
255/* Mark channel as finished processing
256 *
257 * Note that since we will not receive further interrupts for this
258 * channel before we finish processing and call the eventq_read_ack()
259 * method, there is no need to use the interrupt hold-off timers.
260 */
261static inline void efx_channel_processed(struct efx_channel *channel)
262{
5b9e207c
BH		 263 /* The interrupt handler for this channel may set work_pending
264 * as soon as we acknowledge the events we've seen. Make sure
265 * it's cleared before then. */
dc8cfa55 266 channel->work_pending = false;
5b9e207c
BH		 267 smp_wmb();
268
152b6a62 269 efx_nic_eventq_read_ack(channel);
8ceee660
BH		 270}
271
272/* NAPI poll handler
273 *
274 * NAPI guarantees serialisation of polls of the same device, which
275 * provides the guarantee required by efx_process_channel().
276 */
277static int efx_poll(struct napi_struct *napi, int budget)
278{
279 struct efx_channel *channel =
280 container_of(napi, struct efx_channel, napi_str);
8ceee660
BH		 281 int rx_packets;
282
283 EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n",
284 channel->channel, raw_smp_processor_id());
285
42cbe2d7 286 rx_packets = efx_process_channel(channel, budget);
8ceee660
BH		 287
288 if (rx_packets < budget) {
6fb70fd1
BH		 289 struct efx_nic *efx = channel->efx;
290
291 if (channel->used_flags & EFX_USED_BY_RX &&
292 efx->irq_rx_adaptive &&
293 unlikely(++channel->irq_count == 1000)) {
6fb70fd1
BH		 294 if (unlikely(channel->irq_mod_score <
295 irq_adapt_low_thresh)) {
0d86ebd8
BH		 296 if (channel->irq_moderation > 1) {
297 channel->irq_moderation -= 1;
ef2b90ee 298 efx->type->push_irq_moderation(channel);
0d86ebd8 299 }
6fb70fd1
BH		 300 } else if (unlikely(channel->irq_mod_score >
301 irq_adapt_high_thresh)) {
0d86ebd8
BH		 302 if (channel->irq_moderation <
303 efx->irq_rx_moderation) {
304 channel->irq_moderation += 1;
ef2b90ee 305 efx->type->push_irq_moderation(channel);
0d86ebd8 306 }
6fb70fd1 307 }
6fb70fd1
BH		 308 channel->irq_count = 0;
309 channel->irq_mod_score = 0;
310 }
311
8ceee660 312 /* There is no race here; although napi_disable() will
288379f0 313 * only wait for napi_complete(), this isn't a problem
8ceee660
BH		 314 * since efx_channel_processed() will have no effect if
315 * interrupts have already been disabled.
316 */
288379f0 317 napi_complete(napi);
8ceee660
BH		 318 efx_channel_processed(channel);
319 }
320
321 return rx_packets;
322}
323
324/* Process the eventq of the specified channel immediately on this CPU
325 *
326 * Disable hardware generated interrupts, wait for any existing
327 * processing to finish, then directly poll (and ack ) the eventq.
328 * Finally reenable NAPI and interrupts.
329 *
330 * Since we are touching interrupts the caller should hold the suspend lock
331 */
332void efx_process_channel_now(struct efx_channel *channel)
333{
334 struct efx_nic *efx = channel->efx;
335
336 BUG_ON(!channel->used_flags);
337 BUG_ON(!channel->enabled);
338
339 /* Disable interrupts and wait for ISRs to complete */
152b6a62 340 efx_nic_disable_interrupts(efx);
8ceee660
BH		 341 if (efx->legacy_irq)
342 synchronize_irq(efx->legacy_irq);
64ee3120 343 if (channel->irq)
8ceee660
BH		 344 synchronize_irq(channel->irq);
345
346 /* Wait for any NAPI processing to complete */
347 napi_disable(&channel->napi_str);
348
349 /* Poll the channel */
3ffeabdd 350 efx_process_channel(channel, EFX_EVQ_SIZE);
8ceee660
BH		 351
352 /* Ack the eventq. This may cause an interrupt to be generated
353 * when they are reenabled */
354 efx_channel_processed(channel);
355
356 napi_enable(&channel->napi_str);
152b6a62 357 efx_nic_enable_interrupts(efx);
8ceee660
BH		 358}
359
360/* Create event queue
361 * Event queue memory allocations are done only once. If the channel
362 * is reset, the memory buffer will be reused; this guards against
363 * errors during channel reset and also simplifies interrupt handling.
364 */
365static int efx_probe_eventq(struct efx_channel *channel)
366{
367 EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel);
368
152b6a62 369 return efx_nic_probe_eventq(channel);
8ceee660
BH		 370}
371
372/* Prepare channel's event queue */
bc3c90a2 373static void efx_init_eventq(struct efx_channel *channel)
8ceee660
BH		 374{
375 EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel);
376
377 channel->eventq_read_ptr = 0;
378
152b6a62 379 efx_nic_init_eventq(channel);
8ceee660
BH		 380}
381
382static void efx_fini_eventq(struct efx_channel *channel)
383{
384 EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel);
385
152b6a62 386 efx_nic_fini_eventq(channel);
8ceee660
BH		 387}
388
389static void efx_remove_eventq(struct efx_channel *channel)
390{
391 EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel);
392
152b6a62 393 efx_nic_remove_eventq(channel);
8ceee660
BH		 394}
395
396/**************************************************************************
397 *
398 * Channel handling
399 *
400 *************************************************************************/
401
8ceee660
BH		 402static int efx_probe_channel(struct efx_channel *channel)
403{
404 struct efx_tx_queue *tx_queue;
405 struct efx_rx_queue *rx_queue;
406 int rc;
407
408 EFX_LOG(channel->efx, "creating channel %d\n", channel->channel);
409
410 rc = efx_probe_eventq(channel);
411 if (rc)
412 goto fail1;
413
414 efx_for_each_channel_tx_queue(tx_queue, channel) {
415 rc = efx_probe_tx_queue(tx_queue);
416 if (rc)
417 goto fail2;
418 }
419
420 efx_for_each_channel_rx_queue(rx_queue, channel) {
421 rc = efx_probe_rx_queue(rx_queue);
422 if (rc)
423 goto fail3;
424 }
425
426 channel->n_rx_frm_trunc = 0;
427
428 return 0;
429
430 fail3:
431 efx_for_each_channel_rx_queue(rx_queue, channel)
432 efx_remove_rx_queue(rx_queue);
433 fail2:
434 efx_for_each_channel_tx_queue(tx_queue, channel)
435 efx_remove_tx_queue(tx_queue);
436 fail1:
437 return rc;
438}
439
440
56536e9c
BH		 441static void efx_set_channel_names(struct efx_nic *efx)
442{
443 struct efx_channel *channel;
444 const char *type = "";
445 int number;
446
447 efx_for_each_channel(channel, efx) {
448 number = channel->channel;
449 if (efx->n_channels > efx->n_rx_queues) {
450 if (channel->channel < efx->n_rx_queues) {
451 type = "-rx";
452 } else {
453 type = "-tx";
454 number -= efx->n_rx_queues;
455 }
456 }
457 snprintf(channel->name, sizeof(channel->name),
458 "%s%s-%d", efx->name, type, number);
459 }
460}
461
8ceee660
BH		 462/* Channels are shutdown and reinitialised whilst the NIC is running
463 * to propagate configuration changes (mtu, checksum offload), or
464 * to clear hardware error conditions
465 */
bc3c90a2 466static void efx_init_channels(struct efx_nic *efx)
8ceee660
BH		 467{
468 struct efx_tx_queue *tx_queue;
469 struct efx_rx_queue *rx_queue;
470 struct efx_channel *channel;
8ceee660 471
f7f13b0b
BH		 472 /* Calculate the rx buffer allocation parameters required to
473 * support the current MTU, including padding for header
474 * alignment and overruns.
475 */
476 efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) +
477 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
478 efx->type->rx_buffer_padding);
479 efx->rx_buffer_order = get_order(efx->rx_buffer_len);
8ceee660
BH		 480
481 /* Initialise the channels */
482 efx_for_each_channel(channel, efx) {
483 EFX_LOG(channel->efx, "init chan %d\n", channel->channel);
484
bc3c90a2 485 efx_init_eventq(channel);
8ceee660 486
bc3c90a2
BH		 487 efx_for_each_channel_tx_queue(tx_queue, channel)
488 efx_init_tx_queue(tx_queue);
8ceee660
BH		 489
490 /* The rx buffer allocation strategy is MTU dependent */
491 efx_rx_strategy(channel);
492
bc3c90a2
BH		 493 efx_for_each_channel_rx_queue(rx_queue, channel)
494 efx_init_rx_queue(rx_queue);
8ceee660
BH		 495
496 WARN_ON(channel->rx_pkt != NULL);
497 efx_rx_strategy(channel);
498 }
8ceee660
BH		 499}
500
501/* This enables event queue processing and packet transmission.
502 *
503 * Note that this function is not allowed to fail, since that would
504 * introduce too much complexity into the suspend/resume path.
505 */
506static void efx_start_channel(struct efx_channel *channel)
507{
508 struct efx_rx_queue *rx_queue;
509
510 EFX_LOG(channel->efx, "starting chan %d\n", channel->channel);
511
5b9e207c
BH		 512 /* The interrupt handler for this channel may set work_pending
513 * as soon as we enable it. Make sure it's cleared before
514 * then. Similarly, make sure it sees the enabled flag set. */
dc8cfa55
BH		 515 channel->work_pending = false;
516 channel->enabled = true;
5b9e207c 517 smp_wmb();
8ceee660
BH		 518
519 napi_enable(&channel->napi_str);
520
521 /* Load up RX descriptors */
522 efx_for_each_channel_rx_queue(rx_queue, channel)
523 efx_fast_push_rx_descriptors(rx_queue);
524}
525
526/* This disables event queue processing and packet transmission.
527 * This function does not guarantee that all queue processing
528 * (e.g. RX refill) is complete.
529 */
530static void efx_stop_channel(struct efx_channel *channel)
531{
532 struct efx_rx_queue *rx_queue;
533
534 if (!channel->enabled)
535 return;
536
537 EFX_LOG(channel->efx, "stop chan %d\n", channel->channel);
538
dc8cfa55 539 channel->enabled = false;
8ceee660
BH		 540 napi_disable(&channel->napi_str);
541
542 /* Ensure that any worker threads have exited or will be no-ops */
543 efx_for_each_channel_rx_queue(rx_queue, channel) {
544 spin_lock_bh(&rx_queue->add_lock);
545 spin_unlock_bh(&rx_queue->add_lock);
546 }
547}
548
549static void efx_fini_channels(struct efx_nic *efx)
550{
551 struct efx_channel *channel;
552 struct efx_tx_queue *tx_queue;
553 struct efx_rx_queue *rx_queue;
6bc5d3a9 554 int rc;
8ceee660
BH		 555
556 EFX_ASSERT_RESET_SERIALISED(efx);
557 BUG_ON(efx->port_enabled);
558
152b6a62 559 rc = efx_nic_flush_queues(efx);
6bc5d3a9
BH		 560 if (rc)
561 EFX_ERR(efx, "failed to flush queues\n");
562 else
563 EFX_LOG(efx, "successfully flushed all queues\n");
564
8ceee660
BH		 565 efx_for_each_channel(channel, efx) {
566 EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel);
567
568 efx_for_each_channel_rx_queue(rx_queue, channel)
569 efx_fini_rx_queue(rx_queue);
570 efx_for_each_channel_tx_queue(tx_queue, channel)
571 efx_fini_tx_queue(tx_queue);
8ceee660
BH		 572 efx_fini_eventq(channel);
573 }
574}
575
576static void efx_remove_channel(struct efx_channel *channel)
577{
578 struct efx_tx_queue *tx_queue;
579 struct efx_rx_queue *rx_queue;
580
581 EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel);
582
583 efx_for_each_channel_rx_queue(rx_queue, channel)
584 efx_remove_rx_queue(rx_queue);
585 efx_for_each_channel_tx_queue(tx_queue, channel)
586 efx_remove_tx_queue(tx_queue);
587 efx_remove_eventq(channel);
588
589 channel->used_flags = 0;
590}
591
592void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay)
593{
594 queue_delayed_work(refill_workqueue, &rx_queue->work, delay);
595}
596
597/**************************************************************************
598 *
599 * Port handling
600 *
601 **************************************************************************/
602
603/* This ensures that the kernel is kept informed (via
604 * netif_carrier_on/off) of the link status, and also maintains the
605 * link status's stop on the port's TX queue.
606 */
fdaa9aed 607void efx_link_status_changed(struct efx_nic *efx)
8ceee660 608{
eb50c0d6
BH		 609 struct efx_link_state *link_state = &efx->link_state;
610
8ceee660
BH		 611 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
612 * that no events are triggered between unregister_netdev() and the
613 * driver unloading. A more general condition is that NETDEV_CHANGE
614 * can only be generated between NETDEV_UP and NETDEV_DOWN */
615 if (!netif_running(efx->net_dev))
616 return;
617
8c8661e4
BH		 618 if (efx->port_inhibited) {
619 netif_carrier_off(efx->net_dev);
620 return;
621 }
622
eb50c0d6 623 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
8ceee660
BH		 624 efx->n_link_state_changes++;
625
eb50c0d6 626 if (link_state->up)
8ceee660
BH		 627 netif_carrier_on(efx->net_dev);
628 else
629 netif_carrier_off(efx->net_dev);
630 }
631
632 /* Status message for kernel log */
eb50c0d6 633 if (link_state->up) {
f31a45d2 634 EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n",
eb50c0d6 635 link_state->speed, link_state->fd ? "full" : "half",
8ceee660
BH		 636 efx->net_dev->mtu,
637 (efx->promiscuous ? " [PROMISC]" : ""));
638 } else {
639 EFX_INFO(efx, "link down\n");
640 }
641
642}
643
d3245b28
BH		 644void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
645{
646 efx->link_advertising = advertising;
647 if (advertising) {
648 if (advertising & ADVERTISED_Pause)
649 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
650 else
651 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
652 if (advertising & ADVERTISED_Asym_Pause)
653 efx->wanted_fc ^= EFX_FC_TX;
654 }
655}
656
657void efx_link_set_wanted_fc(struct efx_nic *efx, enum efx_fc_type wanted_fc)
658{
659 efx->wanted_fc = wanted_fc;
660 if (efx->link_advertising) {
661 if (wanted_fc & EFX_FC_RX)
662 efx->link_advertising |= (ADVERTISED_Pause |
663 ADVERTISED_Asym_Pause);
664 else
665 efx->link_advertising &= ~(ADVERTISED_Pause |
666 ADVERTISED_Asym_Pause);
667 if (wanted_fc & EFX_FC_TX)
668 efx->link_advertising ^= ADVERTISED_Asym_Pause;
669 }
670}
671
115122af
BH		 672static void efx_fini_port(struct efx_nic *efx);
673
d3245b28
BH		 674/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
675 * the MAC appropriately. All other PHY configuration changes are pushed
676 * through phy_op->set_settings(), and pushed asynchronously to the MAC
677 * through efx_monitor().
678 *
679 * Callers must hold the mac_lock
680 */
681int __efx_reconfigure_port(struct efx_nic *efx)
8ceee660 682{
d3245b28
BH		 683 enum efx_phy_mode phy_mode;
684 int rc;
8ceee660 685
d3245b28 686 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8ceee660 687
a816f75a
BH		 688 /* Serialise the promiscuous flag with efx_set_multicast_list. */
689 if (efx_dev_registered(efx)) {
690 netif_addr_lock_bh(efx->net_dev);
691 netif_addr_unlock_bh(efx->net_dev);
692 }
693
d3245b28
BH		 694 /* Disable PHY transmit in mac level loopbacks */
695 phy_mode = efx->phy_mode;
177dfcd8
BH		 696 if (LOOPBACK_INTERNAL(efx))
697 efx->phy_mode |= PHY_MODE_TX_DISABLED;
698 else
699 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
177dfcd8 700
d3245b28 701 rc = efx->type->reconfigure_port(efx);
8ceee660 702
d3245b28
BH		 703 if (rc)
704 efx->phy_mode = phy_mode;
177dfcd8 705
d3245b28 706 return rc;
8ceee660
BH		 707}
708
709/* Reinitialise the MAC to pick up new PHY settings, even if the port is
710 * disabled. */
d3245b28 711int efx_reconfigure_port(struct efx_nic *efx)
8ceee660 712{
d3245b28
BH		 713 int rc;
714
8ceee660
BH		 715 EFX_ASSERT_RESET_SERIALISED(efx);
716
717 mutex_lock(&efx->mac_lock);
d3245b28 718 rc = __efx_reconfigure_port(efx);
8ceee660 719 mutex_unlock(&efx->mac_lock);
d3245b28
BH		 720
721 return rc;
8ceee660
BH		 722}
723
8be4f3e6
BH		 724/* Asynchronous work item for changing MAC promiscuity and multicast
725 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
726 * MAC directly. */
766ca0fa
BH		 727static void efx_mac_work(struct work_struct *data)
728{
729 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
730
731 mutex_lock(&efx->mac_lock);
8be4f3e6 732 if (efx->port_enabled) {
ef2b90ee 733 efx->type->push_multicast_hash(efx);
8be4f3e6
BH		 734 efx->mac_op->reconfigure(efx);
735 }
766ca0fa
BH		 736 mutex_unlock(&efx->mac_lock);
737}
738
8ceee660
BH		 739static int efx_probe_port(struct efx_nic *efx)
740{
741 int rc;
742
743 EFX_LOG(efx, "create port\n");
744
ff3b00a0
SH		 745 if (phy_flash_cfg)
746 efx->phy_mode = PHY_MODE_SPECIAL;
747
ef2b90ee
BH		 748 /* Connect up MAC/PHY operations table */
749 rc = efx->type->probe_port(efx);
8ceee660
BH		 750 if (rc)
751 goto err;
752
753 /* Sanity check MAC address */
754 if (is_valid_ether_addr(efx->mac_address)) {
755 memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN);
756 } else {
e174961c
JB		 757 EFX_ERR(efx, "invalid MAC address %pM\n",
758 efx->mac_address);
8ceee660
BH		 759 if (!allow_bad_hwaddr) {
760 rc = -EINVAL;
761 goto err;
762 }
763 random_ether_addr(efx->net_dev->dev_addr);
e174961c
JB		 764 EFX_INFO(efx, "using locally-generated MAC %pM\n",
765 efx->net_dev->dev_addr);
8ceee660
BH		 766 }
767
768 return 0;
769
770 err:
771 efx_remove_port(efx);
772 return rc;
773}
774
775static int efx_init_port(struct efx_nic *efx)
776{
777 int rc;
778
779 EFX_LOG(efx, "init port\n");
780
1dfc5cea
BH		 781 mutex_lock(&efx->mac_lock);
782
177dfcd8 783 rc = efx->phy_op->init(efx);
8ceee660 784 if (rc)
1dfc5cea 785 goto fail1;
8ceee660 786
dc8cfa55 787 efx->port_initialized = true;
1dfc5cea 788
d3245b28
BH		 789 /* Reconfigure the MAC before creating dma queues (required for
790 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
791 efx->mac_op->reconfigure(efx);
792
793 /* Ensure the PHY advertises the correct flow control settings */
794 rc = efx->phy_op->reconfigure(efx);
795 if (rc)
796 goto fail2;
797
1dfc5cea 798 mutex_unlock(&efx->mac_lock);
8ceee660 799 return 0;
177dfcd8 800
1dfc5cea 801fail2:
177dfcd8 802 efx->phy_op->fini(efx);
1dfc5cea
BH		 803fail1:
804 mutex_unlock(&efx->mac_lock);
177dfcd8 805 return rc;
8ceee660
BH		 806}
807
8ceee660
BH		 808static void efx_start_port(struct efx_nic *efx)
809{
810 EFX_LOG(efx, "start port\n");
811 BUG_ON(efx->port_enabled);
812
813 mutex_lock(&efx->mac_lock);
dc8cfa55 814 efx->port_enabled = true;
8be4f3e6
BH		 815
816 /* efx_mac_work() might have been scheduled after efx_stop_port(),
817 * and then cancelled by efx_flush_all() */
ef2b90ee 818 efx->type->push_multicast_hash(efx);
8be4f3e6
BH		 819 efx->mac_op->reconfigure(efx);
820
8ceee660
BH		 821 mutex_unlock(&efx->mac_lock);
822}
823
fdaa9aed 824/* Prevent efx_mac_work() and efx_monitor() from working */
8ceee660
BH		 825static void efx_stop_port(struct efx_nic *efx)
826{
827 EFX_LOG(efx, "stop port\n");
828
829 mutex_lock(&efx->mac_lock);
dc8cfa55 830 efx->port_enabled = false;
8ceee660
BH		 831 mutex_unlock(&efx->mac_lock);
832
833 /* Serialise against efx_set_multicast_list() */
55668611 834 if (efx_dev_registered(efx)) {
b9e40857
DM		 835 netif_addr_lock_bh(efx->net_dev);
836 netif_addr_unlock_bh(efx->net_dev);
8ceee660
BH		 837 }
838}
839
840static void efx_fini_port(struct efx_nic *efx)
841{
842 EFX_LOG(efx, "shut down port\n");
843
844 if (!efx->port_initialized)
845 return;
846
177dfcd8 847 efx->phy_op->fini(efx);
dc8cfa55 848 efx->port_initialized = false;
8ceee660 849
eb50c0d6 850 efx->link_state.up = false;
8ceee660
BH		 851 efx_link_status_changed(efx);
852}
853
854static void efx_remove_port(struct efx_nic *efx)
855{
856 EFX_LOG(efx, "destroying port\n");
857
ef2b90ee 858 efx->type->remove_port(efx);
8ceee660
BH		 859}
860
861/**************************************************************************
862 *
863 * NIC handling
864 *
865 **************************************************************************/
866
867/* This configures the PCI device to enable I/O and DMA. */
868static int efx_init_io(struct efx_nic *efx)
869{
870 struct pci_dev *pci_dev = efx->pci_dev;
871 dma_addr_t dma_mask = efx->type->max_dma_mask;
872 int rc;
873
874 EFX_LOG(efx, "initialising I/O\n");
875
876 rc = pci_enable_device(pci_dev);
877 if (rc) {
878 EFX_ERR(efx, "failed to enable PCI device\n");
879 goto fail1;
880 }
881
882 pci_set_master(pci_dev);
883
884 /* Set the PCI DMA mask. Try all possibilities from our
885 * genuine mask down to 32 bits, because some architectures
886 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
887 * masks event though they reject 46 bit masks.
888 */
889 while (dma_mask > 0x7fffffffUL) {
890 if (pci_dma_supported(pci_dev, dma_mask) &&
891 ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0))
892 break;
893 dma_mask >>= 1;
894 }
895 if (rc) {
896 EFX_ERR(efx, "could not find a suitable DMA mask\n");
897 goto fail2;
898 }
899 EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask);
900 rc = pci_set_consistent_dma_mask(pci_dev, dma_mask);
901 if (rc) {
902 /* pci_set_consistent_dma_mask() is not *allowed* to
903 * fail with a mask that pci_set_dma_mask() accepted,
904 * but just in case...
905 */
906 EFX_ERR(efx, "failed to set consistent DMA mask\n");
907 goto fail2;
908 }
909
dc803df8
BH		 910 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
911 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
8ceee660
BH		 912 if (rc) {
913 EFX_ERR(efx, "request for memory BAR failed\n");
914 rc = -EIO;
915 goto fail3;
916 }
917 efx->membase = ioremap_nocache(efx->membase_phys,
918 efx->type->mem_map_size);
919 if (!efx->membase) {
dc803df8 920 EFX_ERR(efx, "could not map memory BAR at %llx+%x\n",
086ea356 921 (unsigned long long)efx->membase_phys,
8ceee660
BH		 922 efx->type->mem_map_size);
923 rc = -ENOMEM;
924 goto fail4;
925 }
dc803df8
BH		 926 EFX_LOG(efx, "memory BAR at %llx+%x (virtual %p)\n",
927 (unsigned long long)efx->membase_phys,
086ea356 928 efx->type->mem_map_size, efx->membase);
8ceee660
BH		 929
930 return 0;
931
932 fail4:
dc803df8 933 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
8ceee660 934 fail3:
2c118e0f 935 efx->membase_phys = 0;
8ceee660
BH		 936 fail2:
937 pci_disable_device(efx->pci_dev);
938 fail1:
939 return rc;
940}
941
942static void efx_fini_io(struct efx_nic *efx)
943{
944 EFX_LOG(efx, "shutting down I/O\n");
945
946 if (efx->membase) {
947 iounmap(efx->membase);
948 efx->membase = NULL;
949 }
950
951 if (efx->membase_phys) {
dc803df8 952 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
2c118e0f 953 efx->membase_phys = 0;
8ceee660
BH		 954 }
955
956 pci_disable_device(efx->pci_dev);
957}
958
46123d04
BH		 959/* Get number of RX queues wanted. Return number of online CPU
960 * packages in the expectation that an IRQ balancer will spread
961 * interrupts across them. */
962static int efx_wanted_rx_queues(void)
963{
2f8975fb 964 cpumask_var_t core_mask;
46123d04
BH		 965 int count;
966 int cpu;
967
79f55997 968 if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) {
2f8975fb 969 printk(KERN_WARNING
3977d033 970 "sfc: RSS disabled due to allocation failure\n");
2f8975fb
RR		 971 return 1;
972 }
973
46123d04
BH		 974 count = 0;
975 for_each_online_cpu(cpu) {
2f8975fb 976 if (!cpumask_test_cpu(cpu, core_mask)) {
46123d04 977 ++count;
2f8975fb 978 cpumask_or(core_mask, core_mask,
fbd59a8d 979 topology_core_cpumask(cpu));
46123d04
BH		 980 }
981 }
982
2f8975fb 983 free_cpumask_var(core_mask);
46123d04
BH		 984 return count;
985}
986
987/* Probe the number and type of interrupts we are able to obtain, and
988 * the resulting numbers of channels and RX queues.
989 */
8ceee660
BH		 990static void efx_probe_interrupts(struct efx_nic *efx)
991{
46123d04
BH		 992 int max_channels =
993 min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS);
8ceee660
BH		 994 int rc, i;
995
996 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
46123d04
BH		 997 struct msix_entry xentries[EFX_MAX_CHANNELS];
998 int wanted_ints;
28b581ab 999 int rx_queues;
aa6ef27e 1000
46123d04
BH		 1001 /* We want one RX queue and interrupt per CPU package
1002 * (or as specified by the rss_cpus module parameter).
1003 * We will need one channel per interrupt.
1004 */
28b581ab
NT		 1005 rx_queues = rss_cpus ? rss_cpus : efx_wanted_rx_queues();
1006 wanted_ints = rx_queues + (separate_tx_channels ? 1 : 0);
1007 wanted_ints = min(wanted_ints, max_channels);
8ceee660 1008
28b581ab 1009 for (i = 0; i < wanted_ints; i++)
8ceee660 1010 xentries[i].entry = i;
28b581ab 1011 rc = pci_enable_msix(efx->pci_dev, xentries, wanted_ints);
8ceee660 1012 if (rc > 0) {
28b581ab
NT		 1013 EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors"
1014 " available (%d < %d).\n", rc, wanted_ints);
1015 EFX_ERR(efx, "WARNING: Performance may be reduced.\n");
1016 EFX_BUG_ON_PARANOID(rc >= wanted_ints);
1017 wanted_ints = rc;
8ceee660 1018 rc = pci_enable_msix(efx->pci_dev, xentries,
28b581ab 1019 wanted_ints);
8ceee660
BH		 1020 }
1021
1022 if (rc == 0) {
28b581ab
NT		 1023 efx->n_rx_queues = min(rx_queues, wanted_ints);
1024 efx->n_channels = wanted_ints;
1025 for (i = 0; i < wanted_ints; i++)
8ceee660 1026 efx->channel[i].irq = xentries[i].vector;
8ceee660
BH		 1027 } else {
1028 /* Fall back to single channel MSI */
1029 efx->interrupt_mode = EFX_INT_MODE_MSI;
1030 EFX_ERR(efx, "could not enable MSI-X\n");
1031 }
1032 }
1033
1034 /* Try single interrupt MSI */
1035 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
8831da7b 1036 efx->n_rx_queues = 1;
28b581ab 1037 efx->n_channels = 1;
8ceee660
BH		 1038 rc = pci_enable_msi(efx->pci_dev);
1039 if (rc == 0) {
1040 efx->channel[0].irq = efx->pci_dev->irq;
8ceee660
BH		 1041 } else {
1042 EFX_ERR(efx, "could not enable MSI\n");
1043 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1044 }
1045 }
1046
1047 /* Assume legacy interrupts */
1048 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
8831da7b 1049 efx->n_rx_queues = 1;
28b581ab 1050 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
8ceee660
BH		 1051 efx->legacy_irq = efx->pci_dev->irq;
1052 }
1053}
1054
1055static void efx_remove_interrupts(struct efx_nic *efx)
1056{
1057 struct efx_channel *channel;
1058
1059 /* Remove MSI/MSI-X interrupts */
64ee3120 1060 efx_for_each_channel(channel, efx)
8ceee660
BH		 1061 channel->irq = 0;
1062 pci_disable_msi(efx->pci_dev);
1063 pci_disable_msix(efx->pci_dev);
1064
1065 /* Remove legacy interrupt */
1066 efx->legacy_irq = 0;
1067}
1068
8831da7b 1069static void efx_set_channels(struct efx_nic *efx)
8ceee660
BH		 1070{
1071 struct efx_tx_queue *tx_queue;
1072 struct efx_rx_queue *rx_queue;
8ceee660 1073
60ac1065 1074 efx_for_each_tx_queue(tx_queue, efx) {
28b581ab
NT		 1075 if (separate_tx_channels)
1076 tx_queue->channel = &efx->channel[efx->n_channels-1];
60ac1065
BH		 1077 else
1078 tx_queue->channel = &efx->channel[0];
1079 tx_queue->channel->used_flags |= EFX_USED_BY_TX;
1080 }
8ceee660 1081
8831da7b
BH		 1082 efx_for_each_rx_queue(rx_queue, efx) {
1083 rx_queue->channel = &efx->channel[rx_queue->queue];
1084 rx_queue->channel->used_flags |= EFX_USED_BY_RX;
8ceee660
BH		 1085 }
1086}
1087
1088static int efx_probe_nic(struct efx_nic *efx)
1089{
1090 int rc;
1091
1092 EFX_LOG(efx, "creating NIC\n");
1093
1094 /* Carry out hardware-type specific initialisation */
ef2b90ee 1095 rc = efx->type->probe(efx);
8ceee660
BH		 1096 if (rc)
1097 return rc;
1098
1099 /* Determine the number of channels and RX queues by trying to hook
1100 * in MSI-X interrupts. */
1101 efx_probe_interrupts(efx);
1102
8831da7b 1103 efx_set_channels(efx);
8ceee660
BH		 1104
1105 /* Initialise the interrupt moderation settings */
6fb70fd1 1106 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true);
8ceee660
BH		 1107
1108 return 0;
1109}
1110
1111static void efx_remove_nic(struct efx_nic *efx)
1112{
1113 EFX_LOG(efx, "destroying NIC\n");
1114
1115 efx_remove_interrupts(efx);
ef2b90ee 1116 efx->type->remove(efx);
8ceee660
BH		 1117}
1118
1119/**************************************************************************
1120 *
1121 * NIC startup/shutdown
1122 *
1123 *************************************************************************/
1124
1125static int efx_probe_all(struct efx_nic *efx)
1126{
1127 struct efx_channel *channel;
1128 int rc;
1129
1130 /* Create NIC */
1131 rc = efx_probe_nic(efx);
1132 if (rc) {
1133 EFX_ERR(efx, "failed to create NIC\n");
1134 goto fail1;
1135 }
1136
1137 /* Create port */
1138 rc = efx_probe_port(efx);
1139 if (rc) {
1140 EFX_ERR(efx, "failed to create port\n");
1141 goto fail2;
1142 }
1143
1144 /* Create channels */
1145 efx_for_each_channel(channel, efx) {
1146 rc = efx_probe_channel(channel);
1147 if (rc) {
1148 EFX_ERR(efx, "failed to create channel %d\n",
1149 channel->channel);
1150 goto fail3;
1151 }
1152 }
56536e9c 1153 efx_set_channel_names(efx);
8ceee660
BH		 1154
1155 return 0;
1156
1157 fail3:
1158 efx_for_each_channel(channel, efx)
1159 efx_remove_channel(channel);
1160 efx_remove_port(efx);
1161 fail2:
1162 efx_remove_nic(efx);
1163 fail1:
1164 return rc;
1165}
1166
1167/* Called after previous invocation(s) of efx_stop_all, restarts the
1168 * port, kernel transmit queue, NAPI processing and hardware interrupts,
1169 * and ensures that the port is scheduled to be reconfigured.
1170 * This function is safe to call multiple times when the NIC is in any
1171 * state. */
1172static void efx_start_all(struct efx_nic *efx)
1173{
1174 struct efx_channel *channel;
1175
1176 EFX_ASSERT_RESET_SERIALISED(efx);
1177
1178 /* Check that it is appropriate to restart the interface. All
1179 * of these flags are safe to read under just the rtnl lock */
1180 if (efx->port_enabled)
1181 return;
1182 if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT))
1183 return;
55668611 1184 if (efx_dev_registered(efx) && !netif_running(efx->net_dev))
8ceee660
BH		 1185 return;
1186
1187 /* Mark the port as enabled so port reconfigurations can start, then
1188 * restart the transmit interface early so the watchdog timer stops */
1189 efx_start_port(efx);
dacccc74
SH		 1190 if (efx_dev_registered(efx))
1191 efx_wake_queue(efx);
8ceee660
BH		 1192
1193 efx_for_each_channel(channel, efx)
1194 efx_start_channel(channel);
1195
152b6a62 1196 efx_nic_enable_interrupts(efx);
8ceee660 1197
8880f4ec
BH		 1198 /* Switch to event based MCDI completions after enabling interrupts.
1199 * If a reset has been scheduled, then we need to stay in polled mode.
1200 * Rather than serialising efx_mcdi_mode_event() [which sleeps] and
1201 * reset_pending [modified from an atomic context], we instead guarantee
1202 * that efx_mcdi_mode_poll() isn't reverted erroneously */
1203 efx_mcdi_mode_event(efx);
1204 if (efx->reset_pending != RESET_TYPE_NONE)
1205 efx_mcdi_mode_poll(efx);
1206
78c1f0a0
SH		 1207 /* Start the hardware monitor if there is one. Otherwise (we're link
1208 * event driven), we have to poll the PHY because after an event queue
1209 * flush, we could have a missed a link state change */
1210 if (efx->type->monitor != NULL) {
8ceee660
BH		 1211 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1212 efx_monitor_interval);
78c1f0a0
SH		 1213 } else {
1214 mutex_lock(&efx->mac_lock);
1215 if (efx->phy_op->poll(efx))
1216 efx_link_status_changed(efx);
1217 mutex_unlock(&efx->mac_lock);
1218 }
55edc6e6 1219
ef2b90ee 1220 efx->type->start_stats(efx);
8ceee660
BH		 1221}
1222
1223/* Flush all delayed work. Should only be called when no more delayed work
1224 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1225 * since we're holding the rtnl_lock at this point. */
1226static void efx_flush_all(struct efx_nic *efx)
1227{
1228 struct efx_rx_queue *rx_queue;
1229
1230 /* Make sure the hardware monitor is stopped */
1231 cancel_delayed_work_sync(&efx->monitor_work);
1232
1233 /* Ensure that all RX slow refills are complete. */
b3475645 1234 efx_for_each_rx_queue(rx_queue, efx)
8ceee660 1235 cancel_delayed_work_sync(&rx_queue->work);
8ceee660
BH		 1236
1237 /* Stop scheduled port reconfigurations */
766ca0fa 1238 cancel_work_sync(&efx->mac_work);
8ceee660
BH		 1239}
1240
1241/* Quiesce hardware and software without bringing the link down.
1242 * Safe to call multiple times, when the nic and interface is in any
1243 * state. The caller is guaranteed to subsequently be in a position
1244 * to modify any hardware and software state they see fit without
1245 * taking locks. */
1246static void efx_stop_all(struct efx_nic *efx)
1247{
1248 struct efx_channel *channel;
1249
1250 EFX_ASSERT_RESET_SERIALISED(efx);
1251
1252 /* port_enabled can be read safely under the rtnl lock */
1253 if (!efx->port_enabled)
1254 return;
1255
ef2b90ee 1256 efx->type->stop_stats(efx);
55edc6e6 1257
8880f4ec
BH		 1258 /* Switch to MCDI polling on Siena before disabling interrupts */
1259 efx_mcdi_mode_poll(efx);
1260
8ceee660 1261 /* Disable interrupts and wait for ISR to complete */
152b6a62 1262 efx_nic_disable_interrupts(efx);
8ceee660
BH		 1263 if (efx->legacy_irq)
1264 synchronize_irq(efx->legacy_irq);
64ee3120 1265 efx_for_each_channel(channel, efx) {
8ceee660
BH		 1266 if (channel->irq)
1267 synchronize_irq(channel->irq);
b3475645 1268 }
8ceee660
BH		 1269
1270 /* Stop all NAPI processing and synchronous rx refills */
1271 efx_for_each_channel(channel, efx)
1272 efx_stop_channel(channel);
1273
1274 /* Stop all asynchronous port reconfigurations. Since all
1275 * event processing has already been stopped, there is no
1276 * window to loose phy events */
1277 efx_stop_port(efx);
1278
fdaa9aed 1279 /* Flush efx_mac_work(), refill_workqueue, monitor_work */
8ceee660
BH		 1280 efx_flush_all(efx);
1281
8ceee660
BH		 1282 /* Stop the kernel transmit interface late, so the watchdog
1283 * timer isn't ticking over the flush */
55668611 1284 if (efx_dev_registered(efx)) {
dacccc74 1285 efx_stop_queue(efx);
8ceee660
BH		 1286 netif_tx_lock_bh(efx->net_dev);
1287 netif_tx_unlock_bh(efx->net_dev);
1288 }
1289}
1290
1291static void efx_remove_all(struct efx_nic *efx)
1292{
1293 struct efx_channel *channel;
1294
1295 efx_for_each_channel(channel, efx)
1296 efx_remove_channel(channel);
1297 efx_remove_port(efx);
1298 efx_remove_nic(efx);
1299}
1300
8ceee660
BH		 1301/**************************************************************************
1302 *
1303 * Interrupt moderation
1304 *
1305 **************************************************************************/
1306
0d86ebd8
BH		 1307static unsigned irq_mod_ticks(int usecs, int resolution)
1308{
1309 if (usecs <= 0)
1310 return 0; /* cannot receive interrupts ahead of time :-) */
1311 if (usecs < resolution)
1312 return 1; /* never round down to 0 */
1313 return usecs / resolution;
1314}
1315
8ceee660 1316/* Set interrupt moderation parameters */
6fb70fd1
BH		 1317void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs,
1318 bool rx_adaptive)
8ceee660
BH		 1319{
1320 struct efx_tx_queue *tx_queue;
1321 struct efx_rx_queue *rx_queue;
152b6a62
BH		 1322 unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION);
1323 unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION);
8ceee660
BH		 1324
1325 EFX_ASSERT_RESET_SERIALISED(efx);
1326
1327 efx_for_each_tx_queue(tx_queue, efx)
0d86ebd8 1328 tx_queue->channel->irq_moderation = tx_ticks;
8ceee660 1329
6fb70fd1 1330 efx->irq_rx_adaptive = rx_adaptive;
0d86ebd8 1331 efx->irq_rx_moderation = rx_ticks;
8ceee660 1332 efx_for_each_rx_queue(rx_queue, efx)
0d86ebd8 1333 rx_queue->channel->irq_moderation = rx_ticks;
8ceee660
BH		 1334}
1335
1336/**************************************************************************
1337 *
1338 * Hardware monitor
1339 *
1340 **************************************************************************/
1341
1342/* Run periodically off the general workqueue. Serialised against
1343 * efx_reconfigure_port via the mac_lock */
1344static void efx_monitor(struct work_struct *data)
1345{
1346 struct efx_nic *efx = container_of(data, struct efx_nic,
1347 monitor_work.work);
8ceee660
BH		 1348
1349 EFX_TRACE(efx, "hardware monitor executing on CPU %d\n",
1350 raw_smp_processor_id());
ef2b90ee 1351 BUG_ON(efx->type->monitor == NULL);
8ceee660 1352
8ceee660
BH		 1353 /* If the mac_lock is already held then it is likely a port
1354 * reconfiguration is already in place, which will likely do
1355 * most of the work of check_hw() anyway. */
766ca0fa
BH		 1356 if (!mutex_trylock(&efx->mac_lock))
1357 goto out_requeue;
1358 if (!efx->port_enabled)
1359 goto out_unlock;
ef2b90ee 1360 efx->type->monitor(efx);
8ceee660 1361
766ca0fa 1362out_unlock:
8ceee660 1363 mutex_unlock(&efx->mac_lock);
766ca0fa 1364out_requeue:
8ceee660
BH		 1365 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1366 efx_monitor_interval);
1367}
1368
1369/**************************************************************************
1370 *
1371 * ioctls
1372 *
1373 *************************************************************************/
1374
1375/* Net device ioctl
1376 * Context: process, rtnl_lock() held.
1377 */
1378static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1379{
767e468c 1380 struct efx_nic *efx = netdev_priv(net_dev);
68e7f45e 1381 struct mii_ioctl_data *data = if_mii(ifr);
8ceee660
BH		 1382
1383 EFX_ASSERT_RESET_SERIALISED(efx);
1384
68e7f45e
BH		 1385 /* Convert phy_id from older PRTAD/DEVAD format */
1386 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1387 (data->phy_id & 0xfc00) == 0x0400)
1388 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1389
1390 return mdio_mii_ioctl(&efx->mdio, data, cmd);
8ceee660
BH		 1391}
1392
1393/**************************************************************************
1394 *
1395 * NAPI interface
1396 *
1397 **************************************************************************/
1398
1399static int efx_init_napi(struct efx_nic *efx)
1400{
1401 struct efx_channel *channel;
8ceee660
BH		 1402
1403 efx_for_each_channel(channel, efx) {
1404 channel->napi_dev = efx->net_dev;
718cff1e
BH		 1405 netif_napi_add(channel->napi_dev, &channel->napi_str,
1406 efx_poll, napi_weight);
8ceee660
BH		 1407 }
1408 return 0;
8ceee660
BH		 1409}
1410
1411static void efx_fini_napi(struct efx_nic *efx)
1412{
1413 struct efx_channel *channel;
1414
1415 efx_for_each_channel(channel, efx) {
718cff1e
BH		 1416 if (channel->napi_dev)
1417 netif_napi_del(&channel->napi_str);
8ceee660
BH		 1418 channel->napi_dev = NULL;
1419 }
1420}
1421
1422/**************************************************************************
1423 *
1424 * Kernel netpoll interface
1425 *
1426 *************************************************************************/
1427
1428#ifdef CONFIG_NET_POLL_CONTROLLER
1429
1430/* Although in the common case interrupts will be disabled, this is not
1431 * guaranteed. However, all our work happens inside the NAPI callback,
1432 * so no locking is required.
1433 */
1434static void efx_netpoll(struct net_device *net_dev)
1435{
767e468c 1436 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1437 struct efx_channel *channel;
1438
64ee3120 1439 efx_for_each_channel(channel, efx)
8ceee660
BH		 1440 efx_schedule_channel(channel);
1441}
1442
1443#endif
1444
1445/**************************************************************************
1446 *
1447 * Kernel net device interface
1448 *
1449 *************************************************************************/
1450
1451/* Context: process, rtnl_lock() held. */
1452static int efx_net_open(struct net_device *net_dev)
1453{
767e468c 1454 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1455 EFX_ASSERT_RESET_SERIALISED(efx);
1456
1457 EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name,
1458 raw_smp_processor_id());
1459
f4bd954e
BH		 1460 if (efx->state == STATE_DISABLED)
1461 return -EIO;
f8b87c17
BH		 1462 if (efx->phy_mode & PHY_MODE_SPECIAL)
1463 return -EBUSY;
8880f4ec
BH		 1464 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
1465 return -EIO;
f8b87c17 1466
78c1f0a0
SH		 1467 /* Notify the kernel of the link state polled during driver load,
1468 * before the monitor starts running */
1469 efx_link_status_changed(efx);
1470
8ceee660
BH		 1471 efx_start_all(efx);
1472 return 0;
1473}
1474
1475/* Context: process, rtnl_lock() held.
1476 * Note that the kernel will ignore our return code; this method
1477 * should really be a void.
1478 */
1479static int efx_net_stop(struct net_device *net_dev)
1480{
767e468c 1481 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1482
1483 EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name,
1484 raw_smp_processor_id());
1485
f4bd954e
BH		 1486 if (efx->state != STATE_DISABLED) {
1487 /* Stop the device and flush all the channels */
1488 efx_stop_all(efx);
1489 efx_fini_channels(efx);
1490 efx_init_channels(efx);
1491 }
8ceee660
BH		 1492
1493 return 0;
1494}
1495
5b9e207c 1496/* Context: process, dev_base_lock or RTNL held, non-blocking. */
8ceee660
BH		 1497static struct net_device_stats *efx_net_stats(struct net_device *net_dev)
1498{
767e468c 1499 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1500 struct efx_mac_stats *mac_stats = &efx->mac_stats;
1501 struct net_device_stats *stats = &net_dev->stats;
1502
55edc6e6 1503 spin_lock_bh(&efx->stats_lock);
ef2b90ee 1504 efx->type->update_stats(efx);
55edc6e6 1505 spin_unlock_bh(&efx->stats_lock);
8ceee660
BH		 1506
1507 stats->rx_packets = mac_stats->rx_packets;
1508 stats->tx_packets = mac_stats->tx_packets;
1509 stats->rx_bytes = mac_stats->rx_bytes;
1510 stats->tx_bytes = mac_stats->tx_bytes;
1511 stats->multicast = mac_stats->rx_multicast;
1512 stats->collisions = mac_stats->tx_collision;
1513 stats->rx_length_errors = (mac_stats->rx_gtjumbo +
1514 mac_stats->rx_length_error);
1515 stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt;
1516 stats->rx_crc_errors = mac_stats->rx_bad;
1517 stats->rx_frame_errors = mac_stats->rx_align_error;
1518 stats->rx_fifo_errors = mac_stats->rx_overflow;
1519 stats->rx_missed_errors = mac_stats->rx_missed;
1520 stats->tx_window_errors = mac_stats->tx_late_collision;
1521
1522 stats->rx_errors = (stats->rx_length_errors +
1523 stats->rx_over_errors +
1524 stats->rx_crc_errors +
1525 stats->rx_frame_errors +
1526 stats->rx_fifo_errors +
1527 stats->rx_missed_errors +
1528 mac_stats->rx_symbol_error);
1529 stats->tx_errors = (stats->tx_window_errors +
1530 mac_stats->tx_bad);
1531
1532 return stats;
1533}
1534
1535/* Context: netif_tx_lock held, BHs disabled. */
1536static void efx_watchdog(struct net_device *net_dev)
1537{
767e468c 1538 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1539
739bb23d
BH		 1540 EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:"
1541 " resetting channels\n",
1542 atomic_read(&efx->netif_stop_count), efx->port_enabled);
8ceee660 1543
739bb23d 1544 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
8ceee660
BH		 1545}
1546
1547
1548/* Context: process, rtnl_lock() held. */
1549static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1550{
767e468c 1551 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1552 int rc = 0;
1553
1554 EFX_ASSERT_RESET_SERIALISED(efx);
1555
1556 if (new_mtu > EFX_MAX_MTU)
1557 return -EINVAL;
1558
1559 efx_stop_all(efx);
1560
1561 EFX_LOG(efx, "changing MTU to %d\n", new_mtu);
1562
1563 efx_fini_channels(efx);
d3245b28
BH		 1564
1565 mutex_lock(&efx->mac_lock);
1566 /* Reconfigure the MAC before enabling the dma queues so that
1567 * the RX buffers don't overflow */
8ceee660 1568 net_dev->mtu = new_mtu;
d3245b28
BH		 1569 efx->mac_op->reconfigure(efx);
1570 mutex_unlock(&efx->mac_lock);
1571
bc3c90a2 1572 efx_init_channels(efx);
8ceee660
BH		 1573
1574 efx_start_all(efx);
1575 return rc;
8ceee660
BH		 1576}
1577
1578static int efx_set_mac_address(struct net_device *net_dev, void *data)
1579{
767e468c 1580 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1581 struct sockaddr *addr = data;
1582 char *new_addr = addr->sa_data;
1583
1584 EFX_ASSERT_RESET_SERIALISED(efx);
1585
1586 if (!is_valid_ether_addr(new_addr)) {
e174961c
JB		 1587 EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n",
1588 new_addr);
8ceee660
BH		 1589 return -EINVAL;
1590 }
1591
1592 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
1593
1594 /* Reconfigure the MAC */
d3245b28
BH		 1595 mutex_lock(&efx->mac_lock);
1596 efx->mac_op->reconfigure(efx);
1597 mutex_unlock(&efx->mac_lock);
8ceee660
BH		 1598
1599 return 0;
1600}
1601
a816f75a 1602/* Context: netif_addr_lock held, BHs disabled. */
8ceee660
BH		 1603static void efx_set_multicast_list(struct net_device *net_dev)
1604{
767e468c 1605 struct efx_nic *efx = netdev_priv(net_dev);
5508590c 1606 struct dev_mc_list *mc_list;
8ceee660 1607 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
8ceee660
BH		 1608 u32 crc;
1609 int bit;
8ceee660 1610
8be4f3e6 1611 efx->promiscuous = !!(net_dev->flags & IFF_PROMISC);
8ceee660
BH		 1612
1613 /* Build multicast hash table */
8be4f3e6 1614 if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) {
8ceee660
BH		 1615 memset(mc_hash, 0xff, sizeof(*mc_hash));
1616 } else {
1617 memset(mc_hash, 0x00, sizeof(*mc_hash));
5508590c 1618 netdev_for_each_mc_addr(mc_list, net_dev) {
8ceee660
BH		 1619 crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr);
1620 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
1621 set_bit_le(bit, mc_hash->byte);
8ceee660 1622 }
8ceee660 1623
8be4f3e6
BH		 1624 /* Broadcast packets go through the multicast hash filter.
1625 * ether_crc_le() of the broadcast address is 0xbe2612ff
1626 * so we always add bit 0xff to the mask.
1627 */
1628 set_bit_le(0xff, mc_hash->byte);
1629 }
a816f75a 1630
8be4f3e6
BH		 1631 if (efx->port_enabled)
1632 queue_work(efx->workqueue, &efx->mac_work);
1633 /* Otherwise efx_start_port() will do this */
8ceee660
BH		 1634}
1635
c3ecb9f3
SH		 1636static const struct net_device_ops efx_netdev_ops = {
1637 .ndo_open = efx_net_open,
1638 .ndo_stop = efx_net_stop,
1639 .ndo_get_stats = efx_net_stats,
1640 .ndo_tx_timeout = efx_watchdog,
1641 .ndo_start_xmit = efx_hard_start_xmit,
1642 .ndo_validate_addr = eth_validate_addr,
1643 .ndo_do_ioctl = efx_ioctl,
1644 .ndo_change_mtu = efx_change_mtu,
1645 .ndo_set_mac_address = efx_set_mac_address,
1646 .ndo_set_multicast_list = efx_set_multicast_list,
1647#ifdef CONFIG_NET_POLL_CONTROLLER
1648 .ndo_poll_controller = efx_netpoll,
1649#endif
1650};
1651
7dde596e
BH		 1652static void efx_update_name(struct efx_nic *efx)
1653{
1654 strcpy(efx->name, efx->net_dev->name);
1655 efx_mtd_rename(efx);
1656 efx_set_channel_names(efx);
1657}
1658
8ceee660
BH		 1659static int efx_netdev_event(struct notifier_block *this,
1660 unsigned long event, void *ptr)
1661{
d3208b5e 1662 struct net_device *net_dev = ptr;
8ceee660 1663
7dde596e
BH		 1664 if (net_dev->netdev_ops == &efx_netdev_ops &&
1665 event == NETDEV_CHANGENAME)
1666 efx_update_name(netdev_priv(net_dev));
8ceee660
BH		 1667
1668 return NOTIFY_DONE;
1669}
1670
1671static struct notifier_block efx_netdev_notifier = {
1672 .notifier_call = efx_netdev_event,
1673};
1674
06d5e193
BH		 1675static ssize_t
1676show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
1677{
1678 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
1679 return sprintf(buf, "%d\n", efx->phy_type);
1680}
1681static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL);
1682
8ceee660
BH		 1683static int efx_register_netdev(struct efx_nic *efx)
1684{
1685 struct net_device *net_dev = efx->net_dev;
1686 int rc;
1687
1688 net_dev->watchdog_timeo = 5 * HZ;
1689 net_dev->irq = efx->pci_dev->irq;
c3ecb9f3 1690 net_dev->netdev_ops = &efx_netdev_ops;
8ceee660
BH		 1691 SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev);
1692 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
1693
8ceee660 1694 /* Clear MAC statistics */
177dfcd8 1695 efx->mac_op->update_stats(efx);
8ceee660
BH		 1696 memset(&efx->mac_stats, 0, sizeof(efx->mac_stats));
1697
7dde596e 1698 rtnl_lock();
aed0628d
BH		 1699
1700 rc = dev_alloc_name(net_dev, net_dev->name);
1701 if (rc < 0)
1702 goto fail_locked;
7dde596e 1703 efx_update_name(efx);
aed0628d
BH		 1704
1705 rc = register_netdevice(net_dev);
1706 if (rc)
1707 goto fail_locked;
1708
1709 /* Always start with carrier off; PHY events will detect the link */
1710 netif_carrier_off(efx->net_dev);
1711
7dde596e 1712 rtnl_unlock();
8ceee660 1713
06d5e193
BH		 1714 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
1715 if (rc) {
1716 EFX_ERR(efx, "failed to init net dev attributes\n");
1717 goto fail_registered;
1718 }
1719
8ceee660 1720 return 0;
06d5e193 1721
aed0628d
BH		 1722fail_locked:
1723 rtnl_unlock();
1724 EFX_ERR(efx, "could not register net dev\n");
1725 return rc;
1726
06d5e193
BH		 1727fail_registered:
1728 unregister_netdev(net_dev);
1729 return rc;
8ceee660
BH		 1730}
1731
1732static void efx_unregister_netdev(struct efx_nic *efx)
1733{
1734 struct efx_tx_queue *tx_queue;
1735
1736 if (!efx->net_dev)
1737 return;
1738
767e468c 1739 BUG_ON(netdev_priv(efx->net_dev) != efx);
8ceee660
BH		 1740
1741 /* Free up any skbs still remaining. This has to happen before
1742 * we try to unregister the netdev as running their destructors
1743 * may be needed to get the device ref. count to 0. */
1744 efx_for_each_tx_queue(tx_queue, efx)
1745 efx_release_tx_buffers(tx_queue);
1746
55668611 1747 if (efx_dev_registered(efx)) {
8ceee660 1748 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
06d5e193 1749 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
8ceee660
BH		 1750 unregister_netdev(efx->net_dev);
1751 }
1752}
1753
1754/**************************************************************************
1755 *
1756 * Device reset and suspend
1757 *
1758 **************************************************************************/
1759
2467ca46
BH		 1760/* Tears down the entire software state and most of the hardware state
1761 * before reset. */
d3245b28 1762void efx_reset_down(struct efx_nic *efx, enum reset_type method)
8ceee660 1763{
8ceee660
BH		 1764 EFX_ASSERT_RESET_SERIALISED(efx);
1765
2467ca46
BH		 1766 efx_stop_all(efx);
1767 mutex_lock(&efx->mac_lock);
f4150724 1768 mutex_lock(&efx->spi_lock);
2467ca46 1769
8ceee660 1770 efx_fini_channels(efx);
4b988280
SH		 1771 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
1772 efx->phy_op->fini(efx);
ef2b90ee 1773 efx->type->fini(efx);
8ceee660
BH		 1774}
1775
2467ca46
BH		 1776/* This function will always ensure that the locks acquired in
1777 * efx_reset_down() are released. A failure return code indicates
1778 * that we were unable to reinitialise the hardware, and the
1779 * driver should be disabled. If ok is false, then the rx and tx
1780 * engines are not restarted, pending a RESET_DISABLE. */
d3245b28 1781int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
8ceee660
BH		 1782{
1783 int rc;
1784
2467ca46 1785 EFX_ASSERT_RESET_SERIALISED(efx);
8ceee660 1786
ef2b90ee 1787 rc = efx->type->init(efx);
8ceee660 1788 if (rc) {
2467ca46 1789 EFX_ERR(efx, "failed to initialise NIC\n");
eb9f6744 1790 goto fail;
8ceee660
BH		 1791 }
1792
eb9f6744
BH		 1793 if (!ok)
1794 goto fail;
1795
4b988280 1796 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
eb9f6744
BH		 1797 rc = efx->phy_op->init(efx);
1798 if (rc)
1799 goto fail;
1800 if (efx->phy_op->reconfigure(efx))
1801 EFX_ERR(efx, "could not restore PHY settings\n");
4b988280
SH		 1802 }
1803
eb9f6744 1804 efx->mac_op->reconfigure(efx);
8ceee660 1805
eb9f6744
BH		 1806 efx_init_channels(efx);
1807
1808 mutex_unlock(&efx->spi_lock);
1809 mutex_unlock(&efx->mac_lock);
1810
1811 efx_start_all(efx);
1812
1813 return 0;
1814
1815fail:
1816 efx->port_initialized = false;
2467ca46 1817
f4150724 1818 mutex_unlock(&efx->spi_lock);
2467ca46
BH		 1819 mutex_unlock(&efx->mac_lock);
1820
8ceee660
BH		 1821 return rc;
1822}
1823
eb9f6744
BH		 1824/* Reset the NIC using the specified method. Note that the reset may
1825 * fail, in which case the card will be left in an unusable state.
8ceee660 1826 *
eb9f6744 1827 * Caller must hold the rtnl_lock.
8ceee660 1828 */
eb9f6744 1829int efx_reset(struct efx_nic *efx, enum reset_type method)
8ceee660 1830{
eb9f6744
BH		 1831 int rc, rc2;
1832 bool disabled;
8ceee660 1833
c459302d 1834 EFX_INFO(efx, "resetting (%s)\n", RESET_TYPE(method));
8ceee660 1835
d3245b28 1836 efx_reset_down(efx, method);
8ceee660 1837
ef2b90ee 1838 rc = efx->type->reset(efx, method);
8ceee660
BH		 1839 if (rc) {
1840 EFX_ERR(efx, "failed to reset hardware\n");
eb9f6744 1841 goto out;
8ceee660
BH		 1842 }
1843
1844 /* Allow resets to be rescheduled. */
1845 efx->reset_pending = RESET_TYPE_NONE;
1846
1847 /* Reinitialise bus-mastering, which may have been turned off before
1848 * the reset was scheduled. This is still appropriate, even in the
1849 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
1850 * can respond to requests. */
1851 pci_set_master(efx->pci_dev);
1852
eb9f6744 1853out:
8ceee660 1854 /* Leave device stopped if necessary */
eb9f6744
BH		 1855 disabled = rc || method == RESET_TYPE_DISABLE;
1856 rc2 = efx_reset_up(efx, method, !disabled);
1857 if (rc2) {
1858 disabled = true;
1859 if (!rc)
1860 rc = rc2;
8ceee660
BH		 1861 }
1862
eb9f6744 1863 if (disabled) {
f49a4589 1864 dev_close(efx->net_dev);
f4bd954e
BH		 1865 EFX_ERR(efx, "has been disabled\n");
1866 efx->state = STATE_DISABLED;
f4bd954e
BH		 1867 } else {
1868 EFX_LOG(efx, "reset complete\n");
1869 }
8ceee660
BH		 1870 return rc;
1871}
1872
1873/* The worker thread exists so that code that cannot sleep can
1874 * schedule a reset for later.
1875 */
1876static void efx_reset_work(struct work_struct *data)
1877{
eb9f6744 1878 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
8ceee660 1879
eb9f6744
BH		 1880 /* If we're not RUNNING then don't reset. Leave the reset_pending
1881 * flag set so that efx_pci_probe_main will be retried */
1882 if (efx->state != STATE_RUNNING) {
1883 EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n");
1884 return;
1885 }
1886
1887 rtnl_lock();
f49a4589 1888 (void)efx_reset(efx, efx->reset_pending);
eb9f6744 1889 rtnl_unlock();
8ceee660
BH		 1890}
1891
1892void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
1893{
1894 enum reset_type method;
1895
1896 if (efx->reset_pending != RESET_TYPE_NONE) {
1897 EFX_INFO(efx, "quenching already scheduled reset\n");
1898 return;
1899 }
1900
1901 switch (type) {
1902 case RESET_TYPE_INVISIBLE:
1903 case RESET_TYPE_ALL:
1904 case RESET_TYPE_WORLD:
1905 case RESET_TYPE_DISABLE:
1906 method = type;
1907 break;
1908 case RESET_TYPE_RX_RECOVERY:
1909 case RESET_TYPE_RX_DESC_FETCH:
1910 case RESET_TYPE_TX_DESC_FETCH:
1911 case RESET_TYPE_TX_SKIP:
1912 method = RESET_TYPE_INVISIBLE;
1913 break;
8880f4ec 1914 case RESET_TYPE_MC_FAILURE:
8ceee660
BH		 1915 default:
1916 method = RESET_TYPE_ALL;
1917 break;
1918 }
1919
1920 if (method != type)
c459302d
BH		 1921 EFX_LOG(efx, "scheduling %s reset for %s\n",
1922 RESET_TYPE(method), RESET_TYPE(type));
8ceee660 1923 else
c459302d 1924 EFX_LOG(efx, "scheduling %s reset\n", RESET_TYPE(method));
8ceee660
BH		 1925
1926 efx->reset_pending = method;
1927
8880f4ec
BH		 1928 /* efx_process_channel() will no longer read events once a
1929 * reset is scheduled. So switch back to poll'd MCDI completions. */
1930 efx_mcdi_mode_poll(efx);
1931
1ab00629 1932 queue_work(reset_workqueue, &efx->reset_work);
8ceee660
BH		 1933}
1934
1935/**************************************************************************
1936 *
1937 * List of NICs we support
1938 *
1939 **************************************************************************/
1940
1941/* PCI device ID table */
a3aa1884 1942static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
8ceee660 1943 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID),
daeda630 1944 .driver_data = (unsigned long) &falcon_a1_nic_type},
8ceee660 1945 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID),
daeda630 1946 .driver_data = (unsigned long) &falcon_b0_nic_type},
8880f4ec
BH		 1947 {PCI_DEVICE(EFX_VENDID_SFC, BETHPAGE_A_P_DEVID),
1948 .driver_data = (unsigned long) &siena_a0_nic_type},
1949 {PCI_DEVICE(EFX_VENDID_SFC, SIENA_A_P_DEVID),
1950 .driver_data = (unsigned long) &siena_a0_nic_type},
8ceee660
BH		 1951 {0} /* end of list */
1952};
1953
1954/**************************************************************************
1955 *
3759433d 1956 * Dummy PHY/MAC operations
8ceee660 1957 *
01aad7b6 1958 * Can be used for some unimplemented operations
8ceee660
BH		 1959 * Needed so all function pointers are valid and do not have to be tested
1960 * before use
1961 *
1962 **************************************************************************/
1963int efx_port_dummy_op_int(struct efx_nic *efx)
1964{
1965 return 0;
1966}
1967void efx_port_dummy_op_void(struct efx_nic *efx) {}
398468ed
BH		 1968void efx_port_dummy_op_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1969{
1970}
fdaa9aed
SH		 1971bool efx_port_dummy_op_poll(struct efx_nic *efx)
1972{
1973 return false;
1974}
8ceee660
BH		 1975
1976static struct efx_phy_operations efx_dummy_phy_operations = {
1977 .init = efx_port_dummy_op_int,
d3245b28 1978 .reconfigure = efx_port_dummy_op_int,
fdaa9aed 1979 .poll = efx_port_dummy_op_poll,
8ceee660 1980 .fini = efx_port_dummy_op_void,
8ceee660
BH		 1981};
1982
8ceee660
BH		 1983/**************************************************************************
1984 *
1985 * Data housekeeping
1986 *
1987 **************************************************************************/
1988
1989/* This zeroes out and then fills in the invariants in a struct
1990 * efx_nic (including all sub-structures).
1991 */
1992static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type,
1993 struct pci_dev *pci_dev, struct net_device *net_dev)
1994{
1995 struct efx_channel *channel;
1996 struct efx_tx_queue *tx_queue;
1997 struct efx_rx_queue *rx_queue;
1ab00629 1998 int i;
8ceee660
BH		 1999
2000 /* Initialise common structures */
2001 memset(efx, 0, sizeof(*efx));
2002 spin_lock_init(&efx->biu_lock);
ab867461 2003 mutex_init(&efx->mdio_lock);
f4150724 2004 mutex_init(&efx->spi_lock);
76884835
BH		 2005#ifdef CONFIG_SFC_MTD
2006 INIT_LIST_HEAD(&efx->mtd_list);
2007#endif
8ceee660
BH		 2008 INIT_WORK(&efx->reset_work, efx_reset_work);
2009 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
2010 efx->pci_dev = pci_dev;
2011 efx->state = STATE_INIT;
2012 efx->reset_pending = RESET_TYPE_NONE;
2013 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
8ceee660
BH		 2014
2015 efx->net_dev = net_dev;
dc8cfa55 2016 efx->rx_checksum_enabled = true;
8ceee660
BH		 2017 spin_lock_init(&efx->netif_stop_lock);
2018 spin_lock_init(&efx->stats_lock);
2019 mutex_init(&efx->mac_lock);
b895d73e 2020 efx->mac_op = type->default_mac_ops;
8ceee660 2021 efx->phy_op = &efx_dummy_phy_operations;
68e7f45e 2022 efx->mdio.dev = net_dev;
766ca0fa 2023 INIT_WORK(&efx->mac_work, efx_mac_work);
8ceee660
BH		 2024 atomic_set(&efx->netif_stop_count, 1);
2025
2026 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
2027 channel = &efx->channel[i];
2028 channel->efx = efx;
2029 channel->channel = i;
dc8cfa55 2030 channel->work_pending = false;
8ceee660 2031 }
60ac1065 2032 for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) {
8ceee660
BH		 2033 tx_queue = &efx->tx_queue[i];
2034 tx_queue->efx = efx;
2035 tx_queue->queue = i;
2036 tx_queue->buffer = NULL;
2037 tx_queue->channel = &efx->channel[0]; /* for safety */
b9b39b62 2038 tx_queue->tso_headers_free = NULL;
8ceee660
BH		 2039 }
2040 for (i = 0; i < EFX_MAX_RX_QUEUES; i++) {
2041 rx_queue = &efx->rx_queue[i];
2042 rx_queue->efx = efx;
2043 rx_queue->queue = i;
2044 rx_queue->channel = &efx->channel[0]; /* for safety */
2045 rx_queue->buffer = NULL;
2046 spin_lock_init(&rx_queue->add_lock);
2047 INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work);
2048 }
2049
2050 efx->type = type;
2051
8ceee660 2052 /* As close as we can get to guaranteeing that we don't overflow */
3ffeabdd
BH		 2053 BUILD_BUG_ON(EFX_EVQ_SIZE < EFX_TXQ_SIZE + EFX_RXQ_SIZE);
2054
8ceee660
BH		 2055 EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS);
2056
2057 /* Higher numbered interrupt modes are less capable! */
2058 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2059 interrupt_mode);
2060
6977dc63
BH		 2061 /* Would be good to use the net_dev name, but we're too early */
2062 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2063 pci_name(pci_dev));
2064 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1ab00629
SH		 2065 if (!efx->workqueue)
2066 return -ENOMEM;
8d9853d9 2067
8ceee660 2068 return 0;
8ceee660
BH		 2069}
2070
2071static void efx_fini_struct(struct efx_nic *efx)
2072{
2073 if (efx->workqueue) {
2074 destroy_workqueue(efx->workqueue);
2075 efx->workqueue = NULL;
2076 }
2077}
2078
2079/**************************************************************************
2080 *
2081 * PCI interface
2082 *
2083 **************************************************************************/
2084
2085/* Main body of final NIC shutdown code
2086 * This is called only at module unload (or hotplug removal).
2087 */
2088static void efx_pci_remove_main(struct efx_nic *efx)
2089{
152b6a62 2090 efx_nic_fini_interrupt(efx);
8ceee660
BH		 2091 efx_fini_channels(efx);
2092 efx_fini_port(efx);
ef2b90ee 2093 efx->type->fini(efx);
8ceee660
BH		 2094 efx_fini_napi(efx);
2095 efx_remove_all(efx);
2096}
2097
2098/* Final NIC shutdown
2099 * This is called only at module unload (or hotplug removal).
2100 */
2101static void efx_pci_remove(struct pci_dev *pci_dev)
2102{
2103 struct efx_nic *efx;
2104
2105 efx = pci_get_drvdata(pci_dev);
2106 if (!efx)
2107 return;
2108
2109 /* Mark the NIC as fini, then stop the interface */
2110 rtnl_lock();
2111 efx->state = STATE_FINI;
2112 dev_close(efx->net_dev);
2113
2114 /* Allow any queued efx_resets() to complete */
2115 rtnl_unlock();
2116
8ceee660
BH		 2117 efx_unregister_netdev(efx);
2118
7dde596e
BH		 2119 efx_mtd_remove(efx);
2120
8ceee660
BH		 2121 /* Wait for any scheduled resets to complete. No more will be
2122 * scheduled from this point because efx_stop_all() has been
2123 * called, we are no longer registered with driverlink, and
2124 * the net_device's have been removed. */
1ab00629 2125 cancel_work_sync(&efx->reset_work);
8ceee660
BH		 2126
2127 efx_pci_remove_main(efx);
2128
8ceee660
BH		 2129 efx_fini_io(efx);
2130 EFX_LOG(efx, "shutdown successful\n");
2131
2132 pci_set_drvdata(pci_dev, NULL);
2133 efx_fini_struct(efx);
2134 free_netdev(efx->net_dev);
2135};
2136
2137/* Main body of NIC initialisation
2138 * This is called at module load (or hotplug insertion, theoretically).
2139 */
2140static int efx_pci_probe_main(struct efx_nic *efx)
2141{
2142 int rc;
2143
2144 /* Do start-of-day initialisation */
2145 rc = efx_probe_all(efx);
2146 if (rc)
2147 goto fail1;
2148
2149 rc = efx_init_napi(efx);
2150 if (rc)
2151 goto fail2;
2152
ef2b90ee 2153 rc = efx->type->init(efx);
8ceee660
BH		 2154 if (rc) {
2155 EFX_ERR(efx, "failed to initialise NIC\n");
278c0621 2156 goto fail3;
8ceee660
BH		 2157 }
2158
2159 rc = efx_init_port(efx);
2160 if (rc) {
2161 EFX_ERR(efx, "failed to initialise port\n");
278c0621 2162 goto fail4;
8ceee660
BH		 2163 }
2164
bc3c90a2 2165 efx_init_channels(efx);
8ceee660 2166
152b6a62 2167 rc = efx_nic_init_interrupt(efx);
8ceee660 2168 if (rc)
278c0621 2169 goto fail5;
8ceee660
BH		 2170
2171 return 0;
2172
278c0621 2173 fail5:
bc3c90a2 2174 efx_fini_channels(efx);
8ceee660 2175 efx_fini_port(efx);
8ceee660 2176 fail4:
ef2b90ee 2177 efx->type->fini(efx);
8ceee660
BH		 2178 fail3:
2179 efx_fini_napi(efx);
2180 fail2:
2181 efx_remove_all(efx);
2182 fail1:
2183 return rc;
2184}
2185
2186/* NIC initialisation
2187 *
2188 * This is called at module load (or hotplug insertion,
2189 * theoretically). It sets up PCI mappings, tests and resets the NIC,
2190 * sets up and registers the network devices with the kernel and hooks
2191 * the interrupt service routine. It does not prepare the device for
2192 * transmission; this is left to the first time one of the network
2193 * interfaces is brought up (i.e. efx_net_open).
2194 */
2195static int __devinit efx_pci_probe(struct pci_dev *pci_dev,
2196 const struct pci_device_id *entry)
2197{
2198 struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data;
2199 struct net_device *net_dev;
2200 struct efx_nic *efx;
2201 int i, rc;
2202
2203 /* Allocate and initialise a struct net_device and struct efx_nic */
2204 net_dev = alloc_etherdev(sizeof(*efx));
2205 if (!net_dev)
2206 return -ENOMEM;
c383b537 2207 net_dev->features |= (type->offload_features | NETIF_F_SG |
97bc5415
BH		 2208 NETIF_F_HIGHDMA | NETIF_F_TSO |
2209 NETIF_F_GRO);
738a8f4b
BH		 2210 if (type->offload_features & NETIF_F_V6_CSUM)
2211 net_dev->features |= NETIF_F_TSO6;
28506563
BH		 2212 /* Mask for features that also apply to VLAN devices */
2213 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
740847da 2214 NETIF_F_HIGHDMA | NETIF_F_TSO);
767e468c 2215 efx = netdev_priv(net_dev);
8ceee660
BH		 2216 pci_set_drvdata(pci_dev, efx);
2217 rc = efx_init_struct(efx, type, pci_dev, net_dev);
2218 if (rc)
2219 goto fail1;
2220
2221 EFX_INFO(efx, "Solarflare Communications NIC detected\n");
2222
2223 /* Set up basic I/O (BAR mappings etc) */
2224 rc = efx_init_io(efx);
2225 if (rc)
2226 goto fail2;
2227
2228 /* No serialisation is required with the reset path because
2229 * we're in STATE_INIT. */
2230 for (i = 0; i < 5; i++) {
2231 rc = efx_pci_probe_main(efx);
8ceee660
BH		 2232
2233 /* Serialise against efx_reset(). No more resets will be
2234 * scheduled since efx_stop_all() has been called, and we
2235 * have not and never have been registered with either
2236 * the rtnetlink or driverlink layers. */
1ab00629 2237 cancel_work_sync(&efx->reset_work);
8ceee660 2238
fa402b2e
SH		 2239 if (rc == 0) {
2240 if (efx->reset_pending != RESET_TYPE_NONE) {
2241 /* If there was a scheduled reset during
2242 * probe, the NIC is probably hosed anyway */
2243 efx_pci_remove_main(efx);
2244 rc = -EIO;
2245 } else {
2246 break;
2247 }
2248 }
2249
8ceee660
BH		 2250 /* Retry if a recoverably reset event has been scheduled */
2251 if ((efx->reset_pending != RESET_TYPE_INVISIBLE) &&
2252 (efx->reset_pending != RESET_TYPE_ALL))
2253 goto fail3;
2254
2255 efx->reset_pending = RESET_TYPE_NONE;
2256 }
2257
2258 if (rc) {
2259 EFX_ERR(efx, "Could not reset NIC\n");
2260 goto fail4;
2261 }
2262
55edc6e6
BH		 2263 /* Switch to the running state before we expose the device to the OS,
2264 * so that dev_open()|efx_start_all() will actually start the device */
8ceee660 2265 efx->state = STATE_RUNNING;
7dde596e 2266
8ceee660
BH		 2267 rc = efx_register_netdev(efx);
2268 if (rc)
2269 goto fail5;
2270
2271 EFX_LOG(efx, "initialisation successful\n");
a5211bb5
BH		 2272
2273 rtnl_lock();
2274 efx_mtd_probe(efx); /* allowed to fail */
2275 rtnl_unlock();
8ceee660
BH		 2276 return 0;
2277
2278 fail5:
2279 efx_pci_remove_main(efx);
2280 fail4:
2281 fail3:
2282 efx_fini_io(efx);
2283 fail2:
2284 efx_fini_struct(efx);
2285 fail1:
5e2a911c 2286 WARN_ON(rc > 0);
8ceee660
BH		 2287 EFX_LOG(efx, "initialisation failed. rc=%d\n", rc);
2288 free_netdev(net_dev);
2289 return rc;
2290}
2291
89c758fa
BH		 2292static int efx_pm_freeze(struct device *dev)
2293{
2294 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2295
2296 efx->state = STATE_FINI;
2297
2298 netif_device_detach(efx->net_dev);
2299
2300 efx_stop_all(efx);
2301 efx_fini_channels(efx);
2302
2303 return 0;
2304}
2305
2306static int efx_pm_thaw(struct device *dev)
2307{
2308 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2309
2310 efx->state = STATE_INIT;
2311
2312 efx_init_channels(efx);
2313
2314 mutex_lock(&efx->mac_lock);
2315 efx->phy_op->reconfigure(efx);
2316 mutex_unlock(&efx->mac_lock);
2317
2318 efx_start_all(efx);
2319
2320 netif_device_attach(efx->net_dev);
2321
2322 efx->state = STATE_RUNNING;
2323
2324 efx->type->resume_wol(efx);
2325
2326 return 0;
2327}
2328
2329static int efx_pm_poweroff(struct device *dev)
2330{
2331 struct pci_dev *pci_dev = to_pci_dev(dev);
2332 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2333
2334 efx->type->fini(efx);
2335
2336 efx->reset_pending = RESET_TYPE_NONE;
2337
2338 pci_save_state(pci_dev);
2339 return pci_set_power_state(pci_dev, PCI_D3hot);
2340}
2341
2342/* Used for both resume and restore */
2343static int efx_pm_resume(struct device *dev)
2344{
2345 struct pci_dev *pci_dev = to_pci_dev(dev);
2346 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2347 int rc;
2348
2349 rc = pci_set_power_state(pci_dev, PCI_D0);
2350 if (rc)
2351 return rc;
2352 pci_restore_state(pci_dev);
2353 rc = pci_enable_device(pci_dev);
2354 if (rc)
2355 return rc;
2356 pci_set_master(efx->pci_dev);
2357 rc = efx->type->reset(efx, RESET_TYPE_ALL);
2358 if (rc)
2359 return rc;
2360 rc = efx->type->init(efx);
2361 if (rc)
2362 return rc;
2363 efx_pm_thaw(dev);
2364 return 0;
2365}
2366
2367static int efx_pm_suspend(struct device *dev)
2368{
2369 int rc;
2370
2371 efx_pm_freeze(dev);
2372 rc = efx_pm_poweroff(dev);
2373 if (rc)
2374 efx_pm_resume(dev);
2375 return rc;
2376}
2377
2378static struct dev_pm_ops efx_pm_ops = {
2379 .suspend = efx_pm_suspend,
2380 .resume = efx_pm_resume,
2381 .freeze = efx_pm_freeze,
2382 .thaw = efx_pm_thaw,
2383 .poweroff = efx_pm_poweroff,
2384 .restore = efx_pm_resume,
2385};
2386
8ceee660
BH		 2387static struct pci_driver efx_pci_driver = {
2388 .name = EFX_DRIVER_NAME,
2389 .id_table = efx_pci_table,
2390 .probe = efx_pci_probe,
2391 .remove = efx_pci_remove,
89c758fa 2392 .driver.pm = &efx_pm_ops,
8ceee660
BH		 2393};
2394
2395/**************************************************************************
2396 *
2397 * Kernel module interface
2398 *
2399 *************************************************************************/
2400
2401module_param(interrupt_mode, uint, 0444);
2402MODULE_PARM_DESC(interrupt_mode,
2403 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
2404
2405static int __init efx_init_module(void)
2406{
2407 int rc;
2408
2409 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
2410
2411 rc = register_netdevice_notifier(&efx_netdev_notifier);
2412 if (rc)
2413 goto err_notifier;
2414
2415 refill_workqueue = create_workqueue("sfc_refill");
2416 if (!refill_workqueue) {
2417 rc = -ENOMEM;
2418 goto err_refill;
2419 }
1ab00629
SH		 2420 reset_workqueue = create_singlethread_workqueue("sfc_reset");
2421 if (!reset_workqueue) {
2422 rc = -ENOMEM;
2423 goto err_reset;
2424 }
8ceee660
BH		 2425
2426 rc = pci_register_driver(&efx_pci_driver);
2427 if (rc < 0)
2428 goto err_pci;
2429
2430 return 0;
2431
2432 err_pci:
1ab00629
SH		 2433 destroy_workqueue(reset_workqueue);
2434 err_reset:
8ceee660
BH		 2435 destroy_workqueue(refill_workqueue);
2436 err_refill:
2437 unregister_netdevice_notifier(&efx_netdev_notifier);
2438 err_notifier:
2439 return rc;
2440}
2441
2442static void __exit efx_exit_module(void)
2443{
2444 printk(KERN_INFO "Solarflare NET driver unloading\n");
2445
2446 pci_unregister_driver(&efx_pci_driver);
1ab00629 2447 destroy_workqueue(reset_workqueue);
8ceee660
BH		 2448 destroy_workqueue(refill_workqueue);
2449 unregister_netdevice_notifier(&efx_netdev_notifier);
2450
2451}
2452
2453module_init(efx_init_module);
2454module_exit(efx_exit_module);
2455
906bb26c
BH		 2456MODULE_AUTHOR("Solarflare Communications and "
2457 "Michael Brown <mbrown@fensystems.co.uk>");
8ceee660
BH		 2458MODULE_DESCRIPTION("Solarflare Communications network driver");
2459MODULE_LICENSE("GPL");
2460MODULE_DEVICE_TABLE(pci, efx_pci_table);
Linux 6.x block layer and io_uring tree(s)