projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'bkl/procfs' of git://git.kernel.org/pub/scm/linux/kernel/git/frederic...
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
10a9948d
LB		 54#include <linux/io.h>
55#include <linux/types.h>
eaf5d590 56#include <linux/inet_lro.h>
5a0e3ad6 57#include <linux/slab.h>
1da177e4 58#include <asm/system.h>
fbd6a754 59
e5371493 60static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 61static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 62
fbd6a754 63
fbd6a754
LB		 64/*
65 * Registers shared between all ports.
66 */
3cb4667c
LB		 67#define PHY_ADDR 0x0000
68#define SMI_REG 0x0004
45c5d3bc
LB		 69#define SMI_BUSY 0x10000000
70#define SMI_READ_VALID 0x08000000
71#define SMI_OPCODE_READ 0x04000000
72#define SMI_OPCODE_WRITE 0x00000000
73#define ERR_INT_CAUSE 0x0080
74#define ERR_INT_SMI_DONE 0x00000010
75#define ERR_INT_MASK 0x0084
3cb4667c
LB		 76#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79#define WINDOW_BAR_ENABLE 0x0290
80#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 81
82/*
37a6084f
LB		 83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 85 */
37a6084f 86#define PORT_CONFIG 0x0000
d9a073ea 87#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 88#define PORT_CONFIG_EXT 0x0004
89#define MAC_ADDR_LOW 0x0014
90#define MAC_ADDR_HIGH 0x0018
91#define SDMA_CONFIG 0x001c
becfad97
LB		 92#define TX_BURST_SIZE_16_64BIT 0x01000000
93#define TX_BURST_SIZE_4_64BIT 0x00800000
94#define BLM_TX_NO_SWAP 0x00000020
95#define BLM_RX_NO_SWAP 0x00000010
96#define RX_BURST_SIZE_16_64BIT 0x00000008
97#define RX_BURST_SIZE_4_64BIT 0x00000004
37a6084f 98#define PORT_SERIAL_CONTROL 0x003c
becfad97
LB		 99#define SET_MII_SPEED_TO_100 0x01000000
100#define SET_GMII_SPEED_TO_1000 0x00800000
101#define SET_FULL_DUPLEX_MODE 0x00200000
102#define MAX_RX_PACKET_9700BYTE 0x000a0000
103#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104#define DO_NOT_FORCE_LINK_FAIL 0x00000400
105#define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108#define FORCE_LINK_PASS 0x00000002
109#define SERIAL_PORT_ENABLE 0x00000001
37a6084f 110#define PORT_STATUS 0x0044
a2a41689 111#define TX_FIFO_EMPTY 0x00000400
ae9ae064 112#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 113#define PORT_SPEED_MASK 0x00000030
114#define PORT_SPEED_1000 0x00000010
115#define PORT_SPEED_100 0x00000020
116#define PORT_SPEED_10 0x00000000
117#define FLOW_CONTROL_ENABLED 0x00000008
118#define FULL_DUPLEX 0x00000004
81600eea 119#define LINK_UP 0x00000002
37a6084f
LB		 120#define TXQ_COMMAND 0x0048
121#define TXQ_FIX_PRIO_CONF 0x004c
122#define TX_BW_RATE 0x0050
123#define TX_BW_MTU 0x0058
124#define TX_BW_BURST 0x005c
125#define INT_CAUSE 0x0060
226bb6b7 126#define INT_TX_END 0x07f80000
e0ca8410 127#define INT_TX_END_0 0x00080000
befefe21 128#define INT_RX 0x000003fc
e0ca8410 129#define INT_RX_0 0x00000004
073a345c 130#define INT_EXT 0x00000002
37a6084f 131#define INT_CAUSE_EXT 0x0064
befefe21
LB		 132#define INT_EXT_LINK_PHY 0x00110000
133#define INT_EXT_TX 0x000000ff
37a6084f
LB		 134#define INT_MASK 0x0068
135#define INT_MASK_EXT 0x006c
136#define TX_FIFO_URGENT_THRESHOLD 0x0074
137#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
138#define TX_BW_RATE_MOVED 0x00e0
139#define TX_BW_MTU_MOVED 0x00e8
140#define TX_BW_BURST_MOVED 0x00ec
141#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
142#define RXQ_COMMAND 0x0280
143#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
144#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
145#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
146#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
147
148/*
149 * Misc per-port registers.
150 */
3cb4667c
LB		 151#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
152#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
153#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
154#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 155
2679a550
LB		 156
157/*
becfad97 158 * SDMA configuration register default value.
2679a550 159 */
fbd6a754
LB		 160#if defined(__BIG_ENDIAN)
161#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 162 (RX_BURST_SIZE_4_64BIT | \
163 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 164#elif defined(__LITTLE_ENDIAN)
165#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 166 (RX_BURST_SIZE_4_64BIT | \
167 BLM_RX_NO_SWAP | \
168 BLM_TX_NO_SWAP | \
169 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 170#else
171#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
172#endif
173
2beff77b
LB		 174
175/*
becfad97 176 * Misc definitions.
2beff77b 177 */
becfad97
LB		 178#define DEFAULT_RX_QUEUE_SIZE 128
179#define DEFAULT_TX_QUEUE_SIZE 256
7fd96ce4 180#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
fbd6a754 181
fbd6a754 182
7ca72a3b
LB		 183/*
184 * RX/TX descriptors.
fbd6a754
LB		 185 */
186#if defined(__BIG_ENDIAN)
cc9754b3 187struct rx_desc {
fbd6a754
LB		 188 u16 byte_cnt; /* Descriptor buffer byte count */
189 u16 buf_size; /* Buffer size */
190 u32 cmd_sts; /* Descriptor command status */
191 u32 next_desc_ptr; /* Next descriptor pointer */
192 u32 buf_ptr; /* Descriptor buffer pointer */
193};
194
cc9754b3 195struct tx_desc {
fbd6a754
LB		 196 u16 byte_cnt; /* buffer byte count */
197 u16 l4i_chk; /* CPU provided TCP checksum */
198 u32 cmd_sts; /* Command/status field */
199 u32 next_desc_ptr; /* Pointer to next descriptor */
200 u32 buf_ptr; /* pointer to buffer for this descriptor*/
201};
202#elif defined(__LITTLE_ENDIAN)
cc9754b3 203struct rx_desc {
fbd6a754
LB		 204 u32 cmd_sts; /* Descriptor command status */
205 u16 buf_size; /* Buffer size */
206 u16 byte_cnt; /* Descriptor buffer byte count */
207 u32 buf_ptr; /* Descriptor buffer pointer */
208 u32 next_desc_ptr; /* Next descriptor pointer */
209};
210
cc9754b3 211struct tx_desc {
fbd6a754
LB		 212 u32 cmd_sts; /* Command/status field */
213 u16 l4i_chk; /* CPU provided TCP checksum */
214 u16 byte_cnt; /* buffer byte count */
215 u32 buf_ptr; /* pointer to buffer for this descriptor*/
216 u32 next_desc_ptr; /* Pointer to next descriptor */
217};
218#else
219#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
220#endif
221
7ca72a3b 222/* RX & TX descriptor command */
cc9754b3 223#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 224
225/* RX & TX descriptor status */
cc9754b3 226#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 227
228/* RX descriptor status */
cc9754b3
LB		 229#define LAYER_4_CHECKSUM_OK 0x40000000
230#define RX_ENABLE_INTERRUPT 0x20000000
231#define RX_FIRST_DESC 0x08000000
232#define RX_LAST_DESC 0x04000000
eaf5d590
LB		 233#define RX_IP_HDR_OK 0x02000000
234#define RX_PKT_IS_IPV4 0x01000000
235#define RX_PKT_IS_ETHERNETV2 0x00800000
236#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
237#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
238#define RX_PKT_IS_VLAN_TAGGED 0x00080000
7ca72a3b
LB		 239
240/* TX descriptor command */
cc9754b3
LB		 241#define TX_ENABLE_INTERRUPT 0x00800000
242#define GEN_CRC 0x00400000
243#define TX_FIRST_DESC 0x00200000
244#define TX_LAST_DESC 0x00100000
245#define ZERO_PADDING 0x00080000
246#define GEN_IP_V4_CHECKSUM 0x00040000
247#define GEN_TCP_UDP_CHECKSUM 0x00020000
248#define UDP_FRAME 0x00010000
e32b6617
LB		 249#define MAC_HDR_EXTRA_4_BYTES 0x00008000
250#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 251
cc9754b3 252#define TX_IHL_SHIFT 11
7ca72a3b
LB		 253
254
c9df406f 255/* global *******************************************************************/
e5371493 256struct mv643xx_eth_shared_private {
fc32b0e2
LB		 257 /*
258 * Ethernet controller base address.
259 */
cc9754b3 260 void __iomem *base;
c9df406f 261
fc0eb9f2
LB		 262 /*
263 * Points at the right SMI instance to use.
264 */
265 struct mv643xx_eth_shared_private *smi;
266
fc32b0e2 267 /*
ed94493f 268 * Provides access to local SMI interface.
fc32b0e2 269 */
298cf9be 270 struct mii_bus *smi_bus;
c9df406f 271
45c5d3bc
LB		 272 /*
273 * If we have access to the error interrupt pin (which is
274 * somewhat misnamed as it not only reflects internal errors
275 * but also reflects SMI completion), use that to wait for
276 * SMI access completion instead of polling the SMI busy bit.
277 */
278 int err_interrupt;
279 wait_queue_head_t smi_busy_wait;
280
fc32b0e2
LB		 281 /*
282 * Per-port MBUS window access register value.
283 */
c9df406f
LB		 284 u32 win_protect;
285
fc32b0e2
LB		 286 /*
287 * Hardware-specific parameters.
288 */
c9df406f 289 unsigned int t_clk;
773fc3ee 290 int extended_rx_coal_limit;
457b1d5a 291 int tx_bw_control;
c9df406f
LB		 292};
293
457b1d5a
LB		 294#define TX_BW_CONTROL_ABSENT 0
295#define TX_BW_CONTROL_OLD_LAYOUT 1
296#define TX_BW_CONTROL_NEW_LAYOUT 2
297
e7d2f4db
LB		 298static int mv643xx_eth_open(struct net_device *dev);
299static int mv643xx_eth_stop(struct net_device *dev);
300
c9df406f
LB		 301
302/* per-port *****************************************************************/
e5371493 303struct mib_counters {
fbd6a754
LB		 304 u64 good_octets_received;
305 u32 bad_octets_received;
306 u32 internal_mac_transmit_err;
307 u32 good_frames_received;
308 u32 bad_frames_received;
309 u32 broadcast_frames_received;
310 u32 multicast_frames_received;
311 u32 frames_64_octets;
312 u32 frames_65_to_127_octets;
313 u32 frames_128_to_255_octets;
314 u32 frames_256_to_511_octets;
315 u32 frames_512_to_1023_octets;
316 u32 frames_1024_to_max_octets;
317 u64 good_octets_sent;
318 u32 good_frames_sent;
319 u32 excessive_collision;
320 u32 multicast_frames_sent;
321 u32 broadcast_frames_sent;
322 u32 unrec_mac_control_received;
323 u32 fc_sent;
324 u32 good_fc_received;
325 u32 bad_fc_received;
326 u32 undersize_received;
327 u32 fragments_received;
328 u32 oversize_received;
329 u32 jabber_received;
330 u32 mac_receive_error;
331 u32 bad_crc_event;
332 u32 collision;
333 u32 late_collision;
334};
335
eaf5d590
LB		 336struct lro_counters {
337 u32 lro_aggregated;
338 u32 lro_flushed;
339 u32 lro_no_desc;
340};
341
8a578111 342struct rx_queue {
64da80a2
LB		 343 int index;
344
8a578111
LB		 345 int rx_ring_size;
346
347 int rx_desc_count;
348 int rx_curr_desc;
349 int rx_used_desc;
350
351 struct rx_desc *rx_desc_area;
352 dma_addr_t rx_desc_dma;
353 int rx_desc_area_size;
354 struct sk_buff **rx_skb;
eaf5d590 355
eaf5d590
LB		 356 struct net_lro_mgr lro_mgr;
357 struct net_lro_desc lro_arr[8];
8a578111
LB		 358};
359
13d64285 360struct tx_queue {
3d6b35bc
LB		 361 int index;
362
13d64285 363 int tx_ring_size;
fbd6a754 364
13d64285
LB		 365 int tx_desc_count;
366 int tx_curr_desc;
367 int tx_used_desc;
fbd6a754 368
5daffe94 369 struct tx_desc *tx_desc_area;
fbd6a754
LB		 370 dma_addr_t tx_desc_dma;
371 int tx_desc_area_size;
99ab08e0
LB		 372
373 struct sk_buff_head tx_skb;
8fd89211
LB		 374
375 unsigned long tx_packets;
376 unsigned long tx_bytes;
377 unsigned long tx_dropped;
13d64285
LB		 378};
379
380struct mv643xx_eth_private {
381 struct mv643xx_eth_shared_private *shared;
37a6084f 382 void __iomem *base;
fc32b0e2 383 int port_num;
13d64285 384
fc32b0e2 385 struct net_device *dev;
fbd6a754 386
ed94493f 387 struct phy_device *phy;
fbd6a754 388
4ff3495a
LB		 389 struct timer_list mib_counters_timer;
390 spinlock_t mib_counters_lock;
fc32b0e2 391 struct mib_counters mib_counters;
4ff3495a 392
eaf5d590
LB		 393 struct lro_counters lro_counters;
394
fc32b0e2 395 struct work_struct tx_timeout_task;
8a578111 396
1fa38c58 397 struct napi_struct napi;
e0ca8410 398 u32 int_mask;
1319ebad 399 u8 oom;
1fa38c58
LB		 400 u8 work_link;
401 u8 work_tx;
402 u8 work_tx_end;
403 u8 work_rx;
404 u8 work_rx_refill;
1fa38c58 405
2bcb4b0f
LB		 406 int skb_size;
407 struct sk_buff_head rx_recycle;
408
8a578111
LB		 409 /*
410 * RX state.
411 */
e7d2f4db 412 int rx_ring_size;
8a578111
LB		 413 unsigned long rx_desc_sram_addr;
414 int rx_desc_sram_size;
f7981c1c 415 int rxq_count;
2257e05c 416 struct timer_list rx_oom;
64da80a2 417 struct rx_queue rxq[8];
13d64285
LB		 418
419 /*
420 * TX state.
421 */
e7d2f4db 422 int tx_ring_size;
13d64285
LB		 423 unsigned long tx_desc_sram_addr;
424 int tx_desc_sram_size;
f7981c1c 425 int txq_count;
3d6b35bc 426 struct tx_queue txq[8];
fbd6a754 427};
1da177e4 428
fbd6a754 429
c9df406f 430/* port register accessors **************************************************/
e5371493 431static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 432{
cc9754b3 433 return readl(mp->shared->base + offset);
c9df406f 434}
fbd6a754 435
37a6084f
LB		 436static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
437{
438 return readl(mp->base + offset);
439}
440
e5371493 441static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 442{
cc9754b3 443 writel(data, mp->shared->base + offset);
c9df406f 444}
fbd6a754 445
37a6084f
LB		 446static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
447{
448 writel(data, mp->base + offset);
449}
450
fbd6a754 451
c9df406f 452/* rxq/txq helper functions *************************************************/
8a578111 453static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 454{
64da80a2 455 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 456}
fbd6a754 457
13d64285
LB		 458static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
459{
3d6b35bc 460 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 461}
462
8a578111 463static void rxq_enable(struct rx_queue *rxq)
c9df406f 464{
8a578111 465 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 466 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 467}
1da177e4 468
8a578111
LB		 469static void rxq_disable(struct rx_queue *rxq)
470{
471 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 472 u8 mask = 1 << rxq->index;
1da177e4 473
37a6084f
LB		 474 wrlp(mp, RXQ_COMMAND, mask << 8);
475 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 476 udelay(10);
c9df406f
LB		 477}
478
6b368f68
LB		 479static void txq_reset_hw_ptr(struct tx_queue *txq)
480{
481 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 482 u32 addr;
483
484 addr = (u32)txq->tx_desc_dma;
485 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 486 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 487}
488
13d64285 489static void txq_enable(struct tx_queue *txq)
1da177e4 490{
13d64285 491 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 492 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 493}
494
13d64285 495static void txq_disable(struct tx_queue *txq)
1da177e4 496{
13d64285 497 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 498 u8 mask = 1 << txq->index;
c9df406f 499
37a6084f
LB		 500 wrlp(mp, TXQ_COMMAND, mask << 8);
501 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 502 udelay(10);
503}
504
1fa38c58 505static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 506{
507 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 508 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 509
8fd89211
LB		 510 if (netif_tx_queue_stopped(nq)) {
511 __netif_tx_lock(nq, smp_processor_id());
512 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
513 netif_tx_wake_queue(nq);
514 __netif_tx_unlock(nq);
515 }
1da177e4
LT		 516}
517
c9df406f 518
1fa38c58 519/* rx napi ******************************************************************/
eaf5d590
LB		 520static int
521mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
522 u64 *hdr_flags, void *priv)
523{
524 unsigned long cmd_sts = (unsigned long)priv;
525
526 /*
527 * Make sure that this packet is Ethernet II, is not VLAN
528 * tagged, is IPv4, has a valid IP header, and is TCP.
529 */
530 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
531 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
532 RX_PKT_IS_VLAN_TAGGED)) !=
533 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
534 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
535 return -1;
536
537 skb_reset_network_header(skb);
538 skb_set_transport_header(skb, ip_hdrlen(skb));
539 *iphdr = ip_hdr(skb);
540 *tcph = tcp_hdr(skb);
541 *hdr_flags = LRO_IPV4 | LRO_TCP;
542
543 return 0;
544}
eaf5d590 545
8a578111 546static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 547{
8a578111
LB		 548 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
549 struct net_device_stats *stats = &mp->dev->stats;
eaf5d590 550 int lro_flush_needed;
8a578111 551 int rx;
1da177e4 552
eaf5d590 553 lro_flush_needed = 0;
8a578111 554 rx = 0;
9e1f3772 555 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 556 struct rx_desc *rx_desc;
96587661 557 unsigned int cmd_sts;
fc32b0e2 558 struct sk_buff *skb;
6b8f90c2 559 u16 byte_cnt;
ff561eef 560
8a578111 561 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 562
96587661 563 cmd_sts = rx_desc->cmd_sts;
2257e05c 564 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 565 break;
96587661 566 rmb();
1da177e4 567
8a578111
LB		 568 skb = rxq->rx_skb[rxq->rx_curr_desc];
569 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 570
9da78745
LB		 571 rxq->rx_curr_desc++;
572 if (rxq->rx_curr_desc == rxq->rx_ring_size)
573 rxq->rx_curr_desc = 0;
ff561eef 574
eb0519b5 575 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
abe78717 576 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 577 rxq->rx_desc_count--;
578 rx++;
b1dd9ca1 579
1fa38c58
LB		 580 mp->work_rx_refill |= 1 << rxq->index;
581
6b8f90c2
LB		 582 byte_cnt = rx_desc->byte_cnt;
583
468d09f8
DF		 584 /*
585 * Update statistics.
fc32b0e2
LB		 586 *
587 * Note that the descriptor byte count includes 2 dummy
588 * bytes automatically inserted by the hardware at the
589 * start of the packet (which we don't count), and a 4
590 * byte CRC at the end of the packet (which we do count).
468d09f8 591 */
1da177e4 592 stats->rx_packets++;
6b8f90c2 593 stats->rx_bytes += byte_cnt - 2;
96587661 594
1da177e4 595 /*
fc32b0e2
LB		 596 * In case we received a packet without first / last bits
597 * on, or the error summary bit is set, the packet needs
598 * to be dropped.
1da177e4 599 */
f61e5547
LB		 600 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
601 != (RX_FIRST_DESC | RX_LAST_DESC))
602 goto err;
603
604 /*
605 * The -4 is for the CRC in the trailer of the
606 * received packet
607 */
608 skb_put(skb, byte_cnt - 2 - 4);
609
610 if (cmd_sts & LAYER_4_CHECKSUM_OK)
611 skb->ip_summed = CHECKSUM_UNNECESSARY;
612 skb->protocol = eth_type_trans(skb, mp->dev);
eaf5d590 613
eaf5d590
LB		 614 if (skb->dev->features & NETIF_F_LRO &&
615 skb->ip_summed == CHECKSUM_UNNECESSARY) {
616 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
617 lro_flush_needed = 1;
618 } else
eaf5d590 619 netif_receive_skb(skb);
f61e5547
LB		 620
621 continue;
622
623err:
624 stats->rx_dropped++;
625
626 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
627 (RX_FIRST_DESC | RX_LAST_DESC)) {
628 if (net_ratelimit())
629 dev_printk(KERN_ERR, &mp->dev->dev,
630 "received packet spanning "
631 "multiple descriptors\n");
1da177e4 632 }
f61e5547
LB		 633
634 if (cmd_sts & ERROR_SUMMARY)
635 stats->rx_errors++;
636
637 dev_kfree_skb(skb);
1da177e4 638 }
fc32b0e2 639
eaf5d590
LB		 640 if (lro_flush_needed)
641 lro_flush_all(&rxq->lro_mgr);
eaf5d590 642
1fa38c58
LB		 643 if (rx < budget)
644 mp->work_rx &= ~(1 << rxq->index);
645
8a578111 646 return rx;
1da177e4
LT		 647}
648
1fa38c58 649static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 650{
1fa38c58 651 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 652 int refilled;
8a578111 653
1fa38c58
LB		 654 refilled = 0;
655 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
656 struct sk_buff *skb;
1fa38c58 657 int rx;
53771522 658 struct rx_desc *rx_desc;
530e557a 659 int size;
d0412d96 660
2bcb4b0f
LB		 661 skb = __skb_dequeue(&mp->rx_recycle);
662 if (skb == NULL)
7fd96ce4 663 skb = dev_alloc_skb(mp->skb_size);
2bcb4b0f 664
1fa38c58 665 if (skb == NULL) {
1319ebad 666 mp->oom = 1;
1fa38c58
LB		 667 goto oom;
668 }
d0412d96 669
7fd96ce4
LB		 670 if (SKB_DMA_REALIGN)
671 skb_reserve(skb, SKB_DMA_REALIGN);
2257e05c 672
1fa38c58
LB		 673 refilled++;
674 rxq->rx_desc_count++;
c9df406f 675
1fa38c58
LB		 676 rx = rxq->rx_used_desc++;
677 if (rxq->rx_used_desc == rxq->rx_ring_size)
678 rxq->rx_used_desc = 0;
2257e05c 679
53771522
LB		 680 rx_desc = rxq->rx_desc_area + rx;
681
530e557a 682 size = skb->end - skb->data;
eb0519b5 683 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
530e557a 684 skb->data, size,
eb0519b5 685 DMA_FROM_DEVICE);
530e557a 686 rx_desc->buf_size = size;
1fa38c58
LB		 687 rxq->rx_skb[rx] = skb;
688 wmb();
53771522 689 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 690 wmb();
2257e05c 691
1fa38c58
LB		 692 /*
693 * The hardware automatically prepends 2 bytes of
694 * dummy data to each received packet, so that the
695 * IP header ends up 16-byte aligned.
696 */
697 skb_reserve(skb, 2);
698 }
699
700 if (refilled < budget)
701 mp->work_rx_refill &= ~(1 << rxq->index);
702
703oom:
704 return refilled;
d0412d96
JC		 705}
706
c9df406f
LB		 707
708/* tx ***********************************************************************/
c9df406f 709static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 710{
13d64285 711 int frag;
1da177e4 712
c9df406f 713 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 714 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
715 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 716 return 1;
1da177e4 717 }
13d64285 718
c9df406f
LB		 719 return 0;
720}
7303fde8 721
13d64285 722static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 723{
eb0519b5 724 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 725 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 726 int frag;
1da177e4 727
13d64285
LB		 728 for (frag = 0; frag < nr_frags; frag++) {
729 skb_frag_t *this_frag;
730 int tx_index;
731 struct tx_desc *desc;
732
733 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 734 tx_index = txq->tx_curr_desc++;
735 if (txq->tx_curr_desc == txq->tx_ring_size)
736 txq->tx_curr_desc = 0;
13d64285
LB		 737 desc = &txq->tx_desc_area[tx_index];
738
739 /*
740 * The last fragment will generate an interrupt
741 * which will free the skb on TX completion.
742 */
743 if (frag == nr_frags - 1) {
744 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
745 ZERO_PADDING | TX_LAST_DESC |
746 TX_ENABLE_INTERRUPT;
13d64285
LB		 747 } else {
748 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 749 }
750
c9df406f
LB		 751 desc->l4i_chk = 0;
752 desc->byte_cnt = this_frag->size;
eb0519b5
GP		 753 desc->buf_ptr = dma_map_page(mp->dev->dev.parent,
754 this_frag->page,
755 this_frag->page_offset,
756 this_frag->size, DMA_TO_DEVICE);
c9df406f 757 }
1da177e4
LT		 758}
759
c9df406f
LB		 760static inline __be16 sum16_as_be(__sum16 sum)
761{
762 return (__force __be16)sum;
763}
1da177e4 764
4df89bd5 765static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 766{
8fa89bf5 767 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 768 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 769 int tx_index;
cc9754b3 770 struct tx_desc *desc;
c9df406f 771 u32 cmd_sts;
4df89bd5 772 u16 l4i_chk;
c9df406f 773 int length;
1da177e4 774
cc9754b3 775 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 776 l4i_chk = 0;
c9df406f
LB		 777
778 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 779 int tag_bytes;
e32b6617
LB		 780
781 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
782 skb->protocol != htons(ETH_P_8021Q));
c9df406f 783
4df89bd5
LB		 784 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
785 if (unlikely(tag_bytes & ~12)) {
786 if (skb_checksum_help(skb) == 0)
787 goto no_csum;
788 kfree_skb(skb);
789 return 1;
790 }
c9df406f 791
4df89bd5 792 if (tag_bytes & 4)
e32b6617 793 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 794 if (tag_bytes & 8)
e32b6617 795 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 796
797 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
798 GEN_IP_V4_CHECKSUM |
799 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 800
c9df406f
LB		 801 switch (ip_hdr(skb)->protocol) {
802 case IPPROTO_UDP:
cc9754b3 803 cmd_sts |= UDP_FRAME;
4df89bd5 804 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 805 break;
806 case IPPROTO_TCP:
4df89bd5 807 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 808 break;
809 default:
810 BUG();
811 }
812 } else {
4df89bd5 813no_csum:
c9df406f 814 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 815 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 816 }
817
66823b92
LB		 818 tx_index = txq->tx_curr_desc++;
819 if (txq->tx_curr_desc == txq->tx_ring_size)
820 txq->tx_curr_desc = 0;
4df89bd5
LB		 821 desc = &txq->tx_desc_area[tx_index];
822
823 if (nr_frags) {
824 txq_submit_frag_skb(txq, skb);
825 length = skb_headlen(skb);
826 } else {
827 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
828 length = skb->len;
829 }
830
831 desc->l4i_chk = l4i_chk;
832 desc->byte_cnt = length;
eb0519b5
GP		 833 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
834 length, DMA_TO_DEVICE);
4df89bd5 835
99ab08e0
LB		 836 __skb_queue_tail(&txq->tx_skb, skb);
837
c9df406f
LB		 838 /* ensure all other descriptors are written before first cmd_sts */
839 wmb();
840 desc->cmd_sts = cmd_sts;
841
1fa38c58
LB		 842 /* clear TX_END status */
843 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 844
c9df406f
LB		 845 /* ensure all descriptors are written before poking hardware */
846 wmb();
13d64285 847 txq_enable(txq);
c9df406f 848
13d64285 849 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 850
851 return 0;
1da177e4 852}
1da177e4 853
0ccfe64d 854static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 855{
e5371493 856 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 857 int queue;
13d64285 858 struct tx_queue *txq;
e5ef1de1 859 struct netdev_queue *nq;
afdb57a2 860
8fd89211
LB		 861 queue = skb_get_queue_mapping(skb);
862 txq = mp->txq + queue;
863 nq = netdev_get_tx_queue(dev, queue);
864
c9df406f 865 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 866 txq->tx_dropped++;
fc32b0e2
LB		 867 dev_printk(KERN_DEBUG, &dev->dev,
868 "failed to linearize skb with tiny "
869 "unaligned fragment\n");
c9df406f
LB		 870 return NETDEV_TX_BUSY;
871 }
872
17cd0a59 873 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 874 if (net_ratelimit())
875 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 876 kfree_skb(skb);
877 return NETDEV_TX_OK;
c9df406f
LB		 878 }
879
4df89bd5
LB		 880 if (!txq_submit_skb(txq, skb)) {
881 int entries_left;
882
883 txq->tx_bytes += skb->len;
884 txq->tx_packets++;
885 dev->trans_start = jiffies;
c9df406f 886
4df89bd5
LB		 887 entries_left = txq->tx_ring_size - txq->tx_desc_count;
888 if (entries_left < MAX_SKB_FRAGS + 1)
889 netif_tx_stop_queue(nq);
890 }
c9df406f 891
c9df406f 892 return NETDEV_TX_OK;
1da177e4
LT		 893}
894
c9df406f 895
1fa38c58
LB		 896/* tx napi ******************************************************************/
897static void txq_kick(struct tx_queue *txq)
898{
899 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 900 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 901 u32 hw_desc_ptr;
902 u32 expected_ptr;
903
8fd89211 904 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 905
37a6084f 906 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 907 goto out;
908
37a6084f 909 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 910 expected_ptr = (u32)txq->tx_desc_dma +
911 txq->tx_curr_desc * sizeof(struct tx_desc);
912
913 if (hw_desc_ptr != expected_ptr)
914 txq_enable(txq);
915
916out:
8fd89211 917 __netif_tx_unlock(nq);
1fa38c58
LB		 918
919 mp->work_tx_end &= ~(1 << txq->index);
920}
921
922static int txq_reclaim(struct tx_queue *txq, int budget, int force)
923{
924 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 925 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 926 int reclaimed;
927
8fd89211 928 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 929
930 reclaimed = 0;
931 while (reclaimed < budget && txq->tx_desc_count > 0) {
932 int tx_index;
933 struct tx_desc *desc;
934 u32 cmd_sts;
935 struct sk_buff *skb;
1fa38c58
LB		 936
937 tx_index = txq->tx_used_desc;
938 desc = &txq->tx_desc_area[tx_index];
939 cmd_sts = desc->cmd_sts;
940
941 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
942 if (!force)
943 break;
944 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
945 }
946
947 txq->tx_used_desc = tx_index + 1;
948 if (txq->tx_used_desc == txq->tx_ring_size)
949 txq->tx_used_desc = 0;
950
951 reclaimed++;
952 txq->tx_desc_count--;
953
99ab08e0
LB		 954 skb = NULL;
955 if (cmd_sts & TX_LAST_DESC)
956 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 957
958 if (cmd_sts & ERROR_SUMMARY) {
959 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
960 mp->dev->stats.tx_errors++;
961 }
962
a418950c 963 if (cmd_sts & TX_FIRST_DESC) {
eb0519b5 964 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 965 desc->byte_cnt, DMA_TO_DEVICE);
966 } else {
eb0519b5 967 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 968 desc->byte_cnt, DMA_TO_DEVICE);
969 }
1fa38c58 970
2bcb4b0f
LB		 971 if (skb != NULL) {
972 if (skb_queue_len(&mp->rx_recycle) <
e7d2f4db 973 mp->rx_ring_size &&
7fd96ce4 974 skb_recycle_check(skb, mp->skb_size))
2bcb4b0f
LB		 975 __skb_queue_head(&mp->rx_recycle, skb);
976 else
977 dev_kfree_skb(skb);
978 }
1fa38c58
LB		 979 }
980
8fd89211
LB		 981 __netif_tx_unlock(nq);
982
1fa38c58
LB		 983 if (reclaimed < budget)
984 mp->work_tx &= ~(1 << txq->index);
985
1fa38c58
LB		 986 return reclaimed;
987}
988
989
89df5fdc
LB		 990/* tx rate control **********************************************************/
991/*
992 * Set total maximum TX rate (shared by all TX queues for this port)
993 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
994 */
995static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
996{
997 int token_rate;
998 int mtu;
999 int bucket_size;
1000
1001 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1002 if (token_rate > 1023)
1003 token_rate = 1023;
1004
1005 mtu = (mp->dev->mtu + 255) >> 8;
1006 if (mtu > 63)
1007 mtu = 63;
1008
1009 bucket_size = (burst + 255) >> 8;
1010 if (bucket_size > 65535)
1011 bucket_size = 65535;
1012
457b1d5a
LB		 1013 switch (mp->shared->tx_bw_control) {
1014 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 1015 wrlp(mp, TX_BW_RATE, token_rate);
1016 wrlp(mp, TX_BW_MTU, mtu);
1017 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 1018 break;
1019 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 1020 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1021 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1022 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 1023 break;
1e881592 1024 }
89df5fdc
LB		 1025}
1026
1027static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1028{
1029 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1030 int token_rate;
1031 int bucket_size;
1032
1033 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1034 if (token_rate > 1023)
1035 token_rate = 1023;
1036
1037 bucket_size = (burst + 255) >> 8;
1038 if (bucket_size > 65535)
1039 bucket_size = 65535;
1040
37a6084f
LB		 1041 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1042 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 1043}
1044
1045static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1046{
1047 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1048 int off;
1049 u32 val;
1050
1051 /*
1052 * Turn on fixed priority mode.
1053 */
457b1d5a
LB		 1054 off = 0;
1055 switch (mp->shared->tx_bw_control) {
1056 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1057 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1058 break;
1059 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1060 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1061 break;
1062 }
89df5fdc 1063
457b1d5a 1064 if (off) {
37a6084f 1065 val = rdlp(mp, off);
457b1d5a 1066 val |= 1 << txq->index;
37a6084f 1067 wrlp(mp, off, val);
457b1d5a 1068 }
89df5fdc
LB		 1069}
1070
89df5fdc 1071
c9df406f 1072/* mii management interface *************************************************/
45c5d3bc
LB		 1073static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1074{
1075 struct mv643xx_eth_shared_private *msp = dev_id;
1076
1077 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1078 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1079 wake_up(&msp->smi_busy_wait);
1080 return IRQ_HANDLED;
1081 }
1082
1083 return IRQ_NONE;
1084}
c9df406f 1085
45c5d3bc 1086static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1087{
45c5d3bc
LB		 1088 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1089}
1da177e4 1090
45c5d3bc
LB		 1091static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1092{
1093 if (msp->err_interrupt == NO_IRQ) {
1094 int i;
c9df406f 1095
45c5d3bc
LB		 1096 for (i = 0; !smi_is_done(msp); i++) {
1097 if (i == 10)
1098 return -ETIMEDOUT;
1099 msleep(10);
c9df406f 1100 }
45c5d3bc
LB		 1101
1102 return 0;
1103 }
1104
ee04448d
LB		 1105 if (!smi_is_done(msp)) {
1106 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1107 msecs_to_jiffies(100));
1108 if (!smi_is_done(msp))
1109 return -ETIMEDOUT;
1110 }
45c5d3bc
LB		 1111
1112 return 0;
1113}
1114
ed94493f 1115static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1116{
ed94493f 1117 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1118 void __iomem *smi_reg = msp->base + SMI_REG;
1119 int ret;
1120
45c5d3bc 1121 if (smi_wait_ready(msp)) {
10a9948d 1122 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1123 return -ETIMEDOUT;
1da177e4
LT		 1124 }
1125
fc32b0e2 1126 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1127
45c5d3bc 1128 if (smi_wait_ready(msp)) {
10a9948d 1129 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1130 return -ETIMEDOUT;
45c5d3bc
LB		 1131 }
1132
1133 ret = readl(smi_reg);
1134 if (!(ret & SMI_READ_VALID)) {
10a9948d 1135 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
ed94493f 1136 return -ENODEV;
c9df406f
LB		 1137 }
1138
ed94493f 1139 return ret & 0xffff;
1da177e4
LT		 1140}
1141
ed94493f 1142static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1143{
ed94493f 1144 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1145 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1146
45c5d3bc 1147 if (smi_wait_ready(msp)) {
10a9948d 1148 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1149 return -ETIMEDOUT;
1da177e4
LT		 1150 }
1151
fc32b0e2 1152 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1153 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1154
ed94493f 1155 if (smi_wait_ready(msp)) {
10a9948d 1156 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f
LB		 1157 return -ETIMEDOUT;
1158 }
45c5d3bc
LB		 1159
1160 return 0;
c9df406f 1161}
1da177e4 1162
c9df406f 1163
8fd89211
LB		 1164/* statistics ***************************************************************/
1165static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1166{
1167 struct mv643xx_eth_private *mp = netdev_priv(dev);
1168 struct net_device_stats *stats = &dev->stats;
1169 unsigned long tx_packets = 0;
1170 unsigned long tx_bytes = 0;
1171 unsigned long tx_dropped = 0;
1172 int i;
1173
1174 for (i = 0; i < mp->txq_count; i++) {
1175 struct tx_queue *txq = mp->txq + i;
1176
1177 tx_packets += txq->tx_packets;
1178 tx_bytes += txq->tx_bytes;
1179 tx_dropped += txq->tx_dropped;
1180 }
1181
1182 stats->tx_packets = tx_packets;
1183 stats->tx_bytes = tx_bytes;
1184 stats->tx_dropped = tx_dropped;
1185
1186 return stats;
1187}
1188
eaf5d590
LB		 1189static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1190{
1191 u32 lro_aggregated = 0;
1192 u32 lro_flushed = 0;
1193 u32 lro_no_desc = 0;
1194 int i;
1195
eaf5d590
LB		 1196 for (i = 0; i < mp->rxq_count; i++) {
1197 struct rx_queue *rxq = mp->rxq + i;
1198
1199 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1200 lro_flushed += rxq->lro_mgr.stats.flushed;
1201 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1202 }
eaf5d590
LB		 1203
1204 mp->lro_counters.lro_aggregated = lro_aggregated;
1205 mp->lro_counters.lro_flushed = lro_flushed;
1206 mp->lro_counters.lro_no_desc = lro_no_desc;
1207}
1208
fc32b0e2 1209static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1210{
fc32b0e2 1211 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1212}
1213
fc32b0e2 1214static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1215{
fc32b0e2
LB		 1216 int i;
1217
1218 for (i = 0; i < 0x80; i += 4)
1219 mib_read(mp, i);
c9df406f 1220}
d0412d96 1221
fc32b0e2 1222static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1223{
e5371493 1224 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1225
57e8f26a 1226 spin_lock_bh(&mp->mib_counters_lock);
fc32b0e2 1227 p->good_octets_received += mib_read(mp, 0x00);
fc32b0e2
LB		 1228 p->bad_octets_received += mib_read(mp, 0x08);
1229 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1230 p->good_frames_received += mib_read(mp, 0x10);
1231 p->bad_frames_received += mib_read(mp, 0x14);
1232 p->broadcast_frames_received += mib_read(mp, 0x18);
1233 p->multicast_frames_received += mib_read(mp, 0x1c);
1234 p->frames_64_octets += mib_read(mp, 0x20);
1235 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1236 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1237 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1238 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1239 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1240 p->good_octets_sent += mib_read(mp, 0x38);
fc32b0e2
LB		 1241 p->good_frames_sent += mib_read(mp, 0x40);
1242 p->excessive_collision += mib_read(mp, 0x44);
1243 p->multicast_frames_sent += mib_read(mp, 0x48);
1244 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1245 p->unrec_mac_control_received += mib_read(mp, 0x50);
1246 p->fc_sent += mib_read(mp, 0x54);
1247 p->good_fc_received += mib_read(mp, 0x58);
1248 p->bad_fc_received += mib_read(mp, 0x5c);
1249 p->undersize_received += mib_read(mp, 0x60);
1250 p->fragments_received += mib_read(mp, 0x64);
1251 p->oversize_received += mib_read(mp, 0x68);
1252 p->jabber_received += mib_read(mp, 0x6c);
1253 p->mac_receive_error += mib_read(mp, 0x70);
1254 p->bad_crc_event += mib_read(mp, 0x74);
1255 p->collision += mib_read(mp, 0x78);
1256 p->late_collision += mib_read(mp, 0x7c);
57e8f26a 1257 spin_unlock_bh(&mp->mib_counters_lock);
4ff3495a
LB		 1258
1259 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1260}
1261
1262static void mib_counters_timer_wrapper(unsigned long _mp)
1263{
1264 struct mv643xx_eth_private *mp = (void *)_mp;
1265
1266 mib_counters_update(mp);
d0412d96
JC		 1267}
1268
c9df406f 1269
3e508034
LB		 1270/* interrupt coalescing *****************************************************/
1271/*
1272 * Hardware coalescing parameters are set in units of 64 t_clk
1273 * cycles. I.e.:
1274 *
1275 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1276 *
1277 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1278 *
1279 * In the ->set*() methods, we round the computed register value
1280 * to the nearest integer.
1281 */
1282static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1283{
1284 u32 val = rdlp(mp, SDMA_CONFIG);
1285 u64 temp;
1286
1287 if (mp->shared->extended_rx_coal_limit)
1288 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1289 else
1290 temp = (val & 0x003fff00) >> 8;
1291
1292 temp *= 64000000;
1293 do_div(temp, mp->shared->t_clk);
1294
1295 return (unsigned int)temp;
1296}
1297
1298static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1299{
1300 u64 temp;
1301 u32 val;
1302
1303 temp = (u64)usec * mp->shared->t_clk;
1304 temp += 31999999;
1305 do_div(temp, 64000000);
1306
1307 val = rdlp(mp, SDMA_CONFIG);
1308 if (mp->shared->extended_rx_coal_limit) {
1309 if (temp > 0xffff)
1310 temp = 0xffff;
1311 val &= ~0x023fff80;
1312 val |= (temp & 0x8000) << 10;
1313 val |= (temp & 0x7fff) << 7;
1314 } else {
1315 if (temp > 0x3fff)
1316 temp = 0x3fff;
1317 val &= ~0x003fff00;
1318 val |= (temp & 0x3fff) << 8;
1319 }
1320 wrlp(mp, SDMA_CONFIG, val);
1321}
1322
1323static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1324{
1325 u64 temp;
1326
1327 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1328 temp *= 64000000;
1329 do_div(temp, mp->shared->t_clk);
1330
1331 return (unsigned int)temp;
1332}
1333
1334static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1335{
1336 u64 temp;
1337
1338 temp = (u64)usec * mp->shared->t_clk;
1339 temp += 31999999;
1340 do_div(temp, 64000000);
1341
1342 if (temp > 0x3fff)
1343 temp = 0x3fff;
1344
1345 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1346}
1347
1348
c9df406f 1349/* ethtool ******************************************************************/
e5371493 1350struct mv643xx_eth_stats {
c9df406f
LB		 1351 char stat_string[ETH_GSTRING_LEN];
1352 int sizeof_stat;
16820054
LB		 1353 int netdev_off;
1354 int mp_off;
c9df406f
LB		 1355};
1356
16820054
LB		 1357#define SSTAT(m) \
1358 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1359 offsetof(struct net_device, stats.m), -1 }
1360
1361#define MIBSTAT(m) \
1362 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1363 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1364
eaf5d590
LB		 1365#define LROSTAT(m) \
1366 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1367 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1368
16820054
LB		 1369static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1370 SSTAT(rx_packets),
1371 SSTAT(tx_packets),
1372 SSTAT(rx_bytes),
1373 SSTAT(tx_bytes),
1374 SSTAT(rx_errors),
1375 SSTAT(tx_errors),
1376 SSTAT(rx_dropped),
1377 SSTAT(tx_dropped),
1378 MIBSTAT(good_octets_received),
1379 MIBSTAT(bad_octets_received),
1380 MIBSTAT(internal_mac_transmit_err),
1381 MIBSTAT(good_frames_received),
1382 MIBSTAT(bad_frames_received),
1383 MIBSTAT(broadcast_frames_received),
1384 MIBSTAT(multicast_frames_received),
1385 MIBSTAT(frames_64_octets),
1386 MIBSTAT(frames_65_to_127_octets),
1387 MIBSTAT(frames_128_to_255_octets),
1388 MIBSTAT(frames_256_to_511_octets),
1389 MIBSTAT(frames_512_to_1023_octets),
1390 MIBSTAT(frames_1024_to_max_octets),
1391 MIBSTAT(good_octets_sent),
1392 MIBSTAT(good_frames_sent),
1393 MIBSTAT(excessive_collision),
1394 MIBSTAT(multicast_frames_sent),
1395 MIBSTAT(broadcast_frames_sent),
1396 MIBSTAT(unrec_mac_control_received),
1397 MIBSTAT(fc_sent),
1398 MIBSTAT(good_fc_received),
1399 MIBSTAT(bad_fc_received),
1400 MIBSTAT(undersize_received),
1401 MIBSTAT(fragments_received),
1402 MIBSTAT(oversize_received),
1403 MIBSTAT(jabber_received),
1404 MIBSTAT(mac_receive_error),
1405 MIBSTAT(bad_crc_event),
1406 MIBSTAT(collision),
1407 MIBSTAT(late_collision),
eaf5d590
LB		 1408 LROSTAT(lro_aggregated),
1409 LROSTAT(lro_flushed),
1410 LROSTAT(lro_no_desc),
c9df406f
LB		 1411};
1412
10a9948d 1413static int
6bdf576e
LB		 1414mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1415 struct ethtool_cmd *cmd)
d0412d96 1416{
d0412d96
JC		 1417 int err;
1418
ed94493f
LB		 1419 err = phy_read_status(mp->phy);
1420 if (err == 0)
1421 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1422
fc32b0e2
LB		 1423 /*
1424 * The MAC does not support 1000baseT_Half.
1425 */
d0412d96
JC		 1426 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1427 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1428
1429 return err;
1430}
1431
10a9948d 1432static int
6bdf576e 1433mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
10a9948d 1434 struct ethtool_cmd *cmd)
bedfe324 1435{
81600eea
LB		 1436 u32 port_status;
1437
37a6084f 1438 port_status = rdlp(mp, PORT_STATUS);
81600eea 1439
bedfe324
LB		 1440 cmd->supported = SUPPORTED_MII;
1441 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1442 switch (port_status & PORT_SPEED_MASK) {
1443 case PORT_SPEED_10:
1444 cmd->speed = SPEED_10;
1445 break;
1446 case PORT_SPEED_100:
1447 cmd->speed = SPEED_100;
1448 break;
1449 case PORT_SPEED_1000:
1450 cmd->speed = SPEED_1000;
1451 break;
1452 default:
1453 cmd->speed = -1;
1454 break;
1455 }
1456 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1457 cmd->port = PORT_MII;
1458 cmd->phy_address = 0;
1459 cmd->transceiver = XCVR_INTERNAL;
1460 cmd->autoneg = AUTONEG_DISABLE;
1461 cmd->maxtxpkt = 1;
1462 cmd->maxrxpkt = 1;
1463
1464 return 0;
1465}
1466
6bdf576e
LB		 1467static int
1468mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1469{
1470 struct mv643xx_eth_private *mp = netdev_priv(dev);
1471
1472 if (mp->phy != NULL)
1473 return mv643xx_eth_get_settings_phy(mp, cmd);
1474 else
1475 return mv643xx_eth_get_settings_phyless(mp, cmd);
1476}
1477
10a9948d
LB		 1478static int
1479mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1480{
e5371493 1481 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1482
6bdf576e
LB		 1483 if (mp->phy == NULL)
1484 return -EINVAL;
1485
fc32b0e2
LB		 1486 /*
1487 * The MAC does not support 1000baseT_Half.
1488 */
1489 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1490
ed94493f 1491 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1492}
1da177e4 1493
fc32b0e2
LB		 1494static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1495 struct ethtool_drvinfo *drvinfo)
c9df406f 1496{
e5371493
LB		 1497 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1498 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1499 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1500 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1501 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1502}
1da177e4 1503
fc32b0e2 1504static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1505{
e5371493 1506 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1507
6bdf576e
LB		 1508 if (mp->phy == NULL)
1509 return -EINVAL;
1da177e4 1510
6bdf576e 1511 return genphy_restart_aneg(mp->phy);
bedfe324
LB		 1512}
1513
c9df406f
LB		 1514static u32 mv643xx_eth_get_link(struct net_device *dev)
1515{
ed94493f 1516 return !!netif_carrier_ok(dev);
bedfe324
LB		 1517}
1518
3e508034
LB		 1519static int
1520mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1521{
1522 struct mv643xx_eth_private *mp = netdev_priv(dev);
1523
1524 ec->rx_coalesce_usecs = get_rx_coal(mp);
1525 ec->tx_coalesce_usecs = get_tx_coal(mp);
1526
1527 return 0;
1528}
1529
1530static int
1531mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1532{
1533 struct mv643xx_eth_private *mp = netdev_priv(dev);
1534
1535 set_rx_coal(mp, ec->rx_coalesce_usecs);
1536 set_tx_coal(mp, ec->tx_coalesce_usecs);
1537
1538 return 0;
1539}
1540
e7d2f4db
LB		 1541static void
1542mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1543{
1544 struct mv643xx_eth_private *mp = netdev_priv(dev);
1545
1546 er->rx_max_pending = 4096;
1547 er->tx_max_pending = 4096;
1548 er->rx_mini_max_pending = 0;
1549 er->rx_jumbo_max_pending = 0;
1550
1551 er->rx_pending = mp->rx_ring_size;
1552 er->tx_pending = mp->tx_ring_size;
1553 er->rx_mini_pending = 0;
1554 er->rx_jumbo_pending = 0;
1555}
1556
1557static int
1558mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1559{
1560 struct mv643xx_eth_private *mp = netdev_priv(dev);
1561
1562 if (er->rx_mini_pending || er->rx_jumbo_pending)
1563 return -EINVAL;
1564
1565 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1566 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1567
1568 if (netif_running(dev)) {
1569 mv643xx_eth_stop(dev);
1570 if (mv643xx_eth_open(dev)) {
1571 dev_printk(KERN_ERR, &dev->dev,
1572 "fatal error on re-opening device after "
1573 "ring param change\n");
1574 return -ENOMEM;
1575 }
1576 }
1577
1578 return 0;
1579}
1580
d888b373
LB		 1581static u32
1582mv643xx_eth_get_rx_csum(struct net_device *dev)
1583{
1584 struct mv643xx_eth_private *mp = netdev_priv(dev);
1585
1586 return !!(rdlp(mp, PORT_CONFIG) & 0x02000000);
1587}
1588
1589static int
1590mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum)
1591{
1592 struct mv643xx_eth_private *mp = netdev_priv(dev);
1593
1594 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1595
1596 return 0;
1597}
1598
fc32b0e2
LB		 1599static void mv643xx_eth_get_strings(struct net_device *dev,
1600 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1601{
1602 int i;
1da177e4 1603
fc32b0e2
LB		 1604 if (stringset == ETH_SS_STATS) {
1605 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1606 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1607 mv643xx_eth_stats[i].stat_string,
e5371493 1608 ETH_GSTRING_LEN);
c9df406f 1609 }
c9df406f
LB		 1610 }
1611}
1da177e4 1612
fc32b0e2
LB		 1613static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1614 struct ethtool_stats *stats,
1615 uint64_t *data)
c9df406f 1616{
b9873841 1617 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1618 int i;
1da177e4 1619
8fd89211 1620 mv643xx_eth_get_stats(dev);
fc32b0e2 1621 mib_counters_update(mp);
eaf5d590 1622 mv643xx_eth_grab_lro_stats(mp);
1da177e4 1623
16820054
LB		 1624 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1625 const struct mv643xx_eth_stats *stat;
1626 void *p;
1627
1628 stat = mv643xx_eth_stats + i;
1629
1630 if (stat->netdev_off >= 0)
1631 p = ((void *)mp->dev) + stat->netdev_off;
1632 else
1633 p = ((void *)mp) + stat->mp_off;
1634
1635 data[i] = (stat->sizeof_stat == 8) ?
1636 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1637 }
c9df406f 1638}
1da177e4 1639
fc32b0e2 1640static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1641{
fc32b0e2 1642 if (sset == ETH_SS_STATS)
16820054 1643 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1644
1645 return -EOPNOTSUPP;
c9df406f 1646}
1da177e4 1647
e5371493 1648static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1649 .get_settings = mv643xx_eth_get_settings,
1650 .set_settings = mv643xx_eth_set_settings,
1651 .get_drvinfo = mv643xx_eth_get_drvinfo,
1652 .nway_reset = mv643xx_eth_nway_reset,
1653 .get_link = mv643xx_eth_get_link,
3e508034
LB		 1654 .get_coalesce = mv643xx_eth_get_coalesce,
1655 .set_coalesce = mv643xx_eth_set_coalesce,
e7d2f4db
LB		 1656 .get_ringparam = mv643xx_eth_get_ringparam,
1657 .set_ringparam = mv643xx_eth_set_ringparam,
d888b373
LB		 1658 .get_rx_csum = mv643xx_eth_get_rx_csum,
1659 .set_rx_csum = mv643xx_eth_set_rx_csum,
b8df184f 1660 .set_tx_csum = ethtool_op_set_tx_csum,
c9df406f 1661 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1662 .get_strings = mv643xx_eth_get_strings,
1663 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
eaf5d590
LB		 1664 .get_flags = ethtool_op_get_flags,
1665 .set_flags = ethtool_op_set_flags,
e5371493 1666 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1667};
1da177e4 1668
bea3348e 1669
c9df406f 1670/* address handling *********************************************************/
5daffe94 1671static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1672{
66e63ffb
LB		 1673 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1674 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1675
5daffe94
LB		 1676 addr[0] = (mac_h >> 24) & 0xff;
1677 addr[1] = (mac_h >> 16) & 0xff;
1678 addr[2] = (mac_h >> 8) & 0xff;
1679 addr[3] = mac_h & 0xff;
1680 addr[4] = (mac_l >> 8) & 0xff;
1681 addr[5] = mac_l & 0xff;
c9df406f 1682}
1da177e4 1683
66e63ffb 1684static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1685{
66e63ffb
LB		 1686 wrlp(mp, MAC_ADDR_HIGH,
1687 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1688 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1689}
d0412d96 1690
66e63ffb 1691static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1692{
ccffad25 1693 struct netdev_hw_addr *ha;
66e63ffb 1694 u32 nibbles;
1da177e4 1695
66e63ffb
LB		 1696 if (dev->flags & IFF_PROMISC)
1697 return 0;
1da177e4 1698
66e63ffb 1699 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
32e7bfc4 1700 netdev_for_each_uc_addr(ha, dev) {
ccffad25 1701 if (memcmp(dev->dev_addr, ha->addr, 5))
66e63ffb 1702 return 0;
ccffad25 1703 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
66e63ffb 1704 return 0;
ff561eef 1705
ccffad25 1706 nibbles |= 1 << (ha->addr[5] & 0x0f);
66e63ffb 1707 }
1da177e4 1708
66e63ffb 1709 return nibbles;
1da177e4
LT		 1710}
1711
66e63ffb 1712static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1713{
e5371493 1714 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1715 u32 port_config;
1716 u32 nibbles;
1717 int i;
1da177e4 1718
cc9754b3 1719 uc_addr_set(mp, dev->dev_addr);
1da177e4 1720
6877f54e
PS		 1721 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1722
66e63ffb
LB		 1723 nibbles = uc_addr_filter_mask(dev);
1724 if (!nibbles) {
1725 port_config |= UNICAST_PROMISCUOUS_MODE;
6877f54e 1726 nibbles = 0xffff;
66e63ffb
LB		 1727 }
1728
1729 for (i = 0; i < 16; i += 4) {
1730 int off = UNICAST_TABLE(mp->port_num) + i;
1731 u32 v;
1732
1733 v = 0;
1734 if (nibbles & 1)
1735 v |= 0x00000001;
1736 if (nibbles & 2)
1737 v |= 0x00000100;
1738 if (nibbles & 4)
1739 v |= 0x00010000;
1740 if (nibbles & 8)
1741 v |= 0x01000000;
1742 nibbles >>= 4;
1743
1744 wrl(mp, off, v);
1745 }
1746
66e63ffb 1747 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1748}
1749
69876569
LB		 1750static int addr_crc(unsigned char *addr)
1751{
1752 int crc = 0;
1753 int i;
1754
1755 for (i = 0; i < 6; i++) {
1756 int j;
1757
1758 crc = (crc ^ addr[i]) << 8;
1759 for (j = 7; j >= 0; j--) {
1760 if (crc & (0x100 << j))
1761 crc ^= 0x107 << j;
1762 }
1763 }
1764
1765 return crc;
1766}
1767
66e63ffb 1768static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1769{
fc32b0e2 1770 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1771 u32 *mc_spec;
1772 u32 *mc_other;
fc32b0e2
LB		 1773 struct dev_addr_list *addr;
1774 int i;
c8aaea25 1775
fc32b0e2 1776 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1777 int port_num;
1778 u32 accept;
c8aaea25 1779
66e63ffb
LB		 1780oom:
1781 port_num = mp->port_num;
1782 accept = 0x01010101;
fc32b0e2
LB		 1783 for (i = 0; i < 0x100; i += 4) {
1784 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1785 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1786 }
1787 return;
1788 }
c8aaea25 1789
82a5bd6a 1790 mc_spec = kmalloc(0x200, GFP_ATOMIC);
66e63ffb
LB		 1791 if (mc_spec == NULL)
1792 goto oom;
1793 mc_other = mc_spec + (0x100 >> 2);
1794
1795 memset(mc_spec, 0, 0x100);
1796 memset(mc_other, 0, 0x100);
1da177e4 1797
f9dcbcc9 1798 netdev_for_each_mc_addr(addr, dev) {
fc32b0e2 1799 u8 *a = addr->da_addr;
66e63ffb
LB		 1800 u32 *table;
1801 int entry;
1da177e4 1802
fc32b0e2 1803 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1804 table = mc_spec;
1805 entry = a[5];
fc32b0e2 1806 } else {
66e63ffb
LB		 1807 table = mc_other;
1808 entry = addr_crc(a);
fc32b0e2 1809 }
66e63ffb 1810
2b448334 1811 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1812 }
66e63ffb
LB		 1813
1814 for (i = 0; i < 0x100; i += 4) {
1815 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1816 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1817 }
1818
1819 kfree(mc_spec);
1820}
1821
1822static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1823{
1824 mv643xx_eth_program_unicast_filter(dev);
1825 mv643xx_eth_program_multicast_filter(dev);
1826}
1827
1828static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1829{
1830 struct sockaddr *sa = addr;
1831
a29ec08a
DK		 1832 if (!is_valid_ether_addr(sa->sa_data))
1833 return -EINVAL;
1834
66e63ffb
LB		 1835 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1836
1837 netif_addr_lock_bh(dev);
1838 mv643xx_eth_program_unicast_filter(dev);
1839 netif_addr_unlock_bh(dev);
1840
1841 return 0;
c9df406f 1842}
c8aaea25 1843
c8aaea25 1844
c9df406f 1845/* rx/tx queue initialisation ***********************************************/
64da80a2 1846static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1847{
64da80a2 1848 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1849 struct rx_desc *rx_desc;
1850 int size;
c9df406f
LB		 1851 int i;
1852
64da80a2
LB		 1853 rxq->index = index;
1854
e7d2f4db 1855 rxq->rx_ring_size = mp->rx_ring_size;
8a578111
LB		 1856
1857 rxq->rx_desc_count = 0;
1858 rxq->rx_curr_desc = 0;
1859 rxq->rx_used_desc = 0;
1860
1861 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1862
f7981c1c 1863 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1864 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1865 mp->rx_desc_sram_size);
1866 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1867 } else {
eb0519b5
GP		 1868 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1869 size, &rxq->rx_desc_dma,
1870 GFP_KERNEL);
f7ea3337
PJ		 1871 }
1872
8a578111
LB		 1873 if (rxq->rx_desc_area == NULL) {
1874 dev_printk(KERN_ERR, &mp->dev->dev,
1875 "can't allocate rx ring (%d bytes)\n", size);
1876 goto out;
1877 }
1878 memset(rxq->rx_desc_area, 0, size);
1da177e4 1879
8a578111
LB		 1880 rxq->rx_desc_area_size = size;
1881 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1882 GFP_KERNEL);
1883 if (rxq->rx_skb == NULL) {
1884 dev_printk(KERN_ERR, &mp->dev->dev,
1885 "can't allocate rx skb ring\n");
1886 goto out_free;
1887 }
1888
1889 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1890 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1891 int nexti;
1892
1893 nexti = i + 1;
1894 if (nexti == rxq->rx_ring_size)
1895 nexti = 0;
1896
8a578111
LB		 1897 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1898 nexti * sizeof(struct rx_desc);
1899 }
1900
eaf5d590
LB		 1901 rxq->lro_mgr.dev = mp->dev;
1902 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1903 rxq->lro_mgr.features = LRO_F_NAPI;
1904 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1905 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1906 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1907 rxq->lro_mgr.max_aggr = 32;
1908 rxq->lro_mgr.frag_align_pad = 0;
1909 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1910 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1911
1912 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
eaf5d590 1913
8a578111
LB		 1914 return 0;
1915
1916
1917out_free:
f7981c1c 1918 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1919 iounmap(rxq->rx_desc_area);
1920 else
eb0519b5 1921 dma_free_coherent(mp->dev->dev.parent, size,
8a578111
LB		 1922 rxq->rx_desc_area,
1923 rxq->rx_desc_dma);
1924
1925out:
1926 return -ENOMEM;
c9df406f 1927}
c8aaea25 1928
8a578111 1929static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1930{
8a578111
LB		 1931 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1932 int i;
1933
1934 rxq_disable(rxq);
c8aaea25 1935
8a578111
LB		 1936 for (i = 0; i < rxq->rx_ring_size; i++) {
1937 if (rxq->rx_skb[i]) {
1938 dev_kfree_skb(rxq->rx_skb[i]);
1939 rxq->rx_desc_count--;
1da177e4 1940 }
c8aaea25 1941 }
1da177e4 1942
8a578111
LB		 1943 if (rxq->rx_desc_count) {
1944 dev_printk(KERN_ERR, &mp->dev->dev,
1945 "error freeing rx ring -- %d skbs stuck\n",
1946 rxq->rx_desc_count);
1947 }
1948
f7981c1c 1949 if (rxq->index == 0 &&
64da80a2 1950 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1951 iounmap(rxq->rx_desc_area);
c9df406f 1952 else
eb0519b5 1953 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
8a578111
LB		 1954 rxq->rx_desc_area, rxq->rx_desc_dma);
1955
1956 kfree(rxq->rx_skb);
c9df406f 1957}
1da177e4 1958
3d6b35bc 1959static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1960{
3d6b35bc 1961 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1962 struct tx_desc *tx_desc;
1963 int size;
c9df406f 1964 int i;
1da177e4 1965
3d6b35bc
LB		 1966 txq->index = index;
1967
e7d2f4db 1968 txq->tx_ring_size = mp->tx_ring_size;
13d64285
LB		 1969
1970 txq->tx_desc_count = 0;
1971 txq->tx_curr_desc = 0;
1972 txq->tx_used_desc = 0;
1973
1974 size = txq->tx_ring_size * sizeof(struct tx_desc);
1975
f7981c1c 1976 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1977 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1978 mp->tx_desc_sram_size);
1979 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1980 } else {
eb0519b5
GP		 1981 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1982 size, &txq->tx_desc_dma,
1983 GFP_KERNEL);
13d64285
LB		 1984 }
1985
1986 if (txq->tx_desc_area == NULL) {
1987 dev_printk(KERN_ERR, &mp->dev->dev,
1988 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1989 return -ENOMEM;
c9df406f 1990 }
13d64285
LB		 1991 memset(txq->tx_desc_area, 0, size);
1992
1993 txq->tx_desc_area_size = size;
13d64285
LB		 1994
1995 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1996 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1997 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1998 int nexti;
1999
2000 nexti = i + 1;
2001 if (nexti == txq->tx_ring_size)
2002 nexti = 0;
6b368f68
LB		 2003
2004 txd->cmd_sts = 0;
2005 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 2006 nexti * sizeof(struct tx_desc);
2007 }
2008
99ab08e0 2009 skb_queue_head_init(&txq->tx_skb);
c9df406f 2010
99ab08e0 2011 return 0;
c8aaea25 2012}
1da177e4 2013
13d64285 2014static void txq_deinit(struct tx_queue *txq)
c9df406f 2015{
13d64285 2016 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 2017
13d64285 2018 txq_disable(txq);
1fa38c58 2019 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 2020
13d64285 2021 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 2022
f7981c1c 2023 if (txq->index == 0 &&
3d6b35bc 2024 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 2025 iounmap(txq->tx_desc_area);
c9df406f 2026 else
eb0519b5 2027 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
13d64285 2028 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 2029}
1da177e4 2030
1da177e4 2031
c9df406f 2032/* netdev ops and related ***************************************************/
1fa38c58
LB		 2033static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2034{
2035 u32 int_cause;
2036 u32 int_cause_ext;
2037
e0ca8410 2038 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1fa38c58
LB		 2039 if (int_cause == 0)
2040 return 0;
2041
2042 int_cause_ext = 0;
e0ca8410
SB		 2043 if (int_cause & INT_EXT) {
2044 int_cause &= ~INT_EXT;
37a6084f 2045 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
e0ca8410 2046 }
1fa38c58 2047
1fa38c58 2048 if (int_cause) {
37a6084f 2049 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 2050 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 2051 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 2052 mp->work_rx |= (int_cause & INT_RX) >> 2;
2053 }
2054
2055 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2056 if (int_cause_ext) {
37a6084f 2057 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 2058 if (int_cause_ext & INT_EXT_LINK_PHY)
2059 mp->work_link = 1;
2060 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2061 }
2062
2063 return 1;
2064}
2065
2066static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2067{
2068 struct net_device *dev = (struct net_device *)dev_id;
2069 struct mv643xx_eth_private *mp = netdev_priv(dev);
2070
2071 if (unlikely(!mv643xx_eth_collect_events(mp)))
2072 return IRQ_NONE;
2073
37a6084f 2074 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 2075 napi_schedule(&mp->napi);
2076
2077 return IRQ_HANDLED;
2078}
2079
2f7eb47a
LB		 2080static void handle_link_event(struct mv643xx_eth_private *mp)
2081{
2082 struct net_device *dev = mp->dev;
2083 u32 port_status;
2084 int speed;
2085 int duplex;
2086 int fc;
2087
37a6084f 2088 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 2089 if (!(port_status & LINK_UP)) {
2090 if (netif_carrier_ok(dev)) {
2091 int i;
2092
2093 printk(KERN_INFO "%s: link down\n", dev->name);
2094
2095 netif_carrier_off(dev);
2f7eb47a 2096
f7981c1c 2097 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 2098 struct tx_queue *txq = mp->txq + i;
2099
1fa38c58 2100 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 2101 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 2102 }
2103 }
2104 return;
2105 }
2106
2107 switch (port_status & PORT_SPEED_MASK) {
2108 case PORT_SPEED_10:
2109 speed = 10;
2110 break;
2111 case PORT_SPEED_100:
2112 speed = 100;
2113 break;
2114 case PORT_SPEED_1000:
2115 speed = 1000;
2116 break;
2117 default:
2118 speed = -1;
2119 break;
2120 }
2121 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2122 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2123
2124 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
2125 "flow control %sabled\n", dev->name,
2126 speed, duplex ? "full" : "half",
2127 fc ? "en" : "dis");
2128
4fdeca3f 2129 if (!netif_carrier_ok(dev))
2f7eb47a 2130 netif_carrier_on(dev);
2f7eb47a
LB		 2131}
2132
1fa38c58 2133static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 2134{
1fa38c58
LB		 2135 struct mv643xx_eth_private *mp;
2136 int work_done;
ce4e2e45 2137
1fa38c58 2138 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 2139
1319ebad
LB		 2140 if (unlikely(mp->oom)) {
2141 mp->oom = 0;
2142 del_timer(&mp->rx_oom);
2143 }
1da177e4 2144
1fa38c58
LB		 2145 work_done = 0;
2146 while (work_done < budget) {
2147 u8 queue_mask;
2148 int queue;
2149 int work_tbd;
2150
2151 if (mp->work_link) {
2152 mp->work_link = 0;
2153 handle_link_event(mp);
26ef1f17 2154 work_done++;
1fa38c58
LB		 2155 continue;
2156 }
1da177e4 2157
1319ebad
LB		 2158 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2159 if (likely(!mp->oom))
2160 queue_mask |= mp->work_rx_refill;
2161
1fa38c58
LB		 2162 if (!queue_mask) {
2163 if (mv643xx_eth_collect_events(mp))
2164 continue;
2165 break;
2166 }
1da177e4 2167
1fa38c58
LB		 2168 queue = fls(queue_mask) - 1;
2169 queue_mask = 1 << queue;
2170
2171 work_tbd = budget - work_done;
2172 if (work_tbd > 16)
2173 work_tbd = 16;
2174
2175 if (mp->work_tx_end & queue_mask) {
2176 txq_kick(mp->txq + queue);
2177 } else if (mp->work_tx & queue_mask) {
2178 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2179 txq_maybe_wake(mp->txq + queue);
2180 } else if (mp->work_rx & queue_mask) {
2181 work_done += rxq_process(mp->rxq + queue, work_tbd);
1319ebad 2182 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
1fa38c58
LB		 2183 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2184 } else {
2185 BUG();
2186 }
84dd619e 2187 }
fc32b0e2 2188
1fa38c58 2189 if (work_done < budget) {
1319ebad 2190 if (mp->oom)
1fa38c58
LB		 2191 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2192 napi_complete(napi);
e0ca8410 2193 wrlp(mp, INT_MASK, mp->int_mask);
226bb6b7 2194 }
3d6b35bc 2195
1fa38c58
LB		 2196 return work_done;
2197}
8fa89bf5 2198
1fa38c58
LB		 2199static inline void oom_timer_wrapper(unsigned long data)
2200{
2201 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 2202
1fa38c58 2203 napi_schedule(&mp->napi);
1da177e4
LT		 2204}
2205
e5371493 2206static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 2207{
45c5d3bc
LB		 2208 int data;
2209
ed94493f 2210 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 2211 if (data < 0)
2212 return;
1da177e4 2213
7f106c1d 2214 data |= BMCR_RESET;
ed94493f 2215 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 2216 return;
1da177e4 2217
c9df406f 2218 do {
ed94493f 2219 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 2220 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 2221}
2222
fc32b0e2 2223static void port_start(struct mv643xx_eth_private *mp)
1da177e4 2224{
d0412d96 2225 u32 pscr;
8a578111 2226 int i;
1da177e4 2227
bedfe324
LB		 2228 /*
2229 * Perform PHY reset, if there is a PHY.
2230 */
ed94493f 2231 if (mp->phy != NULL) {
bedfe324
LB		 2232 struct ethtool_cmd cmd;
2233
2234 mv643xx_eth_get_settings(mp->dev, &cmd);
2235 phy_reset(mp);
2236 mv643xx_eth_set_settings(mp->dev, &cmd);
2237 }
1da177e4 2238
81600eea
LB		 2239 /*
2240 * Configure basic link parameters.
2241 */
37a6084f 2242 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2243
2244 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2245 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2246
2247 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2248 if (mp->phy == NULL)
81600eea 2249 pscr |= FORCE_LINK_PASS;
37a6084f 2250 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2251
13d64285
LB		 2252 /*
2253 * Configure TX path and queues.
2254 */
89df5fdc 2255 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2256 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2257 struct tx_queue *txq = mp->txq + i;
13d64285 2258
6b368f68 2259 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2260 txq_set_rate(txq, 1000000000, 16777216);
2261 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2262 }
2263
d9a073ea
LB		 2264 /*
2265 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2266 * frames to RX queue #0, and include the pseudo-header when
2267 * calculating receive checksums.
d9a073ea 2268 */
37a6084f 2269 wrlp(mp, PORT_CONFIG, 0x02000000);
01999873 2270
376489a2
LB		 2271 /*
2272 * Treat BPDUs as normal multicasts, and disable partition mode.
2273 */
37a6084f 2274 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2275
5a893922
LB		 2276 /*
2277 * Add configured unicast addresses to address filter table.
2278 */
2279 mv643xx_eth_program_unicast_filter(mp->dev);
2280
8a578111 2281 /*
64da80a2 2282 * Enable the receive queues.
8a578111 2283 */
f7981c1c 2284 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2285 struct rx_queue *rxq = mp->rxq + i;
8a578111 2286 u32 addr;
1da177e4 2287
8a578111
LB		 2288 addr = (u32)rxq->rx_desc_dma;
2289 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2290 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2291
8a578111
LB		 2292 rxq_enable(rxq);
2293 }
1da177e4
LT		 2294}
2295
2bcb4b0f
LB		 2296static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2297{
2298 int skb_size;
2299
2300 /*
2301 * Reserve 2+14 bytes for an ethernet header (the hardware
2302 * automatically prepends 2 bytes of dummy data to each
2303 * received packet), 16 bytes for up to four VLAN tags, and
2304 * 4 bytes for the trailing FCS -- 36 bytes total.
2305 */
2306 skb_size = mp->dev->mtu + 36;
2307
2308 /*
2309 * Make sure that the skb size is a multiple of 8 bytes, as
2310 * the lower three bits of the receive descriptor's buffer
2311 * size field are ignored by the hardware.
2312 */
2313 mp->skb_size = (skb_size + 7) & ~7;
7fd96ce4
LB		 2314
2315 /*
2316 * If NET_SKB_PAD is smaller than a cache line,
2317 * netdev_alloc_skb() will cause skb->data to be misaligned
2318 * to a cache line boundary. If this is the case, include
2319 * some extra space to allow re-aligning the data area.
2320 */
2321 mp->skb_size += SKB_DMA_REALIGN;
2bcb4b0f
LB		 2322}
2323
c9df406f 2324static int mv643xx_eth_open(struct net_device *dev)
16e03018 2325{
e5371493 2326 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2327 int err;
64da80a2 2328 int i;
16e03018 2329
37a6084f
LB		 2330 wrlp(mp, INT_CAUSE, 0);
2331 wrlp(mp, INT_CAUSE_EXT, 0);
2332 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2333
fc32b0e2 2334 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2335 IRQF_SHARED, dev->name, dev);
c9df406f 2336 if (err) {
fc32b0e2 2337 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2338 return -EAGAIN;
16e03018
DF		 2339 }
2340
2bcb4b0f
LB		 2341 mv643xx_eth_recalc_skb_size(mp);
2342
2257e05c
LB		 2343 napi_enable(&mp->napi);
2344
2bcb4b0f
LB		 2345 skb_queue_head_init(&mp->rx_recycle);
2346
e0ca8410
SB		 2347 mp->int_mask = INT_EXT;
2348
f7981c1c 2349 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2350 err = rxq_init(mp, i);
2351 if (err) {
2352 while (--i >= 0)
f7981c1c 2353 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2354 goto out;
2355 }
2356
1fa38c58 2357 rxq_refill(mp->rxq + i, INT_MAX);
e0ca8410 2358 mp->int_mask |= INT_RX_0 << i;
2257e05c
LB		 2359 }
2360
1319ebad 2361 if (mp->oom) {
2257e05c
LB		 2362 mp->rx_oom.expires = jiffies + (HZ / 10);
2363 add_timer(&mp->rx_oom);
64da80a2 2364 }
8a578111 2365
f7981c1c 2366 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2367 err = txq_init(mp, i);
2368 if (err) {
2369 while (--i >= 0)
f7981c1c 2370 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2371 goto out_free;
2372 }
e0ca8410 2373 mp->int_mask |= INT_TX_END_0 << i;
3d6b35bc 2374 }
16e03018 2375
fc32b0e2 2376 port_start(mp);
16e03018 2377
37a6084f 2378 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
e0ca8410 2379 wrlp(mp, INT_MASK, mp->int_mask);
16e03018 2380
c9df406f
LB		 2381 return 0;
2382
13d64285 2383
fc32b0e2 2384out_free:
f7981c1c
LB		 2385 for (i = 0; i < mp->rxq_count; i++)
2386 rxq_deinit(mp->rxq + i);
fc32b0e2 2387out:
c9df406f
LB		 2388 free_irq(dev->irq, dev);
2389
2390 return err;
16e03018
DF		 2391}
2392
e5371493 2393static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2394{
fc32b0e2 2395 unsigned int data;
64da80a2 2396 int i;
1da177e4 2397
f7981c1c
LB		 2398 for (i = 0; i < mp->rxq_count; i++)
2399 rxq_disable(mp->rxq + i);
2400 for (i = 0; i < mp->txq_count; i++)
2401 txq_disable(mp->txq + i);
ae9ae064
LB		 2402
2403 while (1) {
37a6084f 2404 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2405
2406 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2407 break;
13d64285 2408 udelay(10);
ae9ae064 2409 }
1da177e4 2410
c9df406f 2411 /* Reset the Enable bit in the Configuration Register */
37a6084f 2412 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2413 data &= ~(SERIAL_PORT_ENABLE |
2414 DO_NOT_FORCE_LINK_FAIL |
2415 FORCE_LINK_PASS);
37a6084f 2416 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2417}
2418
c9df406f 2419static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2420{
e5371493 2421 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2422 int i;
1da177e4 2423
fe65e704 2424 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2425 wrlp(mp, INT_MASK, 0x00000000);
2426 rdlp(mp, INT_MASK);
1da177e4 2427
c9df406f 2428 napi_disable(&mp->napi);
78fff83b 2429
2257e05c
LB		 2430 del_timer_sync(&mp->rx_oom);
2431
c9df406f 2432 netif_carrier_off(dev);
1da177e4 2433
fc32b0e2
LB		 2434 free_irq(dev->irq, dev);
2435
cc9754b3 2436 port_reset(mp);
8fd89211 2437 mv643xx_eth_get_stats(dev);
fc32b0e2 2438 mib_counters_update(mp);
57e8f26a 2439 del_timer_sync(&mp->mib_counters_timer);
1da177e4 2440
2bcb4b0f
LB		 2441 skb_queue_purge(&mp->rx_recycle);
2442
f7981c1c
LB		 2443 for (i = 0; i < mp->rxq_count; i++)
2444 rxq_deinit(mp->rxq + i);
2445 for (i = 0; i < mp->txq_count; i++)
2446 txq_deinit(mp->txq + i);
1da177e4 2447
c9df406f 2448 return 0;
1da177e4
LT		 2449}
2450
fc32b0e2 2451static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2452{
e5371493 2453 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2454
ed94493f
LB		 2455 if (mp->phy != NULL)
2456 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2457
2458 return -EOPNOTSUPP;
1da177e4
LT		 2459}
2460
c9df406f 2461static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2462{
89df5fdc
LB		 2463 struct mv643xx_eth_private *mp = netdev_priv(dev);
2464
fc32b0e2 2465 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2466 return -EINVAL;
1da177e4 2467
c9df406f 2468 dev->mtu = new_mtu;
2bcb4b0f 2469 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2470 tx_set_rate(mp, 1000000000, 16777216);
2471
c9df406f
LB		 2472 if (!netif_running(dev))
2473 return 0;
1da177e4 2474
c9df406f
LB		 2475 /*
2476 * Stop and then re-open the interface. This will allocate RX
2477 * skbs of the new MTU.
2478 * There is a possible danger that the open will not succeed,
fc32b0e2 2479 * due to memory being full.
c9df406f
LB		 2480 */
2481 mv643xx_eth_stop(dev);
2482 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2483 dev_printk(KERN_ERR, &dev->dev,
2484 "fatal error on re-opening device after "
2485 "MTU change\n");
c9df406f
LB		 2486 }
2487
2488 return 0;
1da177e4
LT		 2489}
2490
fc32b0e2 2491static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2492{
fc32b0e2 2493 struct mv643xx_eth_private *mp;
1da177e4 2494
fc32b0e2
LB		 2495 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2496 if (netif_running(mp->dev)) {
e5ef1de1 2497 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2498 port_reset(mp);
2499 port_start(mp);
e5ef1de1 2500 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2501 }
c9df406f
LB		 2502}
2503
c9df406f 2504static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2505{
e5371493 2506 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2507
fc32b0e2 2508 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2509
c9df406f 2510 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2511}
2512
c9df406f 2513#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2514static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2515{
fc32b0e2 2516 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2517
37a6084f
LB		 2518 wrlp(mp, INT_MASK, 0x00000000);
2519 rdlp(mp, INT_MASK);
c9df406f 2520
fc32b0e2 2521 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2522
e0ca8410 2523 wrlp(mp, INT_MASK, mp->int_mask);
9f8dd319 2524}
c9df406f 2525#endif
9f8dd319 2526
9f8dd319 2527
c9df406f 2528/* platform glue ************************************************************/
e5371493
LB		 2529static void
2530mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2531 struct mbus_dram_target_info *dram)
c9df406f 2532{
cc9754b3 2533 void __iomem *base = msp->base;
c9df406f
LB		 2534 u32 win_enable;
2535 u32 win_protect;
2536 int i;
9f8dd319 2537
c9df406f
LB		 2538 for (i = 0; i < 6; i++) {
2539 writel(0, base + WINDOW_BASE(i));
2540 writel(0, base + WINDOW_SIZE(i));
2541 if (i < 4)
2542 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2543 }
2544
c9df406f
LB		 2545 win_enable = 0x3f;
2546 win_protect = 0;
2547
2548 for (i = 0; i < dram->num_cs; i++) {
2549 struct mbus_dram_window *cs = dram->cs + i;
2550
2551 writel((cs->base & 0xffff0000) |
2552 (cs->mbus_attr << 8) |
2553 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2554 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2555
2556 win_enable &= ~(1 << i);
2557 win_protect |= 3 << (2 * i);
2558 }
2559
2560 writel(win_enable, base + WINDOW_BAR_ENABLE);
2561 msp->win_protect = win_protect;
9f8dd319
DF		 2562}
2563
773fc3ee
LB		 2564static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2565{
2566 /*
2567 * Check whether we have a 14-bit coal limit field in bits
2568 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2569 * SDMA config register.
2570 */
37a6084f
LB		 2571 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2572 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2573 msp->extended_rx_coal_limit = 1;
2574 else
2575 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2576
2577 /*
457b1d5a
LB		 2578 * Check whether the MAC supports TX rate control, and if
2579 * yes, whether its associated registers are in the old or
2580 * the new place.
1e881592 2581 */
37a6084f
LB		 2582 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2583 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2584 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2585 } else {
37a6084f
LB		 2586 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2587 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2588 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2589 else
2590 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2591 }
773fc3ee
LB		 2592}
2593
c9df406f 2594static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2595{
10a9948d 2596 static int mv643xx_eth_version_printed;
c9df406f 2597 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2598 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2599 struct resource *res;
2600 int ret;
9f8dd319 2601
e5371493 2602 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2603 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2604 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2605
c9df406f
LB		 2606 ret = -EINVAL;
2607 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2608 if (res == NULL)
2609 goto out;
9f8dd319 2610
c9df406f
LB		 2611 ret = -ENOMEM;
2612 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2613 if (msp == NULL)
2614 goto out;
2615 memset(msp, 0, sizeof(*msp));
2616
cc9754b3
LB		 2617 msp->base = ioremap(res->start, res->end - res->start + 1);
2618 if (msp->base == NULL)
c9df406f
LB		 2619 goto out_free;
2620
ed94493f
LB		 2621 /*
2622 * Set up and register SMI bus.
2623 */
2624 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2625 msp->smi_bus = mdiobus_alloc();
2626 if (msp->smi_bus == NULL)
ed94493f 2627 goto out_unmap;
298cf9be
LB		 2628
2629 msp->smi_bus->priv = msp;
2630 msp->smi_bus->name = "mv643xx_eth smi";
2631 msp->smi_bus->read = smi_bus_read;
2632 msp->smi_bus->write = smi_bus_write,
2633 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2634 msp->smi_bus->parent = &pdev->dev;
2635 msp->smi_bus->phy_mask = 0xffffffff;
2636 if (mdiobus_register(msp->smi_bus) < 0)
2637 goto out_free_mii_bus;
ed94493f
LB		 2638 msp->smi = msp;
2639 } else {
fc0eb9f2 2640 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2641 }
c9df406f 2642
45c5d3bc
LB		 2643 msp->err_interrupt = NO_IRQ;
2644 init_waitqueue_head(&msp->smi_busy_wait);
2645
2646 /*
2647 * Check whether the error interrupt is hooked up.
2648 */
2649 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2650 if (res != NULL) {
2651 int err;
2652
2653 err = request_irq(res->start, mv643xx_eth_err_irq,
2654 IRQF_SHARED, "mv643xx_eth", msp);
2655 if (!err) {
2656 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2657 msp->err_interrupt = res->start;
2658 }
2659 }
2660
c9df406f
LB		 2661 /*
2662 * (Re-)program MBUS remapping windows if we are asked to.
2663 */
2664 if (pd != NULL && pd->dram != NULL)
2665 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2666
fc32b0e2
LB		 2667 /*
2668 * Detect hardware parameters.
2669 */
2670 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2671 infer_hw_params(msp);
fc32b0e2
LB		 2672
2673 platform_set_drvdata(pdev, msp);
2674
c9df406f
LB		 2675 return 0;
2676
298cf9be
LB		 2677out_free_mii_bus:
2678 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2679out_unmap:
2680 iounmap(msp->base);
c9df406f
LB		 2681out_free:
2682 kfree(msp);
2683out:
2684 return ret;
2685}
2686
2687static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2688{
e5371493 2689 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2690 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2691
298cf9be 2692 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2693 mdiobus_unregister(msp->smi_bus);
bcb3336c 2694 mdiobus_free(msp->smi_bus);
298cf9be 2695 }
45c5d3bc
LB		 2696 if (msp->err_interrupt != NO_IRQ)
2697 free_irq(msp->err_interrupt, msp);
cc9754b3 2698 iounmap(msp->base);
c9df406f
LB		 2699 kfree(msp);
2700
2701 return 0;
9f8dd319
DF		 2702}
2703
c9df406f 2704static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2705 .probe = mv643xx_eth_shared_probe,
2706 .remove = mv643xx_eth_shared_remove,
c9df406f 2707 .driver = {
fc32b0e2 2708 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2709 .owner = THIS_MODULE,
2710 },
2711};
2712
e5371493 2713static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2714{
c9df406f 2715 int addr_shift = 5 * mp->port_num;
fc32b0e2 2716 u32 data;
1da177e4 2717
fc32b0e2
LB		 2718 data = rdl(mp, PHY_ADDR);
2719 data &= ~(0x1f << addr_shift);
2720 data |= (phy_addr & 0x1f) << addr_shift;
2721 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2722}
2723
e5371493 2724static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2725{
fc32b0e2
LB		 2726 unsigned int data;
2727
2728 data = rdl(mp, PHY_ADDR);
2729
2730 return (data >> (5 * mp->port_num)) & 0x1f;
2731}
2732
2733static void set_params(struct mv643xx_eth_private *mp,
2734 struct mv643xx_eth_platform_data *pd)
2735{
2736 struct net_device *dev = mp->dev;
2737
2738 if (is_valid_ether_addr(pd->mac_addr))
2739 memcpy(dev->dev_addr, pd->mac_addr, 6);
2740 else
2741 uc_addr_get(mp, dev->dev_addr);
2742
e7d2f4db 2743 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
fc32b0e2 2744 if (pd->rx_queue_size)
e7d2f4db 2745 mp->rx_ring_size = pd->rx_queue_size;
fc32b0e2
LB		 2746 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2747 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2748
f7981c1c 2749 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2750
e7d2f4db 2751 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
fc32b0e2 2752 if (pd->tx_queue_size)
e7d2f4db 2753 mp->tx_ring_size = pd->tx_queue_size;
fc32b0e2
LB		 2754 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2755 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2756
f7981c1c 2757 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2758}
2759
ed94493f
LB		 2760static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2761 int phy_addr)
1da177e4 2762{
298cf9be 2763 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2764 struct phy_device *phydev;
2765 int start;
2766 int num;
2767 int i;
45c5d3bc 2768
ed94493f
LB		 2769 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2770 start = phy_addr_get(mp) & 0x1f;
2771 num = 32;
2772 } else {
2773 start = phy_addr & 0x1f;
2774 num = 1;
2775 }
45c5d3bc 2776
ed94493f
LB		 2777 phydev = NULL;
2778 for (i = 0; i < num; i++) {
2779 int addr = (start + i) & 0x1f;
fc32b0e2 2780
ed94493f
LB		 2781 if (bus->phy_map[addr] == NULL)
2782 mdiobus_scan(bus, addr);
1da177e4 2783
ed94493f
LB		 2784 if (phydev == NULL) {
2785 phydev = bus->phy_map[addr];
2786 if (phydev != NULL)
2787 phy_addr_set(mp, addr);
2788 }
2789 }
1da177e4 2790
ed94493f 2791 return phydev;
1da177e4
LT		 2792}
2793
ed94493f 2794static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2795{
ed94493f 2796 struct phy_device *phy = mp->phy;
c28a4f89 2797
fc32b0e2
LB		 2798 phy_reset(mp);
2799
db1d7bf7 2800 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
ed94493f
LB		 2801
2802 if (speed == 0) {
2803 phy->autoneg = AUTONEG_ENABLE;
2804 phy->speed = 0;
2805 phy->duplex = 0;
2806 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2807 } else {
ed94493f
LB		 2808 phy->autoneg = AUTONEG_DISABLE;
2809 phy->advertising = 0;
2810 phy->speed = speed;
2811 phy->duplex = duplex;
c9df406f 2812 }
ed94493f 2813 phy_start_aneg(phy);
c28a4f89
JC		 2814}
2815
81600eea
LB		 2816static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2817{
2818 u32 pscr;
2819
37a6084f 2820 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2821 if (pscr & SERIAL_PORT_ENABLE) {
2822 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2823 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2824 }
2825
2826 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2827 if (mp->phy == NULL) {
81600eea
LB		 2828 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2829 if (speed == SPEED_1000)
2830 pscr |= SET_GMII_SPEED_TO_1000;
2831 else if (speed == SPEED_100)
2832 pscr |= SET_MII_SPEED_TO_100;
2833
2834 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2835
2836 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2837 if (duplex == DUPLEX_FULL)
2838 pscr |= SET_FULL_DUPLEX_MODE;
2839 }
2840
37a6084f 2841 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2842}
2843
ea8a8642
LB		 2844static const struct net_device_ops mv643xx_eth_netdev_ops = {
2845 .ndo_open = mv643xx_eth_open,
2846 .ndo_stop = mv643xx_eth_stop,
2847 .ndo_start_xmit = mv643xx_eth_xmit,
2848 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2849 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
1d4bd947 2850 .ndo_validate_addr = eth_validate_addr,
ea8a8642
LB		 2851 .ndo_do_ioctl = mv643xx_eth_ioctl,
2852 .ndo_change_mtu = mv643xx_eth_change_mtu,
2853 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2854 .ndo_get_stats = mv643xx_eth_get_stats,
2855#ifdef CONFIG_NET_POLL_CONTROLLER
2856 .ndo_poll_controller = mv643xx_eth_netpoll,
2857#endif
2858};
2859
c9df406f 2860static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2861{
c9df406f 2862 struct mv643xx_eth_platform_data *pd;
e5371493 2863 struct mv643xx_eth_private *mp;
c9df406f 2864 struct net_device *dev;
c9df406f 2865 struct resource *res;
fc32b0e2 2866 int err;
1da177e4 2867
c9df406f
LB		 2868 pd = pdev->dev.platform_data;
2869 if (pd == NULL) {
fc32b0e2
LB		 2870 dev_printk(KERN_ERR, &pdev->dev,
2871 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2872 return -ENODEV;
2873 }
1da177e4 2874
c9df406f 2875 if (pd->shared == NULL) {
fc32b0e2
LB		 2876 dev_printk(KERN_ERR, &pdev->dev,
2877 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2878 return -ENODEV;
2879 }
8f518703 2880
e5ef1de1 2881 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2882 if (!dev)
2883 return -ENOMEM;
1da177e4 2884
c9df406f 2885 mp = netdev_priv(dev);
fc32b0e2
LB		 2886 platform_set_drvdata(pdev, mp);
2887
2888 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2889 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2890 mp->port_num = pd->port_number;
2891
c9df406f 2892 mp->dev = dev;
78fff83b 2893
fc32b0e2 2894 set_params(mp, pd);
e5ef1de1 2895 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2896
ed94493f
LB		 2897 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2898 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2899
6bdf576e 2900 if (mp->phy != NULL)
ed94493f 2901 phy_init(mp, pd->speed, pd->duplex);
6bdf576e
LB		 2902
2903 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
ed94493f 2904
81600eea 2905 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2906
4ff3495a
LB		 2907
2908 mib_counters_clear(mp);
2909
2910 init_timer(&mp->mib_counters_timer);
2911 mp->mib_counters_timer.data = (unsigned long)mp;
2912 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2913 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2914 add_timer(&mp->mib_counters_timer);
2915
2916 spin_lock_init(&mp->mib_counters_lock);
2917
2918 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2919
2257e05c
LB		 2920 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2921
2922 init_timer(&mp->rx_oom);
2923 mp->rx_oom.data = (unsigned long)mp;
2924 mp->rx_oom.function = oom_timer_wrapper;
2925
fc32b0e2 2926
c9df406f
LB		 2927 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2928 BUG_ON(!res);
2929 dev->irq = res->start;
1da177e4 2930
ea8a8642
LB		 2931 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2932
c9df406f
LB		 2933 dev->watchdog_timeo = 2 * HZ;
2934 dev->base_addr = 0;
1da177e4 2935
c9df406f 2936 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2937 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2938
fc32b0e2 2939 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2940
c9df406f 2941 if (mp->shared->win_protect)
fc32b0e2 2942 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2943
a5fe3616
LB		 2944 netif_carrier_off(dev);
2945
b5e86db4
LB		 2946 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2947
4fb0a54a 2948 set_rx_coal(mp, 250);
a5fe3616
LB		 2949 set_tx_coal(mp, 0);
2950
c9df406f
LB		 2951 err = register_netdev(dev);
2952 if (err)
2953 goto out;
1da177e4 2954
e174961c
JB		 2955 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2956 mp->port_num, dev->dev_addr);
1da177e4 2957
13d64285 2958 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2959 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2960
c9df406f 2961 return 0;
1da177e4 2962
c9df406f
LB		 2963out:
2964 free_netdev(dev);
1da177e4 2965
c9df406f 2966 return err;
1da177e4
LT		 2967}
2968
c9df406f 2969static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2970{
fc32b0e2 2971 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2972
fc32b0e2 2973 unregister_netdev(mp->dev);
ed94493f
LB		 2974 if (mp->phy != NULL)
2975 phy_detach(mp->phy);
c9df406f 2976 flush_scheduled_work();
fc32b0e2 2977 free_netdev(mp->dev);
c9df406f 2978
c9df406f 2979 platform_set_drvdata(pdev, NULL);
fc32b0e2 2980
c9df406f 2981 return 0;
1da177e4
LT		 2982}
2983
c9df406f 2984static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2985{
fc32b0e2 2986 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2987
c9df406f 2988 /* Mask all interrupts on ethernet port */
37a6084f
LB		 2989 wrlp(mp, INT_MASK, 0);
2990 rdlp(mp, INT_MASK);
c9df406f 2991
fc32b0e2
LB		 2992 if (netif_running(mp->dev))
2993 port_reset(mp);
d0412d96
JC		 2994}
2995
c9df406f 2996static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2997 .probe = mv643xx_eth_probe,
2998 .remove = mv643xx_eth_remove,
2999 .shutdown = mv643xx_eth_shutdown,
c9df406f 3000 .driver = {
fc32b0e2 3001 .name = MV643XX_ETH_NAME,
c9df406f
LB		 3002 .owner = THIS_MODULE,
3003 },
3004};
3005
e5371493 3006static int __init mv643xx_eth_init_module(void)
d0412d96 3007{
c9df406f 3008 int rc;
d0412d96 3009
c9df406f
LB		 3010 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3011 if (!rc) {
3012 rc = platform_driver_register(&mv643xx_eth_driver);
3013 if (rc)
3014 platform_driver_unregister(&mv643xx_eth_shared_driver);
3015 }
fc32b0e2 3016
c9df406f 3017 return rc;
d0412d96 3018}
fc32b0e2 3019module_init(mv643xx_eth_init_module);
d0412d96 3020
e5371493 3021static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 3022{
c9df406f
LB		 3023 platform_driver_unregister(&mv643xx_eth_driver);
3024 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 3025}
e5371493 3026module_exit(mv643xx_eth_cleanup_module);
1da177e4 3027
45675bc6
LB		 3028MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3029 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 3030MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 3031MODULE_LICENSE("GPL");
c9df406f 3032MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 3033MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 6.x block layer and io_uring tree(s)