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Merge branch 'bkl/procfs' of git://git.kernel.org/pub/scm/linux/kernel/git/frederic...
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
11afc1b1
PW		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
096a58fd 34#include "ixgbe_mbx.h"
11afc1b1
PW		 35
36#define IXGBE_82599_MAX_TX_QUEUES 128
37#define IXGBE_82599_MAX_RX_QUEUES 128
38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128
41
61fac744
PW		 42void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
1097cd17 44void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
8620a103
MC		 45s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
cd7e1f0b
DS		 49static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
8620a103
MC		 53s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
11afc1b1
PW		 59static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed *speed,
61 bool *autoneg);
8620a103
MC		 62static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
63 ixgbe_link_speed speed,
64 bool autoneg,
65 bool autoneg_wait_to_complete);
794caeb2 66static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
11afc1b1 67
7b25cdba 68static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 69{
70 struct ixgbe_mac_info *mac = &hw->mac;
71 if (hw->phy.multispeed_fiber) {
72 /* Set up dual speed SFP+ support */
8620a103 73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
61fac744
PW		 74 mac->ops.disable_tx_laser =
75 &ixgbe_disable_tx_laser_multispeed_fiber;
76 mac->ops.enable_tx_laser =
77 &ixgbe_enable_tx_laser_multispeed_fiber;
1097cd17 78 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
11afc1b1 79 } else {
61fac744
PW		 80 mac->ops.disable_tx_laser = NULL;
81 mac->ops.enable_tx_laser = NULL;
1097cd17 82 mac->ops.flap_tx_laser = NULL;
cd7e1f0b
DS		 83 if ((mac->ops.get_media_type(hw) ==
84 ixgbe_media_type_backplane) &&
85 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
86 hw->phy.smart_speed == ixgbe_smart_speed_on))
87 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
88 else
89 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 90 }
91}
92
7b25cdba 93static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 94{
95 s32 ret_val = 0;
96 u16 list_offset, data_offset, data_value;
97
98 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
99 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 100
101 hw->phy.ops.reset = NULL;
102
11afc1b1
PW		 103 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
104 &data_offset);
105
106 if (ret_val != 0)
107 goto setup_sfp_out;
108
aa5aec88
PWJ		 109 /* PHY config will finish before releasing the semaphore */
110 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
111 if (ret_val != 0) {
112 ret_val = IXGBE_ERR_SWFW_SYNC;
113 goto setup_sfp_out;
114 }
115
11afc1b1
PW		 116 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
117 while (data_value != 0xffff) {
118 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
119 IXGBE_WRITE_FLUSH(hw);
120 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
121 }
1479ad4f
PWJ		 122 /* Now restart DSP by setting Restart_AN */
123 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
124 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
aa5aec88
PWJ		 125
126 /* Release the semaphore */
127 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
128 /* Delay obtaining semaphore again to allow FW access */
129 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 130 }
131
132setup_sfp_out:
133 return ret_val;
134}
135
136/**
137 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
138 * @hw: pointer to hardware structure
139 *
140 * Read PCIe configuration space, and get the MSI-X vector count from
141 * the capabilities table.
142 **/
7b25cdba 143static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 144{
145 struct ixgbe_adapter *adapter = hw->back;
146 u16 msix_count;
147 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
148 &msix_count);
149 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
150
151 /* MSI-X count is zero-based in HW, so increment to give proper value */
152 msix_count++;
153
154 return msix_count;
155}
156
157static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
158{
159 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 160
04f165ef 161 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 162
04f165ef
PW		 163 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
164 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
165 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
166 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
167 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
168 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
11afc1b1 169
04f165ef
PW		 170 return 0;
171}
11afc1b1 172
04f165ef
PW		 173/**
174 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
175 * @hw: pointer to hardware structure
176 *
177 * Initialize any function pointers that were not able to be
178 * set during get_invariants because the PHY/SFP type was
179 * not known. Perform the SFP init if necessary.
180 *
181 **/
7b25cdba 182static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 183{
184 struct ixgbe_mac_info *mac = &hw->mac;
185 struct ixgbe_phy_info *phy = &hw->phy;
186 s32 ret_val = 0;
11afc1b1 187
04f165ef
PW		 188 /* Identify the PHY or SFP module */
189 ret_val = phy->ops.identify(hw);
190
191 /* Setup function pointers based on detected SFP module and speeds */
192 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 193
194 /* If copper media, overwrite with copper function pointers */
195 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
196 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1
PW		 197 mac->ops.get_link_capabilities =
198 &ixgbe_get_copper_link_capabilities_82599;
199 }
200
04f165ef 201 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 202 switch (hw->phy.type) {
203 case ixgbe_phy_tn:
204 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
205 phy->ops.get_firmware_version =
04f165ef 206 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 207 break;
208 default:
209 break;
210 }
211
11afc1b1
PW		 212 return ret_val;
213}
214
215/**
216 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
217 * @hw: pointer to hardware structure
218 * @speed: pointer to link speed
219 * @negotiation: true when autoneg or autotry is enabled
220 *
221 * Determines the link capabilities by reading the AUTOC register.
222 **/
7b25cdba
DS		 223static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
224 ixgbe_link_speed *speed,
225 bool *negotiation)
11afc1b1
PW		 226{
227 s32 status = 0;
1eb99d5a 228 u32 autoc = 0;
11afc1b1 229
1eb99d5a
PW		 230 /*
231 * Determine link capabilities based on the stored value of AUTOC,
232 * which represents EEPROM defaults. If AUTOC value has not been
233 * stored, use the current register value.
234 */
235 if (hw->mac.orig_link_settings_stored)
236 autoc = hw->mac.orig_autoc;
237 else
238 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
239
240 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 241 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
242 *speed = IXGBE_LINK_SPEED_1GB_FULL;
243 *negotiation = false;
244 break;
245
246 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
247 *speed = IXGBE_LINK_SPEED_10GB_FULL;
248 *negotiation = false;
249 break;
250
251 case IXGBE_AUTOC_LMS_1G_AN:
252 *speed = IXGBE_LINK_SPEED_1GB_FULL;
253 *negotiation = true;
254 break;
255
256 case IXGBE_AUTOC_LMS_10G_SERIAL:
257 *speed = IXGBE_LINK_SPEED_10GB_FULL;
258 *negotiation = false;
259 break;
260
261 case IXGBE_AUTOC_LMS_KX4_KX_KR:
262 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
263 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 264 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 265 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 266 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 267 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 268 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 269 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
270 *negotiation = true;
271 break;
272
273 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
274 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 275 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 276 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 277 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 278 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 279 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 280 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
281 *negotiation = true;
282 break;
283
284 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
285 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
286 *negotiation = false;
287 break;
288
289 default:
290 status = IXGBE_ERR_LINK_SETUP;
291 goto out;
292 break;
293 }
294
295 if (hw->phy.multispeed_fiber) {
296 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
297 IXGBE_LINK_SPEED_1GB_FULL;
298 *negotiation = true;
299 }
300
301out:
302 return status;
303}
304
305/**
306 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
307 * @hw: pointer to hardware structure
308 * @speed: pointer to link speed
309 * @autoneg: boolean auto-negotiation value
310 *
311 * Determines the link capabilities by reading the AUTOC register.
312 **/
313static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
314 ixgbe_link_speed *speed,
315 bool *autoneg)
316{
317 s32 status = IXGBE_ERR_LINK_SETUP;
318 u16 speed_ability;
319
320 *speed = 0;
321 *autoneg = true;
322
6b73e10d 323 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 324 &speed_ability);
325
326 if (status == 0) {
6b73e10d 327 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 328 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 329 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 330 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
331 }
332
333 return status;
334}
335
336/**
337 * ixgbe_get_media_type_82599 - Get media type
338 * @hw: pointer to hardware structure
339 *
340 * Returns the media type (fiber, copper, backplane)
341 **/
7b25cdba 342static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 343{
344 enum ixgbe_media_type media_type;
345
346 /* Detect if there is a copper PHY attached. */
347 if (hw->phy.type == ixgbe_phy_cu_unknown ||
348 hw->phy.type == ixgbe_phy_tn) {
349 media_type = ixgbe_media_type_copper;
350 goto out;
351 }
352
353 switch (hw->device_id) {
11afc1b1 354 case IXGBE_DEV_ID_82599_KX4:
dbfec662 355 case IXGBE_DEV_ID_82599_KX4_MEZZ:
312eb931 356 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
74757d49 357 case IXGBE_DEV_ID_82599_KR:
1fcf03e6 358 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 359 /* Default device ID is mezzanine card KX/KX4 */
360 media_type = ixgbe_media_type_backplane;
361 break;
362 case IXGBE_DEV_ID_82599_SFP:
38ad1c8e 363 case IXGBE_DEV_ID_82599_SFP_EM:
11afc1b1
PW		 364 media_type = ixgbe_media_type_fiber;
365 break;
8911184f 366 case IXGBE_DEV_ID_82599_CX4:
6b1be199 367 media_type = ixgbe_media_type_cx4;
8911184f 368 break;
11afc1b1
PW		 369 default:
370 media_type = ixgbe_media_type_unknown;
371 break;
372 }
373out:
374 return media_type;
375}
376
377/**
8620a103 378 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 379 * @hw: pointer to hardware structure
8620a103 380 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 381 *
382 * Configures link settings based on values in the ixgbe_hw struct.
383 * Restarts the link. Performs autonegotiation if needed.
384 **/
8620a103
MC		 385s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
386 bool autoneg_wait_to_complete)
11afc1b1
PW		 387{
388 u32 autoc_reg;
389 u32 links_reg;
390 u32 i;
391 s32 status = 0;
392
393 /* Restart link */
394 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
395 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
396 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
397
398 /* Only poll for autoneg to complete if specified to do so */
8620a103 399 if (autoneg_wait_to_complete) {
11afc1b1
PW		 400 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
401 IXGBE_AUTOC_LMS_KX4_KX_KR ||
402 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
403 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
404 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
405 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
406 links_reg = 0; /* Just in case Autoneg time = 0 */
407 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
408 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
409 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
410 break;
411 msleep(100);
412 }
413 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
414 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
415 hw_dbg(hw, "Autoneg did not complete.\n");
416 }
417 }
418 }
419
11afc1b1
PW		 420 /* Add delay to filter out noises during initial link setup */
421 msleep(50);
422
423 return status;
424}
425
61fac744
PW		 426 /**
427 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
428 * @hw: pointer to hardware structure
429 *
430 * The base drivers may require better control over SFP+ module
431 * PHY states. This includes selectively shutting down the Tx
432 * laser on the PHY, effectively halting physical link.
433 **/
434void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
435{
436 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
437
438 /* Disable tx laser; allow 100us to go dark per spec */
439 esdp_reg |= IXGBE_ESDP_SDP3;
440 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
441 IXGBE_WRITE_FLUSH(hw);
442 udelay(100);
443}
444
445/**
446 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
447 * @hw: pointer to hardware structure
448 *
449 * The base drivers may require better control over SFP+ module
450 * PHY states. This includes selectively turning on the Tx
451 * laser on the PHY, effectively starting physical link.
452 **/
453void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
454{
455 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
456
457 /* Enable tx laser; allow 100ms to light up */
458 esdp_reg &= ~IXGBE_ESDP_SDP3;
459 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
460 IXGBE_WRITE_FLUSH(hw);
461 msleep(100);
462}
463
1097cd17
MC		 464/**
465 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
466 * @hw: pointer to hardware structure
467 *
468 * When the driver changes the link speeds that it can support,
469 * it sets autotry_restart to true to indicate that we need to
470 * initiate a new autotry session with the link partner. To do
471 * so, we set the speed then disable and re-enable the tx laser, to
472 * alert the link partner that it also needs to restart autotry on its
473 * end. This is consistent with true clause 37 autoneg, which also
474 * involves a loss of signal.
475 **/
476void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
477{
1097cd17
MC		 478 hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n");
479
480 if (hw->mac.autotry_restart) {
61fac744
PW		 481 ixgbe_disable_tx_laser_multispeed_fiber(hw);
482 ixgbe_enable_tx_laser_multispeed_fiber(hw);
1097cd17
MC		 483 hw->mac.autotry_restart = false;
484 }
485}
486
11afc1b1 487/**
8620a103 488 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 489 * @hw: pointer to hardware structure
490 * @speed: new link speed
491 * @autoneg: true if autonegotiation enabled
492 * @autoneg_wait_to_complete: true when waiting for completion is needed
493 *
494 * Set the link speed in the AUTOC register and restarts link.
495 **/
8620a103
MC		 496s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
497 ixgbe_link_speed speed,
498 bool autoneg,
499 bool autoneg_wait_to_complete)
11afc1b1
PW		 500{
501 s32 status = 0;
502 ixgbe_link_speed phy_link_speed;
503 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
504 u32 speedcnt = 0;
505 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
506 bool link_up = false;
507 bool negotiation;
50ac58ba 508 int i;
11afc1b1
PW		 509
510 /* Mask off requested but non-supported speeds */
511 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
512 speed &= phy_link_speed;
513
514 /*
515 * Try each speed one by one, highest priority first. We do this in
516 * software because 10gb fiber doesn't support speed autonegotiation.
517 */
518 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
519 speedcnt++;
520 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
521
50ac58ba
PWJ		 522 /* If we already have link at this speed, just jump out */
523 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
524
525 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
526 goto out;
527
528 /* Set the module link speed */
11afc1b1
PW		 529 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
530 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 531 IXGBE_WRITE_FLUSH(hw);
11afc1b1 532
50ac58ba
PWJ		 533 /* Allow module to change analog characteristics (1G->10G) */
534 msleep(40);
11afc1b1 535
8620a103
MC		 536 status = ixgbe_setup_mac_link_82599(hw,
537 IXGBE_LINK_SPEED_10GB_FULL,
538 autoneg,
539 autoneg_wait_to_complete);
50ac58ba 540 if (status != 0)
c3c74327 541 return status;
50ac58ba
PWJ		 542
543 /* Flap the tx laser if it has not already been done */
1097cd17 544 hw->mac.ops.flap_tx_laser(hw);
50ac58ba 545
cd7e1f0b
DS		 546 /*
547 * Wait for the controller to acquire link. Per IEEE 802.3ap,
548 * Section 73.10.2, we may have to wait up to 500ms if KR is
549 * attempted. 82599 uses the same timing for 10g SFI.
550 */
551
50ac58ba
PWJ		 552 for (i = 0; i < 5; i++) {
553 /* Wait for the link partner to also set speed */
554 msleep(100);
555
556 /* If we have link, just jump out */
557 hw->mac.ops.check_link(hw, &phy_link_speed,
558 &link_up, false);
559 if (link_up)
560 goto out;
561 }
11afc1b1
PW		 562 }
563
564 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
565 speedcnt++;
566 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
567 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
568
50ac58ba
PWJ		 569 /* If we already have link at this speed, just jump out */
570 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
571
572 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
573 goto out;
574
575 /* Set the module link speed */
11afc1b1
PW		 576 esdp_reg &= ~IXGBE_ESDP_SDP5;
577 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
578 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 579 IXGBE_WRITE_FLUSH(hw);
11afc1b1 580
50ac58ba
PWJ		 581 /* Allow module to change analog characteristics (10G->1G) */
582 msleep(40);
11afc1b1 583
8620a103 584 status = ixgbe_setup_mac_link_82599(hw,
50ac58ba
PWJ		 585 IXGBE_LINK_SPEED_1GB_FULL,
586 autoneg,
587 autoneg_wait_to_complete);
588 if (status != 0)
c3c74327 589 return status;
50ac58ba
PWJ		 590
591 /* Flap the tx laser if it has not already been done */
1097cd17 592 hw->mac.ops.flap_tx_laser(hw);
50ac58ba
PWJ		 593
594 /* Wait for the link partner to also set speed */
595 msleep(100);
11afc1b1
PW		 596
597 /* If we have link, just jump out */
598 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
599 if (link_up)
600 goto out;
601 }
602
603 /*
604 * We didn't get link. Configure back to the highest speed we tried,
605 * (if there was more than one). We call ourselves back with just the
606 * single highest speed that the user requested.
607 */
608 if (speedcnt > 1)
8620a103
MC		 609 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
610 highest_link_speed,
611 autoneg,
612 autoneg_wait_to_complete);
11afc1b1
PW		 613
614out:
c3c74327
MC		 615 /* Set autoneg_advertised value based on input link speed */
616 hw->phy.autoneg_advertised = 0;
617
618 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
619 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
620
621 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
622 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
623
11afc1b1
PW		 624 return status;
625}
626
cd7e1f0b
DS		 627/**
628 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
629 * @hw: pointer to hardware structure
630 * @speed: new link speed
631 * @autoneg: true if autonegotiation enabled
632 * @autoneg_wait_to_complete: true when waiting for completion is needed
633 *
634 * Implements the Intel SmartSpeed algorithm.
635 **/
636static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
637 ixgbe_link_speed speed, bool autoneg,
638 bool autoneg_wait_to_complete)
639{
640 s32 status = 0;
641 ixgbe_link_speed link_speed;
642 s32 i, j;
643 bool link_up = false;
644 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
645
646 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
647
648 /* Set autoneg_advertised value based on input link speed */
649 hw->phy.autoneg_advertised = 0;
650
651 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
652 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
653
654 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
655 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
656
657 if (speed & IXGBE_LINK_SPEED_100_FULL)
658 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
659
660 /*
661 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
662 * autoneg advertisement if link is unable to be established at the
663 * highest negotiated rate. This can sometimes happen due to integrity
664 * issues with the physical media connection.
665 */
666
667 /* First, try to get link with full advertisement */
668 hw->phy.smart_speed_active = false;
669 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
670 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
671 autoneg_wait_to_complete);
672 if (status)
673 goto out;
674
675 /*
676 * Wait for the controller to acquire link. Per IEEE 802.3ap,
677 * Section 73.10.2, we may have to wait up to 500ms if KR is
678 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
679 * Table 9 in the AN MAS.
680 */
681 for (i = 0; i < 5; i++) {
682 mdelay(100);
683
684 /* If we have link, just jump out */
685 hw->mac.ops.check_link(hw, &link_speed,
686 &link_up, false);
687 if (link_up)
688 goto out;
689 }
690 }
691
692 /*
693 * We didn't get link. If we advertised KR plus one of KX4/KX
694 * (or BX4/BX), then disable KR and try again.
695 */
696 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
697 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
698 goto out;
699
700 /* Turn SmartSpeed on to disable KR support */
701 hw->phy.smart_speed_active = true;
702 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
703 autoneg_wait_to_complete);
704 if (status)
705 goto out;
706
707 /*
708 * Wait for the controller to acquire link. 600ms will allow for
709 * the AN link_fail_inhibit_timer as well for multiple cycles of
710 * parallel detect, both 10g and 1g. This allows for the maximum
711 * connect attempts as defined in the AN MAS table 73-7.
712 */
713 for (i = 0; i < 6; i++) {
714 mdelay(100);
715
716 /* If we have link, just jump out */
717 hw->mac.ops.check_link(hw, &link_speed,
718 &link_up, false);
719 if (link_up)
720 goto out;
721 }
722
723 /* We didn't get link. Turn SmartSpeed back off. */
724 hw->phy.smart_speed_active = false;
725 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
726 autoneg_wait_to_complete);
727
728out:
729 return status;
730}
731
11afc1b1
PW		 732/**
733 * ixgbe_check_mac_link_82599 - Determine link and speed status
734 * @hw: pointer to hardware structure
735 * @speed: pointer to link speed
736 * @link_up: true when link is up
737 * @link_up_wait_to_complete: bool used to wait for link up or not
738 *
739 * Reads the links register to determine if link is up and the current speed
740 **/
7b25cdba
DS		 741static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
742 ixgbe_link_speed *speed,
743 bool *link_up,
744 bool link_up_wait_to_complete)
11afc1b1
PW		 745{
746 u32 links_reg;
747 u32 i;
748
749 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
750 if (link_up_wait_to_complete) {
751 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
752 if (links_reg & IXGBE_LINKS_UP) {
753 *link_up = true;
754 break;
755 } else {
756 *link_up = false;
757 }
758 msleep(100);
759 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
760 }
761 } else {
762 if (links_reg & IXGBE_LINKS_UP)
763 *link_up = true;
764 else
765 *link_up = false;
766 }
767
768 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
769 IXGBE_LINKS_SPEED_10G_82599)
770 *speed = IXGBE_LINK_SPEED_10GB_FULL;
771 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
772 IXGBE_LINKS_SPEED_1G_82599)
773 *speed = IXGBE_LINK_SPEED_1GB_FULL;
774 else
775 *speed = IXGBE_LINK_SPEED_100_FULL;
776
620fa036
MC		 777 /* if link is down, zero out the current_mode */
778 if (*link_up == false) {
779 hw->fc.current_mode = ixgbe_fc_none;
780 hw->fc.fc_was_autonegged = false;
781 }
11afc1b1
PW		 782
783 return 0;
784}
785
786/**
8620a103 787 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 788 * @hw: pointer to hardware structure
789 * @speed: new link speed
790 * @autoneg: true if autonegotiation enabled
791 * @autoneg_wait_to_complete: true when waiting for completion is needed
792 *
793 * Set the link speed in the AUTOC register and restarts link.
794 **/
8620a103
MC		 795s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
796 ixgbe_link_speed speed, bool autoneg,
797 bool autoneg_wait_to_complete)
11afc1b1
PW		 798{
799 s32 status = 0;
800 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
801 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 802 u32 start_autoc = autoc;
1eb99d5a 803 u32 orig_autoc = 0;
11afc1b1
PW		 804 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
805 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
806 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
807 u32 links_reg;
808 u32 i;
809 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
810
811 /* Check to see if speed passed in is supported. */
812 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
813 speed &= link_capabilities;
814
50ac58ba
PWJ		 815 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
816 status = IXGBE_ERR_LINK_SETUP;
817 goto out;
818 }
819
1eb99d5a
PW		 820 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
821 if (hw->mac.orig_link_settings_stored)
822 orig_autoc = hw->mac.orig_autoc;
823 else
824 orig_autoc = autoc;
825
826
50ac58ba
PWJ		 827 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
828 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
829 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 830 /* Set KX4/KX/KR support according to speed requested */
831 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
832 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 833 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 834 autoc |= IXGBE_AUTOC_KX4_SUPP;
cd7e1f0b
DS		 835 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
836 (hw->phy.smart_speed_active == false))
11afc1b1
PW		 837 autoc |= IXGBE_AUTOC_KR_SUPP;
838 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
839 autoc |= IXGBE_AUTOC_KX_SUPP;
840 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
841 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
842 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
843 /* Switch from 1G SFI to 10G SFI if requested */
844 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
845 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
846 autoc &= ~IXGBE_AUTOC_LMS_MASK;
847 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
848 }
849 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
850 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
851 /* Switch from 10G SFI to 1G SFI if requested */
852 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
853 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
854 autoc &= ~IXGBE_AUTOC_LMS_MASK;
855 if (autoneg)
856 autoc |= IXGBE_AUTOC_LMS_1G_AN;
857 else
858 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
859 }
860 }
861
50ac58ba 862 if (autoc != start_autoc) {
11afc1b1
PW		 863 /* Restart link */
864 autoc |= IXGBE_AUTOC_AN_RESTART;
865 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
866
867 /* Only poll for autoneg to complete if specified to do so */
868 if (autoneg_wait_to_complete) {
869 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
870 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
871 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
872 links_reg = 0; /*Just in case Autoneg time=0*/
873 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
874 links_reg =
875 IXGBE_READ_REG(hw, IXGBE_LINKS);
876 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
877 break;
878 msleep(100);
879 }
880 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
881 status =
882 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
883 hw_dbg(hw, "Autoneg did not "
884 "complete.\n");
885 }
886 }
887 }
888
11afc1b1
PW		 889 /* Add delay to filter out noises during initial link setup */
890 msleep(50);
891 }
892
50ac58ba 893out:
11afc1b1
PW		 894 return status;
895}
896
897/**
8620a103 898 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 899 * @hw: pointer to hardware structure
900 * @speed: new link speed
901 * @autoneg: true if autonegotiation enabled
902 * @autoneg_wait_to_complete: true if waiting is needed to complete
903 *
904 * Restarts link on PHY and MAC based on settings passed in.
905 **/
8620a103
MC		 906static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
907 ixgbe_link_speed speed,
908 bool autoneg,
909 bool autoneg_wait_to_complete)
11afc1b1
PW		 910{
911 s32 status;
912
913 /* Setup the PHY according to input speed */
914 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
915 autoneg_wait_to_complete);
916 /* Set up MAC */
8620a103 917 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 918
919 return status;
920}
921
922/**
923 * ixgbe_reset_hw_82599 - Perform hardware reset
924 * @hw: pointer to hardware structure
925 *
926 * Resets the hardware by resetting the transmit and receive units, masks
927 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
928 * reset.
929 **/
7b25cdba 930static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 931{
932 s32 status = 0;
c9205697 933 u32 ctrl;
11afc1b1
PW		 934 u32 i;
935 u32 autoc;
936 u32 autoc2;
937
938 /* Call adapter stop to disable tx/rx and clear interrupts */
939 hw->mac.ops.stop_adapter(hw);
940
553b4497 941 /* PHY ops must be identified and initialized prior to reset */
04f165ef 942
553b4497
PW		 943 /* Init PHY and function pointers, perform SFP setup */
944 status = hw->phy.ops.init(hw);
04f165ef 945
553b4497
PW		 946 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
947 goto reset_hw_out;
04f165ef 948
553b4497
PW		 949 /* Setup SFP module if there is one present. */
950 if (hw->phy.sfp_setup_needed) {
951 status = hw->mac.ops.setup_sfp(hw);
952 hw->phy.sfp_setup_needed = false;
04f165ef 953 }
11afc1b1 954
553b4497
PW		 955 /* Reset PHY */
956 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
957 hw->phy.ops.reset(hw);
958
11afc1b1
PW		 959 /*
960 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
961 * access and verify no pending requests before reset
962 */
04f165ef
PW		 963 status = ixgbe_disable_pcie_master(hw);
964 if (status != 0) {
11afc1b1
PW		 965 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
966 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
967 }
968
969 /*
970 * Issue global reset to the MAC. This needs to be a SW reset.
971 * If link reset is used, it might reset the MAC when mng is using it
972 */
973 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
974 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
975 IXGBE_WRITE_FLUSH(hw);
976
977 /* Poll for reset bit to self-clear indicating reset is complete */
978 for (i = 0; i < 10; i++) {
979 udelay(1);
980 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
981 if (!(ctrl & IXGBE_CTRL_RST))
982 break;
983 }
984 if (ctrl & IXGBE_CTRL_RST) {
985 status = IXGBE_ERR_RESET_FAILED;
986 hw_dbg(hw, "Reset polling failed to complete.\n");
987 }
11afc1b1
PW		 988
989 msleep(50);
990
11afc1b1
PW		 991 /*
992 * Store the original AUTOC/AUTOC2 values if they have not been
993 * stored off yet. Otherwise restore the stored original
994 * values since the reset operation sets back to defaults.
995 */
996 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
997 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
998 if (hw->mac.orig_link_settings_stored == false) {
999 hw->mac.orig_autoc = autoc;
1000 hw->mac.orig_autoc2 = autoc2;
1001 hw->mac.orig_link_settings_stored = true;
4df10466 1002 } else {
11afc1b1
PW		 1003 if (autoc != hw->mac.orig_autoc)
1004 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
1005 IXGBE_AUTOC_AN_RESTART));
1006
1007 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1008 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1009 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1010 autoc2 |= (hw->mac.orig_autoc2 &
1011 IXGBE_AUTOC2_UPPER_MASK);
1012 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1013 }
1014 }
1015
aca6bee7
WJP		 1016 /*
1017 * Store MAC address from RAR0, clear receive address registers, and
1018 * clear the multicast table. Also reset num_rar_entries to 128,
1019 * since we modify this value when programming the SAN MAC address.
1020 */
1021 hw->mac.num_rar_entries = 128;
1022 hw->mac.ops.init_rx_addrs(hw);
1023
11afc1b1
PW		 1024 /* Store the permanent mac address */
1025 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1026
0365e6e4
PW		 1027 /* Store the permanent SAN mac address */
1028 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1029
aca6bee7
WJP		 1030 /* Add the SAN MAC address to the RAR only if it's a valid address */
1031 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1032 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1033 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1034
1035 /* Reserve the last RAR for the SAN MAC address */
1036 hw->mac.num_rar_entries--;
1037 }
1038
383ff34b
YZ		 1039 /* Store the alternative WWNN/WWPN prefix */
1040 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1041 &hw->mac.wwpn_prefix);
1042
04f165ef 1043reset_hw_out:
11afc1b1
PW		 1044 return status;
1045}
1046
1047/**
1048 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
1049 * @hw: pointer to hardware struct
1050 * @rar: receive address register index to disassociate
1051 * @vmdq: VMDq pool index to remove from the rar
1052 **/
7b25cdba 1053static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 1054{
1055 u32 mpsar_lo, mpsar_hi;
1056 u32 rar_entries = hw->mac.num_rar_entries;
1057
1058 if (rar < rar_entries) {
1059 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1060 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1061
1062 if (!mpsar_lo && !mpsar_hi)
1063 goto done;
1064
1065 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
1066 if (mpsar_lo) {
1067 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
1068 mpsar_lo = 0;
1069 }
1070 if (mpsar_hi) {
1071 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
1072 mpsar_hi = 0;
1073 }
1074 } else if (vmdq < 32) {
1075 mpsar_lo &= ~(1 << vmdq);
1076 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
1077 } else {
1078 mpsar_hi &= ~(1 << (vmdq - 32));
1079 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
1080 }
1081
1082 /* was that the last pool using this rar? */
1083 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
1084 hw->mac.ops.clear_rar(hw, rar);
1085 } else {
1086 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1087 }
1088
1089done:
1090 return 0;
1091}
1092
1093/**
1094 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
1095 * @hw: pointer to hardware struct
1096 * @rar: receive address register index to associate with a VMDq index
1097 * @vmdq: VMDq pool index
1098 **/
7b25cdba 1099static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 1100{
1101 u32 mpsar;
1102 u32 rar_entries = hw->mac.num_rar_entries;
1103
1104 if (rar < rar_entries) {
1105 if (vmdq < 32) {
1106 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1107 mpsar |= 1 << vmdq;
1108 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
1109 } else {
1110 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1111 mpsar |= 1 << (vmdq - 32);
1112 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
1113 }
1114 } else {
1115 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1116 }
1117 return 0;
1118}
1119
1120/**
1121 * ixgbe_set_vfta_82599 - Set VLAN filter table
1122 * @hw: pointer to hardware structure
1123 * @vlan: VLAN id to write to VLAN filter
1124 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1125 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1126 *
1127 * Turn on/off specified VLAN in the VLAN filter table.
1128 **/
7b25cdba
DS		 1129static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1130 bool vlan_on)
11afc1b1
PW		 1131{
1132 u32 regindex;
096a58fd 1133 u32 vlvf_index;
11afc1b1
PW		 1134 u32 bitindex;
1135 u32 bits;
1136 u32 first_empty_slot;
096a58fd 1137 u32 vt_ctl;
11afc1b1
PW		 1138
1139 if (vlan > 4095)
1140 return IXGBE_ERR_PARAM;
1141
1142 /*
1143 * this is a 2 part operation - first the VFTA, then the
1144 * VLVF and VLVFB if vind is set
1145 */
1146
1147 /* Part 1
1148 * The VFTA is a bitstring made up of 128 32-bit registers
1149 * that enable the particular VLAN id, much like the MTA:
1150 * bits[11-5]: which register
1151 * bits[4-0]: which bit in the register
1152 */
1153 regindex = (vlan >> 5) & 0x7F;
1154 bitindex = vlan & 0x1F;
1155 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1156 if (vlan_on)
1157 bits |= (1 << bitindex);
1158 else
1159 bits &= ~(1 << bitindex);
1160 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1161
1162
1163 /* Part 2
096a58fd 1164 * If VT mode is set
11afc1b1
PW		 1165 * Either vlan_on
1166 * make sure the vlan is in VLVF
1167 * set the vind bit in the matching VLVFB
1168 * Or !vlan_on
1169 * clear the pool bit and possibly the vind
1170 */
096a58fd
GR		 1171 vt_ctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1172 if (!(vt_ctl & IXGBE_VT_CTL_VT_ENABLE))
1173 goto out;
11afc1b1 1174
096a58fd
GR		 1175 /* find the vlanid or the first empty slot */
1176 first_empty_slot = 0;
1177
1178 for (vlvf_index = 1; vlvf_index < IXGBE_VLVF_ENTRIES; vlvf_index++) {
1179 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(vlvf_index));
1180 if (!bits && !first_empty_slot)
1181 first_empty_slot = vlvf_index;
1182 else if ((bits & 0x0FFF) == vlan)
1183 break;
1184 }
1185
1186 if (vlvf_index >= IXGBE_VLVF_ENTRIES) {
1187 if (first_empty_slot)
1188 vlvf_index = first_empty_slot;
1189 else {
1190 hw_dbg(hw, "No space in VLVF.\n");
1191 goto out;
11afc1b1 1192 }
096a58fd 1193 }
11afc1b1 1194
096a58fd
GR		 1195 if (vlan_on) {
1196 /* set the pool bit */
1197 if (vind < 32) {
1198 bits = IXGBE_READ_REG(hw,
1199 IXGBE_VLVFB(vlvf_index * 2));
1200 bits |= (1 << vind);
1201 IXGBE_WRITE_REG(hw,
1202 IXGBE_VLVFB(vlvf_index * 2), bits);
11afc1b1 1203 } else {
096a58fd
GR		 1204 bits = IXGBE_READ_REG(hw,
1205 IXGBE_VLVFB((vlvf_index * 2) + 1));
1206 bits |= (1 << (vind - 32));
1207 IXGBE_WRITE_REG(hw,
1208 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1209 }
1210 } else {
1211 /* clear the pool bit */
1212 if (vind < 32) {
1213 bits = IXGBE_READ_REG(hw,
1214 IXGBE_VLVFB(vlvf_index * 2));
11afc1b1 1215 bits &= ~(1 << vind);
096a58fd
GR		 1216 IXGBE_WRITE_REG(hw,
1217 IXGBE_VLVFB(vlvf_index * 2), bits);
1218 bits |= IXGBE_READ_REG(hw,
1219 IXGBE_VLVFB((vlvf_index * 2) + 1));
1220 } else {
1221 bits = IXGBE_READ_REG(hw,
1222 IXGBE_VLVFB((vlvf_index * 2) + 1));
1223 bits &= ~(1 << (vind - 32));
1224 IXGBE_WRITE_REG(hw,
1225 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1226 bits |= IXGBE_READ_REG(hw,
1227 IXGBE_VLVFB(vlvf_index * 2));
11afc1b1 1228 }
096a58fd 1229 }
11afc1b1 1230
096a58fd
GR		 1231 if (bits) {
1232 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
1233 (IXGBE_VLVF_VIEN | vlan));
1234 /* if bits is non-zero then some pools/VFs are still
1235 * using this VLAN ID. Force the VFTA entry to on */
1236 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1237 bits |= (1 << bitindex);
1238 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
11afc1b1 1239 }
096a58fd
GR		 1240 else
1241 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
11afc1b1
PW		 1242
1243out:
1244 return 0;
1245}
1246
1247/**
1248 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1249 * @hw: pointer to hardware structure
1250 *
1251 * Clears the VLAN filer table, and the VMDq index associated with the filter
1252 **/
7b25cdba 1253static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1254{
1255 u32 offset;
1256
1257 for (offset = 0; offset < hw->mac.vft_size; offset++)
1258 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1259
1260 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1261 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1262 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1263 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1264 }
1265
1266 return 0;
1267}
1268
11afc1b1
PW		 1269/**
1270 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1271 * @hw: pointer to hardware structure
1272 **/
7b25cdba 1273static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1274{
1275 int i;
1276 hw_dbg(hw, " Clearing UTA\n");
1277
1278 for (i = 0; i < 128; i++)
1279 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1280
1281 return 0;
1282}
1283
ffff4772
PWJ		 1284/**
1285 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1286 * @hw: pointer to hardware structure
1287 **/
1288s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1289{
1290 int i;
1291 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1292 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1293
1294 /*
1295 * Before starting reinitialization process,
1296 * FDIRCMD.CMD must be zero.
1297 */
1298 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1299 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1300 IXGBE_FDIRCMD_CMD_MASK))
1301 break;
1302 udelay(10);
1303 }
1304 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1305 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1306 "aborting table re-initialization. \n");
1307 return IXGBE_ERR_FDIR_REINIT_FAILED;
1308 }
1309
1310 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1311 IXGBE_WRITE_FLUSH(hw);
1312 /*
1313 * 82599 adapters flow director init flow cannot be restarted,
1314 * Workaround 82599 silicon errata by performing the following steps
1315 * before re-writing the FDIRCTRL control register with the same value.
1316 * - write 1 to bit 8 of FDIRCMD register &
1317 * - write 0 to bit 8 of FDIRCMD register
1318 */
1319 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1320 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1321 IXGBE_FDIRCMD_CLEARHT));
1322 IXGBE_WRITE_FLUSH(hw);
1323 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1324 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1325 ~IXGBE_FDIRCMD_CLEARHT));
1326 IXGBE_WRITE_FLUSH(hw);
1327 /*
1328 * Clear FDIR Hash register to clear any leftover hashes
1329 * waiting to be programmed.
1330 */
1331 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1332 IXGBE_WRITE_FLUSH(hw);
1333
1334 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1335 IXGBE_WRITE_FLUSH(hw);
1336
1337 /* Poll init-done after we write FDIRCTRL register */
1338 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1339 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1340 IXGBE_FDIRCTRL_INIT_DONE)
1341 break;
1342 udelay(10);
1343 }
1344 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1345 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1346 return IXGBE_ERR_FDIR_REINIT_FAILED;
1347 }
1348
1349 /* Clear FDIR statistics registers (read to clear) */
1350 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1351 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1352 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1353 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1354 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1355
1356 return 0;
1357}
1358
1359/**
1360 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1361 * @hw: pointer to hardware structure
1362 * @pballoc: which mode to allocate filters with
1363 **/
1364s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1365{
1366 u32 fdirctrl = 0;
1367 u32 pbsize;
1368 int i;
1369
1370 /*
1371 * Before enabling Flow Director, the Rx Packet Buffer size
1372 * must be reduced. The new value is the current size minus
1373 * flow director memory usage size.
1374 */
1375 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1376 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1377 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1378
1379 /*
1380 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1381 * intialized to zero for non DCB mode otherwise actual total RX PB
1382 * would be bigger than programmed and filter space would run into
1383 * the PB 0 region.
1384 */
1385 for (i = 1; i < 8; i++)
1386 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1387
1388 /* Send interrupt when 64 filters are left */
1389 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1390
1391 /* Set the maximum length per hash bucket to 0xA filters */
1392 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1393
1394 switch (pballoc) {
1395 case IXGBE_FDIR_PBALLOC_64K:
1396 /* 8k - 1 signature filters */
1397 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1398 break;
1399 case IXGBE_FDIR_PBALLOC_128K:
1400 /* 16k - 1 signature filters */
1401 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1402 break;
1403 case IXGBE_FDIR_PBALLOC_256K:
1404 /* 32k - 1 signature filters */
1405 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1406 break;
1407 default:
1408 /* bad value */
1409 return IXGBE_ERR_CONFIG;
1410 };
1411
1412 /* Move the flexible bytes to use the ethertype - shift 6 words */
1413 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1414
1415 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1416
1417 /* Prime the keys for hashing */
1418 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1419 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1420 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1421 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1422
1423 /*
1424 * Poll init-done after we write the register. Estimated times:
1425 * 10G: PBALLOC = 11b, timing is 60us
1426 * 1G: PBALLOC = 11b, timing is 600us
1427 * 100M: PBALLOC = 11b, timing is 6ms
1428 *
1429 * Multiple these timings by 4 if under full Rx load
1430 *
1431 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1432 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1433 * this might not finish in our poll time, but we can live with that
1434 * for now.
1435 */
1436 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1437 IXGBE_WRITE_FLUSH(hw);
1438 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1439 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1440 IXGBE_FDIRCTRL_INIT_DONE)
1441 break;
1442 msleep(1);
1443 }
1444 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1445 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1446
1447 return 0;
1448}
1449
1450/**
1451 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1452 * @hw: pointer to hardware structure
1453 * @pballoc: which mode to allocate filters with
1454 **/
1455s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1456{
1457 u32 fdirctrl = 0;
1458 u32 pbsize;
1459 int i;
1460
1461 /*
1462 * Before enabling Flow Director, the Rx Packet Buffer size
1463 * must be reduced. The new value is the current size minus
1464 * flow director memory usage size.
1465 */
1466 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1467 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1468 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1469
1470 /*
1471 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1472 * intialized to zero for non DCB mode otherwise actual total RX PB
1473 * would be bigger than programmed and filter space would run into
1474 * the PB 0 region.
1475 */
1476 for (i = 1; i < 8; i++)
1477 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1478
1479 /* Send interrupt when 64 filters are left */
1480 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1481
9a713e7c
PW		 1482 /* Initialize the drop queue to Rx queue 127 */
1483 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1484
ffff4772
PWJ		 1485 switch (pballoc) {
1486 case IXGBE_FDIR_PBALLOC_64K:
1487 /* 2k - 1 perfect filters */
1488 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1489 break;
1490 case IXGBE_FDIR_PBALLOC_128K:
1491 /* 4k - 1 perfect filters */
1492 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1493 break;
1494 case IXGBE_FDIR_PBALLOC_256K:
1495 /* 8k - 1 perfect filters */
1496 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1497 break;
1498 default:
1499 /* bad value */
1500 return IXGBE_ERR_CONFIG;
1501 };
1502
1503 /* Turn perfect match filtering on */
1504 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1505 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1506
1507 /* Move the flexible bytes to use the ethertype - shift 6 words */
1508 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1509
1510 /* Prime the keys for hashing */
1511 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1512 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1513 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1514 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1515
1516 /*
1517 * Poll init-done after we write the register. Estimated times:
1518 * 10G: PBALLOC = 11b, timing is 60us
1519 * 1G: PBALLOC = 11b, timing is 600us
1520 * 100M: PBALLOC = 11b, timing is 6ms
1521 *
1522 * Multiple these timings by 4 if under full Rx load
1523 *
1524 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1525 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1526 * this might not finish in our poll time, but we can live with that
1527 * for now.
1528 */
1529
1530 /* Set the maximum length per hash bucket to 0xA filters */
1531 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1532
1533 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1534 IXGBE_WRITE_FLUSH(hw);
1535 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1536 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1537 IXGBE_FDIRCTRL_INIT_DONE)
1538 break;
1539 msleep(1);
1540 }
1541 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1542 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1543
1544 return 0;
1545}
1546
1547
1548/**
1549 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1550 * @stream: input bitstream to compute the hash on
1551 * @key: 32-bit hash key
1552 **/
7b25cdba
DS		 1553static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1554 u32 key)
ffff4772
PWJ		 1555{
1556 /*
1557 * The algorithm is as follows:
1558 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1559 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1560 * and A[n] x B[n] is bitwise AND between same length strings
1561 *
1562 * K[n] is 16 bits, defined as:
1563 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1564 * for n modulo 32 < 15, K[n] =
1565 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1566 *
1567 * S[n] is 16 bits, defined as:
1568 * for n >= 15, S[n] = S[n:n - 15]
1569 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1570 *
1571 * To simplify for programming, the algorithm is implemented
1572 * in software this way:
1573 *
1574 * Key[31:0], Stream[335:0]
1575 *
1576 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1577 * int_key[350:0] = tmp_key[351:1]
1578 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1579 *
1580 * hash[15:0] = 0;
1581 * for (i = 0; i < 351; i++) {
1582 * if (int_key[i])
1583 * hash ^= int_stream[(i + 15):i];
1584 * }
1585 */
1586
1587 union {
1588 u64 fill[6];
1589 u32 key[11];
1590 u8 key_stream[44];
1591 } tmp_key;
1592
1593 u8 *stream = (u8 *)atr_input;
1594 u8 int_key[44]; /* upper-most bit unused */
1595 u8 hash_str[46]; /* upper-most 2 bits unused */
1596 u16 hash_result = 0;
1597 int i, j, k, h;
1598
1599 /*
1600 * Initialize the fill member to prevent warnings
1601 * on some compilers
1602 */
1603 tmp_key.fill[0] = 0;
1604
1605 /* First load the temporary key stream */
1606 for (i = 0; i < 6; i++) {
1607 u64 fillkey = ((u64)key << 32) | key;
1608 tmp_key.fill[i] = fillkey;
1609 }
1610
1611 /*
1612 * Set the interim key for the hashing. Bit 352 is unused, so we must
1613 * shift and compensate when building the key.
1614 */
1615
1616 int_key[0] = tmp_key.key_stream[0] >> 1;
1617 for (i = 1, j = 0; i < 44; i++) {
1618 unsigned int this_key = tmp_key.key_stream[j] << 7;
1619 j++;
1620 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1621 }
1622
1623 /*
1624 * Set the interim bit string for the hashing. Bits 368 and 367 are
1625 * unused, so shift and compensate when building the string.
1626 */
1627 hash_str[0] = (stream[40] & 0x7f) >> 1;
1628 for (i = 1, j = 40; i < 46; i++) {
1629 unsigned int this_str = stream[j] << 7;
1630 j++;
1631 if (j > 41)
1632 j = 0;
1633 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1634 }
1635
1636 /*
1637 * Now compute the hash. i is the index into hash_str, j is into our
1638 * key stream, k is counting the number of bits, and h interates within
1639 * each byte.
1640 */
1641 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1642 for (h = 0; h < 8 && k < 351; h++, k++) {
1643 if (int_key[j] & (1 << h)) {
1644 /*
1645 * Key bit is set, XOR in the current 16-bit
1646 * string. Example of processing:
1647 * h = 0,
1648 * tmp = (hash_str[i - 2] & 0 << 16) |
1649 * (hash_str[i - 1] & 0xff << 8) |
1650 * (hash_str[i] & 0xff >> 0)
1651 * So tmp = hash_str[15 + k:k], since the
1652 * i + 2 clause rolls off the 16-bit value
1653 * h = 7,
1654 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1655 * (hash_str[i - 1] & 0xff << 1) |
1656 * (hash_str[i] & 0x80 >> 7)
1657 */
1658 int tmp = (hash_str[i] >> h);
1659 tmp |= (hash_str[i - 1] << (8 - h));
1660 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1661 << (16 - h);
1662 hash_result ^= (u16)tmp;
1663 }
1664 }
1665 }
1666
1667 return hash_result;
1668}
1669
1670/**
1671 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1672 * @input: input stream to modify
1673 * @vlan: the VLAN id to load
1674 **/
1675s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1676{
1677 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1678 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1679
1680 return 0;
1681}
1682
1683/**
1684 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1685 * @input: input stream to modify
1686 * @src_addr: the IP address to load
1687 **/
1688s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1689{
1690 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1691 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1692 (src_addr >> 16) & 0xff;
1693 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1694 (src_addr >> 8) & 0xff;
1695 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1696
1697 return 0;
1698}
1699
1700/**
1701 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1702 * @input: input stream to modify
1703 * @dst_addr: the IP address to load
1704 **/
1705s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1706{
1707 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1708 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1709 (dst_addr >> 16) & 0xff;
1710 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1711 (dst_addr >> 8) & 0xff;
1712 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1713
1714 return 0;
1715}
1716
1717/**
1718 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1719 * @input: input stream to modify
1720 * @src_addr_1: the first 4 bytes of the IP address to load
1721 * @src_addr_2: the second 4 bytes of the IP address to load
1722 * @src_addr_3: the third 4 bytes of the IP address to load
1723 * @src_addr_4: the fourth 4 bytes of the IP address to load
1724 **/
1725s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
9a713e7c
PW		 1726 u32 src_addr_1, u32 src_addr_2,
1727 u32 src_addr_3, u32 src_addr_4)
ffff4772
PWJ		 1728{
1729 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1730 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1731 (src_addr_4 >> 8) & 0xff;
1732 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1733 (src_addr_4 >> 16) & 0xff;
1734 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1735
1736 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1737 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1738 (src_addr_3 >> 8) & 0xff;
1739 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1740 (src_addr_3 >> 16) & 0xff;
1741 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1742
1743 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1744 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1745 (src_addr_2 >> 8) & 0xff;
1746 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1747 (src_addr_2 >> 16) & 0xff;
1748 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1749
1750 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1751 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1752 (src_addr_1 >> 8) & 0xff;
1753 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1754 (src_addr_1 >> 16) & 0xff;
1755 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1756
1757 return 0;
1758}
1759
1760/**
1761 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1762 * @input: input stream to modify
1763 * @dst_addr_1: the first 4 bytes of the IP address to load
1764 * @dst_addr_2: the second 4 bytes of the IP address to load
1765 * @dst_addr_3: the third 4 bytes of the IP address to load
1766 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1767 **/
1768s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
9a713e7c
PW		 1769 u32 dst_addr_1, u32 dst_addr_2,
1770 u32 dst_addr_3, u32 dst_addr_4)
ffff4772
PWJ		 1771{
1772 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1773 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1774 (dst_addr_4 >> 8) & 0xff;
1775 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1776 (dst_addr_4 >> 16) & 0xff;
1777 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1778
1779 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1780 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1781 (dst_addr_3 >> 8) & 0xff;
1782 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1783 (dst_addr_3 >> 16) & 0xff;
1784 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1785
1786 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1787 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1788 (dst_addr_2 >> 8) & 0xff;
1789 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1790 (dst_addr_2 >> 16) & 0xff;
1791 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1792
1793 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1794 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1795 (dst_addr_1 >> 8) & 0xff;
1796 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1797 (dst_addr_1 >> 16) & 0xff;
1798 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1799
1800 return 0;
1801}
1802
1803/**
1804 * ixgbe_atr_set_src_port_82599 - Sets the source port
1805 * @input: input stream to modify
1806 * @src_port: the source port to load
1807 **/
1808s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1809{
1810 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1811 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1812
1813 return 0;
1814}
1815
1816/**
1817 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1818 * @input: input stream to modify
1819 * @dst_port: the destination port to load
1820 **/
1821s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1822{
1823 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1824 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1825
1826 return 0;
1827}
1828
1829/**
1830 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1831 * @input: input stream to modify
1832 * @flex_bytes: the flexible bytes to load
1833 **/
1834s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1835{
1836 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1837 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1838
1839 return 0;
1840}
1841
1842/**
1843 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1844 * @input: input stream to modify
1845 * @vm_pool: the Virtual Machine pool to load
1846 **/
7b25cdba 1847s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
9a713e7c 1848 u8 vm_pool)
ffff4772
PWJ		 1849{
1850 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1851
1852 return 0;
1853}
1854
1855/**
1856 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1857 * @input: input stream to modify
1858 * @l4type: the layer 4 type value to load
1859 **/
1860s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1861{
1862 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1863
1864 return 0;
1865}
1866
1867/**
1868 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1869 * @input: input stream to search
1870 * @vlan: the VLAN id to load
1871 **/
9a713e7c 1872static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
ffff4772
PWJ		 1873{
1874 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1875 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1876
1877 return 0;
1878}
1879
1880/**
1881 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1882 * @input: input stream to search
1883 * @src_addr: the IP address to load
1884 **/
7b25cdba
DS		 1885static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1886 u32 *src_addr)
ffff4772
PWJ		 1887{
1888 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1889 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1890 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1891 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1892
1893 return 0;
1894}
1895
1896/**
1897 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1898 * @input: input stream to search
1899 * @dst_addr: the IP address to load
1900 **/
7b25cdba
DS		 1901static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1902 u32 *dst_addr)
ffff4772
PWJ		 1903{
1904 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1905 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1906 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1907 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1908
1909 return 0;
1910}
1911
1912/**
1913 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1914 * @input: input stream to search
1915 * @src_addr_1: the first 4 bytes of the IP address to load
1916 * @src_addr_2: the second 4 bytes of the IP address to load
1917 * @src_addr_3: the third 4 bytes of the IP address to load
1918 * @src_addr_4: the fourth 4 bytes of the IP address to load
1919 **/
7b25cdba
DS		 1920static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1921 u32 *src_addr_1, u32 *src_addr_2,
1922 u32 *src_addr_3, u32 *src_addr_4)
ffff4772
PWJ		 1923{
1924 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1925 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1926 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1927 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1928
1929 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1930 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1931 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1932 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1933
1934 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1935 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1936 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1937 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1938
1939 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1940 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1941 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1942 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1943
1944 return 0;
1945}
1946
1947/**
1948 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1949 * @input: input stream to search
1950 * @dst_addr_1: the first 4 bytes of the IP address to load
1951 * @dst_addr_2: the second 4 bytes of the IP address to load
1952 * @dst_addr_3: the third 4 bytes of the IP address to load
1953 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1954 **/
1955s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1956 u32 *dst_addr_1, u32 *dst_addr_2,
1957 u32 *dst_addr_3, u32 *dst_addr_4)
ffff4772
PWJ		 1958{
1959 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1960 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1961 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1962 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1963
1964 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1965 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1966 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1967 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1968
1969 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1970 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1971 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1972 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1973
1974 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1975 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1976 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1977 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1978
1979 return 0;
1980}
1981
1982/**
1983 * ixgbe_atr_get_src_port_82599 - Gets the source port
1984 * @input: input stream to modify
1985 * @src_port: the source port to load
1986 *
1987 * Even though the input is given in big-endian, the FDIRPORT registers
1988 * expect the ports to be programmed in little-endian. Hence the need to swap
1989 * endianness when retrieving the data. This can be confusing since the
1990 * internal hash engine expects it to be big-endian.
1991 **/
7b25cdba
DS		 1992static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1993 u16 *src_port)
ffff4772
PWJ		 1994{
1995 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1996 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1997
1998 return 0;
1999}
2000
2001/**
2002 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
2003 * @input: input stream to modify
2004 * @dst_port: the destination port to load
2005 *
2006 * Even though the input is given in big-endian, the FDIRPORT registers
2007 * expect the ports to be programmed in little-endian. Hence the need to swap
2008 * endianness when retrieving the data. This can be confusing since the
2009 * internal hash engine expects it to be big-endian.
2010 **/
7b25cdba
DS		 2011static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
2012 u16 *dst_port)
ffff4772
PWJ		 2013{
2014 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
2015 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
2016
2017 return 0;
2018}
2019
2020/**
2021 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
2022 * @input: input stream to modify
2023 * @flex_bytes: the flexible bytes to load
2024 **/
7b25cdba
DS		 2025static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
2026 u16 *flex_byte)
ffff4772
PWJ		 2027{
2028 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
2029 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
2030
2031 return 0;
2032}
2033
2034/**
2035 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
2036 * @input: input stream to modify
2037 * @vm_pool: the Virtual Machine pool to load
2038 **/
7b25cdba
DS		 2039s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
2040 u8 *vm_pool)
ffff4772
PWJ		 2041{
2042 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
2043
2044 return 0;
2045}
2046
2047/**
2048 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
2049 * @input: input stream to modify
2050 * @l4type: the layer 4 type value to load
2051 **/
7b25cdba
DS		 2052static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
2053 u8 *l4type)
ffff4772
PWJ		 2054{
2055 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
2056
2057 return 0;
2058}
2059
2060/**
2061 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
2062 * @hw: pointer to hardware structure
2063 * @stream: input bitstream
2064 * @queue: queue index to direct traffic to
2065 **/
2066s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
2067 struct ixgbe_atr_input *input,
2068 u8 queue)
2069{
2070 u64 fdirhashcmd;
2071 u64 fdircmd;
2072 u32 fdirhash;
2073 u16 bucket_hash, sig_hash;
2074 u8 l4type;
2075
2076 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2077 IXGBE_ATR_BUCKET_HASH_KEY);
2078
2079 /* bucket_hash is only 15 bits */
2080 bucket_hash &= IXGBE_ATR_HASH_MASK;
2081
2082 sig_hash = ixgbe_atr_compute_hash_82599(input,
2083 IXGBE_ATR_SIGNATURE_HASH_KEY);
2084
2085 /* Get the l4type in order to program FDIRCMD properly */
2086 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
2087 ixgbe_atr_get_l4type_82599(input, &l4type);
2088
2089 /*
2090 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
2091 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
2092 */
2093 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2094
2095 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
2096 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
2097
2098 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2099 case IXGBE_ATR_L4TYPE_TCP:
2100 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2101 break;
2102 case IXGBE_ATR_L4TYPE_UDP:
2103 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2104 break;
2105 case IXGBE_ATR_L4TYPE_SCTP:
2106 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2107 break;
2108 default:
2109 hw_dbg(hw, "Error on l4type input\n");
2110 return IXGBE_ERR_CONFIG;
2111 }
2112
2113 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
2114 fdircmd |= IXGBE_FDIRCMD_IPV6;
2115
2116 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
2117 fdirhashcmd = ((fdircmd << 32) | fdirhash);
2118
2119 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
2120
2121 return 0;
2122}
2123
2124/**
2125 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2126 * @hw: pointer to hardware structure
2127 * @input: input bitstream
9a713e7c
PW		 2128 * @input_masks: bitwise masks for relevant fields
2129 * @soft_id: software index into the silicon hash tables for filter storage
ffff4772
PWJ		 2130 * @queue: queue index to direct traffic to
2131 *
2132 * Note that the caller to this function must lock before calling, since the
2133 * hardware writes must be protected from one another.
2134 **/
2135s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
9a713e7c
PW		 2136 struct ixgbe_atr_input *input,
2137 struct ixgbe_atr_input_masks *input_masks,
2138 u16 soft_id, u8 queue)
ffff4772
PWJ		 2139{
2140 u32 fdircmd = 0;
2141 u32 fdirhash;
9a713e7c 2142 u32 src_ipv4 = 0, dst_ipv4 = 0;
ffff4772
PWJ		 2143 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
2144 u16 src_port, dst_port, vlan_id, flex_bytes;
2145 u16 bucket_hash;
2146 u8 l4type;
9a713e7c 2147 u8 fdirm = 0;
ffff4772
PWJ		 2148
2149 /* Get our input values */
2150 ixgbe_atr_get_l4type_82599(input, &l4type);
2151
2152 /*
2153 * Check l4type formatting, and bail out before we touch the hardware
2154 * if there's a configuration issue
2155 */
2156 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2157 case IXGBE_ATR_L4TYPE_TCP:
2158 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2159 break;
2160 case IXGBE_ATR_L4TYPE_UDP:
2161 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2162 break;
2163 case IXGBE_ATR_L4TYPE_SCTP:
2164 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2165 break;
2166 default:
2167 hw_dbg(hw, "Error on l4type input\n");
2168 return IXGBE_ERR_CONFIG;
2169 }
2170
2171 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2172 IXGBE_ATR_BUCKET_HASH_KEY);
2173
2174 /* bucket_hash is only 15 bits */
2175 bucket_hash &= IXGBE_ATR_HASH_MASK;
2176
2177 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
2178 ixgbe_atr_get_src_port_82599(input, &src_port);
2179 ixgbe_atr_get_dst_port_82599(input, &dst_port);
2180 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
2181
2182 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2183
2184 /* Now figure out if we're IPv4 or IPv6 */
2185 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2186 /* IPv6 */
2187 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2188 &src_ipv6_3, &src_ipv6_4);
2189
2190 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2191 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2192 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2193 /* The last 4 bytes is the same register as IPv4 */
2194 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2195
2196 fdircmd |= IXGBE_FDIRCMD_IPV6;
2197 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2198 } else {
2199 /* IPv4 */
2200 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2201 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
ffff4772
PWJ		 2202 }
2203
2204 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2205 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2206
2207 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2208 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2209 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
9a713e7c
PW		 2210 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2211
2212 /*
2213 * Program the relevant mask registers. If src/dst_port or src/dst_addr
2214 * are zero, then assume a full mask for that field. Also assume that
2215 * a VLAN of 0 is unspecified, so mask that out as well. L4type
2216 * cannot be masked out in this implementation.
2217 *
2218 * This also assumes IPv4 only. IPv6 masking isn't supported at this
2219 * point in time.
2220 */
2221 if (src_ipv4 == 0)
2222 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xffffffff);
2223 else
2224 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
2225
2226 if (dst_ipv4 == 0)
2227 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xffffffff);
2228 else
2229 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
2230
2231 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2232 case IXGBE_ATR_L4TYPE_TCP:
2233 if (src_port == 0)
2234 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xffff);
2235 else
2236 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
2237 input_masks->src_port_mask);
2238
2239 if (dst_port == 0)
2240 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
2241 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
2242 (0xffff << 16)));
2243 else
2244 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
2245 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
2246 (input_masks->dst_port_mask << 16)));
2247 break;
2248 case IXGBE_ATR_L4TYPE_UDP:
2249 if (src_port == 0)
2250 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xffff);
2251 else
2252 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
2253 input_masks->src_port_mask);
2254
2255 if (dst_port == 0)
2256 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
2257 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
2258 (0xffff << 16)));
2259 else
2260 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
2261 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
2262 (input_masks->src_port_mask << 16)));
2263 break;
2264 default:
2265 /* this already would have failed above */
2266 break;
2267 }
2268
2269 /* Program the last mask register, FDIRM */
2270 if (input_masks->vlan_id_mask || !vlan_id)
2271 /* Mask both VLAN and VLANP - bits 0 and 1 */
2272 fdirm |= 0x3;
2273
2274 if (input_masks->data_mask || !flex_bytes)
2275 /* Flex bytes need masking, so mask the whole thing - bit 4 */
2276 fdirm |= 0x10;
2277
2278 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
2279 fdirm |= 0x24;
2280
2281 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
ffff4772
PWJ		 2282
2283 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2284 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2285 fdircmd |= IXGBE_FDIRCMD_LAST;
2286 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2287 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2288
2289 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2290 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2291
2292 return 0;
2293}
11afc1b1
PW		 2294/**
2295 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2296 * @hw: pointer to hardware structure
2297 * @reg: analog register to read
2298 * @val: read value
2299 *
2300 * Performs read operation to Omer analog register specified.
2301 **/
7b25cdba 2302static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 2303{
2304 u32 core_ctl;
2305
2306 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2307 (reg << 8));
2308 IXGBE_WRITE_FLUSH(hw);
2309 udelay(10);
2310 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2311 *val = (u8)core_ctl;
2312
2313 return 0;
2314}
2315
2316/**
2317 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2318 * @hw: pointer to hardware structure
2319 * @reg: atlas register to write
2320 * @val: value to write
2321 *
2322 * Performs write operation to Omer analog register specified.
2323 **/
7b25cdba 2324static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 2325{
2326 u32 core_ctl;
2327
2328 core_ctl = (reg << 8) | val;
2329 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2330 IXGBE_WRITE_FLUSH(hw);
2331 udelay(10);
2332
2333 return 0;
2334}
2335
2336/**
2337 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2338 * @hw: pointer to hardware structure
2339 *
2340 * Starts the hardware using the generic start_hw function.
2341 * Then performs device-specific:
2342 * Clears the rate limiter registers.
2343 **/
7b25cdba 2344static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2345{
2346 u32 q_num;
794caeb2 2347 s32 ret_val;
11afc1b1 2348
794caeb2 2349 ret_val = ixgbe_start_hw_generic(hw);
11afc1b1
PW		 2350
2351 /* Clear the rate limiters */
2352 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2353 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2354 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2355 }
2356 IXGBE_WRITE_FLUSH(hw);
2357
50ac58ba
PWJ		 2358 /* We need to run link autotry after the driver loads */
2359 hw->mac.autotry_restart = true;
2360
794caeb2
PWJ		 2361 if (ret_val == 0)
2362 ret_val = ixgbe_verify_fw_version_82599(hw);
2363
2364 return ret_val;
11afc1b1
PW		 2365}
2366
2367/**
2368 * ixgbe_identify_phy_82599 - Get physical layer module
2369 * @hw: pointer to hardware structure
2370 *
2371 * Determines the physical layer module found on the current adapter.
2372 **/
7b25cdba 2373static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2374{
2375 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2376 status = ixgbe_identify_phy_generic(hw);
2377 if (status != 0)
2378 status = ixgbe_identify_sfp_module_generic(hw);
2379 return status;
2380}
2381
2382/**
2383 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2384 * @hw: pointer to hardware structure
2385 *
2386 * Determines physical layer capabilities of the current configuration.
2387 **/
7b25cdba 2388static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2389{
2390 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 2391 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2392 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2393 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2394 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2395 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2396 u16 ext_ability = 0;
1339b9e9 2397 u8 comp_codes_10g = 0;
11afc1b1 2398
04193058
PWJ		 2399 hw->phy.ops.identify(hw);
2400
2401 if (hw->phy.type == ixgbe_phy_tn ||
2402 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 2403 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2404 &ext_ability);
2405 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 2406 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 2407 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 2408 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 2409 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 2410 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2411 goto out;
2412 }
2413
2414 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2415 case IXGBE_AUTOC_LMS_1G_AN:
2416 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2417 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2418 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2419 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2420 goto out;
2421 } else
2422 /* SFI mode so read SFP module */
2423 goto sfp_check;
11afc1b1 2424 break;
04193058
PWJ		 2425 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2426 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2427 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2428 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2429 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 2430 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2431 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 2432 goto out;
2433 break;
2434 case IXGBE_AUTOC_LMS_10G_SERIAL:
2435 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2436 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2437 goto out;
2438 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2439 goto sfp_check;
2440 break;
2441 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2442 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2443 if (autoc & IXGBE_AUTOC_KX_SUPP)
2444 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2445 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2446 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2447 if (autoc & IXGBE_AUTOC_KR_SUPP)
2448 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2449 goto out;
2450 break;
2451 default:
2452 goto out;
2453 break;
2454 }
11afc1b1 2455
04193058
PWJ		 2456sfp_check:
2457 /* SFP check must be done last since DA modules are sometimes used to
2458 * test KR mode - we need to id KR mode correctly before SFP module.
2459 * Call identify_sfp because the pluggable module may have changed */
2460 hw->phy.ops.identify_sfp(hw);
2461 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2462 goto out;
2463
2464 switch (hw->phy.type) {
2465 case ixgbe_phy_tw_tyco:
2466 case ixgbe_phy_tw_unknown:
2467 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2468 break;
2469 case ixgbe_phy_sfp_avago:
2470 case ixgbe_phy_sfp_ftl:
2471 case ixgbe_phy_sfp_intel:
2472 case ixgbe_phy_sfp_unknown:
2473 hw->phy.ops.read_i2c_eeprom(hw,
2474 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2475 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 2476 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 2477 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 2478 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
11afc1b1
PW		 2479 break;
2480 default:
11afc1b1
PW		 2481 break;
2482 }
2483
04193058 2484out:
11afc1b1
PW		 2485 return physical_layer;
2486}
2487
2488/**
2489 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2490 * @hw: pointer to hardware structure
2491 * @regval: register value to write to RXCTRL
2492 *
2493 * Enables the Rx DMA unit for 82599
2494 **/
7b25cdba 2495static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 2496{
2497#define IXGBE_MAX_SECRX_POLL 30
2498 int i;
2499 int secrxreg;
2500
2501 /*
2502 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2503 * If traffic is incoming before we enable the Rx unit, it could hang
2504 * the Rx DMA unit. Therefore, make sure the security engine is
2505 * completely disabled prior to enabling the Rx unit.
2506 */
2507 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2508 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2509 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2510 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2511 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2512 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2513 break;
2514 else
2515 udelay(10);
2516 }
2517
2518 /* For informational purposes only */
2519 if (i >= IXGBE_MAX_SECRX_POLL)
2520 hw_dbg(hw, "Rx unit being enabled before security "
2521 "path fully disabled. Continuing with init.\n");
2522
2523 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2524 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2525 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2526 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2527 IXGBE_WRITE_FLUSH(hw);
2528
2529 return 0;
2530}
2531
04193058
PWJ		 2532/**
2533 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2534 * @hw: pointer to hardware structure
2535 * @device_caps: the EEPROM word with the extra device capabilities
2536 *
2537 * This function will read the EEPROM location for the device capabilities,
2538 * and return the word through device_caps.
2539 **/
7b25cdba 2540static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
04193058
PWJ		 2541{
2542 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2543
2544 return 0;
2545}
2546
0365e6e4
PW		 2547/**
2548 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2549 * @hw: pointer to hardware structure
2550 * @san_mac_offset: SAN MAC address offset
2551 *
2552 * This function will read the EEPROM location for the SAN MAC address
2553 * pointer, and returns the value at that location. This is used in both
2554 * get and set mac_addr routines.
2555 **/
7b25cdba
DS		 2556static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2557 u16 *san_mac_offset)
0365e6e4
PW		 2558{
2559 /*
2560 * First read the EEPROM pointer to see if the MAC addresses are
2561 * available.
2562 */
2563 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2564
2565 return 0;
2566}
2567
2568/**
2569 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2570 * @hw: pointer to hardware structure
2571 * @san_mac_addr: SAN MAC address
2572 *
2573 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2574 * per-port, so set_lan_id() must be called before reading the addresses.
2575 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2576 * upon for non-SFP connections, so we must call it here.
2577 **/
7b25cdba 2578static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
0365e6e4
PW		 2579{
2580 u16 san_mac_data, san_mac_offset;
2581 u8 i;
2582
2583 /*
2584 * First read the EEPROM pointer to see if the MAC addresses are
2585 * available. If they're not, no point in calling set_lan_id() here.
2586 */
2587 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2588
2589 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2590 /*
2591 * No addresses available in this EEPROM. It's not an
2592 * error though, so just wipe the local address and return.
2593 */
2594 for (i = 0; i < 6; i++)
2595 san_mac_addr[i] = 0xFF;
2596
2597 goto san_mac_addr_out;
2598 }
2599
2600 /* make sure we know which port we need to program */
2601 hw->mac.ops.set_lan_id(hw);
2602 /* apply the port offset to the address offset */
2603 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2604 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2605 for (i = 0; i < 3; i++) {
2606 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2607 san_mac_addr[i * 2] = (u8)(san_mac_data);
2608 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2609 san_mac_offset++;
2610 }
2611
2612san_mac_addr_out:
2613 return 0;
2614}
2615
794caeb2
PWJ		 2616/**
2617 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2618 * @hw: pointer to hardware structure
2619 *
2620 * Verifies that installed the firmware version is 0.6 or higher
2621 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2622 *
2623 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2624 * if the FW version is not supported.
2625 **/
2626static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2627{
2628 s32 status = IXGBE_ERR_EEPROM_VERSION;
2629 u16 fw_offset, fw_ptp_cfg_offset;
2630 u16 fw_version = 0;
2631
2632 /* firmware check is only necessary for SFI devices */
2633 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2634 status = 0;
2635 goto fw_version_out;
2636 }
2637
2638 /* get the offset to the Firmware Module block */
2639 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2640
2641 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2642 goto fw_version_out;
2643
2644 /* get the offset to the Pass Through Patch Configuration block */
2645 hw->eeprom.ops.read(hw, (fw_offset +
2646 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2647 &fw_ptp_cfg_offset);
2648
2649 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2650 goto fw_version_out;
2651
2652 /* get the firmware version */
2653 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2654 IXGBE_FW_PATCH_VERSION_4),
2655 &fw_version);
2656
2657 if (fw_version > 0x5)
2658 status = 0;
2659
2660fw_version_out:
2661 return status;
2662}
2663
383ff34b
YZ		 2664/**
2665 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2666 * the EEPROM
2667 * @hw: pointer to hardware structure
2668 * @wwnn_prefix: the alternative WWNN prefix
2669 * @wwpn_prefix: the alternative WWPN prefix
2670 *
2671 * This function will read the EEPROM from the alternative SAN MAC address
2672 * block to check the support for the alternative WWNN/WWPN prefix support.
2673 **/
2674static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2675 u16 *wwpn_prefix)
2676{
2677 u16 offset, caps;
2678 u16 alt_san_mac_blk_offset;
2679
2680 /* clear output first */
2681 *wwnn_prefix = 0xFFFF;
2682 *wwpn_prefix = 0xFFFF;
2683
2684 /* check if alternative SAN MAC is supported */
2685 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2686 &alt_san_mac_blk_offset);
2687
2688 if ((alt_san_mac_blk_offset == 0) ||
2689 (alt_san_mac_blk_offset == 0xFFFF))
2690 goto wwn_prefix_out;
2691
2692 /* check capability in alternative san mac address block */
2693 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2694 hw->eeprom.ops.read(hw, offset, &caps);
2695 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2696 goto wwn_prefix_out;
2697
2698 /* get the corresponding prefix for WWNN/WWPN */
2699 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2700 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2701
2702 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2703 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2704
2705wwn_prefix_out:
2706 return 0;
2707}
2708
11afc1b1
PW		 2709static struct ixgbe_mac_operations mac_ops_82599 = {
2710 .init_hw = &ixgbe_init_hw_generic,
2711 .reset_hw = &ixgbe_reset_hw_82599,
2712 .start_hw = &ixgbe_start_hw_82599,
2713 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2714 .get_media_type = &ixgbe_get_media_type_82599,
2715 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2716 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2717 .get_mac_addr = &ixgbe_get_mac_addr_generic,
0365e6e4 2718 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
04193058 2719 .get_device_caps = &ixgbe_get_device_caps_82599,
383ff34b 2720 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
11afc1b1
PW		 2721 .stop_adapter = &ixgbe_stop_adapter_generic,
2722 .get_bus_info = &ixgbe_get_bus_info_generic,
2723 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2724 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2725 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2726 .setup_link = &ixgbe_setup_mac_link_82599,
11afc1b1
PW		 2727 .check_link = &ixgbe_check_mac_link_82599,
2728 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2729 .led_on = &ixgbe_led_on_generic,
2730 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2731 .blink_led_start = &ixgbe_blink_led_start_generic,
2732 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2733 .set_rar = &ixgbe_set_rar_generic,
2734 .clear_rar = &ixgbe_clear_rar_generic,
2735 .set_vmdq = &ixgbe_set_vmdq_82599,
2736 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2737 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2738 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2739 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2740 .enable_mc = &ixgbe_enable_mc_generic,
2741 .disable_mc = &ixgbe_disable_mc_generic,
2742 .clear_vfta = &ixgbe_clear_vfta_82599,
2743 .set_vfta = &ixgbe_set_vfta_82599,
620fa036 2744 .fc_enable = &ixgbe_fc_enable_generic,
11afc1b1
PW		 2745 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2746 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2747};
2748
2749static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2750 .init_params = &ixgbe_init_eeprom_params_generic,
2751 .read = &ixgbe_read_eeprom_generic,
2752 .write = &ixgbe_write_eeprom_generic,
2753 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2754 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2755};
2756
2757static struct ixgbe_phy_operations phy_ops_82599 = {
2758 .identify = &ixgbe_identify_phy_82599,
2759 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 2760 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 2761 .reset = &ixgbe_reset_phy_generic,
2762 .read_reg = &ixgbe_read_phy_reg_generic,
2763 .write_reg = &ixgbe_write_phy_reg_generic,
2764 .setup_link = &ixgbe_setup_phy_link_generic,
2765 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2766 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2767 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2768 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2769 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2770};
2771
2772struct ixgbe_info ixgbe_82599_info = {
2773 .mac = ixgbe_mac_82599EB,
2774 .get_invariants = &ixgbe_get_invariants_82599,
2775 .mac_ops = &mac_ops_82599,
2776 .eeprom_ops = &eeprom_ops_82599,
2777 .phy_ops = &phy_ops_82599,
096a58fd 2778 .mbx_ops = &mbx_ops_82599,
11afc1b1 2779};
Linux 6.x block layer and io_uring tree(s)