[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / dwmac4_dma.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
 * DWC Ether MAC version 4.xx  has been used for  developing this code.
 *
 * This contains the functions to handle the dma.
 *
 * Copyright (C) 2015  STMicroelectronics Ltd
 *
 * Author: Alexandre Torgue <alexandre.torgue@st.com>
 */

#include <linux/io.h>
#include "dwmac4.h"
#include "dwmac4_dma.h"

static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
{
	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
	int i;

	pr_info("dwmac4: Master AXI performs %s burst length\n",
		(value & DMA_SYS_BUS_FB) ? "fixed" : "any");

	if (axi->axi_lpi_en)
		value |= DMA_AXI_EN_LPI;
	if (axi->axi_xit_frm)
		value |= DMA_AXI_LPI_XIT_FRM;

	value &= ~DMA_AXI_WR_OSR_LMT;
	value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
		 DMA_AXI_WR_OSR_LMT_SHIFT;

	value &= ~DMA_AXI_RD_OSR_LMT;
	value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
		 DMA_AXI_RD_OSR_LMT_SHIFT;

	/* Depending on the UNDEF bit the Master AXI will perform any burst
	 * length according to the BLEN programmed (by default all BLEN are
	 * set).
	 */
	for (i = 0; i < AXI_BLEN; i++) {
		switch (axi->axi_blen[i]) {
		case 256:
			value |= DMA_AXI_BLEN256;
			break;
		case 128:
			value |= DMA_AXI_BLEN128;
			break;
		case 64:
			value |= DMA_AXI_BLEN64;
			break;
		case 32:
			value |= DMA_AXI_BLEN32;
			break;
		case 16:
			value |= DMA_AXI_BLEN16;
			break;
		case 8:
			value |= DMA_AXI_BLEN8;
			break;
		case 4:
			value |= DMA_AXI_BLEN4;
			break;
		}
	}

	writel(value, ioaddr + DMA_SYS_BUS_MODE);
}

static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
				    struct stmmac_dma_cfg *dma_cfg,
				    dma_addr_t dma_rx_phy, u32 chan)
{
	u32 value;
	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;

	value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
	value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));

	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
		writel(upper_32_bits(dma_rx_phy),
		       ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan));

	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
}

static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
				    struct stmmac_dma_cfg *dma_cfg,
				    dma_addr_t dma_tx_phy, u32 chan)
{
	u32 value;
	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;

	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
	value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT);

	/* Enable OSP to get best performance */
	value |= DMA_CONTROL_OSP;

	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));

	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
		writel(upper_32_bits(dma_tx_phy),
		       ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan));

	writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
}

static void dwmac4_dma_init_channel(void __iomem *ioaddr,
				    struct stmmac_dma_cfg *dma_cfg, u32 chan)
{
	u32 value;

	/* common channel control register config */
	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
	if (dma_cfg->pblx8)
		value = value | DMA_BUS_MODE_PBL;
	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));

	/* Mask interrupts by writing to CSR7 */
	writel(DMA_CHAN_INTR_DEFAULT_MASK,
	       ioaddr + DMA_CHAN_INTR_ENA(chan));
}

static void dwmac4_dma_init(void __iomem *ioaddr,
			    struct stmmac_dma_cfg *dma_cfg, int atds)
{
	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);

	/* Set the Fixed burst mode */
	if (dma_cfg->fixed_burst)
		value |= DMA_SYS_BUS_FB;

	/* Mixed Burst has no effect when fb is set */
	if (dma_cfg->mixed_burst)
		value |= DMA_SYS_BUS_MB;

	if (dma_cfg->aal)
		value |= DMA_SYS_BUS_AAL;

	if (dma_cfg->eame)
		value |= DMA_SYS_BUS_EAME;

	writel(value, ioaddr + DMA_SYS_BUS_MODE);
}

static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
				  u32 *reg_space)
{
	reg_space[DMA_CHAN_CONTROL(channel) / 4] =
		readl(ioaddr + DMA_CHAN_CONTROL(channel));
	reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
		readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
	reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
		readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
	reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
		readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
	reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
		readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
	reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
		readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
	reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
		readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
	reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
		readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
	reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
		readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
	reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
		readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
	reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
		readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
	reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
		readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
	reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
		readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
	reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
		readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
	reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
		readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
	reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
		readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
	reg_space[DMA_CHAN_STATUS(channel) / 4] =
		readl(ioaddr + DMA_CHAN_STATUS(channel));
}

static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
{
	int i;

	for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
		_dwmac4_dump_dma_regs(ioaddr, i, reg_space);
}

static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan)
{
	u32 chan;

	for (chan = 0; chan < number_chan; chan++)
		writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(chan));
}

static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,
				       u32 channel, int fifosz, u8 qmode)
{
	unsigned int rqs = fifosz / 256 - 1;
	u32 mtl_rx_op, mtl_rx_int;

	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));

	if (mode == SF_DMA_MODE) {
		pr_debug("GMAC: enable RX store and forward mode\n");
		mtl_rx_op |= MTL_OP_MODE_RSF;
	} else {
		pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
		mtl_rx_op &= ~MTL_OP_MODE_RSF;
		mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
		if (mode <= 32)
			mtl_rx_op |= MTL_OP_MODE_RTC_32;
		else if (mode <= 64)
			mtl_rx_op |= MTL_OP_MODE_RTC_64;
		else if (mode <= 96)
			mtl_rx_op |= MTL_OP_MODE_RTC_96;
		else
			mtl_rx_op |= MTL_OP_MODE_RTC_128;
	}

	mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
	mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT;

	/* Enable flow control only if each channel gets 4 KiB or more FIFO and
	 * only if channel is not an AVB channel.
	 */
	if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
		unsigned int rfd, rfa;

		mtl_rx_op |= MTL_OP_MODE_EHFC;

		/* Set Threshold for Activating Flow Control to min 2 frames,
		 * i.e. 1500 * 2 = 3000 bytes.
		 *
		 * Set Threshold for Deactivating Flow Control to min 1 frame,
		 * i.e. 1500 bytes.
		 */
		switch (fifosz) {
		case 4096:
			/* This violates the above formula because of FIFO size
			 * limit therefore overflow may occur in spite of this.
			 */
			rfd = 0x03; /* Full-2.5K */
			rfa = 0x01; /* Full-1.5K */
			break;

		case 8192:
			rfd = 0x06; /* Full-4K */
			rfa = 0x0a; /* Full-6K */
			break;

		case 16384:
			rfd = 0x06; /* Full-4K */
			rfa = 0x12; /* Full-10K */
			break;

		default:
			rfd = 0x06; /* Full-4K */
			rfa = 0x1e; /* Full-16K */
			break;
		}

		mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;
		mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT;

		mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;
		mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT;
	}

	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));

	/* Enable MTL RX overflow */
	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
	writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN,
	       ioaddr + MTL_CHAN_INT_CTRL(channel));
}

static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
				       u32 channel, int fifosz, u8 qmode)
{
	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
	unsigned int tqs = fifosz / 256 - 1;

	if (mode == SF_DMA_MODE) {
		pr_debug("GMAC: enable TX store and forward mode\n");
		/* Transmit COE type 2 cannot be done in cut-through mode. */
		mtl_tx_op |= MTL_OP_MODE_TSF;
	} else {
		pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
		mtl_tx_op &= ~MTL_OP_MODE_TSF;
		mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
		/* Set the transmit threshold */
		if (mode <= 32)
			mtl_tx_op |= MTL_OP_MODE_TTC_32;
		else if (mode <= 64)
			mtl_tx_op |= MTL_OP_MODE_TTC_64;
		else if (mode <= 96)
			mtl_tx_op |= MTL_OP_MODE_TTC_96;
		else if (mode <= 128)
			mtl_tx_op |= MTL_OP_MODE_TTC_128;
		else if (mode <= 192)
			mtl_tx_op |= MTL_OP_MODE_TTC_192;
		else if (mode <= 256)
			mtl_tx_op |= MTL_OP_MODE_TTC_256;
		else if (mode <= 384)
			mtl_tx_op |= MTL_OP_MODE_TTC_384;
		else
			mtl_tx_op |= MTL_OP_MODE_TTC_512;
	}
	/* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
	 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
	 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
	 * with reset values: TXQEN off, TQS 256 bytes.
	 *
	 * TXQEN must be written for multi-channel operation and TQS must
	 * reflect the available fifo size per queue (total fifo size / number
	 * of enabled queues).
	 */
	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
	if (qmode != MTL_QUEUE_AVB)
		mtl_tx_op |= MTL_OP_MODE_TXQEN;
	else
		mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
	mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;
	mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;

	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
}

static void dwmac4_get_hw_feature(void __iomem *ioaddr,
				  struct dma_features *dma_cap)
{
	u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);

	/*  MAC HW feature0 */
	dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
	dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
	dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
	dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
	dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
	dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
	dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
	dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
	dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
	/* MMC */
	dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
	/* IEEE 1588-2008 */
	dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
	/* 802.3az - Energy-Efficient Ethernet (EEE) */
	dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
	/* TX and RX csum */
	dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
	dma_cap->rx_coe =  (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
	dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
	dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;

	/* MAC HW feature1 */
	hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
	dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
	dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
	dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;

	dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
	switch (dma_cap->addr64) {
	case 0:
		dma_cap->addr64 = 32;
		break;
	case 1:
		dma_cap->addr64 = 40;
		break;
	case 2:
		dma_cap->addr64 = 48;
		break;
	default:
		dma_cap->addr64 = 32;
		break;
	}

	/* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
	 * shifting and store the sizes in bytes.
	 */
	dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);
	dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);
	/* MAC HW feature2 */
	hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
	/* TX and RX number of channels */
	dma_cap->number_rx_channel =
		((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
	dma_cap->number_tx_channel =
		((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
	/* TX and RX number of queues */
	dma_cap->number_rx_queues =
		((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
	dma_cap->number_tx_queues =
		((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
	/* PPS output */
	dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;

	/* IEEE 1588-2002 */
	dma_cap->time_stamp = 0;

	/* MAC HW feature3 */
	hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);

	/* 5.10 Features */
	dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
	dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
	dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
	dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
	dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;
}

/* Enable/disable TSO feature and set MSS */
static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
{
	u32 value;

	if (en) {
		/* enable TSO */
		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
		writel(value | DMA_CONTROL_TSE,
		       ioaddr + DMA_CHAN_TX_CONTROL(chan));
	} else {
		/* enable TSO */
		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
		writel(value & ~DMA_CONTROL_TSE,
		       ioaddr + DMA_CHAN_TX_CONTROL(chan));
	}
}

static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
{
	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));

	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
	if (qmode != MTL_QUEUE_AVB)
		mtl_tx_op |= MTL_OP_MODE_TXQEN;
	else
		mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;

	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
}

static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
{
	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));

	value &= ~DMA_RBSZ_MASK;
	value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK;

	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
}

const struct stmmac_dma_ops dwmac4_dma_ops = {
	.reset = dwmac4_dma_reset,
	.init = dwmac4_dma_init,
	.init_chan = dwmac4_dma_init_channel,
	.init_rx_chan = dwmac4_dma_init_rx_chan,
	.init_tx_chan = dwmac4_dma_init_tx_chan,
	.axi = dwmac4_dma_axi,
	.dump_regs = dwmac4_dump_dma_regs,
	.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
	.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
	.enable_dma_irq = dwmac4_enable_dma_irq,
	.disable_dma_irq = dwmac4_disable_dma_irq,
	.start_tx = dwmac4_dma_start_tx,
	.stop_tx = dwmac4_dma_stop_tx,
	.start_rx = dwmac4_dma_start_rx,
	.stop_rx = dwmac4_dma_stop_rx,
	.dma_interrupt = dwmac4_dma_interrupt,
	.get_hw_feature = dwmac4_get_hw_feature,
	.rx_watchdog = dwmac4_rx_watchdog,
	.set_rx_ring_len = dwmac4_set_rx_ring_len,
	.set_tx_ring_len = dwmac4_set_tx_ring_len,
	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
	.enable_tso = dwmac4_enable_tso,
	.qmode = dwmac4_qmode,
	.set_bfsize = dwmac4_set_bfsize,
};

const struct stmmac_dma_ops dwmac410_dma_ops = {
	.reset = dwmac4_dma_reset,
	.init = dwmac4_dma_init,
	.init_chan = dwmac4_dma_init_channel,
	.init_rx_chan = dwmac4_dma_init_rx_chan,
	.init_tx_chan = dwmac4_dma_init_tx_chan,
	.axi = dwmac4_dma_axi,
	.dump_regs = dwmac4_dump_dma_regs,
	.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
	.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
	.enable_dma_irq = dwmac410_enable_dma_irq,
	.disable_dma_irq = dwmac4_disable_dma_irq,
	.start_tx = dwmac4_dma_start_tx,
	.stop_tx = dwmac4_dma_stop_tx,
	.start_rx = dwmac4_dma_start_rx,
	.stop_rx = dwmac4_dma_stop_rx,
	.dma_interrupt = dwmac4_dma_interrupt,
	.get_hw_feature = dwmac4_get_hw_feature,
	.rx_watchdog = dwmac4_rx_watchdog,
	.set_rx_ring_len = dwmac4_set_rx_ring_len,
	.set_tx_ring_len = dwmac4_set_tx_ring_len,
	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
	.enable_tso = dwmac4_enable_tso,
	.qmode = dwmac4_qmode,
	.set_bfsize = dwmac4_set_bfsize,
};
Commit	Line	Data
75a6faf6	1	// SPDX-License-Identifier: GPL-2.0-only
48863ce5 AT	2	/*
	3	* This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
	4	* DWC Ether MAC version 4.xx has been used for developing this code.
	5	*
	6	* This contains the functions to handle the dma.
	7	*
	8	* Copyright (C) 2015 STMicroelectronics Ltd
	9	*
48863ce5 AT	10	* Author: Alexandre Torgue <alexandre.torgue@st.com>
	11	*/
	12
	13	#include <linux/io.h>
	14	#include "dwmac4.h"
	15	#include "dwmac4_dma.h"
	16
	17	static void dwmac4_dma_axi(void __iomem ioaddr, struct stmmac_axi axi)
	18	{
	19	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
	20	int i;
	21
	22	pr_info("dwmac4: Master AXI performs %s burst length\n",
	23	(value & DMA_SYS_BUS_FB) ? "fixed" : "any");
	24
	25	if (axi->axi_lpi_en)
	26	value \|= DMA_AXI_EN_LPI;
	27	if (axi->axi_xit_frm)
	28	value \|= DMA_AXI_LPI_XIT_FRM;
	29
6b3374cb	30	value &= ~DMA_AXI_WR_OSR_LMT;
48863ce5 AT	31	value \|= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
	32	DMA_AXI_WR_OSR_LMT_SHIFT;
	33
6b3374cb	34	value &= ~DMA_AXI_RD_OSR_LMT;
48863ce5 AT	35	value \|= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
	36	DMA_AXI_RD_OSR_LMT_SHIFT;
	37
	38	/* Depending on the UNDEF bit the Master AXI will perform any burst
	39	* length according to the BLEN programmed (by default all BLEN are
	40	* set).
	41	*/
	42	for (i = 0; i < AXI_BLEN; i++) {
	43	switch (axi->axi_blen[i]) {
	44	case 256:
	45	value \|= DMA_AXI_BLEN256;
	46	break;
	47	case 128:
	48	value \|= DMA_AXI_BLEN128;
	49	break;
	50	case 64:
	51	value \|= DMA_AXI_BLEN64;
	52	break;
	53	case 32:
	54	value \|= DMA_AXI_BLEN32;
	55	break;
	56	case 16:
	57	value \|= DMA_AXI_BLEN16;
	58	break;
	59	case 8:
	60	value \|= DMA_AXI_BLEN8;
	61	break;
	62	case 4:
	63	value \|= DMA_AXI_BLEN4;
	64	break;
	65	}
	66	}
	67
	68	writel(value, ioaddr + DMA_SYS_BUS_MODE);
	69	}
	70
72de4655 CIK	71	static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
72de4655 CIK	72	struct stmmac_dma_cfg *dma_cfg,
06a80a7d	73	dma_addr_t dma_rx_phy, u32 chan)
48863ce5 AT	74	{
48863ce5 AT	75	u32 value;
47f2a9ce	76	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
48863ce5	77
47f2a9ce JP	78	value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
	79	value = value \| (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
	80	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
	81
560c07cb TR	82	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
	83	writel(upper_32_bits(dma_rx_phy),
	84	ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan));
	85
06a80a7d	86	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
47f2a9ce	87	}
48863ce5	88
72de4655 CIK	89	static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
72de4655 CIK	90	struct stmmac_dma_cfg *dma_cfg,
06a80a7d	91	dma_addr_t dma_tx_phy, u32 chan)
47f2a9ce JP	92	{
	93	u32 value;
	94	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
	95
	96	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
89caaa2d	97	value = value \| (txpbl << DMA_BUS_MODE_PBL_SHIFT);
67e1c406 JA	98
	99	/* Enable OSP to get best performance */
	100	value \|= DMA_CONTROL_OSP;
	101
47f2a9ce	102	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
48863ce5	103
560c07cb TR	104	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
	105	writel(upper_32_bits(dma_tx_phy),
	106	ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan));
	107
06a80a7d	108	writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
47f2a9ce	109	}
48863ce5	110
72de4655 CIK	111	static void dwmac4_dma_init_channel(void __iomem *ioaddr,
72de4655 CIK	112	struct stmmac_dma_cfg *dma_cfg, u32 chan)
47f2a9ce JP	113	{
	114	u32 value;
	115
	116	/* common channel control register config */
	117	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
	118	if (dma_cfg->pblx8)
	119	value = value \| DMA_BUS_MODE_PBL;
	120	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
48863ce5	121
47f2a9ce JP	122	/* Mask interrupts by writing to CSR7 */
	123	writel(DMA_CHAN_INTR_DEFAULT_MASK,
	124	ioaddr + DMA_CHAN_INTR_ENA(chan));
48863ce5 AT	125	}
48863ce5 AT	126
50ca903a	127	static void dwmac4_dma_init(void __iomem *ioaddr,
24aaed0c	128	struct stmmac_dma_cfg *dma_cfg, int atds)
48863ce5 AT	129	{
48863ce5 AT	130	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
48863ce5 AT	131
48863ce5 AT	132	/* Set the Fixed burst mode */
50ca903a	133	if (dma_cfg->fixed_burst)
48863ce5 AT	134	value \|= DMA_SYS_BUS_FB;
	135
	136	/* Mixed Burst has no effect when fb is set */
50ca903a	137	if (dma_cfg->mixed_burst)
48863ce5 AT	138	value \|= DMA_SYS_BUS_MB;
48863ce5 AT	139
50ca903a	140	if (dma_cfg->aal)
48863ce5 AT	141	value \|= DMA_SYS_BUS_AAL;
48863ce5 AT	142
560c07cb TR	143	if (dma_cfg->eame)
	144	value \|= DMA_SYS_BUS_EAME;
	145
48863ce5	146	writel(value, ioaddr + DMA_SYS_BUS_MODE);
48863ce5 AT	147	}
48863ce5 AT	148
fbf68229 LC	149	static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
fbf68229 LC	150	u32 *reg_space)
48863ce5	151	{
fbf68229 LC	152	reg_space[DMA_CHAN_CONTROL(channel) / 4] =
	153	readl(ioaddr + DMA_CHAN_CONTROL(channel));
	154	reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
	155	readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
	156	reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
	157	readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
	158	reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
	159	readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
	160	reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
	161	readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
	162	reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
	163	readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
	164	reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
	165	readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
	166	reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
	167	readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
	168	reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
	169	readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
	170	reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
	171	readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
	172	reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
	173	readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
	174	reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
	175	readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
	176	reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
	177	readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
	178	reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
	179	readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
	180	reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
	181	readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
	182	reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
	183	readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
	184	reg_space[DMA_CHAN_STATUS(channel) / 4] =
	185	readl(ioaddr + DMA_CHAN_STATUS(channel));
48863ce5 AT	186	}
48863ce5 AT	187
fbf68229	188	static void dwmac4_dump_dma_regs(void __iomem ioaddr, u32 reg_space)
48863ce5 AT	189	{
	190	int i;
	191
48863ce5	192	for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
fbf68229	193	_dwmac4_dump_dma_regs(ioaddr, i, reg_space);
48863ce5 AT	194	}
48863ce5 AT	195
3c55d4d0	196	static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan)
48863ce5	197	{
3c55d4d0	198	u32 chan;
48863ce5	199
3c55d4d0 JP	200	for (chan = 0; chan < number_chan; chan++)
3c55d4d0 JP	201	writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(chan));
48863ce5 AT	202	}
48863ce5 AT	203
6deee222	204	static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,
a0daae13	205	u32 channel, int fifosz, u8 qmode)
48863ce5	206	{
6deee222 JP	207	unsigned int rqs = fifosz / 256 - 1;
6deee222 JP	208	u32 mtl_rx_op, mtl_rx_int;
48863ce5 AT	209
	210	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
	211
6deee222	212	if (mode == SF_DMA_MODE) {
48863ce5 AT	213	pr_debug("GMAC: enable RX store and forward mode\n");
	214	mtl_rx_op \|= MTL_OP_MODE_RSF;
	215	} else {
6deee222	216	pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
48863ce5 AT	217	mtl_rx_op &= ~MTL_OP_MODE_RSF;
48863ce5 AT	218	mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
6deee222	219	if (mode <= 32)
48863ce5	220	mtl_rx_op \|= MTL_OP_MODE_RTC_32;
6deee222	221	else if (mode <= 64)
48863ce5	222	mtl_rx_op \|= MTL_OP_MODE_RTC_64;
6deee222	223	else if (mode <= 96)
48863ce5 AT	224	mtl_rx_op \|= MTL_OP_MODE_RTC_96;
	225	else
	226	mtl_rx_op \|= MTL_OP_MODE_RTC_128;
	227	}
	228
356b7557 TR	229	mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
	230	mtl_rx_op \|= rqs << MTL_OP_MODE_RQS_SHIFT;
	231
a0daae13 JA	232	/* Enable flow control only if each channel gets 4 KiB or more FIFO and
	233	* only if channel is not an AVB channel.
	234	*/
	235	if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
356b7557 TR	236	unsigned int rfd, rfa;
	237
	238	mtl_rx_op \|= MTL_OP_MODE_EHFC;
	239
	240	/* Set Threshold for Activating Flow Control to min 2 frames,
	241	* i.e. 1500 * 2 = 3000 bytes.
	242	*
	243	* Set Threshold for Deactivating Flow Control to min 1 frame,
	244	* i.e. 1500 bytes.
	245	*/
6deee222	246	switch (fifosz) {
356b7557 TR	247	case 4096:
	248	/* This violates the above formula because of FIFO size
	249	* limit therefore overflow may occur in spite of this.
	250	*/
	251	rfd = 0x03; /* Full-2.5K */
	252	rfa = 0x01; /* Full-1.5K */
	253	break;
	254
	255	case 8192:
	256	rfd = 0x06; /* Full-4K */
	257	rfa = 0x0a; /* Full-6K */
	258	break;
	259
	260	case 16384:
	261	rfd = 0x06; /* Full-4K */
	262	rfa = 0x12; /* Full-10K */
	263	break;
	264
	265	default:
	266	rfd = 0x06; /* Full-4K */
	267	rfa = 0x1e; /* Full-16K */
	268	break;
	269	}
	270
	271	mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;
	272	mtl_rx_op \|= rfd << MTL_OP_MODE_RFD_SHIFT;
	273
	274	mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;
	275	mtl_rx_op \|= rfa << MTL_OP_MODE_RFA_SHIFT;
	276	}
	277
48863ce5 AT	278	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
	279
	280	/* Enable MTL RX overflow */
	281	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
	282	writel(mtl_rx_int \| MTL_RX_OVERFLOW_INT_EN,
	283	ioaddr + MTL_CHAN_INT_CTRL(channel));
	284	}
	285
6deee222	286	static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
a0daae13	287	u32 channel, int fifosz, u8 qmode)
48863ce5	288	{
6deee222	289	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
52a76235	290	unsigned int tqs = fifosz / 256 - 1;
6deee222 JP	291
	292	if (mode == SF_DMA_MODE) {
	293	pr_debug("GMAC: enable TX store and forward mode\n");
	294	/* Transmit COE type 2 cannot be done in cut-through mode. */
	295	mtl_tx_op \|= MTL_OP_MODE_TSF;
	296	} else {
	297	pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
	298	mtl_tx_op &= ~MTL_OP_MODE_TSF;
	299	mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
	300	/* Set the transmit threshold */
	301	if (mode <= 32)
	302	mtl_tx_op \|= MTL_OP_MODE_TTC_32;
	303	else if (mode <= 64)
	304	mtl_tx_op \|= MTL_OP_MODE_TTC_64;
	305	else if (mode <= 96)
	306	mtl_tx_op \|= MTL_OP_MODE_TTC_96;
	307	else if (mode <= 128)
	308	mtl_tx_op \|= MTL_OP_MODE_TTC_128;
	309	else if (mode <= 192)
	310	mtl_tx_op \|= MTL_OP_MODE_TTC_192;
	311	else if (mode <= 256)
	312	mtl_tx_op \|= MTL_OP_MODE_TTC_256;
	313	else if (mode <= 384)
	314	mtl_tx_op \|= MTL_OP_MODE_TTC_384;
	315	else
	316	mtl_tx_op \|= MTL_OP_MODE_TTC_512;
	317	}
	318	/* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
	319	* with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
	320	* For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
	321	* with reset values: TXQEN off, TQS 256 bytes.
	322	*
52a76235 JA	323	* TXQEN must be written for multi-channel operation and TQS must
	324	* reflect the available fifo size per queue (total fifo size / number
	325	* of enabled queues).
6deee222	326	*/
a0daae13 JA	327	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
	328	if (qmode != MTL_QUEUE_AVB)
	329	mtl_tx_op \|= MTL_OP_MODE_TXQEN;
	330	else
	331	mtl_tx_op \|= MTL_OP_MODE_TXQEN_AV;
52a76235 JA	332	mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;
	333	mtl_tx_op \|= tqs << MTL_OP_MODE_TQS_SHIFT;
	334
6deee222	335	writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
48863ce5 AT	336	}
	337
	338	static void dwmac4_get_hw_feature(void __iomem *ioaddr,
	339	struct dma_features *dma_cap)
	340	{
	341	u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
	342
	343	/* MAC HW feature0 */
	344	dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
	345	dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
	346	dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
c1be0022	347	dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
48863ce5 AT	348	dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
	349	dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
	350	dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
	351	dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
	352	dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
	353	/* MMC */
	354	dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
	355	/* IEEE 1588-2008 */
	356	dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
	357	/* 802.3az - Energy-Efficient Ethernet (EEE) */
	358	dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
	359	/* TX and RX csum */
	360	dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
	361	dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
1d982e93	362	dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
c9b10043	363	dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;
48863ce5 AT	364
	365	/* MAC HW feature1 */
	366	hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
b8ef7020	367	dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
48863ce5 AT	368	dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
48863ce5 AT	369	dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
560c07cb TR	370
	371	dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
	372	switch (dma_cap->addr64) {
	373	case 0:
	374	dma_cap->addr64 = 32;
	375	break;
	376	case 1:
	377	dma_cap->addr64 = 40;
	378	break;
	379	case 2:
	380	dma_cap->addr64 = 48;
	381	break;
	382	default:
	383	dma_cap->addr64 = 32;
	384	break;
	385	}
	386
11fbf811 TR	387	/* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
	388	* shifting and store the sizes in bytes.
	389	*/
	390	dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);
	391	dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);
48863ce5 AT	392	/* MAC HW feature2 */
	393	hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
	394	/* TX and RX number of channels */
	395	dma_cap->number_rx_channel =
	396	((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
	397	dma_cap->number_tx_channel =
	398	((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
9eb12474	399	/* TX and RX number of queues */
	400	dma_cap->number_rx_queues =
	401	((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
	402	dma_cap->number_tx_queues =
	403	((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
9a8a02c9 JA	404	/* PPS output */
9a8a02c9 JA	405	dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;
48863ce5 AT	406
	407	/* IEEE 1588-2002 */
	408	dma_cap->time_stamp = 0;
8bf993a5 JA	409
	410	/* MAC HW feature3 */
	411	hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);
	412
	413	/* 5.10 Features */
	414	dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
4dbbe8dd JA	415	dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
	416	dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
	417	dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
e94e3f3b	418	dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;
48863ce5 AT	419	}
	420
	421	/* Enable/disable TSO feature and set MSS */
	422	static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
	423	{
	424	u32 value;
	425
	426	if (en) {
	427	/* enable TSO */
	428	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
	429	writel(value \| DMA_CONTROL_TSE,
	430	ioaddr + DMA_CHAN_TX_CONTROL(chan));
	431	} else {
	432	/* enable TSO */
	433	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
	434	writel(value & ~DMA_CONTROL_TSE,
	435	ioaddr + DMA_CHAN_TX_CONTROL(chan));
	436	}
	437	}
	438
1f705bc6 JA	439	static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
	440	{
	441	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
	442
	443	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
	444	if (qmode != MTL_QUEUE_AVB)
	445	mtl_tx_op \|= MTL_OP_MODE_TXQEN;
	446	else
	447	mtl_tx_op \|= MTL_OP_MODE_TXQEN_AV;
	448
	449	writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
	450	}
	451
4205c88e JA	452	static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
	453	{
	454	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
	455
	456	value &= ~DMA_RBSZ_MASK;
	457	value \|= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK;
	458
	459	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
	460	}
	461
48863ce5 AT	462	const struct stmmac_dma_ops dwmac4_dma_ops = {
	463	.reset = dwmac4_dma_reset,
	464	.init = dwmac4_dma_init,
47f2a9ce JP	465	.init_chan = dwmac4_dma_init_channel,
	466	.init_rx_chan = dwmac4_dma_init_rx_chan,
	467	.init_tx_chan = dwmac4_dma_init_tx_chan,
48863ce5 AT	468	.axi = dwmac4_dma_axi,
48863ce5 AT	469	.dump_regs = dwmac4_dump_dma_regs,
6deee222 JP	470	.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
6deee222 JP	471	.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
48863ce5 AT	472	.enable_dma_irq = dwmac4_enable_dma_irq,
	473	.disable_dma_irq = dwmac4_disable_dma_irq,
	474	.start_tx = dwmac4_dma_start_tx,
	475	.stop_tx = dwmac4_dma_stop_tx,
	476	.start_rx = dwmac4_dma_start_rx,
	477	.stop_rx = dwmac4_dma_stop_rx,
	478	.dma_interrupt = dwmac4_dma_interrupt,
	479	.get_hw_feature = dwmac4_get_hw_feature,
	480	.rx_watchdog = dwmac4_rx_watchdog,
	481	.set_rx_ring_len = dwmac4_set_rx_ring_len,
	482	.set_tx_ring_len = dwmac4_set_tx_ring_len,
	483	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
	484	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
	485	.enable_tso = dwmac4_enable_tso,
1f705bc6	486	.qmode = dwmac4_qmode,
4205c88e	487	.set_bfsize = dwmac4_set_bfsize,
48863ce5 AT	488	};
	489
	490	const struct stmmac_dma_ops dwmac410_dma_ops = {
	491	.reset = dwmac4_dma_reset,
	492	.init = dwmac4_dma_init,
47f2a9ce JP	493	.init_chan = dwmac4_dma_init_channel,
	494	.init_rx_chan = dwmac4_dma_init_rx_chan,
	495	.init_tx_chan = dwmac4_dma_init_tx_chan,
48863ce5 AT	496	.axi = dwmac4_dma_axi,
48863ce5 AT	497	.dump_regs = dwmac4_dump_dma_regs,
6deee222 JP	498	.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
6deee222 JP	499	.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
48863ce5 AT	500	.enable_dma_irq = dwmac410_enable_dma_irq,
	501	.disable_dma_irq = dwmac4_disable_dma_irq,
	502	.start_tx = dwmac4_dma_start_tx,
	503	.stop_tx = dwmac4_dma_stop_tx,
	504	.start_rx = dwmac4_dma_start_rx,
	505	.stop_rx = dwmac4_dma_stop_rx,
	506	.dma_interrupt = dwmac4_dma_interrupt,
	507	.get_hw_feature = dwmac4_get_hw_feature,
	508	.rx_watchdog = dwmac4_rx_watchdog,
	509	.set_rx_ring_len = dwmac4_set_rx_ring_len,
	510	.set_tx_ring_len = dwmac4_set_tx_ring_len,
	511	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
	512	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
	513	.enable_tso = dwmac4_enable_tso,
1f705bc6	514	.qmode = dwmac4_qmode,
4205c88e	515	.set_bfsize = dwmac4_set_bfsize,
48863ce5	516	};