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mlx4: Add infrastructure for selecting VFs to enable QP0 via MLX proxy QPs
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
dd41cc3b
MB		 80static uint8_t num_vfs[3] = {0, 0, 0};
81static int num_vfs_argc = 3;
82module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
85
86static uint8_t probe_vf[3] = {0, 0, 0};
87static int probe_vfs_argc = 3;
88module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
ab9c17a0 91
3c439b55 92int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 93module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
3c439b55 97 " 10 gives 248.range: 7 <="
0ff1fb65 98 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 99 " To activate device managed"
100 " flow steering when available, set to -1");
0ec2c0f8 101
be902ab1 102static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 103module_param(enable_64b_cqe_eqe, bool, 0444);
104MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 106
ab9c17a0 107#define HCA_GLOBAL_CAP_MASK 0
08ff3235
OG		 108
109#define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
ab9c17a0 110
f57e6848 111static char mlx4_version[] =
225c7b1f
RD		 112 DRV_NAME ": Mellanox ConnectX core driver v"
113 DRV_VERSION " (" DRV_RELDATE ")\n";
114
115static struct mlx4_profile default_profile = {
ab9c17a0 116 .num_qp = 1 << 18,
225c7b1f 117 .num_srq = 1 << 16,
c9f2ba5e 118 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 119 .num_cq = 1 << 16,
120 .num_mcg = 1 << 13,
ab9c17a0 121 .num_mpt = 1 << 19,
9fd7a1e1 122 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 123};
124
ab9c17a0 125static int log_num_mac = 7;
93fc9e1b
YP		 126module_param_named(log_num_mac, log_num_mac, int, 0444);
127MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
128
129static int log_num_vlan;
130module_param_named(log_num_vlan, log_num_vlan, int, 0444);
131MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 132/* Log2 max number of VLANs per ETH port (0-7) */
133#define MLX4_LOG_NUM_VLANS 7
93fc9e1b 134
eb939922 135static bool use_prio;
93fc9e1b
YP		 136module_param_named(use_prio, use_prio, bool, 0444);
137MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
138 "(0/1, default 0)");
139
2b8fb286 140int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 141module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 142MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 143
8d0fc7b6 144static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 145static int arr_argc = 2;
146module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 147MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
148 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 149
150struct mlx4_port_config {
151 struct list_head list;
152 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
153 struct pci_dev *pdev;
154};
155
97989356
AV		 156static atomic_t pf_loading = ATOMIC_INIT(0);
157
27bf91d6
YP		 158int mlx4_check_port_params(struct mlx4_dev *dev,
159 enum mlx4_port_type *port_type)
7ff93f8b
YP		 160{
161 int i;
162
163 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 164 if (port_type[i] != port_type[i + 1]) {
165 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
166 mlx4_err(dev, "Only same port types supported "
167 "on this HCA, aborting.\n");
168 return -EINVAL;
169 }
7ff93f8b
YP		 170 }
171 }
7ff93f8b
YP		 172
173 for (i = 0; i < dev->caps.num_ports; i++) {
174 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
175 mlx4_err(dev, "Requested port type for port %d is not "
176 "supported on this HCA\n", i + 1);
177 return -EINVAL;
178 }
179 }
180 return 0;
181}
182
183static void mlx4_set_port_mask(struct mlx4_dev *dev)
184{
185 int i;
186
7ff93f8b 187 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 188 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 189}
f2a3f6a3 190
3d73c288 191static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 192{
193 int err;
5ae2a7a8 194 int i;
225c7b1f
RD		 195
196 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
197 if (err) {
198 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
199 return err;
200 }
201
202 if (dev_cap->min_page_sz > PAGE_SIZE) {
203 mlx4_err(dev, "HCA minimum page size of %d bigger than "
204 "kernel PAGE_SIZE of %ld, aborting.\n",
205 dev_cap->min_page_sz, PAGE_SIZE);
206 return -ENODEV;
207 }
208 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
209 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
210 "aborting.\n",
211 dev_cap->num_ports, MLX4_MAX_PORTS);
212 return -ENODEV;
213 }
214
215 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
216 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
217 "PCI resource 2 size of 0x%llx, aborting.\n",
218 dev_cap->uar_size,
219 (unsigned long long) pci_resource_len(dev->pdev, 2));
220 return -ENODEV;
221 }
222
223 dev->caps.num_ports = dev_cap->num_ports;
3fc929e2 224 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
5ae2a7a8
RD		 225 for (i = 1; i <= dev->caps.num_ports; ++i) {
226 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 227 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
6634961c
JM		 228 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
229 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
230 /* set gid and pkey table operating lengths by default
231 * to non-sriov values */
5ae2a7a8
RD		 232 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
233 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
234 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 235 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
236 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 237 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 238 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
239 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 240 dev->caps.trans_type[i] = dev_cap->trans_type[i];
241 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
242 dev->caps.wavelength[i] = dev_cap->wavelength[i];
243 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 244 }
245
ab9c17a0 246 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 247 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 248 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
249 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
250 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
251 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
252 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
253 dev->caps.max_wqes = dev_cap->max_qp_sz;
254 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 255 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
256 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
257 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
258 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
259 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 260 /*
261 * Subtract 1 from the limit because we need to allocate a
262 * spare CQE so the HCA HW can tell the difference between an
263 * empty CQ and a full CQ.
264 */
265 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
266 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
267 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 268 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 269 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 270
271 /* The first 128 UARs are used for EQ doorbells */
272 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 273 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 274 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
275 dev_cap->reserved_xrcds : 0;
276 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
277 dev_cap->max_xrcds : 0;
2b8fb286
MA		 278 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
279
149983af 280 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 281 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
282 dev->caps.flags = dev_cap->flags;
b3416f44 283 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 284 dev->caps.bmme_flags = dev_cap->bmme_flags;
285 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 286 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 287 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 288 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 289
ca3e57a5
RD		 290 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
291 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 292 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 293 /* Don't do sense port on multifunction devices (for now at least) */
294 if (mlx4_is_mfunc(dev))
295 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 296
93fc9e1b 297 dev->caps.log_num_macs = log_num_mac;
cb29688a 298 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
93fc9e1b
YP		 299 dev->caps.log_num_prios = use_prio ? 3 : 0;
300
301 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 302 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
303 if (dev->caps.supported_type[i]) {
304 /* if only ETH is supported - assign ETH */
305 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
306 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 307 /* if only IB is supported, assign IB */
ab9c17a0 308 else if (dev->caps.supported_type[i] ==
105c320f
JM		 309 MLX4_PORT_TYPE_IB)
310 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 311 else {
105c320f
JM		 312 /* if IB and ETH are supported, we set the port
313 * type according to user selection of port type;
314 * if user selected none, take the FW hint */
315 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 316 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
317 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 318 else
105c320f 319 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 320 }
321 }
8d0fc7b6
YP		 322 /*
323 * Link sensing is allowed on the port if 3 conditions are true:
324 * 1. Both protocols are supported on the port.
325 * 2. Different types are supported on the port
326 * 3. FW declared that it supports link sensing
327 */
27bf91d6 328 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 329 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 330 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 331 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 332
8d0fc7b6
YP		 333 /*
334 * If "default_sense" bit is set, we move the port to "AUTO" mode
335 * and perform sense_port FW command to try and set the correct
336 * port type from beginning
337 */
46c46747 338 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 339 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
340 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
341 mlx4_SENSE_PORT(dev, i, &sensed_port);
342 if (sensed_port != MLX4_PORT_TYPE_NONE)
343 dev->caps.port_type[i] = sensed_port;
344 } else {
345 dev->caps.possible_type[i] = dev->caps.port_type[i];
346 }
347
93fc9e1b
YP		 348 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
349 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
350 mlx4_warn(dev, "Requested number of MACs is too much "
351 "for port %d, reducing to %d.\n",
352 i, 1 << dev->caps.log_num_macs);
353 }
354 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
355 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
356 mlx4_warn(dev, "Requested number of VLANs is too much "
357 "for port %d, reducing to %d.\n",
358 i, 1 << dev->caps.log_num_vlans);
359 }
360 }
361
f2a3f6a3
OG		 362 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
363
93fc9e1b
YP		 364 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
365 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
366 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
367 (1 << dev->caps.log_num_macs) *
368 (1 << dev->caps.log_num_vlans) *
369 (1 << dev->caps.log_num_prios) *
370 dev->caps.num_ports;
371 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
372
373 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
374 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
375 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
376 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
377
e2c76824 378 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 379
b3051320 380 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 381 if (dev_cap->flags &
382 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
383 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
384 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
385 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
386 }
387 }
388
f97b4b5d 389 if ((dev->caps.flags &
08ff3235
OG		 390 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
391 mlx4_is_master(dev))
392 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
393
225c7b1f
RD		 394 return 0;
395}
b912b2f8
EP		 396
397static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
398 enum pci_bus_speed *speed,
399 enum pcie_link_width *width)
400{
401 u32 lnkcap1, lnkcap2;
402 int err1, err2;
403
404#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
405
406 *speed = PCI_SPEED_UNKNOWN;
407 *width = PCIE_LNK_WIDTH_UNKNOWN;
408
409 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
410 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
411 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
412 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
413 *speed = PCIE_SPEED_8_0GT;
414 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
415 *speed = PCIE_SPEED_5_0GT;
416 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
417 *speed = PCIE_SPEED_2_5GT;
418 }
419 if (!err1) {
420 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
421 if (!lnkcap2) { /* pre-r3.0 */
422 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
423 *speed = PCIE_SPEED_5_0GT;
424 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
425 *speed = PCIE_SPEED_2_5GT;
426 }
427 }
428
429 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
430 return err1 ? err1 :
431 err2 ? err2 : -EINVAL;
432 }
433 return 0;
434}
435
436static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
437{
438 enum pcie_link_width width, width_cap;
439 enum pci_bus_speed speed, speed_cap;
440 int err;
441
442#define PCIE_SPEED_STR(speed) \
443 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
444 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
445 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
446 "Unknown")
447
448 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
449 if (err) {
450 mlx4_warn(dev,
451 "Unable to determine PCIe device BW capabilities\n");
452 return;
453 }
454
455 err = pcie_get_minimum_link(dev->pdev, &speed, &width);
456 if (err || speed == PCI_SPEED_UNKNOWN ||
457 width == PCIE_LNK_WIDTH_UNKNOWN) {
458 mlx4_warn(dev,
459 "Unable to determine PCI device chain minimum BW\n");
460 return;
461 }
462
463 if (width != width_cap || speed != speed_cap)
464 mlx4_warn(dev,
465 "PCIe BW is different than device's capability\n");
466
467 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
468 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
469 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
470 width, width_cap);
471 return;
472}
473
ab9c17a0
JM		 474/*The function checks if there are live vf, return the num of them*/
475static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
476{
477 struct mlx4_priv *priv = mlx4_priv(dev);
478 struct mlx4_slave_state *s_state;
479 int i;
480 int ret = 0;
481
482 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
483 s_state = &priv->mfunc.master.slave_state[i];
484 if (s_state->active && s_state->last_cmd !=
485 MLX4_COMM_CMD_RESET) {
486 mlx4_warn(dev, "%s: slave: %d is still active\n",
487 __func__, i);
488 ret++;
489 }
490 }
491 return ret;
492}
493
396f2feb
JM		 494int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
495{
496 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 497
498 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
499 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 500 return -EINVAL;
501
47605df9 502 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 503 /* tunnel qp */
47605df9 504 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 505 else
47605df9 506 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 507 *qkey = qk;
508 return 0;
509}
510EXPORT_SYMBOL(mlx4_get_parav_qkey);
511
54679e14
JM		 512void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
513{
514 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
515
516 if (!mlx4_is_master(dev))
517 return;
518
519 priv->virt2phys_pkey[slave][port - 1][i] = val;
520}
521EXPORT_SYMBOL(mlx4_sync_pkey_table);
522
afa8fd1d
JM		 523void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
524{
525 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
526
527 if (!mlx4_is_master(dev))
528 return;
529
530 priv->slave_node_guids[slave] = guid;
531}
532EXPORT_SYMBOL(mlx4_put_slave_node_guid);
533
534__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
535{
536 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
537
538 if (!mlx4_is_master(dev))
539 return 0;
540
541 return priv->slave_node_guids[slave];
542}
543EXPORT_SYMBOL(mlx4_get_slave_node_guid);
544
e10903b0 545int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 546{
547 struct mlx4_priv *priv = mlx4_priv(dev);
548 struct mlx4_slave_state *s_slave;
549
550 if (!mlx4_is_master(dev))
551 return 0;
552
553 s_slave = &priv->mfunc.master.slave_state[slave];
554 return !!s_slave->active;
555}
556EXPORT_SYMBOL(mlx4_is_slave_active);
557
7b8157be
JM		 558static void slave_adjust_steering_mode(struct mlx4_dev *dev,
559 struct mlx4_dev_cap *dev_cap,
560 struct mlx4_init_hca_param *hca_param)
561{
562 dev->caps.steering_mode = hca_param->steering_mode;
563 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
564 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
565 dev->caps.fs_log_max_ucast_qp_range_size =
566 dev_cap->fs_log_max_ucast_qp_range_size;
567 } else
568 dev->caps.num_qp_per_mgm =
569 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
570
571 mlx4_dbg(dev, "Steering mode is: %s\n",
572 mlx4_steering_mode_str(dev->caps.steering_mode));
573}
574
ab9c17a0
JM		 575static int mlx4_slave_cap(struct mlx4_dev *dev)
576{
577 int err;
578 u32 page_size;
579 struct mlx4_dev_cap dev_cap;
580 struct mlx4_func_cap func_cap;
581 struct mlx4_init_hca_param hca_param;
582 int i;
583
584 memset(&hca_param, 0, sizeof(hca_param));
585 err = mlx4_QUERY_HCA(dev, &hca_param);
586 if (err) {
587 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
588 return err;
589 }
590
591 /*fail if the hca has an unknown capability */
592 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
593 HCA_GLOBAL_CAP_MASK) {
594 mlx4_err(dev, "Unknown hca global capabilities\n");
595 return -ENOSYS;
596 }
597
598 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
599
ddd8a6c1
EE		 600 dev->caps.hca_core_clock = hca_param.hca_core_clock;
601
ab9c17a0 602 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 603 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 604 err = mlx4_dev_cap(dev, &dev_cap);
605 if (err) {
606 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
607 return err;
608 }
609
b91cb3eb
JM		 610 err = mlx4_QUERY_FW(dev);
611 if (err)
612 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
613
ab9c17a0
JM		 614 page_size = ~dev->caps.page_size_cap + 1;
615 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
616 if (page_size > PAGE_SIZE) {
617 mlx4_err(dev, "HCA minimum page size of %d bigger than "
618 "kernel PAGE_SIZE of %ld, aborting.\n",
619 page_size, PAGE_SIZE);
620 return -ENODEV;
621 }
622
623 /* slave gets uar page size from QUERY_HCA fw command */
624 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
625
626 /* TODO: relax this assumption */
627 if (dev->caps.uar_page_size != PAGE_SIZE) {
628 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
629 dev->caps.uar_page_size, PAGE_SIZE);
630 return -ENODEV;
631 }
632
633 memset(&func_cap, 0, sizeof(func_cap));
47605df9 634 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 635 if (err) {
47605df9
JM		 636 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
637 err);
ab9c17a0
JM		 638 return err;
639 }
640
641 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
642 PF_CONTEXT_BEHAVIOUR_MASK) {
643 mlx4_err(dev, "Unknown pf context behaviour\n");
644 return -ENOSYS;
645 }
646
ab9c17a0 647 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 648 dev->quotas.qp = func_cap.qp_quota;
649 dev->quotas.srq = func_cap.srq_quota;
650 dev->quotas.cq = func_cap.cq_quota;
651 dev->quotas.mpt = func_cap.mpt_quota;
652 dev->quotas.mtt = func_cap.mtt_quota;
653 dev->caps.num_qps = 1 << hca_param.log_num_qps;
654 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
655 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
656 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
657 dev->caps.num_eqs = func_cap.max_eq;
658 dev->caps.reserved_eqs = func_cap.reserved_eq;
ab9c17a0
JM		 659 dev->caps.num_pds = MLX4_NUM_PDS;
660 dev->caps.num_mgms = 0;
661 dev->caps.num_amgms = 0;
662
ab9c17a0
JM		 663 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
664 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
665 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
666 return -ENODEV;
667 }
668
99ec41d0 669 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
47605df9
JM		 670 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
671 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
672 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
673 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
674
675 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
99ec41d0
JM		 676 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
677 !dev->caps.qp0_qkey) {
47605df9
JM		 678 err = -ENOMEM;
679 goto err_mem;
680 }
681
6634961c 682 for (i = 1; i <= dev->caps.num_ports; ++i) {
47605df9
JM		 683 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
684 if (err) {
685 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
686 " port %d, aborting (%d).\n", i, err);
687 goto err_mem;
688 }
99ec41d0 689 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
47605df9
JM		 690 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
691 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
692 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
693 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 694 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 695 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
6634961c
JM		 696 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
697 &dev->caps.gid_table_len[i],
698 &dev->caps.pkey_table_len[i]))
47605df9 699 goto err_mem;
6634961c 700 }
6230bb23 701
ab9c17a0
JM		 702 if (dev->caps.uar_page_size * (dev->caps.num_uars -
703 dev->caps.reserved_uars) >
704 pci_resource_len(dev->pdev, 2)) {
705 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
706 "PCI resource 2 size of 0x%llx, aborting.\n",
707 dev->caps.uar_page_size * dev->caps.num_uars,
708 (unsigned long long) pci_resource_len(dev->pdev, 2));
47605df9 709 goto err_mem;
ab9c17a0
JM		 710 }
711
08ff3235
OG		 712 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
713 dev->caps.eqe_size = 64;
714 dev->caps.eqe_factor = 1;
715 } else {
716 dev->caps.eqe_size = 32;
717 dev->caps.eqe_factor = 0;
718 }
719
720 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
721 dev->caps.cqe_size = 64;
722 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
723 } else {
724 dev->caps.cqe_size = 32;
725 }
726
f9bd2d7f
AV		 727 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
728 mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
729
7b8157be
JM		 730 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
731
ab9c17a0 732 return 0;
47605df9
JM		 733
734err_mem:
99ec41d0 735 kfree(dev->caps.qp0_qkey);
47605df9
JM		 736 kfree(dev->caps.qp0_tunnel);
737 kfree(dev->caps.qp0_proxy);
738 kfree(dev->caps.qp1_tunnel);
739 kfree(dev->caps.qp1_proxy);
99ec41d0
JM		 740 dev->caps.qp0_qkey = NULL;
741 dev->caps.qp0_tunnel = NULL;
742 dev->caps.qp0_proxy = NULL;
743 dev->caps.qp1_tunnel = NULL;
744 dev->caps.qp1_proxy = NULL;
47605df9
JM		 745
746 return err;
ab9c17a0 747}
225c7b1f 748
b046ffe5
EP		 749static void mlx4_request_modules(struct mlx4_dev *dev)
750{
751 int port;
752 int has_ib_port = false;
753 int has_eth_port = false;
754#define EN_DRV_NAME "mlx4_en"
755#define IB_DRV_NAME "mlx4_ib"
756
757 for (port = 1; port <= dev->caps.num_ports; port++) {
758 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
759 has_ib_port = true;
760 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
761 has_eth_port = true;
762 }
763
b046ffe5
EP		 764 if (has_eth_port)
765 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 766 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
767 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 768}
769
7ff93f8b
YP		 770/*
771 * Change the port configuration of the device.
772 * Every user of this function must hold the port mutex.
773 */
27bf91d6
YP		 774int mlx4_change_port_types(struct mlx4_dev *dev,
775 enum mlx4_port_type *port_types)
7ff93f8b
YP		 776{
777 int err = 0;
778 int change = 0;
779 int port;
780
781 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 782 /* Change the port type only if the new type is different
783 * from the current, and not set to Auto */
3d8f9308 784 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 785 change = 1;
7ff93f8b
YP		 786 }
787 if (change) {
788 mlx4_unregister_device(dev);
789 for (port = 1; port <= dev->caps.num_ports; port++) {
790 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 791 dev->caps.port_type[port] = port_types[port - 1];
6634961c 792 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b
YP		 793 if (err) {
794 mlx4_err(dev, "Failed to set port %d, "
795 "aborting\n", port);
796 goto out;
797 }
798 }
799 mlx4_set_port_mask(dev);
800 err = mlx4_register_device(dev);
b046ffe5
EP		 801 if (err) {
802 mlx4_err(dev, "Failed to register device\n");
803 goto out;
804 }
805 mlx4_request_modules(dev);
7ff93f8b
YP		 806 }
807
808out:
809 return err;
810}
811
812static ssize_t show_port_type(struct device *dev,
813 struct device_attribute *attr,
814 char *buf)
815{
816 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
817 port_attr);
818 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 819 char type[8];
820
821 sprintf(type, "%s",
822 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
823 "ib" : "eth");
824 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
825 sprintf(buf, "auto (%s)\n", type);
826 else
827 sprintf(buf, "%s\n", type);
7ff93f8b 828
27bf91d6 829 return strlen(buf);
7ff93f8b
YP		 830}
831
832static ssize_t set_port_type(struct device *dev,
833 struct device_attribute *attr,
834 const char *buf, size_t count)
835{
836 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
837 port_attr);
838 struct mlx4_dev *mdev = info->dev;
839 struct mlx4_priv *priv = mlx4_priv(mdev);
840 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 841 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 842 int i;
843 int err = 0;
844
845 if (!strcmp(buf, "ib\n"))
846 info->tmp_type = MLX4_PORT_TYPE_IB;
847 else if (!strcmp(buf, "eth\n"))
848 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 849 else if (!strcmp(buf, "auto\n"))
850 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 851 else {
852 mlx4_err(mdev, "%s is not supported port type\n", buf);
853 return -EINVAL;
854 }
855
27bf91d6 856 mlx4_stop_sense(mdev);
7ff93f8b 857 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 858 /* Possible type is always the one that was delivered */
859 mdev->caps.possible_type[info->port] = info->tmp_type;
860
861 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 862 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 863 mdev->caps.possible_type[i+1];
864 if (types[i] == MLX4_PORT_TYPE_AUTO)
865 types[i] = mdev->caps.port_type[i+1];
866 }
7ff93f8b 867
58a60168
YP		 868 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
869 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 870 for (i = 1; i <= mdev->caps.num_ports; i++) {
871 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
872 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
873 err = -EINVAL;
874 }
875 }
876 }
877 if (err) {
878 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
879 "Set only 'eth' or 'ib' for both ports "
880 "(should be the same)\n");
881 goto out;
882 }
883
884 mlx4_do_sense_ports(mdev, new_types, types);
885
886 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 887 if (err)
888 goto out;
889
27bf91d6
YP		 890 /* We are about to apply the changes after the configuration
891 * was verified, no need to remember the temporary types
892 * any more */
893 for (i = 0; i < mdev->caps.num_ports; i++)
894 priv->port[i + 1].tmp_type = 0;
7ff93f8b 895
27bf91d6 896 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 897
898out:
27bf91d6 899 mlx4_start_sense(mdev);
7ff93f8b
YP		 900 mutex_unlock(&priv->port_mutex);
901 return err ? err : count;
902}
903
096335b3
OG		 904enum ibta_mtu {
905 IB_MTU_256 = 1,
906 IB_MTU_512 = 2,
907 IB_MTU_1024 = 3,
908 IB_MTU_2048 = 4,
909 IB_MTU_4096 = 5
910};
911
912static inline int int_to_ibta_mtu(int mtu)
913{
914 switch (mtu) {
915 case 256: return IB_MTU_256;
916 case 512: return IB_MTU_512;
917 case 1024: return IB_MTU_1024;
918 case 2048: return IB_MTU_2048;
919 case 4096: return IB_MTU_4096;
920 default: return -1;
921 }
922}
923
924static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
925{
926 switch (mtu) {
927 case IB_MTU_256: return 256;
928 case IB_MTU_512: return 512;
929 case IB_MTU_1024: return 1024;
930 case IB_MTU_2048: return 2048;
931 case IB_MTU_4096: return 4096;
932 default: return -1;
933 }
934}
935
936static ssize_t show_port_ib_mtu(struct device *dev,
937 struct device_attribute *attr,
938 char *buf)
939{
940 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
941 port_mtu_attr);
942 struct mlx4_dev *mdev = info->dev;
943
944 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
945 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
946
947 sprintf(buf, "%d\n",
948 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
949 return strlen(buf);
950}
951
952static ssize_t set_port_ib_mtu(struct device *dev,
953 struct device_attribute *attr,
954 const char *buf, size_t count)
955{
956 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
957 port_mtu_attr);
958 struct mlx4_dev *mdev = info->dev;
959 struct mlx4_priv *priv = mlx4_priv(mdev);
960 int err, port, mtu, ibta_mtu = -1;
961
962 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
963 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
964 return -EINVAL;
965 }
966
618fad95
DB		 967 err = kstrtoint(buf, 0, &mtu);
968 if (!err)
096335b3
OG		 969 ibta_mtu = int_to_ibta_mtu(mtu);
970
618fad95 971 if (err || ibta_mtu < 0) {
096335b3
OG		 972 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
973 return -EINVAL;
974 }
975
976 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
977
978 mlx4_stop_sense(mdev);
979 mutex_lock(&priv->port_mutex);
980 mlx4_unregister_device(mdev);
981 for (port = 1; port <= mdev->caps.num_ports; port++) {
982 mlx4_CLOSE_PORT(mdev, port);
6634961c 983 err = mlx4_SET_PORT(mdev, port, -1);
096335b3
OG		 984 if (err) {
985 mlx4_err(mdev, "Failed to set port %d, "
986 "aborting\n", port);
987 goto err_set_port;
988 }
989 }
990 err = mlx4_register_device(mdev);
991err_set_port:
992 mutex_unlock(&priv->port_mutex);
993 mlx4_start_sense(mdev);
994 return err ? err : count;
995}
996
e8f9b2ed 997static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 998{
999 struct mlx4_priv *priv = mlx4_priv(dev);
1000 int err;
1001
1002 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1003 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 1004 if (!priv->fw.fw_icm) {
1005 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
1006 return -ENOMEM;
1007 }
1008
1009 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1010 if (err) {
1011 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
1012 goto err_free;
1013 }
1014
1015 err = mlx4_RUN_FW(dev);
1016 if (err) {
1017 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
1018 goto err_unmap_fa;
1019 }
1020
1021 return 0;
1022
1023err_unmap_fa:
1024 mlx4_UNMAP_FA(dev);
1025
1026err_free:
5b0bf5e2 1027 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1028 return err;
1029}
1030
e8f9b2ed
RD		 1031static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1032 int cmpt_entry_sz)
225c7b1f
RD		 1033{
1034 struct mlx4_priv *priv = mlx4_priv(dev);
1035 int err;
ab9c17a0 1036 int num_eqs;
225c7b1f
RD		 1037
1038 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1039 cmpt_base +
1040 ((u64) (MLX4_CMPT_TYPE_QP *
1041 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1042 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1043 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1044 0, 0);
225c7b1f
RD		 1045 if (err)
1046 goto err;
1047
1048 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1049 cmpt_base +
1050 ((u64) (MLX4_CMPT_TYPE_SRQ *
1051 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1052 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1053 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1054 if (err)
1055 goto err_qp;
1056
1057 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1058 cmpt_base +
1059 ((u64) (MLX4_CMPT_TYPE_CQ *
1060 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1061 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1062 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1063 if (err)
1064 goto err_srq;
1065
3fc929e2
MA		 1066 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1067 dev->caps.num_eqs;
225c7b1f
RD		 1068 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1069 cmpt_base +
1070 ((u64) (MLX4_CMPT_TYPE_EQ *
1071 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1072 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1073 if (err)
1074 goto err_cq;
1075
1076 return 0;
1077
1078err_cq:
1079 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1080
1081err_srq:
1082 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1083
1084err_qp:
1085 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1086
1087err:
1088 return err;
1089}
1090
3d73c288
RD		 1091static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1092 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1093{
1094 struct mlx4_priv *priv = mlx4_priv(dev);
1095 u64 aux_pages;
ab9c17a0 1096 int num_eqs;
225c7b1f
RD		 1097 int err;
1098
1099 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1100 if (err) {
1101 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
1102 return err;
1103 }
1104
1105 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
1106 (unsigned long long) icm_size >> 10,
1107 (unsigned long long) aux_pages << 2);
1108
1109 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1110 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 1111 if (!priv->fw.aux_icm) {
1112 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
1113 return -ENOMEM;
1114 }
1115
1116 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1117 if (err) {
1118 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
1119 goto err_free_aux;
1120 }
1121
1122 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1123 if (err) {
1124 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1125 goto err_unmap_aux;
1126 }
1127
ab9c17a0 1128
3fc929e2
MA		 1129 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1130 dev->caps.num_eqs;
fa0681d2
RD		 1131 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1132 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1133 num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1134 if (err) {
1135 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1136 goto err_unmap_cmpt;
1137 }
1138
d7bb58fb
JM		 1139 /*
1140 * Reserved MTT entries must be aligned up to a cacheline
1141 * boundary, since the FW will write to them, while the driver
1142 * writes to all other MTT entries. (The variable
1143 * dev->caps.mtt_entry_sz below is really the MTT segment
1144 * size, not the raw entry size)
1145 */
1146 dev->caps.reserved_mtts =
1147 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1148 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1149
225c7b1f
RD		 1150 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1151 init_hca->mtt_base,
1152 dev->caps.mtt_entry_sz,
2b8fb286 1153 dev->caps.num_mtts,
5b0bf5e2 1154 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 1155 if (err) {
1156 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1157 goto err_unmap_eq;
1158 }
1159
1160 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1161 init_hca->dmpt_base,
1162 dev_cap->dmpt_entry_sz,
1163 dev->caps.num_mpts,
5b0bf5e2 1164 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 1165 if (err) {
1166 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1167 goto err_unmap_mtt;
1168 }
1169
1170 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1171 init_hca->qpc_base,
1172 dev_cap->qpc_entry_sz,
1173 dev->caps.num_qps,
93fc9e1b
YP		 1174 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1175 0, 0);
225c7b1f
RD		 1176 if (err) {
1177 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1178 goto err_unmap_dmpt;
1179 }
1180
1181 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1182 init_hca->auxc_base,
1183 dev_cap->aux_entry_sz,
1184 dev->caps.num_qps,
93fc9e1b
YP		 1185 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1186 0, 0);
225c7b1f
RD		 1187 if (err) {
1188 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1189 goto err_unmap_qp;
1190 }
1191
1192 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1193 init_hca->altc_base,
1194 dev_cap->altc_entry_sz,
1195 dev->caps.num_qps,
93fc9e1b
YP		 1196 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1197 0, 0);
225c7b1f
RD		 1198 if (err) {
1199 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1200 goto err_unmap_auxc;
1201 }
1202
1203 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1204 init_hca->rdmarc_base,
1205 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1206 dev->caps.num_qps,
93fc9e1b
YP		 1207 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1208 0, 0);
225c7b1f
RD		 1209 if (err) {
1210 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1211 goto err_unmap_altc;
1212 }
1213
1214 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1215 init_hca->cqc_base,
1216 dev_cap->cqc_entry_sz,
1217 dev->caps.num_cqs,
5b0bf5e2 1218 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1219 if (err) {
1220 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1221 goto err_unmap_rdmarc;
1222 }
1223
1224 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1225 init_hca->srqc_base,
1226 dev_cap->srq_entry_sz,
1227 dev->caps.num_srqs,
5b0bf5e2 1228 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1229 if (err) {
1230 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1231 goto err_unmap_cq;
1232 }
1233
1234 /*
0ff1fb65
HHZ		 1235 * For flow steering device managed mode it is required to use
1236 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1237 * required, but for simplicity just map the whole multicast
1238 * group table now. The table isn't very big and it's a lot
1239 * easier than trying to track ref counts.
225c7b1f
RD		 1240 */
1241 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1242 init_hca->mc_base,
1243 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1244 dev->caps.num_mgms + dev->caps.num_amgms,
1245 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1246 0, 0);
225c7b1f
RD		 1247 if (err) {
1248 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1249 goto err_unmap_srq;
1250 }
1251
1252 return 0;
1253
1254err_unmap_srq:
1255 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1256
1257err_unmap_cq:
1258 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1259
1260err_unmap_rdmarc:
1261 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1262
1263err_unmap_altc:
1264 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1265
1266err_unmap_auxc:
1267 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1268
1269err_unmap_qp:
1270 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1271
1272err_unmap_dmpt:
1273 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1274
1275err_unmap_mtt:
1276 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1277
1278err_unmap_eq:
fa0681d2 1279 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1280
1281err_unmap_cmpt:
1282 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1283 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1284 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1285 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1286
1287err_unmap_aux:
1288 mlx4_UNMAP_ICM_AUX(dev);
1289
1290err_free_aux:
5b0bf5e2 1291 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1292
1293 return err;
1294}
1295
1296static void mlx4_free_icms(struct mlx4_dev *dev)
1297{
1298 struct mlx4_priv *priv = mlx4_priv(dev);
1299
1300 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1301 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1302 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1303 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1304 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1305 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1306 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1307 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1308 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1309 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1310 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1311 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1312 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1313 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1314
1315 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1316 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1317}
1318
ab9c17a0
JM		 1319static void mlx4_slave_exit(struct mlx4_dev *dev)
1320{
1321 struct mlx4_priv *priv = mlx4_priv(dev);
1322
f3d4c89e 1323 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1324 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1325 mlx4_warn(dev, "Failed to close slave function.\n");
f3d4c89e 1326 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1327}
1328
c1b43dca
EC		 1329static int map_bf_area(struct mlx4_dev *dev)
1330{
1331 struct mlx4_priv *priv = mlx4_priv(dev);
1332 resource_size_t bf_start;
1333 resource_size_t bf_len;
1334 int err = 0;
1335
3d747473
JM		 1336 if (!dev->caps.bf_reg_size)
1337 return -ENXIO;
1338
ab9c17a0
JM		 1339 bf_start = pci_resource_start(dev->pdev, 2) +
1340 (dev->caps.num_uars << PAGE_SHIFT);
1341 bf_len = pci_resource_len(dev->pdev, 2) -
1342 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1343 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1344 if (!priv->bf_mapping)
1345 err = -ENOMEM;
1346
1347 return err;
1348}
1349
1350static void unmap_bf_area(struct mlx4_dev *dev)
1351{
1352 if (mlx4_priv(dev)->bf_mapping)
1353 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1354}
1355
ec693d47
AV		 1356cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1357{
1358 u32 clockhi, clocklo, clockhi1;
1359 cycle_t cycles;
1360 int i;
1361 struct mlx4_priv *priv = mlx4_priv(dev);
1362
1363 for (i = 0; i < 10; i++) {
1364 clockhi = swab32(readl(priv->clock_mapping));
1365 clocklo = swab32(readl(priv->clock_mapping + 4));
1366 clockhi1 = swab32(readl(priv->clock_mapping));
1367 if (clockhi == clockhi1)
1368 break;
1369 }
1370
1371 cycles = (u64) clockhi << 32 | (u64) clocklo;
1372
1373 return cycles;
1374}
1375EXPORT_SYMBOL_GPL(mlx4_read_clock);
1376
1377
ddd8a6c1
EE		 1378static int map_internal_clock(struct mlx4_dev *dev)
1379{
1380 struct mlx4_priv *priv = mlx4_priv(dev);
1381
1382 priv->clock_mapping =
1383 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1384 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1385
1386 if (!priv->clock_mapping)
1387 return -ENOMEM;
1388
1389 return 0;
1390}
1391
1392static void unmap_internal_clock(struct mlx4_dev *dev)
1393{
1394 struct mlx4_priv *priv = mlx4_priv(dev);
1395
1396 if (priv->clock_mapping)
1397 iounmap(priv->clock_mapping);
1398}
1399
225c7b1f
RD		 1400static void mlx4_close_hca(struct mlx4_dev *dev)
1401{
ddd8a6c1 1402 unmap_internal_clock(dev);
c1b43dca 1403 unmap_bf_area(dev);
ab9c17a0
JM		 1404 if (mlx4_is_slave(dev))
1405 mlx4_slave_exit(dev);
1406 else {
1407 mlx4_CLOSE_HCA(dev, 0);
1408 mlx4_free_icms(dev);
1409 mlx4_UNMAP_FA(dev);
1410 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1411 }
1412}
1413
1414static int mlx4_init_slave(struct mlx4_dev *dev)
1415{
1416 struct mlx4_priv *priv = mlx4_priv(dev);
1417 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1418 int ret_from_reset = 0;
1419 u32 slave_read;
1420 u32 cmd_channel_ver;
1421
97989356
AV		 1422 if (atomic_read(&pf_loading)) {
1423 mlx4_warn(dev, "PF is not ready. Deferring probe\n");
1424 return -EPROBE_DEFER;
1425 }
1426
f3d4c89e 1427 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1428 priv->cmd.max_cmds = 1;
1429 mlx4_warn(dev, "Sending reset\n");
1430 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1431 MLX4_COMM_TIME);
1432 /* if we are in the middle of flr the slave will try
1433 * NUM_OF_RESET_RETRIES times before leaving.*/
1434 if (ret_from_reset) {
1435 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
5efe5355
JM		 1436 mlx4_warn(dev, "slave is currently in the "
1437 "middle of FLR. Deferring probe.\n");
1438 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1439 return -EPROBE_DEFER;
ab9c17a0
JM		 1440 } else
1441 goto err;
1442 }
1443
1444 /* check the driver version - the slave I/F revision
1445 * must match the master's */
1446 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1447 cmd_channel_ver = mlx4_comm_get_version();
1448
1449 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1450 MLX4_COMM_GET_IF_REV(slave_read)) {
1451 mlx4_err(dev, "slave driver version is not supported"
1452 " by the master\n");
1453 goto err;
1454 }
1455
1456 mlx4_warn(dev, "Sending vhcr0\n");
1457 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1458 MLX4_COMM_TIME))
1459 goto err;
1460 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1461 MLX4_COMM_TIME))
1462 goto err;
1463 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1464 MLX4_COMM_TIME))
1465 goto err;
1466 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1467 goto err;
f3d4c89e
RD		 1468
1469 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1470 return 0;
1471
1472err:
1473 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
f3d4c89e 1474 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1475 return -EIO;
225c7b1f
RD		 1476}
1477
6634961c
JM		 1478static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1479{
1480 int i;
1481
1482 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 1483 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1484 dev->caps.gid_table_len[i] =
449fc488 1485 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 1486 else
1487 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 1488 dev->caps.pkey_table_len[i] =
1489 dev->phys_caps.pkey_phys_table_len[i] - 1;
1490 }
1491}
1492
3c439b55
JM		 1493static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1494{
1495 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1496
1497 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1498 i++) {
1499 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1500 break;
1501 }
1502
1503 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1504}
1505
7b8157be
JM		 1506static void choose_steering_mode(struct mlx4_dev *dev,
1507 struct mlx4_dev_cap *dev_cap)
1508{
3c439b55
JM		 1509 if (mlx4_log_num_mgm_entry_size == -1 &&
1510 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1511 (!mlx4_is_mfunc(dev) ||
449fc488 1512 (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) &&
3c439b55
JM		 1513 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1514 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1515 dev->oper_log_mgm_entry_size =
1516 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1517 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1518 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1519 dev->caps.fs_log_max_ucast_qp_range_size =
1520 dev_cap->fs_log_max_ucast_qp_range_size;
1521 } else {
1522 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1523 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1524 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1525 else {
1526 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1527
1528 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1529 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1530 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1531 "set to use B0 steering. Falling back to A0 steering mode.\n");
1532 }
3c439b55
JM		 1533 dev->oper_log_mgm_entry_size =
1534 mlx4_log_num_mgm_entry_size > 0 ?
1535 mlx4_log_num_mgm_entry_size :
1536 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1537 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1538 }
3c439b55
JM		 1539 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1540 "modparam log_num_mgm_entry_size = %d\n",
1541 mlx4_steering_mode_str(dev->caps.steering_mode),
1542 dev->oper_log_mgm_entry_size,
1543 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1544}
1545
7ffdf726
OG		 1546static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1547 struct mlx4_dev_cap *dev_cap)
1548{
1549 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1550 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1551 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1552 else
1553 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1554
1555 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1556 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1557}
1558
3d73c288 1559static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1560{
1561 struct mlx4_priv *priv = mlx4_priv(dev);
1562 struct mlx4_adapter adapter;
1563 struct mlx4_dev_cap dev_cap;
2d928651 1564 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 1565 struct mlx4_profile profile;
1566 struct mlx4_init_hca_param init_hca;
1567 u64 icm_size;
1568 int err;
1569
ab9c17a0
JM		 1570 if (!mlx4_is_slave(dev)) {
1571 err = mlx4_QUERY_FW(dev);
1572 if (err) {
1573 if (err == -EACCES)
1574 mlx4_info(dev, "non-primary physical function, skipping.\n");
1575 else
1576 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
bef772eb 1577 return err;
ab9c17a0 1578 }
225c7b1f 1579
ab9c17a0
JM		 1580 err = mlx4_load_fw(dev);
1581 if (err) {
1582 mlx4_err(dev, "Failed to start FW, aborting.\n");
bef772eb 1583 return err;
ab9c17a0 1584 }
225c7b1f 1585
ab9c17a0
JM		 1586 mlx4_cfg.log_pg_sz_m = 1;
1587 mlx4_cfg.log_pg_sz = 0;
1588 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1589 if (err)
1590 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2d928651 1591
ab9c17a0
JM		 1592 err = mlx4_dev_cap(dev, &dev_cap);
1593 if (err) {
1594 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1595 goto err_stop_fw;
1596 }
225c7b1f 1597
7b8157be 1598 choose_steering_mode(dev, &dev_cap);
7ffdf726 1599 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 1600
8e1a28e8
HHZ		 1601 err = mlx4_get_phys_port_id(dev);
1602 if (err)
1603 mlx4_err(dev, "Fail to get physical port id\n");
1604
6634961c
JM		 1605 if (mlx4_is_master(dev))
1606 mlx4_parav_master_pf_caps(dev);
1607
ab9c17a0 1608 profile = default_profile;
0ff1fb65
HHZ		 1609 if (dev->caps.steering_mode ==
1610 MLX4_STEERING_MODE_DEVICE_MANAGED)
1611 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1612
ab9c17a0
JM		 1613 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1614 &init_hca);
1615 if ((long long) icm_size < 0) {
1616 err = icm_size;
1617 goto err_stop_fw;
1618 }
225c7b1f 1619
a5bbe892
EC		 1620 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1621
ab9c17a0
JM		 1622 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1623 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 1624 init_hca.mw_enabled = 0;
1625 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1626 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1627 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 1628
ab9c17a0
JM		 1629 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1630 if (err)
1631 goto err_stop_fw;
225c7b1f 1632
ab9c17a0
JM		 1633 err = mlx4_INIT_HCA(dev, &init_hca);
1634 if (err) {
1635 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1636 goto err_free_icm;
1637 }
ddd8a6c1
EE		 1638 /*
1639 * If TS is supported by FW
1640 * read HCA frequency by QUERY_HCA command
1641 */
1642 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1643 memset(&init_hca, 0, sizeof(init_hca));
1644 err = mlx4_QUERY_HCA(dev, &init_hca);
1645 if (err) {
1646 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1647 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1648 } else {
1649 dev->caps.hca_core_clock =
1650 init_hca.hca_core_clock;
1651 }
1652
1653 /* In case we got HCA frequency 0 - disable timestamping
1654 * to avoid dividing by zero
1655 */
1656 if (!dev->caps.hca_core_clock) {
1657 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1658 mlx4_err(dev,
1659 "HCA frequency is 0. Timestamping is not supported.");
1660 } else if (map_internal_clock(dev)) {
1661 /*
1662 * Map internal clock,
1663 * in case of failure disable timestamping
1664 */
1665 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1666 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1667 }
1668 }
ab9c17a0
JM		 1669 } else {
1670 err = mlx4_init_slave(dev);
1671 if (err) {
5efe5355
JM		 1672 if (err != -EPROBE_DEFER)
1673 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 1674 return err;
ab9c17a0 1675 }
225c7b1f 1676
ab9c17a0
JM		 1677 err = mlx4_slave_cap(dev);
1678 if (err) {
1679 mlx4_err(dev, "Failed to obtain slave caps\n");
1680 goto err_close;
1681 }
225c7b1f
RD		 1682 }
1683
ab9c17a0
JM		 1684 if (map_bf_area(dev))
1685 mlx4_dbg(dev, "Failed to map blue flame area\n");
1686
1687 /*Only the master set the ports, all the rest got it from it.*/
1688 if (!mlx4_is_slave(dev))
1689 mlx4_set_port_mask(dev);
1690
225c7b1f
RD		 1691 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1692 if (err) {
1693 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
bef772eb 1694 goto unmap_bf;
225c7b1f
RD		 1695 }
1696
1697 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1698 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1699
1700 return 0;
1701
bef772eb 1702unmap_bf:
ddd8a6c1 1703 unmap_internal_clock(dev);
bef772eb
AY		 1704 unmap_bf_area(dev);
1705
b38f2879 1706 if (mlx4_is_slave(dev)) {
99ec41d0 1707 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 1708 kfree(dev->caps.qp0_tunnel);
1709 kfree(dev->caps.qp0_proxy);
1710 kfree(dev->caps.qp1_tunnel);
1711 kfree(dev->caps.qp1_proxy);
1712 }
1713
225c7b1f 1714err_close:
41929ed2
DB		 1715 if (mlx4_is_slave(dev))
1716 mlx4_slave_exit(dev);
1717 else
1718 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 1719
1720err_free_icm:
ab9c17a0
JM		 1721 if (!mlx4_is_slave(dev))
1722 mlx4_free_icms(dev);
225c7b1f
RD		 1723
1724err_stop_fw:
ab9c17a0
JM		 1725 if (!mlx4_is_slave(dev)) {
1726 mlx4_UNMAP_FA(dev);
1727 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1728 }
225c7b1f
RD		 1729 return err;
1730}
1731
f2a3f6a3
OG		 1732static int mlx4_init_counters_table(struct mlx4_dev *dev)
1733{
1734 struct mlx4_priv *priv = mlx4_priv(dev);
1735 int nent;
1736
1737 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1738 return -ENOENT;
1739
1740 nent = dev->caps.max_counters;
1741 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1742}
1743
1744static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1745{
1746 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1747}
1748
ba062d52 1749int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 1750{
1751 struct mlx4_priv *priv = mlx4_priv(dev);
1752
1753 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1754 return -ENOENT;
1755
1756 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1757 if (*idx == -1)
1758 return -ENOMEM;
1759
1760 return 0;
1761}
ba062d52
JM		 1762
1763int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1764{
1765 u64 out_param;
1766 int err;
1767
1768 if (mlx4_is_mfunc(dev)) {
1769 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1770 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1771 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1772 if (!err)
1773 *idx = get_param_l(&out_param);
1774
1775 return err;
1776 }
1777 return __mlx4_counter_alloc(dev, idx);
1778}
f2a3f6a3
OG		 1779EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1780
ba062d52 1781void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 1782{
7c6d74d2 1783 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 1784 return;
1785}
ba062d52
JM		 1786
1787void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1788{
e7dbeba8 1789 u64 in_param = 0;
ba062d52
JM		 1790
1791 if (mlx4_is_mfunc(dev)) {
1792 set_param_l(&in_param, idx);
1793 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1794 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1795 MLX4_CMD_WRAPPED);
1796 return;
1797 }
1798 __mlx4_counter_free(dev, idx);
1799}
f2a3f6a3
OG		 1800EXPORT_SYMBOL_GPL(mlx4_counter_free);
1801
3d73c288 1802static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1803{
1804 struct mlx4_priv *priv = mlx4_priv(dev);
1805 int err;
7ff93f8b 1806 int port;
9a5aa622 1807 __be32 ib_port_default_caps;
225c7b1f 1808
225c7b1f
RD		 1809 err = mlx4_init_uar_table(dev);
1810 if (err) {
1811 mlx4_err(dev, "Failed to initialize "
1812 "user access region table, aborting.\n");
1813 return err;
1814 }
1815
1816 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1817 if (err) {
1818 mlx4_err(dev, "Failed to allocate driver access region, "
1819 "aborting.\n");
1820 goto err_uar_table_free;
1821 }
1822
4979d18f 1823 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f
RD		 1824 if (!priv->kar) {
1825 mlx4_err(dev, "Couldn't map kernel access region, "
1826 "aborting.\n");
1827 err = -ENOMEM;
1828 goto err_uar_free;
1829 }
1830
1831 err = mlx4_init_pd_table(dev);
1832 if (err) {
1833 mlx4_err(dev, "Failed to initialize "
1834 "protection domain table, aborting.\n");
1835 goto err_kar_unmap;
1836 }
1837
012a8ff5
SH		 1838 err = mlx4_init_xrcd_table(dev);
1839 if (err) {
1840 mlx4_err(dev, "Failed to initialize "
1841 "reliable connection domain table, aborting.\n");
1842 goto err_pd_table_free;
1843 }
1844
225c7b1f
RD		 1845 err = mlx4_init_mr_table(dev);
1846 if (err) {
1847 mlx4_err(dev, "Failed to initialize "
1848 "memory region table, aborting.\n");
012a8ff5 1849 goto err_xrcd_table_free;
225c7b1f
RD		 1850 }
1851
fe6f700d
YP		 1852 if (!mlx4_is_slave(dev)) {
1853 err = mlx4_init_mcg_table(dev);
1854 if (err) {
1855 mlx4_err(dev, "Failed to initialize multicast group table, aborting.\n");
1856 goto err_mr_table_free;
1857 }
1858 }
1859
225c7b1f
RD		 1860 err = mlx4_init_eq_table(dev);
1861 if (err) {
1862 mlx4_err(dev, "Failed to initialize "
1863 "event queue table, aborting.\n");
fe6f700d 1864 goto err_mcg_table_free;
225c7b1f
RD		 1865 }
1866
1867 err = mlx4_cmd_use_events(dev);
1868 if (err) {
1869 mlx4_err(dev, "Failed to switch to event-driven "
1870 "firmware commands, aborting.\n");
1871 goto err_eq_table_free;
1872 }
1873
1874 err = mlx4_NOP(dev);
1875 if (err) {
08fb1055
MT		 1876 if (dev->flags & MLX4_FLAG_MSI_X) {
1877 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1878 "interrupt IRQ %d).\n",
b8dd786f 1879 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 1880 mlx4_warn(dev, "Trying again without MSI-X.\n");
1881 } else {
1882 mlx4_err(dev, "NOP command failed to generate interrupt "
1883 "(IRQ %d), aborting.\n",
b8dd786f 1884 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 1885 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 1886 }
225c7b1f
RD		 1887
1888 goto err_cmd_poll;
1889 }
1890
1891 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1892
1893 err = mlx4_init_cq_table(dev);
1894 if (err) {
1895 mlx4_err(dev, "Failed to initialize "
1896 "completion queue table, aborting.\n");
1897 goto err_cmd_poll;
1898 }
1899
1900 err = mlx4_init_srq_table(dev);
1901 if (err) {
1902 mlx4_err(dev, "Failed to initialize "
1903 "shared receive queue table, aborting.\n");
1904 goto err_cq_table_free;
1905 }
1906
1907 err = mlx4_init_qp_table(dev);
1908 if (err) {
1909 mlx4_err(dev, "Failed to initialize "
1910 "queue pair table, aborting.\n");
1911 goto err_srq_table_free;
1912 }
1913
f2a3f6a3
OG		 1914 err = mlx4_init_counters_table(dev);
1915 if (err && err != -ENOENT) {
1916 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
fe6f700d 1917 goto err_qp_table_free;
f2a3f6a3
OG		 1918 }
1919
ab9c17a0
JM		 1920 if (!mlx4_is_slave(dev)) {
1921 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 1922 ib_port_default_caps = 0;
1923 err = mlx4_get_port_ib_caps(dev, port,
1924 &ib_port_default_caps);
1925 if (err)
1926 mlx4_warn(dev, "failed to get port %d default "
1927 "ib capabilities (%d). Continuing "
1928 "with caps = 0\n", port, err);
1929 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1930
2aca1172
JM		 1931 /* initialize per-slave default ib port capabilities */
1932 if (mlx4_is_master(dev)) {
1933 int i;
1934 for (i = 0; i < dev->num_slaves; i++) {
1935 if (i == mlx4_master_func_num(dev))
1936 continue;
1937 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1938 ib_port_default_caps;
1939 }
1940 }
1941
096335b3
OG		 1942 if (mlx4_is_mfunc(dev))
1943 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1944 else
1945 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 1946
6634961c
JM		 1947 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1948 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 1949 if (err) {
1950 mlx4_err(dev, "Failed to set port %d, aborting\n",
1951 port);
1952 goto err_counters_table_free;
1953 }
7ff93f8b
YP		 1954 }
1955 }
1956
225c7b1f
RD		 1957 return 0;
1958
f2a3f6a3
OG		 1959err_counters_table_free:
1960 mlx4_cleanup_counters_table(dev);
1961
225c7b1f
RD		 1962err_qp_table_free:
1963 mlx4_cleanup_qp_table(dev);
1964
1965err_srq_table_free:
1966 mlx4_cleanup_srq_table(dev);
1967
1968err_cq_table_free:
1969 mlx4_cleanup_cq_table(dev);
1970
1971err_cmd_poll:
1972 mlx4_cmd_use_polling(dev);
1973
1974err_eq_table_free:
1975 mlx4_cleanup_eq_table(dev);
1976
fe6f700d
YP		 1977err_mcg_table_free:
1978 if (!mlx4_is_slave(dev))
1979 mlx4_cleanup_mcg_table(dev);
1980
ee49bd93 1981err_mr_table_free:
225c7b1f
RD		 1982 mlx4_cleanup_mr_table(dev);
1983
012a8ff5
SH		 1984err_xrcd_table_free:
1985 mlx4_cleanup_xrcd_table(dev);
1986
225c7b1f
RD		 1987err_pd_table_free:
1988 mlx4_cleanup_pd_table(dev);
1989
1990err_kar_unmap:
1991 iounmap(priv->kar);
1992
1993err_uar_free:
1994 mlx4_uar_free(dev, &priv->driver_uar);
1995
1996err_uar_table_free:
1997 mlx4_cleanup_uar_table(dev);
1998 return err;
1999}
2000
e8f9b2ed 2001static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2002{
2003 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2004 struct msix_entry *entries;
0b7ca5a9 2005 int nreq = min_t(int, dev->caps.num_ports *
bb2146bc 2006 min_t(int, num_online_cpus() + 1,
90b1ebe7 2007 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
225c7b1f
RD		 2008 int i;
2009
2010 if (msi_x) {
ca4c7b35
OG		 2011 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2012 nreq);
ab9c17a0 2013
b8dd786f
YP		 2014 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2015 if (!entries)
2016 goto no_msi;
2017
2018 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2019 entries[i].entry = i;
2020
66e2f9c1
AG		 2021 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
2022
2023 if (nreq < 0) {
5bf0da7d 2024 kfree(entries);
225c7b1f 2025 goto no_msi;
66e2f9c1
AG		 2026 } else if (nreq < MSIX_LEGACY_SZ +
2027 dev->caps.num_ports * MIN_MSIX_P_PORT) {
0b7ca5a9
YP		 2028 /*Working in legacy mode , all EQ's shared*/
2029 dev->caps.comp_pool = 0;
2030 dev->caps.num_comp_vectors = nreq - 1;
2031 } else {
2032 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2033 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2034 }
b8dd786f 2035 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2036 priv->eq_table.eq[i].irq = entries[i].vector;
2037
2038 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2039
2040 kfree(entries);
225c7b1f
RD		 2041 return;
2042 }
2043
2044no_msi:
b8dd786f 2045 dev->caps.num_comp_vectors = 1;
0b7ca5a9 2046 dev->caps.comp_pool = 0;
b8dd786f
YP		 2047
2048 for (i = 0; i < 2; ++i)
225c7b1f
RD		 2049 priv->eq_table.eq[i].irq = dev->pdev->irq;
2050}
2051
7ff93f8b 2052static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 2053{
2054 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 2055 int err = 0;
2a2336f8
YP		 2056
2057 info->dev = dev;
2058 info->port = port;
ab9c17a0 2059 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2060 mlx4_init_mac_table(dev, &info->mac_table);
2061 mlx4_init_vlan_table(dev, &info->vlan_table);
16a10ffd 2062 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2063 }
7ff93f8b
YP		 2064
2065 sprintf(info->dev_name, "mlx4_port%d", port);
2066 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2067 if (mlx4_is_mfunc(dev))
2068 info->port_attr.attr.mode = S_IRUGO;
2069 else {
2070 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2071 info->port_attr.store = set_port_type;
2072 }
7ff93f8b 2073 info->port_attr.show = show_port_type;
3691c964 2074 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 2075
2076 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2077 if (err) {
2078 mlx4_err(dev, "Failed to create file for port %d\n", port);
2079 info->port = -1;
2080 }
2081
096335b3
OG		 2082 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2083 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2084 if (mlx4_is_mfunc(dev))
2085 info->port_mtu_attr.attr.mode = S_IRUGO;
2086 else {
2087 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2088 info->port_mtu_attr.store = set_port_ib_mtu;
2089 }
2090 info->port_mtu_attr.show = show_port_ib_mtu;
2091 sysfs_attr_init(&info->port_mtu_attr.attr);
2092
2093 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2094 if (err) {
2095 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2096 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2097 info->port = -1;
2098 }
2099
7ff93f8b
YP		 2100 return err;
2101}
2102
2103static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2104{
2105 if (info->port < 0)
2106 return;
2107
2108 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 2109 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 2110}
2111
b12d93d6
YP		 2112static int mlx4_init_steering(struct mlx4_dev *dev)
2113{
2114 struct mlx4_priv *priv = mlx4_priv(dev);
2115 int num_entries = dev->caps.num_ports;
2116 int i, j;
2117
2118 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2119 if (!priv->steer)
2120 return -ENOMEM;
2121
45b51365 2122 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2123 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2124 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2125 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2126 }
b12d93d6
YP		 2127 return 0;
2128}
2129
2130static void mlx4_clear_steering(struct mlx4_dev *dev)
2131{
2132 struct mlx4_priv *priv = mlx4_priv(dev);
2133 struct mlx4_steer_index *entry, *tmp_entry;
2134 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2135 int num_entries = dev->caps.num_ports;
2136 int i, j;
2137
2138 for (i = 0; i < num_entries; i++) {
2139 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2140 list_for_each_entry_safe(pqp, tmp_pqp,
2141 &priv->steer[i].promisc_qps[j],
2142 list) {
2143 list_del(&pqp->list);
2144 kfree(pqp);
2145 }
2146 list_for_each_entry_safe(entry, tmp_entry,
2147 &priv->steer[i].steer_entries[j],
2148 list) {
2149 list_del(&entry->list);
2150 list_for_each_entry_safe(pqp, tmp_pqp,
2151 &entry->duplicates,
2152 list) {
2153 list_del(&pqp->list);
2154 kfree(pqp);
2155 }
2156 kfree(entry);
2157 }
2158 }
2159 }
2160 kfree(priv->steer);
2161}
2162
ab9c17a0
JM		 2163static int extended_func_num(struct pci_dev *pdev)
2164{
2165 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2166}
2167
2168#define MLX4_OWNER_BASE 0x8069c
2169#define MLX4_OWNER_SIZE 4
2170
2171static int mlx4_get_ownership(struct mlx4_dev *dev)
2172{
2173 void __iomem *owner;
2174 u32 ret;
2175
57dbf29a
KSS		 2176 if (pci_channel_offline(dev->pdev))
2177 return -EIO;
2178
ab9c17a0
JM		 2179 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2180 MLX4_OWNER_SIZE);
2181 if (!owner) {
2182 mlx4_err(dev, "Failed to obtain ownership bit\n");
2183 return -ENOMEM;
2184 }
2185
2186 ret = readl(owner);
2187 iounmap(owner);
2188 return (int) !!ret;
2189}
2190
2191static void mlx4_free_ownership(struct mlx4_dev *dev)
2192{
2193 void __iomem *owner;
2194
57dbf29a
KSS		 2195 if (pci_channel_offline(dev->pdev))
2196 return;
2197
ab9c17a0
JM		 2198 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2199 MLX4_OWNER_SIZE);
2200 if (!owner) {
2201 mlx4_err(dev, "Failed to obtain ownership bit\n");
2202 return;
2203 }
2204 writel(0, owner);
2205 msleep(1000);
2206 iounmap(owner);
2207}
2208
839f1243 2209static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
225c7b1f 2210{
225c7b1f
RD		 2211 struct mlx4_priv *priv;
2212 struct mlx4_dev *dev;
2213 int err;
2a2336f8 2214 int port;
dd41cc3b
MB		 2215 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2216 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2217 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
2218 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
1ab95d37
MB		 2219 unsigned total_vfs = 0;
2220 int sriov_initialized = 0;
2221 unsigned int i;
225c7b1f 2222
0a645e80 2223 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
225c7b1f
RD		 2224
2225 err = pci_enable_device(pdev);
2226 if (err) {
2227 dev_err(&pdev->dev, "Cannot enable PCI device, "
2228 "aborting.\n");
2229 return err;
2230 }
5a0d0a61
JM		 2231
2232 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2233 * per port, we must limit the number of VFs to 63 (since their are
2234 * 128 MACs)
2235 */
dd41cc3b
MB		 2236 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
2237 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
2238 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
1ab95d37
MB		 2239 if (nvfs[i] < 0) {
2240 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
2241 return -EINVAL;
2242 }
2243 }
dd41cc3b
MB		 2244 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
2245 i++) {
2246 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
1ab95d37
MB		 2247 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
2248 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2249 return -EINVAL;
2250 }
2251 }
2252 if (total_vfs >= MLX4_MAX_NUM_VF) {
5a0d0a61
JM		 2253 dev_err(&pdev->dev,
2254 "Requested more VF's (%d) than allowed (%d)\n",
1ab95d37 2255 total_vfs, MLX4_MAX_NUM_VF - 1);
ab9c17a0
JM		 2256 return -EINVAL;
2257 }
30e514a7 2258
1ab95d37
MB		 2259 for (i = 0; i < MLX4_MAX_PORTS; i++) {
2260 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
2261 dev_err(&pdev->dev,
2262 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2263 nvfs[i] + nvfs[2], i + 1,
2264 MLX4_MAX_NUM_VF_P_PORT - 1);
2265 return -EINVAL;
2266 }
30e514a7 2267 }
1ab95d37
MB		 2268
2269
225c7b1f 2270 /*
ab9c17a0 2271 * Check for BARs.
225c7b1f 2272 */
839f1243 2273 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
ab9c17a0
JM		 2274 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2275 dev_err(&pdev->dev, "Missing DCS, aborting."
839f1243
RD		 2276 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2277 pci_dev_data, pci_resource_flags(pdev, 0));
225c7b1f
RD		 2278 err = -ENODEV;
2279 goto err_disable_pdev;
2280 }
2281 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2282 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2283 err = -ENODEV;
2284 goto err_disable_pdev;
2285 }
2286
a01df0fe 2287 err = pci_request_regions(pdev, DRV_NAME);
225c7b1f 2288 if (err) {
a01df0fe 2289 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225c7b1f
RD		 2290 goto err_disable_pdev;
2291 }
2292
225c7b1f
RD		 2293 pci_set_master(pdev);
2294
6a35528a 2295 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 2296 if (err) {
2297 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 2298 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 2299 if (err) {
2300 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
a01df0fe 2301 goto err_release_regions;
225c7b1f
RD		 2302 }
2303 }
6a35528a 2304 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 2305 if (err) {
2306 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2307 "consistent PCI DMA mask.\n");
284901a9 2308 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 2309 if (err) {
2310 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2311 "aborting.\n");
a01df0fe 2312 goto err_release_regions;
225c7b1f
RD		 2313 }
2314 }
2315
7f9e5c48
DD		 2316 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2317 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2318
befdf897
WY		 2319 dev = pci_get_drvdata(pdev);
2320 priv = mlx4_priv(dev);
225c7b1f 2321 dev->pdev = pdev;
b581401e
RD		 2322 INIT_LIST_HEAD(&priv->ctx_list);
2323 spin_lock_init(&priv->ctx_lock);
225c7b1f 2324
7ff93f8b
YP		 2325 mutex_init(&priv->port_mutex);
2326
6296883c
YP		 2327 INIT_LIST_HEAD(&priv->pgdir_list);
2328 mutex_init(&priv->pgdir_mutex);
2329
c1b43dca
EC		 2330 INIT_LIST_HEAD(&priv->bf_list);
2331 mutex_init(&priv->bf_mutex);
2332
aca7a3ac 2333 dev->rev_id = pdev->revision;
6e7136ed 2334 dev->numa_node = dev_to_node(&pdev->dev);
ab9c17a0 2335 /* Detect if this device is a virtual function */
839f1243 2336 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2337 /* When acting as pf, we normally skip vfs unless explicitly
2338 * requested to probe them. */
1ab95d37
MB		 2339 if (total_vfs) {
2340 unsigned vfs_offset = 0;
2341 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
2342 vfs_offset + nvfs[i] < extended_func_num(pdev);
2343 vfs_offset += nvfs[i], i++)
2344 ;
2345 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
2346 err = -ENODEV;
2347 goto err_free_dev;
2348 }
2349 if ((extended_func_num(pdev) - vfs_offset)
2350 > prb_vf[i]) {
2351 mlx4_warn(dev, "Skipping virtual function:%d\n",
2352 extended_func_num(pdev));
2353 err = -ENODEV;
2354 goto err_free_dev;
2355 }
ab9c17a0
JM		 2356 }
2357 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2358 dev->flags |= MLX4_FLAG_SLAVE;
2359 } else {
2360 /* We reset the device and enable SRIOV only for physical
2361 * devices. Try to claim ownership on the device;
2362 * if already taken, skip -- do not allow multiple PFs */
2363 err = mlx4_get_ownership(dev);
2364 if (err) {
2365 if (err < 0)
2366 goto err_free_dev;
2367 else {
2368 mlx4_warn(dev, "Multiple PFs not yet supported."
2369 " Skipping PF.\n");
2370 err = -EINVAL;
2371 goto err_free_dev;
2372 }
2373 }
aca7a3ac 2374
1ab95d37
MB		 2375 if (total_vfs) {
2376 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n",
2377 total_vfs);
2378 dev->dev_vfs = kzalloc(
2379 total_vfs * sizeof(*dev->dev_vfs),
2380 GFP_KERNEL);
2381 if (NULL == dev->dev_vfs) {
2382 mlx4_err(dev, "Failed to allocate memory for VFs\n");
ab9c17a0
JM		 2383 err = 0;
2384 } else {
1ab95d37
MB		 2385 atomic_inc(&pf_loading);
2386 err = pci_enable_sriov(pdev, total_vfs);
1ab95d37
MB		 2387 if (err) {
2388 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2389 err);
e1a5ddc5 2390 atomic_dec(&pf_loading);
1ab95d37
MB		 2391 err = 0;
2392 } else {
2393 mlx4_warn(dev, "Running in master mode\n");
2394 dev->flags |= MLX4_FLAG_SRIOV |
2395 MLX4_FLAG_MASTER;
2396 dev->num_vfs = total_vfs;
2397 sriov_initialized = 1;
2398 }
ab9c17a0
JM		 2399 }
2400 }
2401
fe6f700d
YP		 2402 atomic_set(&priv->opreq_count, 0);
2403 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2404
ab9c17a0
JM		 2405 /*
2406 * Now reset the HCA before we touch the PCI capabilities or
2407 * attempt a firmware command, since a boot ROM may have left
2408 * the HCA in an undefined state.
2409 */
2410 err = mlx4_reset(dev);
2411 if (err) {
2412 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2413 goto err_rel_own;
2414 }
225c7b1f
RD		 2415 }
2416
ab9c17a0 2417slave_start:
521130d1
EE		 2418 err = mlx4_cmd_init(dev);
2419 if (err) {
225c7b1f 2420 mlx4_err(dev, "Failed to init command interface, aborting.\n");
ab9c17a0
JM		 2421 goto err_sriov;
2422 }
2423
2424 /* In slave functions, the communication channel must be initialized
2425 * before posting commands. Also, init num_slaves before calling
2426 * mlx4_init_hca */
2427 if (mlx4_is_mfunc(dev)) {
2428 if (mlx4_is_master(dev))
2429 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2430 else {
2431 dev->num_slaves = 0;
f356fcbe
JM		 2432 err = mlx4_multi_func_init(dev);
2433 if (err) {
ab9c17a0
JM		 2434 mlx4_err(dev, "Failed to init slave mfunc"
2435 " interface, aborting.\n");
2436 goto err_cmd;
2437 }
2438 }
225c7b1f
RD		 2439 }
2440
2441 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2442 if (err) {
2443 if (err == -EACCES) {
2444 /* Not primary Physical function
2445 * Running in slave mode */
2446 mlx4_cmd_cleanup(dev);
2447 dev->flags |= MLX4_FLAG_SLAVE;
2448 dev->flags &= ~MLX4_FLAG_MASTER;
2449 goto slave_start;
2450 } else
2451 goto err_mfunc;
2452 }
2453
b912b2f8
EP		 2454 /* check if the device is functioning at its maximum possible speed.
2455 * No return code for this call, just warn the user in case of PCI
2456 * express device capabilities are under-satisfied by the bus.
2457 */
83d3459a
EP		 2458 if (!mlx4_is_slave(dev))
2459 mlx4_check_pcie_caps(dev);
b912b2f8 2460
ab9c17a0
JM		 2461 /* In master functions, the communication channel must be initialized
2462 * after obtaining its address from fw */
2463 if (mlx4_is_master(dev)) {
1ab95d37 2464 unsigned sum = 0;
f356fcbe
JM		 2465 err = mlx4_multi_func_init(dev);
2466 if (err) {
ab9c17a0
JM		 2467 mlx4_err(dev, "Failed to init master mfunc"
2468 "interface, aborting.\n");
2469 goto err_close;
2470 }
1ab95d37 2471 if (sriov_initialized) {
dd41cc3b
MB		 2472 int ib_ports = 0;
2473 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2474 ib_ports++;
2475
2476 if (ib_ports &&
2477 (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2478 mlx4_err(dev,
2479 "Invalid syntax of num_vfs/probe_vfs "
2480 "with IB port. Single port VFs syntax"
2481 " is only supported when all ports "
2482 "are configured as ethernet\n");
2483 goto err_close;
2484 }
1ab95d37
MB		 2485 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]); i++) {
2486 unsigned j;
2487 for (j = 0; j < nvfs[i]; ++sum, ++j) {
2488 dev->dev_vfs[sum].min_port =
2489 i < 2 ? i + 1 : 1;
2490 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2491 dev->caps.num_ports;
2492 }
2493 }
2494 }
ab9c17a0 2495 }
225c7b1f 2496
b8dd786f
YP		 2497 err = mlx4_alloc_eq_table(dev);
2498 if (err)
ab9c17a0 2499 goto err_master_mfunc;
b8dd786f 2500
0b7ca5a9 2501 priv->msix_ctl.pool_bm = 0;
730c41d5 2502 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2503
08fb1055 2504 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2505 if ((mlx4_is_mfunc(dev)) &&
2506 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2507 err = -ENOSYS;
ab9c17a0
JM		 2508 mlx4_err(dev, "INTx is not supported in multi-function mode."
2509 " aborting.\n");
b12d93d6 2510 goto err_free_eq;
ab9c17a0
JM		 2511 }
2512
2513 if (!mlx4_is_slave(dev)) {
2514 err = mlx4_init_steering(dev);
2515 if (err)
2516 goto err_free_eq;
2517 }
b12d93d6 2518
225c7b1f 2519 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2520 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2521 !mlx4_is_mfunc(dev)) {
08fb1055 2522 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2523 dev->caps.num_comp_vectors = 1;
2524 dev->caps.comp_pool = 0;
08fb1055
MT		 2525 pci_disable_msix(pdev);
2526 err = mlx4_setup_hca(dev);
2527 }
2528
225c7b1f 2529 if (err)
b12d93d6 2530 goto err_steer;
225c7b1f 2531
5a0d0a61
JM		 2532 mlx4_init_quotas(dev);
2533
7ff93f8b
YP		 2534 for (port = 1; port <= dev->caps.num_ports; port++) {
2535 err = mlx4_init_port_info(dev, port);
2536 if (err)
2537 goto err_port;
2538 }
2a2336f8 2539
225c7b1f
RD		 2540 err = mlx4_register_device(dev);
2541 if (err)
7ff93f8b 2542 goto err_port;
225c7b1f 2543
b046ffe5
EP		 2544 mlx4_request_modules(dev);
2545
27bf91d6
YP		 2546 mlx4_sense_init(dev);
2547 mlx4_start_sense(dev);
2548
befdf897 2549 priv->removed = 0;
225c7b1f 2550
e1a5ddc5
AV		 2551 if (mlx4_is_master(dev) && dev->num_vfs)
2552 atomic_dec(&pf_loading);
2553
225c7b1f
RD		 2554 return 0;
2555
7ff93f8b 2556err_port:
b4f77264 2557 for (--port; port >= 1; --port)
7ff93f8b
YP		 2558 mlx4_cleanup_port_info(&priv->port[port]);
2559
f2a3f6a3 2560 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2561 mlx4_cleanup_qp_table(dev);
2562 mlx4_cleanup_srq_table(dev);
2563 mlx4_cleanup_cq_table(dev);
2564 mlx4_cmd_use_polling(dev);
2565 mlx4_cleanup_eq_table(dev);
fe6f700d 2566 mlx4_cleanup_mcg_table(dev);
225c7b1f 2567 mlx4_cleanup_mr_table(dev);
012a8ff5 2568 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2569 mlx4_cleanup_pd_table(dev);
2570 mlx4_cleanup_uar_table(dev);
2571
b12d93d6 2572err_steer:
ab9c17a0
JM		 2573 if (!mlx4_is_slave(dev))
2574 mlx4_clear_steering(dev);
b12d93d6 2575
b8dd786f
YP		 2576err_free_eq:
2577 mlx4_free_eq_table(dev);
2578
ab9c17a0
JM		 2579err_master_mfunc:
2580 if (mlx4_is_master(dev))
2581 mlx4_multi_func_cleanup(dev);
2582
b38f2879 2583 if (mlx4_is_slave(dev)) {
99ec41d0 2584 kfree(dev->caps.qp0_qkey);
b38f2879
DB		 2585 kfree(dev->caps.qp0_tunnel);
2586 kfree(dev->caps.qp0_proxy);
2587 kfree(dev->caps.qp1_tunnel);
2588 kfree(dev->caps.qp1_proxy);
2589 }
2590
225c7b1f 2591err_close:
08fb1055
MT		 2592 if (dev->flags & MLX4_FLAG_MSI_X)
2593 pci_disable_msix(pdev);
2594
225c7b1f
RD		 2595 mlx4_close_hca(dev);
2596
ab9c17a0
JM		 2597err_mfunc:
2598 if (mlx4_is_slave(dev))
2599 mlx4_multi_func_cleanup(dev);
2600
225c7b1f
RD		 2601err_cmd:
2602 mlx4_cmd_cleanup(dev);
2603
ab9c17a0 2604err_sriov:
681372a7 2605 if (dev->flags & MLX4_FLAG_SRIOV)
ab9c17a0
JM		 2606 pci_disable_sriov(pdev);
2607
2608err_rel_own:
2609 if (!mlx4_is_slave(dev))
2610 mlx4_free_ownership(dev);
2611
e1a5ddc5
AV		 2612 if (mlx4_is_master(dev) && dev->num_vfs)
2613 atomic_dec(&pf_loading);
2614
1ab95d37
MB		 2615 kfree(priv->dev.dev_vfs);
2616
225c7b1f 2617err_free_dev:
225c7b1f
RD		 2618 kfree(priv);
2619
a01df0fe
RD		 2620err_release_regions:
2621 pci_release_regions(pdev);
225c7b1f
RD		 2622
2623err_disable_pdev:
2624 pci_disable_device(pdev);
2625 pci_set_drvdata(pdev, NULL);
2626 return err;
2627}
2628
1dd06ae8 2629static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 2630{
befdf897
WY		 2631 struct mlx4_priv *priv;
2632 struct mlx4_dev *dev;
2633
0a645e80 2634 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 2635
befdf897
WY		 2636 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2637 if (!priv)
2638 return -ENOMEM;
2639
2640 dev = &priv->dev;
2641 pci_set_drvdata(pdev, dev);
2642 priv->pci_dev_data = id->driver_data;
2643
839f1243 2644 return __mlx4_init_one(pdev, id->driver_data);
3d73c288
RD		 2645}
2646
befdf897 2647static void __mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 2648{
2649 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2650 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 2651 int pci_dev_data;
225c7b1f
RD		 2652 int p;
2653
befdf897
WY		 2654 if (priv->removed)
2655 return;
225c7b1f 2656
befdf897 2657 pci_dev_data = priv->pci_dev_data;
225c7b1f 2658
befdf897
WY		 2659 /* in SRIOV it is not allowed to unload the pf's
2660 * driver while there are alive vf's */
2661 if (mlx4_is_master(dev) && mlx4_how_many_lives_vf(dev))
2662 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2663 mlx4_stop_sense(dev);
2664 mlx4_unregister_device(dev);
225c7b1f 2665
befdf897
WY		 2666 for (p = 1; p <= dev->caps.num_ports; p++) {
2667 mlx4_cleanup_port_info(&priv->port[p]);
2668 mlx4_CLOSE_PORT(dev, p);
2669 }
2670
2671 if (mlx4_is_master(dev))
2672 mlx4_free_resource_tracker(dev,
2673 RES_TR_FREE_SLAVES_ONLY);
2674
2675 mlx4_cleanup_counters_table(dev);
2676 mlx4_cleanup_qp_table(dev);
2677 mlx4_cleanup_srq_table(dev);
2678 mlx4_cleanup_cq_table(dev);
2679 mlx4_cmd_use_polling(dev);
2680 mlx4_cleanup_eq_table(dev);
2681 mlx4_cleanup_mcg_table(dev);
2682 mlx4_cleanup_mr_table(dev);
2683 mlx4_cleanup_xrcd_table(dev);
2684 mlx4_cleanup_pd_table(dev);
225c7b1f 2685
befdf897
WY		 2686 if (mlx4_is_master(dev))
2687 mlx4_free_resource_tracker(dev,
2688 RES_TR_FREE_STRUCTS_ONLY);
47605df9 2689
befdf897
WY		 2690 iounmap(priv->kar);
2691 mlx4_uar_free(dev, &priv->driver_uar);
2692 mlx4_cleanup_uar_table(dev);
2693 if (!mlx4_is_slave(dev))
2694 mlx4_clear_steering(dev);
2695 mlx4_free_eq_table(dev);
2696 if (mlx4_is_master(dev))
2697 mlx4_multi_func_cleanup(dev);
2698 mlx4_close_hca(dev);
2699 if (mlx4_is_slave(dev))
2700 mlx4_multi_func_cleanup(dev);
2701 mlx4_cmd_cleanup(dev);
47605df9 2702
befdf897
WY		 2703 if (dev->flags & MLX4_FLAG_MSI_X)
2704 pci_disable_msix(pdev);
2705 if (dev->flags & MLX4_FLAG_SRIOV) {
2706 mlx4_warn(dev, "Disabling SR-IOV\n");
2707 pci_disable_sriov(pdev);
e1a5ddc5 2708 dev->num_vfs = 0;
225c7b1f 2709 }
befdf897
WY		 2710
2711 if (!mlx4_is_slave(dev))
2712 mlx4_free_ownership(dev);
2713
99ec41d0 2714 kfree(dev->caps.qp0_qkey);
befdf897
WY		 2715 kfree(dev->caps.qp0_tunnel);
2716 kfree(dev->caps.qp0_proxy);
2717 kfree(dev->caps.qp1_tunnel);
2718 kfree(dev->caps.qp1_proxy);
2719 kfree(dev->dev_vfs);
2720
2721 pci_release_regions(pdev);
2722 pci_disable_device(pdev);
2723 memset(priv, 0, sizeof(*priv));
2724 priv->pci_dev_data = pci_dev_data;
2725 priv->removed = 1;
2726}
2727
2728static void mlx4_remove_one(struct pci_dev *pdev)
2729{
2730 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2731 struct mlx4_priv *priv = mlx4_priv(dev);
2732
2733 __mlx4_remove_one(pdev);
2734 kfree(priv);
2735 pci_set_drvdata(pdev, NULL);
225c7b1f
RD		 2736}
2737
ee49bd93
JM		 2738int mlx4_restart_one(struct pci_dev *pdev)
2739{
839f1243
RD		 2740 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2741 struct mlx4_priv *priv = mlx4_priv(dev);
2742 int pci_dev_data;
2743
2744 pci_dev_data = priv->pci_dev_data;
befdf897 2745 __mlx4_remove_one(pdev);
839f1243 2746 return __mlx4_init_one(pdev, pci_dev_data);
ee49bd93
JM		 2747}
2748
a3aa1884 2749static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
ab9c17a0 2750 /* MT25408 "Hermon" SDR */
ca3e57a5 2751 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2752 /* MT25408 "Hermon" DDR */
ca3e57a5 2753 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2754 /* MT25408 "Hermon" QDR */
ca3e57a5 2755 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2756 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 2757 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2758 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 2759 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2760 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 2761 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2762 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 2763 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2764 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 2765 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2766 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 2767 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2768 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 2769 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2770 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 2771 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2772 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 2773 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2774 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 2775 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2776 /* MT27500 Family [ConnectX-3] */
2777 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2778 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 2779 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2780 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2781 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2782 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2783 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2784 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2785 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2786 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2787 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2788 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2789 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2790 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2791 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 2792 { 0, }
2793};
2794
2795MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2796
57dbf29a
KSS		 2797static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2798 pci_channel_state_t state)
2799{
befdf897 2800 __mlx4_remove_one(pdev);
57dbf29a
KSS		 2801
2802 return state == pci_channel_io_perm_failure ?
2803 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2804}
2805
2806static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2807{
befdf897
WY		 2808 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2809 struct mlx4_priv *priv = mlx4_priv(dev);
2810 int ret;
97a5221f 2811
befdf897 2812 ret = __mlx4_init_one(pdev, priv->pci_dev_data);
57dbf29a
KSS		 2813
2814 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2815}
2816
3646f0e5 2817static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 2818 .error_detected = mlx4_pci_err_detected,
2819 .slot_reset = mlx4_pci_slot_reset,
2820};
2821
225c7b1f
RD		 2822static struct pci_driver mlx4_driver = {
2823 .name = DRV_NAME,
2824 .id_table = mlx4_pci_table,
2825 .probe = mlx4_init_one,
367d56f7 2826 .shutdown = mlx4_remove_one,
f57e6848 2827 .remove = mlx4_remove_one,
57dbf29a 2828 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 2829};
2830
7ff93f8b
YP		 2831static int __init mlx4_verify_params(void)
2832{
2833 if ((log_num_mac < 0) || (log_num_mac > 7)) {
0a645e80 2834 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 2835 return -1;
2836 }
2837
cb29688a
OG		 2838 if (log_num_vlan != 0)
2839 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2840 MLX4_LOG_NUM_VLANS);
7ff93f8b 2841
0498628f 2842 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
0a645e80 2843 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
ab6bf42e
EC		 2844 return -1;
2845 }
2846
ab9c17a0
JM		 2847 /* Check if module param for ports type has legal combination */
2848 if (port_type_array[0] == false && port_type_array[1] == true) {
2849 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2850 port_type_array[0] = true;
2851 }
2852
3c439b55
JM		 2853 if (mlx4_log_num_mgm_entry_size != -1 &&
2854 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2855 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2856 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2857 "in legal range (-1 or %d..%d)\n",
2858 mlx4_log_num_mgm_entry_size,
2859 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2860 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2861 return -1;
2862 }
2863
7ff93f8b
YP		 2864 return 0;
2865}
2866
225c7b1f
RD		 2867static int __init mlx4_init(void)
2868{
2869 int ret;
2870
7ff93f8b
YP		 2871 if (mlx4_verify_params())
2872 return -EINVAL;
2873
27bf91d6
YP		 2874 mlx4_catas_init();
2875
2876 mlx4_wq = create_singlethread_workqueue("mlx4");
2877 if (!mlx4_wq)
2878 return -ENOMEM;
ee49bd93 2879
225c7b1f 2880 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 2881 if (ret < 0)
2882 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2883 return ret < 0 ? ret : 0;
2884}
2885
2886static void __exit mlx4_cleanup(void)
2887{
2888 pci_unregister_driver(&mlx4_driver);
27bf91d6 2889 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2890}
2891
2892module_init(mlx4_init);
2893module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)