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Merge branches 'acpi-resources', 'acpi-battery', 'acpi-doc' and 'acpi-pnp'
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/etherdevice.h>
35#include <linux/tcp.h>
36#include <linux/if_vlan.h>
37#include <linux/delay.h>
5a0e3ad6 38#include <linux/slab.h>
1eb8c695
AV		 39#include <linux/hash.h>
40#include <net/ip.h>
076bb0c8 41#include <net/busy_poll.h>
1b136de1 42#include <net/vxlan.h>
c27a02cd
YP		 43
44#include <linux/mlx4/driver.h>
45#include <linux/mlx4/device.h>
46#include <linux/mlx4/cmd.h>
47#include <linux/mlx4/cq.h>
48
49#include "mlx4_en.h"
50#include "en_port.h"
51
d317966b 52int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 53{
bc6a4744
AV		 54 struct mlx4_en_priv *priv = netdev_priv(dev);
55 int i;
d317966b 56 unsigned int offset = 0;
bc6a4744
AV		 57
58 if (up && up != MLX4_EN_NUM_UP)
897d7846
AV		 59 return -EINVAL;
60
bc6a4744
AV		 61 netdev_set_num_tc(dev, up);
62
63 /* Partition Tx queues evenly amongst UP's */
bc6a4744 64 for (i = 0; i < up; i++) {
d317966b
AV		 65 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
66 offset += priv->num_tx_rings_p_up;
bc6a4744
AV		 67 }
68
897d7846
AV		 69 return 0;
70}
71
e0d1095a 72#ifdef CONFIG_NET_RX_BUSY_POLL
9e77a2b8
AV		 73/* must be called with local_bh_disable()d */
74static int mlx4_en_low_latency_recv(struct napi_struct *napi)
75{
76 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
77 struct net_device *dev = cq->dev;
78 struct mlx4_en_priv *priv = netdev_priv(dev);
41d942d5 79 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
9e77a2b8
AV		 80 int done;
81
82 if (!priv->port_up)
83 return LL_FLUSH_FAILED;
84
85 if (!mlx4_en_cq_lock_poll(cq))
86 return LL_FLUSH_BUSY;
87
88 done = mlx4_en_process_rx_cq(dev, cq, 4);
8501841a
AV		 89 if (likely(done))
90 rx_ring->cleaned += done;
91 else
92 rx_ring->misses++;
9e77a2b8
AV		 93
94 mlx4_en_cq_unlock_poll(cq);
95
96 return done;
97}
e0d1095a 98#endif /* CONFIG_NET_RX_BUSY_POLL */
9e77a2b8 99
1eb8c695
AV		 100#ifdef CONFIG_RFS_ACCEL
101
102struct mlx4_en_filter {
103 struct list_head next;
104 struct work_struct work;
105
75a353d4 106 u8 ip_proto;
1eb8c695
AV		 107 __be32 src_ip;
108 __be32 dst_ip;
109 __be16 src_port;
110 __be16 dst_port;
111
112 int rxq_index;
113 struct mlx4_en_priv *priv;
114 u32 flow_id; /* RFS infrastructure id */
115 int id; /* mlx4_en driver id */
116 u64 reg_id; /* Flow steering API id */
117 u8 activated; /* Used to prevent expiry before filter
118 * is attached
119 */
120 struct hlist_node filter_chain;
121};
122
123static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
124
75a353d4
EP		 125static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
126{
127 switch (ip_proto) {
128 case IPPROTO_UDP:
129 return MLX4_NET_TRANS_RULE_ID_UDP;
130 case IPPROTO_TCP:
131 return MLX4_NET_TRANS_RULE_ID_TCP;
132 default:
c3ca5205 133 return MLX4_NET_TRANS_RULE_NUM;
75a353d4
EP		 134 }
135};
136
1eb8c695
AV		 137static void mlx4_en_filter_work(struct work_struct *work)
138{
139 struct mlx4_en_filter *filter = container_of(work,
140 struct mlx4_en_filter,
141 work);
142 struct mlx4_en_priv *priv = filter->priv;
75a353d4
EP		 143 struct mlx4_spec_list spec_tcp_udp = {
144 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
1eb8c695
AV		 145 {
146 .tcp_udp = {
147 .dst_port = filter->dst_port,
148 .dst_port_msk = (__force __be16)-1,
149 .src_port = filter->src_port,
150 .src_port_msk = (__force __be16)-1,
151 },
152 },
153 };
154 struct mlx4_spec_list spec_ip = {
155 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
156 {
157 .ipv4 = {
158 .dst_ip = filter->dst_ip,
159 .dst_ip_msk = (__force __be32)-1,
160 .src_ip = filter->src_ip,
161 .src_ip_msk = (__force __be32)-1,
162 },
163 },
164 };
165 struct mlx4_spec_list spec_eth = {
166 .id = MLX4_NET_TRANS_RULE_ID_ETH,
167 };
168 struct mlx4_net_trans_rule rule = {
169 .list = LIST_HEAD_INIT(rule.list),
170 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
171 .exclusive = 1,
172 .allow_loopback = 1,
f9162539 173 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV		 174 .port = priv->port,
175 .priority = MLX4_DOMAIN_RFS,
176 };
177 int rc;
1eb8c695
AV		 178 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
179
c3ca5205 180 if (spec_tcp_udp.id >= MLX4_NET_TRANS_RULE_NUM) {
75a353d4
EP		 181 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
182 filter->ip_proto);
183 goto ignore;
184 }
1eb8c695
AV		 185 list_add_tail(&spec_eth.list, &rule.list);
186 list_add_tail(&spec_ip.list, &rule.list);
75a353d4 187 list_add_tail(&spec_tcp_udp.list, &rule.list);
1eb8c695 188
1eb8c695 189 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 190 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV		 191 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
192
193 filter->activated = 0;
194
195 if (filter->reg_id) {
196 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
197 if (rc && rc != -ENOENT)
198 en_err(priv, "Error detaching flow. rc = %d\n", rc);
199 }
200
201 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
202 if (rc)
203 en_err(priv, "Error attaching flow. err = %d\n", rc);
204
75a353d4 205ignore:
1eb8c695
AV		 206 mlx4_en_filter_rfs_expire(priv);
207
208 filter->activated = 1;
209}
210
211static inline struct hlist_head *
212filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
213 __be16 src_port, __be16 dst_port)
214{
215 unsigned long l;
216 int bucket_idx;
217
218 l = (__force unsigned long)src_port |
219 ((__force unsigned long)dst_port << 2);
220 l ^= (__force unsigned long)(src_ip ^ dst_ip);
221
222 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
223
224 return &priv->filter_hash[bucket_idx];
225}
226
227static struct mlx4_en_filter *
228mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
75a353d4
EP		 229 __be32 dst_ip, u8 ip_proto, __be16 src_port,
230 __be16 dst_port, u32 flow_id)
1eb8c695
AV		 231{
232 struct mlx4_en_filter *filter = NULL;
233
234 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
235 if (!filter)
236 return NULL;
237
238 filter->priv = priv;
239 filter->rxq_index = rxq_index;
240 INIT_WORK(&filter->work, mlx4_en_filter_work);
241
242 filter->src_ip = src_ip;
243 filter->dst_ip = dst_ip;
75a353d4 244 filter->ip_proto = ip_proto;
1eb8c695
AV		 245 filter->src_port = src_port;
246 filter->dst_port = dst_port;
247
248 filter->flow_id = flow_id;
249
ee64c0ee 250 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV		 251
252 list_add_tail(&filter->next, &priv->filters);
253 hlist_add_head(&filter->filter_chain,
254 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
255 dst_port));
256
257 return filter;
258}
259
260static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
261{
262 struct mlx4_en_priv *priv = filter->priv;
263 int rc;
264
265 list_del(&filter->next);
266
267 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
268 if (rc && rc != -ENOENT)
269 en_err(priv, "Error detaching flow. rc = %d\n", rc);
270
271 kfree(filter);
272}
273
274static inline struct mlx4_en_filter *
275mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
75a353d4 276 u8 ip_proto, __be16 src_port, __be16 dst_port)
1eb8c695 277{
1eb8c695
AV		 278 struct mlx4_en_filter *filter;
279 struct mlx4_en_filter *ret = NULL;
280
b67bfe0d 281 hlist_for_each_entry(filter,
1eb8c695
AV		 282 filter_hash_bucket(priv, src_ip, dst_ip,
283 src_port, dst_port),
284 filter_chain) {
285 if (filter->src_ip == src_ip &&
286 filter->dst_ip == dst_ip &&
75a353d4 287 filter->ip_proto == ip_proto &&
1eb8c695
AV		 288 filter->src_port == src_port &&
289 filter->dst_port == dst_port) {
290 ret = filter;
291 break;
292 }
293 }
294
295 return ret;
296}
297
298static int
299mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
300 u16 rxq_index, u32 flow_id)
301{
302 struct mlx4_en_priv *priv = netdev_priv(net_dev);
303 struct mlx4_en_filter *filter;
304 const struct iphdr *ip;
305 const __be16 *ports;
75a353d4 306 u8 ip_proto;
1eb8c695
AV		 307 __be32 src_ip;
308 __be32 dst_ip;
309 __be16 src_port;
310 __be16 dst_port;
311 int nhoff = skb_network_offset(skb);
312 int ret = 0;
313
314 if (skb->protocol != htons(ETH_P_IP))
315 return -EPROTONOSUPPORT;
316
317 ip = (const struct iphdr *)(skb->data + nhoff);
318 if (ip_is_fragment(ip))
319 return -EPROTONOSUPPORT;
320
75a353d4
EP		 321 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
322 return -EPROTONOSUPPORT;
1eb8c695
AV		 323 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
324
75a353d4 325 ip_proto = ip->protocol;
1eb8c695
AV		 326 src_ip = ip->saddr;
327 dst_ip = ip->daddr;
328 src_port = ports[0];
329 dst_port = ports[1];
330
1eb8c695 331 spin_lock_bh(&priv->filters_lock);
75a353d4
EP		 332 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
333 src_port, dst_port);
1eb8c695
AV		 334 if (filter) {
335 if (filter->rxq_index == rxq_index)
336 goto out;
337
338 filter->rxq_index = rxq_index;
339 } else {
340 filter = mlx4_en_filter_alloc(priv, rxq_index,
75a353d4 341 src_ip, dst_ip, ip_proto,
1eb8c695
AV		 342 src_port, dst_port, flow_id);
343 if (!filter) {
344 ret = -ENOMEM;
345 goto err;
346 }
347 }
348
349 queue_work(priv->mdev->workqueue, &filter->work);
350
351out:
352 ret = filter->id;
353err:
354 spin_unlock_bh(&priv->filters_lock);
355
356 return ret;
357}
358
41d942d5 359void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
1eb8c695
AV		 360{
361 struct mlx4_en_filter *filter, *tmp;
362 LIST_HEAD(del_list);
363
364 spin_lock_bh(&priv->filters_lock);
365 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
366 list_move(&filter->next, &del_list);
367 hlist_del(&filter->filter_chain);
368 }
369 spin_unlock_bh(&priv->filters_lock);
370
371 list_for_each_entry_safe(filter, tmp, &del_list, next) {
372 cancel_work_sync(&filter->work);
373 mlx4_en_filter_free(filter);
374 }
375}
376
377static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
378{
379 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
380 LIST_HEAD(del_list);
381 int i = 0;
382
383 spin_lock_bh(&priv->filters_lock);
384 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
385 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
386 break;
387
388 if (filter->activated &&
389 !work_pending(&filter->work) &&
390 rps_may_expire_flow(priv->dev,
391 filter->rxq_index, filter->flow_id,
392 filter->id)) {
393 list_move(&filter->next, &del_list);
394 hlist_del(&filter->filter_chain);
395 } else
396 last_filter = filter;
397
398 i++;
399 }
400
401 if (last_filter && (&last_filter->next != priv->filters.next))
402 list_move(&priv->filters, &last_filter->next);
403
404 spin_unlock_bh(&priv->filters_lock);
405
406 list_for_each_entry_safe(filter, tmp, &del_list, next)
407 mlx4_en_filter_free(filter);
408}
409#endif
410
80d5c368
PM		 411static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
412 __be16 proto, u16 vid)
c27a02cd
YP		 413{
414 struct mlx4_en_priv *priv = netdev_priv(dev);
415 struct mlx4_en_dev *mdev = priv->mdev;
416 int err;
4c3eb3ca 417 int idx;
c27a02cd 418
f1b553fb 419 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 420
f1b553fb 421 set_bit(vid, priv->active_vlans);
c27a02cd
YP		 422
423 /* Add VID to port VLAN filter */
424 mutex_lock(&mdev->state_lock);
425 if (mdev->device_up && priv->port_up) {
f1b553fb 426 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 427 if (err)
453a6082 428 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd 429 }
4c3eb3ca 430 if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx))
9e19b545 431 en_dbg(HW, priv, "failed adding vlan %d\n", vid);
c27a02cd 432 mutex_unlock(&mdev->state_lock);
4c3eb3ca 433
8e586137 434 return 0;
c27a02cd
YP		 435}
436
80d5c368
PM		 437static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
438 __be16 proto, u16 vid)
c27a02cd
YP		 439{
440 struct mlx4_en_priv *priv = netdev_priv(dev);
441 struct mlx4_en_dev *mdev = priv->mdev;
442 int err;
443
f1b553fb 444 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 445
f1b553fb 446 clear_bit(vid, priv->active_vlans);
c27a02cd
YP		 447
448 /* Remove VID from port VLAN filter */
449 mutex_lock(&mdev->state_lock);
2009d005 450 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 451
c27a02cd 452 if (mdev->device_up && priv->port_up) {
f1b553fb 453 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 454 if (err)
453a6082 455 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP		 456 }
457 mutex_unlock(&mdev->state_lock);
8e586137
JP		 458
459 return 0;
c27a02cd
YP		 460}
461
6bbb6d99
YB		 462static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
463{
bab6a9ea
YB		 464 int i;
465 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB		 466 dst_mac[i] = src_mac & 0xff;
467 src_mac >>= 8;
468 }
469 memset(&dst_mac[ETH_ALEN], 0, 2);
470}
471
837052d0
OG		 472
473static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
474 int qpn, u64 *reg_id)
475{
476 int err;
837052d0 477
5eff6dad
OG		 478 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
479 priv->mdev->dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
837052d0
OG		 480 return 0; /* do nothing */
481
b95089d0
OG		 482 err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn,
483 MLX4_DOMAIN_NIC, reg_id);
837052d0
OG		 484 if (err) {
485 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
486 return err;
487 }
488 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
489 return 0;
490}
491
492
16a10ffd
YB		 493static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
494 unsigned char *mac, int *qpn, u64 *reg_id)
495{
496 struct mlx4_en_dev *mdev = priv->mdev;
497 struct mlx4_dev *dev = mdev->dev;
498 int err;
499
500 switch (dev->caps.steering_mode) {
501 case MLX4_STEERING_MODE_B0: {
502 struct mlx4_qp qp;
503 u8 gid[16] = {0};
504
505 qp.qpn = *qpn;
506 memcpy(&gid[10], mac, ETH_ALEN);
507 gid[5] = priv->port;
508
509 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
510 break;
511 }
512 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
513 struct mlx4_spec_list spec_eth = { {NULL} };
514 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
515
516 struct mlx4_net_trans_rule rule = {
517 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
518 .exclusive = 0,
519 .allow_loopback = 1,
f9162539 520 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB		 521 .priority = MLX4_DOMAIN_NIC,
522 };
523
524 rule.port = priv->port;
525 rule.qpn = *qpn;
526 INIT_LIST_HEAD(&rule.list);
527
528 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
529 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
530 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
531 list_add_tail(&spec_eth.list, &rule.list);
532
533 err = mlx4_flow_attach(dev, &rule, reg_id);
534 break;
535 }
536 default:
537 return -EINVAL;
538 }
539 if (err)
540 en_warn(priv, "Failed Attaching Unicast\n");
541
542 return err;
543}
544
545static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
546 unsigned char *mac, int qpn, u64 reg_id)
547{
548 struct mlx4_en_dev *mdev = priv->mdev;
549 struct mlx4_dev *dev = mdev->dev;
550
551 switch (dev->caps.steering_mode) {
552 case MLX4_STEERING_MODE_B0: {
553 struct mlx4_qp qp;
554 u8 gid[16] = {0};
555
556 qp.qpn = qpn;
557 memcpy(&gid[10], mac, ETH_ALEN);
558 gid[5] = priv->port;
559
560 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
561 break;
562 }
563 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
564 mlx4_flow_detach(dev, reg_id);
565 break;
566 }
567 default:
568 en_err(priv, "Invalid steering mode.\n");
569 }
570}
571
572static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
573{
574 struct mlx4_en_dev *mdev = priv->mdev;
575 struct mlx4_dev *dev = mdev->dev;
576 struct mlx4_mac_entry *entry;
577 int index = 0;
578 int err = 0;
c2a3d4b4 579 u64 reg_id = 0;
16a10ffd 580 int *qpn = &priv->base_qpn;
9813337a 581 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
16a10ffd
YB		 582
583 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
584 priv->dev->dev_addr);
585 index = mlx4_register_mac(dev, priv->port, mac);
586 if (index < 0) {
587 err = index;
588 en_err(priv, "Failed adding MAC: %pM\n",
589 priv->dev->dev_addr);
590 return err;
591 }
592
593 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
594 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
595 *qpn = base_qpn + index;
596 return 0;
597 }
598
d57febe1 599 err = mlx4_qp_reserve_range(dev, 1, 1, qpn, MLX4_RESERVE_A0_QP);
16a10ffd
YB		 600 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
601 if (err) {
602 en_err(priv, "Failed to reserve qp for mac registration\n");
603 goto qp_err;
604 }
605
606 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
607 if (err)
608 goto steer_err;
609
9ba75fb0
WY		 610 err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
611 &priv->tunnel_reg_id);
612 if (err)
837052d0
OG		 613 goto tunnel_err;
614
16a10ffd
YB		 615 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
616 if (!entry) {
617 err = -ENOMEM;
618 goto alloc_err;
619 }
620 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
b94901f3 621 memcpy(priv->current_mac, entry->mac, sizeof(priv->current_mac));
16a10ffd
YB		 622 entry->reg_id = reg_id;
623
c07cb4b0
YB		 624 hlist_add_head_rcu(&entry->hlist,
625 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
16a10ffd 626
c07cb4b0 627 return 0;
16a10ffd
YB		 628
629alloc_err:
837052d0
OG		 630 if (priv->tunnel_reg_id)
631 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
632tunnel_err:
16a10ffd
YB		 633 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
634
635steer_err:
636 mlx4_qp_release_range(dev, *qpn, 1);
637
638qp_err:
639 mlx4_unregister_mac(dev, priv->port, mac);
640 return err;
641}
642
643static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
644{
645 struct mlx4_en_dev *mdev = priv->mdev;
646 struct mlx4_dev *dev = mdev->dev;
16a10ffd 647 int qpn = priv->base_qpn;
83a5a6ce 648 u64 mac;
16a10ffd 649
83a5a6ce 650 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
9813337a 651 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
83a5a6ce
YB		 652 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
653 priv->dev->dev_addr);
654 mlx4_unregister_mac(dev, priv->port, mac);
655 } else {
c07cb4b0 656 struct mlx4_mac_entry *entry;
b67bfe0d 657 struct hlist_node *tmp;
c07cb4b0 658 struct hlist_head *bucket;
83a5a6ce 659 unsigned int i;
c07cb4b0 660
83a5a6ce
YB		 661 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
662 bucket = &priv->mac_hash[i];
663 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
9813337a 664 mac = mlx4_mac_to_u64(entry->mac);
83a5a6ce
YB		 665 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
666 entry->mac);
c07cb4b0
YB		 667 mlx4_en_uc_steer_release(priv, entry->mac,
668 qpn, entry->reg_id);
c07cb4b0 669
83a5a6ce 670 mlx4_unregister_mac(dev, priv->port, mac);
c07cb4b0
YB		 671 hlist_del_rcu(&entry->hlist);
672 kfree_rcu(entry, rcu);
c07cb4b0 673 }
16a10ffd 674 }
83a5a6ce 675
837052d0
OG		 676 if (priv->tunnel_reg_id) {
677 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
678 priv->tunnel_reg_id = 0;
679 }
680
83a5a6ce
YB		 681 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
682 priv->port, qpn);
683 mlx4_qp_release_range(dev, qpn, 1);
684 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB		 685 }
686}
687
688static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 689 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB		 690{
691 struct mlx4_en_dev *mdev = priv->mdev;
692 struct mlx4_dev *dev = mdev->dev;
16a10ffd 693 int err = 0;
9813337a 694 u64 new_mac_u64 = mlx4_mac_to_u64(new_mac);
16a10ffd
YB		 695
696 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB		 697 struct hlist_head *bucket;
698 unsigned int mac_hash;
699 struct mlx4_mac_entry *entry;
b67bfe0d 700 struct hlist_node *tmp;
9813337a 701 u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac);
c07cb4b0
YB		 702
703 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 704 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB		 705 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
706 mlx4_en_uc_steer_release(priv, entry->mac,
707 qpn, entry->reg_id);
708 mlx4_unregister_mac(dev, priv->port,
709 prev_mac_u64);
710 hlist_del_rcu(&entry->hlist);
711 synchronize_rcu();
712 memcpy(entry->mac, new_mac, ETH_ALEN);
713 entry->reg_id = 0;
714 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
715 hlist_add_head_rcu(&entry->hlist,
716 &priv->mac_hash[mac_hash]);
717 mlx4_register_mac(dev, priv->port, new_mac_u64);
718 err = mlx4_en_uc_steer_add(priv, new_mac,
719 &qpn,
720 &entry->reg_id);
2a2083f7
OG		 721 if (err)
722 return err;
723 if (priv->tunnel_reg_id) {
724 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
725 priv->tunnel_reg_id = 0;
726 }
727 err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn,
728 &priv->tunnel_reg_id);
c07cb4b0
YB		 729 return err;
730 }
731 }
732 return -EINVAL;
16a10ffd
YB		 733 }
734
735 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
736}
737
2695bab2
NO		 738static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv,
739 unsigned char new_mac[ETH_ALEN + 2])
c27a02cd 740{
c27a02cd
YP		 741 int err = 0;
742
c27a02cd
YP		 743 if (priv->port_up) {
744 /* Remove old MAC and insert the new one */
16a10ffd 745 err = mlx4_en_replace_mac(priv, priv->base_qpn,
2695bab2 746 new_mac, priv->current_mac);
c27a02cd 747 if (err)
453a6082 748 en_err(priv, "Failed changing HW MAC address\n");
c27a02cd 749 } else
48e551ff 750 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 751
2695bab2
NO		 752 if (!err)
753 memcpy(priv->current_mac, new_mac, sizeof(priv->current_mac));
ee755324 754
bfa8ab47
YB		 755 return err;
756}
757
758static int mlx4_en_set_mac(struct net_device *dev, void *addr)
759{
760 struct mlx4_en_priv *priv = netdev_priv(dev);
761 struct mlx4_en_dev *mdev = priv->mdev;
762 struct sockaddr *saddr = addr;
2695bab2 763 unsigned char new_mac[ETH_ALEN + 2];
bfa8ab47
YB		 764 int err;
765
766 if (!is_valid_ether_addr(saddr->sa_data))
767 return -EADDRNOTAVAIL;
768
bfa8ab47 769 mutex_lock(&mdev->state_lock);
2695bab2
NO		 770 memcpy(new_mac, saddr->sa_data, ETH_ALEN);
771 err = mlx4_en_do_set_mac(priv, new_mac);
772 if (!err)
773 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
c27a02cd 774 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB		 775
776 return err;
c27a02cd
YP		 777}
778
779static void mlx4_en_clear_list(struct net_device *dev)
780{
781 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 782 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 783
6d199937
YP		 784 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
785 list_del(&mc_to_del->list);
786 kfree(mc_to_del);
787 }
c27a02cd
YP		 788}
789
790static void mlx4_en_cache_mclist(struct net_device *dev)
791{
792 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 793 struct netdev_hw_addr *ha;
6d199937 794 struct mlx4_en_mc_list *tmp;
ff6e2163 795
0e03567a 796 mlx4_en_clear_list(dev);
6d199937
YP		 797 netdev_for_each_mc_addr(ha, dev) {
798 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
799 if (!tmp) {
6d199937
YP		 800 mlx4_en_clear_list(dev);
801 return;
802 }
803 memcpy(tmp->addr, ha->addr, ETH_ALEN);
804 list_add_tail(&tmp->list, &priv->mc_list);
805 }
c27a02cd
YP		 806}
807
6d199937
YP		 808static void update_mclist_flags(struct mlx4_en_priv *priv,
809 struct list_head *dst,
810 struct list_head *src)
811{
812 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
813 bool found;
814
815 /* Find all the entries that should be removed from dst,
816 * These are the entries that are not found in src
817 */
818 list_for_each_entry(dst_tmp, dst, list) {
819 found = false;
820 list_for_each_entry(src_tmp, src, list) {
c0623e58 821 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 822 found = true;
823 break;
824 }
825 }
826 if (!found)
827 dst_tmp->action = MCLIST_REM;
828 }
829
830 /* Add entries that exist in src but not in dst
831 * mark them as need to add
832 */
833 list_for_each_entry(src_tmp, src, list) {
834 found = false;
835 list_for_each_entry(dst_tmp, dst, list) {
c0623e58 836 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 837 dst_tmp->action = MCLIST_NONE;
838 found = true;
839 break;
840 }
841 }
842 if (!found) {
14f8dc49
JP		 843 new_mc = kmemdup(src_tmp,
844 sizeof(struct mlx4_en_mc_list),
6d199937 845 GFP_KERNEL);
14f8dc49 846 if (!new_mc)
6d199937 847 return;
14f8dc49 848
6d199937
YP		 849 new_mc->action = MCLIST_ADD;
850 list_add_tail(&new_mc->list, dst);
851 }
852 }
853}
c27a02cd 854
0eb74fdd 855static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP		 856{
857 struct mlx4_en_priv *priv = netdev_priv(dev);
858
859 if (!priv->port_up)
860 return;
861
0eb74fdd 862 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP		 863}
864
0eb74fdd
YB		 865static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
866 struct mlx4_en_dev *mdev)
c27a02cd 867{
c96d97f4 868 int err = 0;
c27a02cd 869
0eb74fdd 870 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 871 if (netif_msg_rx_status(priv))
0eb74fdd
YB		 872 en_warn(priv, "Entering promiscuous mode\n");
873 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 874
0eb74fdd 875 /* Enable promiscouos mode */
c96d97f4 876 switch (mdev->dev->caps.steering_mode) {
592e49dd 877 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB		 878 err = mlx4_flow_steer_promisc_add(mdev->dev,
879 priv->port,
880 priv->base_qpn,
f9162539 881 MLX4_FS_ALL_DEFAULT);
592e49dd 882 if (err)
0eb74fdd
YB		 883 en_err(priv, "Failed enabling promiscuous mode\n");
884 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ		 885 break;
886
c96d97f4 887 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB		 888 err = mlx4_unicast_promisc_add(mdev->dev,
889 priv->base_qpn,
890 priv->port);
c96d97f4 891 if (err)
0eb74fdd
YB		 892 en_err(priv, "Failed enabling unicast promiscuous mode\n");
893
894 /* Add the default qp number as multicast
895 * promisc
896 */
897 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
898 err = mlx4_multicast_promisc_add(mdev->dev,
899 priv->base_qpn,
900 priv->port);
c96d97f4 901 if (err)
0eb74fdd
YB		 902 en_err(priv, "Failed enabling multicast promiscuous mode\n");
903 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ		 904 }
905 break;
c27a02cd 906
c96d97f4
HHZ		 907 case MLX4_STEERING_MODE_A0:
908 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
909 priv->port,
0eb74fdd
YB		 910 priv->base_qpn,
911 1);
1679200f 912 if (err)
0eb74fdd 913 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 914 break;
1679200f
YP		 915 }
916
0eb74fdd
YB		 917 /* Disable port multicast filter (unconditionally) */
918 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
919 0, MLX4_MCAST_DISABLE);
920 if (err)
921 en_err(priv, "Failed disabling multicast filter\n");
0eb74fdd
YB		 922 }
923}
924
925static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
926 struct mlx4_en_dev *mdev)
927{
928 int err = 0;
929
930 if (netif_msg_rx_status(priv))
931 en_warn(priv, "Leaving promiscuous mode\n");
932 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
933
934 /* Disable promiscouos mode */
935 switch (mdev->dev->caps.steering_mode) {
936 case MLX4_STEERING_MODE_DEVICE_MANAGED:
937 err = mlx4_flow_steer_promisc_remove(mdev->dev,
938 priv->port,
f9162539 939 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB		 940 if (err)
941 en_err(priv, "Failed disabling promiscuous mode\n");
942 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
943 break;
944
945 case MLX4_STEERING_MODE_B0:
946 err = mlx4_unicast_promisc_remove(mdev->dev,
947 priv->base_qpn,
948 priv->port);
949 if (err)
950 en_err(priv, "Failed disabling unicast promiscuous mode\n");
951 /* Disable Multicast promisc */
952 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
953 err = mlx4_multicast_promisc_remove(mdev->dev,
954 priv->base_qpn,
955 priv->port);
956 if (err)
957 en_err(priv, "Failed disabling multicast promiscuous mode\n");
958 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
959 }
960 break;
961
962 case MLX4_STEERING_MODE_A0:
963 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
964 priv->port,
965 priv->base_qpn, 0);
966 if (err)
967 en_err(priv, "Failed disabling promiscuous mode\n");
968 break;
c27a02cd 969 }
0eb74fdd
YB		 970}
971
972static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
973 struct net_device *dev,
974 struct mlx4_en_dev *mdev)
975{
976 struct mlx4_en_mc_list *mclist, *tmp;
977 u64 mcast_addr = 0;
978 u8 mc_list[16] = {0};
979 int err = 0;
980
c27a02cd
YP		 981 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
982 if (dev->flags & IFF_ALLMULTI) {
983 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
984 0, MLX4_MCAST_DISABLE);
985 if (err)
453a6082 986 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP		 987
988 /* Add the default qp number as multicast promisc */
989 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 990 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 991 case MLX4_STEERING_MODE_DEVICE_MANAGED:
992 err = mlx4_flow_steer_promisc_add(mdev->dev,
993 priv->port,
994 priv->base_qpn,
f9162539 995 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 996 break;
997
c96d97f4
HHZ		 998 case MLX4_STEERING_MODE_B0:
999 err = mlx4_multicast_promisc_add(mdev->dev,
1000 priv->base_qpn,
1001 priv->port);
1002 break;
1003
1004 case MLX4_STEERING_MODE_A0:
1005 break;
1006 }
1679200f
YP		 1007 if (err)
1008 en_err(priv, "Failed entering multicast promisc mode\n");
1009 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
1010 }
c27a02cd 1011 } else {
1679200f
YP		 1012 /* Disable Multicast promisc */
1013 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 1014 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1015 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1016 err = mlx4_flow_steer_promisc_remove(mdev->dev,
1017 priv->port,
f9162539 1018 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1019 break;
1020
c96d97f4
HHZ		 1021 case MLX4_STEERING_MODE_B0:
1022 err = mlx4_multicast_promisc_remove(mdev->dev,
1023 priv->base_qpn,
1024 priv->port);
1025 break;
1026
1027 case MLX4_STEERING_MODE_A0:
1028 break;
1029 }
1679200f 1030 if (err)
25985edc 1031 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP		 1032 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1033 }
ff6e2163 1034
c27a02cd
YP		 1035 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1036 0, MLX4_MCAST_DISABLE);
1037 if (err)
453a6082 1038 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP		 1039
1040 /* Flush mcast filter and init it with broadcast address */
1041 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
1042 1, MLX4_MCAST_CONFIG);
1043
1044 /* Update multicast list - we cache all addresses so they won't
1045 * change while HW is updated holding the command semaphor */
dbd501a8 1046 netif_addr_lock_bh(dev);
c27a02cd 1047 mlx4_en_cache_mclist(dev);
dbd501a8 1048 netif_addr_unlock_bh(dev);
6d199937 1049 list_for_each_entry(mclist, &priv->mc_list, list) {
9813337a 1050 mcast_addr = mlx4_mac_to_u64(mclist->addr);
c27a02cd
YP		 1051 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
1052 mcast_addr, 0, MLX4_MCAST_CONFIG);
1053 }
1054 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1055 0, MLX4_MCAST_ENABLE);
1056 if (err)
453a6082 1057 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP		 1058
1059 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
1060 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1061 if (mclist->action == MCLIST_REM) {
1062 /* detach this address and delete from list */
1063 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1064 mc_list[5] = priv->port;
1065 err = mlx4_multicast_detach(mdev->dev,
1066 &priv->rss_map.indir_qp,
1067 mc_list,
0ff1fb65
HHZ		 1068 MLX4_PROT_ETH,
1069 mclist->reg_id);
6d199937
YP		 1070 if (err)
1071 en_err(priv, "Fail to detach multicast address\n");
1072
837052d0
OG		 1073 if (mclist->tunnel_reg_id) {
1074 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
1075 if (err)
1076 en_err(priv, "Failed to detach multicast address\n");
1077 }
1078
6d199937
YP		 1079 /* remove from list */
1080 list_del(&mclist->list);
1081 kfree(mclist);
9c64508a 1082 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP		 1083 /* attach the address */
1084 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 1085 /* needed for B0 steering support */
6d199937
YP		 1086 mc_list[5] = priv->port;
1087 err = mlx4_multicast_attach(mdev->dev,
1088 &priv->rss_map.indir_qp,
0ff1fb65
HHZ		 1089 mc_list,
1090 priv->port, 0,
1091 MLX4_PROT_ETH,
1092 &mclist->reg_id);
6d199937
YP		 1093 if (err)
1094 en_err(priv, "Fail to attach multicast address\n");
1095
837052d0
OG		 1096 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1097 &mclist->tunnel_reg_id);
1098 if (err)
1099 en_err(priv, "Failed to attach multicast address\n");
6d199937
YP		 1100 }
1101 }
c27a02cd 1102 }
0eb74fdd
YB		 1103}
1104
cc5387f7
YB		 1105static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1106 struct net_device *dev,
1107 struct mlx4_en_dev *mdev)
1108{
1109 struct netdev_hw_addr *ha;
1110 struct mlx4_mac_entry *entry;
b67bfe0d 1111 struct hlist_node *tmp;
cc5387f7
YB		 1112 bool found;
1113 u64 mac;
1114 int err = 0;
1115 struct hlist_head *bucket;
1116 unsigned int i;
1117 int removed = 0;
1118 u32 prev_flags;
1119
1120 /* Note that we do not need to protect our mac_hash traversal with rcu,
1121 * since all modification code is protected by mdev->state_lock
1122 */
1123
1124 /* find what to remove */
1125 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1126 bucket = &priv->mac_hash[i];
b67bfe0d 1127 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB		 1128 found = false;
1129 netdev_for_each_uc_addr(ha, dev) {
1130 if (ether_addr_equal_64bits(entry->mac,
1131 ha->addr)) {
1132 found = true;
1133 break;
1134 }
1135 }
1136
1137 /* MAC address of the port is not in uc list */
2695bab2
NO		 1138 if (ether_addr_equal_64bits(entry->mac,
1139 priv->current_mac))
cc5387f7
YB		 1140 found = true;
1141
1142 if (!found) {
9813337a 1143 mac = mlx4_mac_to_u64(entry->mac);
cc5387f7
YB		 1144 mlx4_en_uc_steer_release(priv, entry->mac,
1145 priv->base_qpn,
1146 entry->reg_id);
1147 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1148
1149 hlist_del_rcu(&entry->hlist);
1150 kfree_rcu(entry, rcu);
1151 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1152 entry->mac, priv->port);
1153 ++removed;
1154 }
1155 }
1156 }
1157
1158 /* if we didn't remove anything, there is no use in trying to add
1159 * again once we are in a forced promisc mode state
1160 */
1161 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1162 return;
1163
1164 prev_flags = priv->flags;
1165 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1166
1167 /* find what to add */
1168 netdev_for_each_uc_addr(ha, dev) {
1169 found = false;
1170 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1171 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB		 1172 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1173 found = true;
1174 break;
1175 }
1176 }
1177
1178 if (!found) {
1179 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1180 if (!entry) {
1181 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1182 ha->addr, priv->port);
1183 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1184 break;
1185 }
9813337a 1186 mac = mlx4_mac_to_u64(ha->addr);
cc5387f7
YB		 1187 memcpy(entry->mac, ha->addr, ETH_ALEN);
1188 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1189 if (err < 0) {
1190 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1191 ha->addr, priv->port, err);
1192 kfree(entry);
1193 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1194 break;
1195 }
1196 err = mlx4_en_uc_steer_add(priv, ha->addr,
1197 &priv->base_qpn,
1198 &entry->reg_id);
1199 if (err) {
1200 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1201 ha->addr, priv->port, err);
1202 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1203 kfree(entry);
1204 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1205 break;
1206 } else {
1207 unsigned int mac_hash;
1208 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1209 ha->addr, priv->port);
1210 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1211 bucket = &priv->mac_hash[mac_hash];
1212 hlist_add_head_rcu(&entry->hlist, bucket);
1213 }
1214 }
1215 }
1216
1217 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1218 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1219 priv->port);
1220 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1221 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1222 priv->port);
1223 }
1224}
1225
0eb74fdd
YB		 1226static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1227{
1228 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1229 rx_mode_task);
1230 struct mlx4_en_dev *mdev = priv->mdev;
1231 struct net_device *dev = priv->dev;
1232
1233 mutex_lock(&mdev->state_lock);
1234 if (!mdev->device_up) {
1235 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1236 goto out;
1237 }
1238 if (!priv->port_up) {
1239 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1240 goto out;
1241 }
1242
1243 if (!netif_carrier_ok(dev)) {
1244 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1245 if (priv->port_state.link_state) {
1246 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1247 netif_carrier_on(dev);
1248 en_dbg(LINK, priv, "Link Up\n");
1249 }
1250 }
1251 }
1252
cc5387f7
YB		 1253 if (dev->priv_flags & IFF_UNICAST_FLT)
1254 mlx4_en_do_uc_filter(priv, dev, mdev);
1255
0eb74fdd 1256 /* Promsicuous mode: disable all filters */
cc5387f7
YB		 1257 if ((dev->flags & IFF_PROMISC) ||
1258 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB		 1259 mlx4_en_set_promisc_mode(priv, mdev);
1260 goto out;
1261 }
1262
1263 /* Not in promiscuous mode */
1264 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1265 mlx4_en_clear_promisc_mode(priv, mdev);
1266
1267 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP		 1268out:
1269 mutex_unlock(&mdev->state_lock);
1270}
1271
1272#ifdef CONFIG_NET_POLL_CONTROLLER
1273static void mlx4_en_netpoll(struct net_device *dev)
1274{
1275 struct mlx4_en_priv *priv = netdev_priv(dev);
1276 struct mlx4_en_cq *cq;
c27a02cd
YP		 1277 int i;
1278
1279 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1280 cq = priv->rx_cq[i];
c98235cb 1281 napi_schedule(&cq->napi);
c27a02cd
YP		 1282 }
1283}
1284#endif
1285
1286static void mlx4_en_tx_timeout(struct net_device *dev)
1287{
1288 struct mlx4_en_priv *priv = netdev_priv(dev);
1289 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1290 int i;
c27a02cd
YP		 1291
1292 if (netif_msg_timer(priv))
453a6082 1293 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1294
b944ebec
YP		 1295 for (i = 0; i < priv->tx_ring_num; i++) {
1296 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1297 continue;
1298 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
41d942d5
EE		 1299 i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn,
1300 priv->tx_ring[i]->cons, priv->tx_ring[i]->prod);
b944ebec
YP		 1301 }
1302
1e338db5 1303 priv->port_stats.tx_timeout++;
453a6082 1304 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1305 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP		 1306}
1307
1308
1309static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev)
1310{
1311 struct mlx4_en_priv *priv = netdev_priv(dev);
1312
1313 spin_lock_bh(&priv->stats_lock);
1314 memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats));
1315 spin_unlock_bh(&priv->stats_lock);
1316
1317 return &priv->ret_stats;
1318}
1319
1320static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1321{
c27a02cd
YP		 1322 struct mlx4_en_cq *cq;
1323 int i;
1324
1325 /* If we haven't received a specific coalescing setting
98a1708d 1326 * (module param), we set the moderation parameters as follows:
c27a02cd 1327 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1328 * satisfy our coalescing target.
c27a02cd
YP		 1329 * - moder_time is set to a fixed value.
1330 */
3db36fb2 1331 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1332 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP		 1333 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1334 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
48e551ff
YB		 1335 en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1336 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP		 1337
1338 /* Setup cq moderation params */
1339 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1340 cq = priv->rx_cq[i];
c27a02cd
YP		 1341 cq->moder_cnt = priv->rx_frames;
1342 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG		 1343 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1344 priv->last_moder_packets[i] = 0;
1345 priv->last_moder_bytes[i] = 0;
c27a02cd
YP		 1346 }
1347
1348 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1349 cq = priv->tx_cq[i];
a19a848a
YP		 1350 cq->moder_cnt = priv->tx_frames;
1351 cq->moder_time = priv->tx_usecs;
c27a02cd
YP		 1352 }
1353
1354 /* Reset auto-moderation params */
1355 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1356 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1357 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1358 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1359 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1360 priv->adaptive_rx_coal = 1;
c27a02cd 1361 priv->last_moder_jiffies = 0;
c27a02cd 1362 priv->last_moder_tx_packets = 0;
c27a02cd
YP		 1363}
1364
1365static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1366{
1367 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
c27a02cd
YP		 1368 struct mlx4_en_cq *cq;
1369 unsigned long packets;
1370 unsigned long rate;
1371 unsigned long avg_pkt_size;
1372 unsigned long rx_packets;
1373 unsigned long rx_bytes;
c27a02cd
YP		 1374 unsigned long rx_pkt_diff;
1375 int moder_time;
6b4d8d9f 1376 int ring, err;
c27a02cd
YP		 1377
1378 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1379 return;
1380
6b4d8d9f
AG		 1381 for (ring = 0; ring < priv->rx_ring_num; ring++) {
1382 spin_lock_bh(&priv->stats_lock);
41d942d5
EE		 1383 rx_packets = priv->rx_ring[ring]->packets;
1384 rx_bytes = priv->rx_ring[ring]->bytes;
6b4d8d9f
AG		 1385 spin_unlock_bh(&priv->stats_lock);
1386
1387 rx_pkt_diff = ((unsigned long) (rx_packets -
1388 priv->last_moder_packets[ring]));
1389 packets = rx_pkt_diff;
1390 rate = packets * HZ / period;
1391 avg_pkt_size = packets ? ((unsigned long) (rx_bytes -
1392 priv->last_moder_bytes[ring])) / packets : 0;
1393
1394 /* Apply auto-moderation only when packet rate
1395 * exceeds a rate that it matters */
1396 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1397 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
c27a02cd
YP		 1398 if (rate < priv->pkt_rate_low)
1399 moder_time = priv->rx_usecs_low;
1400 else if (rate > priv->pkt_rate_high)
1401 moder_time = priv->rx_usecs_high;
1402 else
1403 moder_time = (rate - priv->pkt_rate_low) *
1404 (priv->rx_usecs_high - priv->rx_usecs_low) /
1405 (priv->pkt_rate_high - priv->pkt_rate_low) +
1406 priv->rx_usecs_low;
6b4d8d9f
AG		 1407 } else {
1408 moder_time = priv->rx_usecs_low;
c27a02cd 1409 }
c27a02cd 1410
6b4d8d9f
AG		 1411 if (moder_time != priv->last_moder_time[ring]) {
1412 priv->last_moder_time[ring] = moder_time;
41d942d5 1413 cq = priv->rx_cq[ring];
c27a02cd 1414 cq->moder_time = moder_time;
a1c6693a 1415 cq->moder_cnt = priv->rx_frames;
c27a02cd 1416 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1417 if (err)
48e551ff
YB		 1418 en_err(priv, "Failed modifying moderation for cq:%d\n",
1419 ring);
c27a02cd 1420 }
6b4d8d9f
AG		 1421 priv->last_moder_packets[ring] = rx_packets;
1422 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP		 1423 }
1424
c27a02cd
YP		 1425 priv->last_moder_jiffies = jiffies;
1426}
1427
1428static void mlx4_en_do_get_stats(struct work_struct *work)
1429{
bf6aede7 1430 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP		 1431 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1432 stats_task);
1433 struct mlx4_en_dev *mdev = priv->mdev;
1434 int err;
1435
c27a02cd
YP		 1436 mutex_lock(&mdev->state_lock);
1437 if (mdev->device_up) {
6123db2e
JM		 1438 if (priv->port_up) {
1439 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1440 if (err)
1441 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1442
c27a02cd 1443 mlx4_en_auto_moderation(priv);
6123db2e 1444 }
c27a02cd
YP		 1445
1446 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1447 }
d7e1a487 1448 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
2695bab2 1449 mlx4_en_do_set_mac(priv, priv->current_mac);
d7e1a487
YP		 1450 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1451 }
c27a02cd
YP		 1452 mutex_unlock(&mdev->state_lock);
1453}
1454
b6c39bfc
AV		 1455/* mlx4_en_service_task - Run service task for tasks that needed to be done
1456 * periodically
1457 */
1458static void mlx4_en_service_task(struct work_struct *work)
1459{
1460 struct delayed_work *delay = to_delayed_work(work);
1461 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1462 service_task);
1463 struct mlx4_en_dev *mdev = priv->mdev;
1464
1465 mutex_lock(&mdev->state_lock);
1466 if (mdev->device_up) {
dc8142ea
AV		 1467 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1468 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc 1469
07841f9d 1470 mlx4_en_recover_from_oom(priv);
b6c39bfc
AV		 1471 queue_delayed_work(mdev->workqueue, &priv->service_task,
1472 SERVICE_TASK_DELAY);
1473 }
1474 mutex_unlock(&mdev->state_lock);
1475}
1476
c27a02cd
YP		 1477static void mlx4_en_linkstate(struct work_struct *work)
1478{
1479 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1480 linkstate_task);
1481 struct mlx4_en_dev *mdev = priv->mdev;
1482 int linkstate = priv->link_state;
1483
1484 mutex_lock(&mdev->state_lock);
1485 /* If observable port state changed set carrier state and
1486 * report to system log */
1487 if (priv->last_link_state != linkstate) {
1488 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1489 en_info(priv, "Link Down\n");
c27a02cd
YP		 1490 netif_carrier_off(priv->dev);
1491 } else {
e5cc44b2 1492 en_info(priv, "Link Up\n");
c27a02cd
YP		 1493 netif_carrier_on(priv->dev);
1494 }
1495 }
1496 priv->last_link_state = linkstate;
1497 mutex_unlock(&mdev->state_lock);
1498}
1499
9e311e77
YA		 1500static int mlx4_en_init_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1501{
1502 struct mlx4_en_rx_ring *ring = priv->rx_ring[ring_idx];
1503 int numa_node = priv->mdev->dev->numa_node;
1504 int ret = 0;
1505
1506 if (!zalloc_cpumask_var(&ring->affinity_mask, GFP_KERNEL))
1507 return -ENOMEM;
1508
1509 ret = cpumask_set_cpu_local_first(ring_idx, numa_node,
1510 ring->affinity_mask);
1511 if (ret)
1512 free_cpumask_var(ring->affinity_mask);
1513
1514 return ret;
1515}
1516
1517static void mlx4_en_free_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1518{
1519 free_cpumask_var(priv->rx_ring[ring_idx]->affinity_mask);
1520}
c27a02cd 1521
18cc42a3 1522int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP		 1523{
1524 struct mlx4_en_priv *priv = netdev_priv(dev);
1525 struct mlx4_en_dev *mdev = priv->mdev;
1526 struct mlx4_en_cq *cq;
1527 struct mlx4_en_tx_ring *tx_ring;
c27a02cd
YP		 1528 int rx_index = 0;
1529 int tx_index = 0;
c27a02cd
YP		 1530 int err = 0;
1531 int i;
1532 int j;
1679200f 1533 u8 mc_list[16] = {0};
c27a02cd
YP		 1534
1535 if (priv->port_up) {
453a6082 1536 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP		 1537 return 0;
1538 }
1539
6d199937
YP		 1540 INIT_LIST_HEAD(&priv->mc_list);
1541 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ		 1542 INIT_LIST_HEAD(&priv->ethtool_list);
1543 memset(&priv->ethtool_rules[0], 0,
1544 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1545
c27a02cd
YP		 1546 /* Calculate Rx buf size */
1547 dev->mtu = min(dev->mtu, priv->max_mtu);
1548 mlx4_en_calc_rx_buf(dev);
453a6082 1549 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1550
c27a02cd 1551 /* Configure rx cq's and rings */
38aab07c
YP		 1552 err = mlx4_en_activate_rx_rings(priv);
1553 if (err) {
453a6082 1554 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP		 1555 return err;
1556 }
c27a02cd 1557 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1558 cq = priv->rx_cq[i];
c27a02cd 1559
9e77a2b8
AV		 1560 mlx4_en_cq_init_lock(cq);
1561
9e311e77
YA		 1562 err = mlx4_en_init_affinity_hint(priv, i);
1563 if (err) {
1564 en_err(priv, "Failed preparing IRQ affinity hint\n");
1565 goto cq_err;
1566 }
1567
76532d0c 1568 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1569 if (err) {
453a6082 1570 en_err(priv, "Failed activating Rx CQ\n");
9e311e77 1571 mlx4_en_free_affinity_hint(priv, i);
a4233304 1572 goto cq_err;
c27a02cd 1573 }
c3f2511f
IS		 1574
1575 for (j = 0; j < cq->size; j++) {
1576 struct mlx4_cqe *cqe = NULL;
1577
1578 cqe = mlx4_en_get_cqe(cq->buf, j, priv->cqe_size) +
1579 priv->cqe_factor;
1580 cqe->owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1581 }
1582
c27a02cd
YP		 1583 err = mlx4_en_set_cq_moder(priv, cq);
1584 if (err) {
1a91de28 1585 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd 1586 mlx4_en_deactivate_cq(priv, cq);
9e311e77 1587 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1588 goto cq_err;
1589 }
1590 mlx4_en_arm_cq(priv, cq);
41d942d5 1591 priv->rx_ring[i]->cqn = cq->mcq.cqn;
c27a02cd
YP		 1592 ++rx_index;
1593 }
1594
ffe455ad
EE		 1595 /* Set qp number */
1596 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1597 err = mlx4_en_get_qp(priv);
1679200f 1598 if (err) {
ffe455ad 1599 en_err(priv, "Failed getting eth qp\n");
1679200f
YP		 1600 goto cq_err;
1601 }
1602 mdev->mac_removed[priv->port] = 0;
1603
c27a02cd
YP		 1604 err = mlx4_en_config_rss_steer(priv);
1605 if (err) {
453a6082 1606 en_err(priv, "Failed configuring rss steering\n");
1679200f 1607 goto mac_err;
c27a02cd
YP		 1608 }
1609
cabdc8ee
HHZ		 1610 err = mlx4_en_create_drop_qp(priv);
1611 if (err)
1612 goto rss_err;
1613
c27a02cd
YP		 1614 /* Configure tx cq's and rings */
1615 for (i = 0; i < priv->tx_ring_num; i++) {
1616 /* Configure cq */
41d942d5 1617 cq = priv->tx_cq[i];
76532d0c 1618 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1619 if (err) {
453a6082 1620 en_err(priv, "Failed allocating Tx CQ\n");
c27a02cd
YP		 1621 goto tx_err;
1622 }
1623 err = mlx4_en_set_cq_moder(priv, cq);
1624 if (err) {
1a91de28 1625 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd
YP		 1626 mlx4_en_deactivate_cq(priv, cq);
1627 goto tx_err;
1628 }
453a6082 1629 en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i);
c27a02cd
YP		 1630 cq->buf->wqe_index = cpu_to_be16(0xffff);
1631
1632 /* Configure ring */
41d942d5 1633 tx_ring = priv->tx_ring[i];
0e98b523 1634 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
d317966b 1635 i / priv->num_tx_rings_p_up);
c27a02cd 1636 if (err) {
453a6082 1637 en_err(priv, "Failed allocating Tx ring\n");
c27a02cd
YP		 1638 mlx4_en_deactivate_cq(priv, cq);
1639 goto tx_err;
1640 }
5b263f53 1641 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
e22979d9
YP		 1642
1643 /* Arm CQ for TX completions */
1644 mlx4_en_arm_cq(priv, cq);
1645
c27a02cd
YP		 1646 /* Set initial ownership of all Tx TXBBs to SW (1) */
1647 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1648 *((u32 *) (tx_ring->buf + j)) = 0xffffffff;
1649 ++tx_index;
1650 }
1651
1652 /* Configure port */
1653 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1654 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 1655 priv->prof->tx_pause,
1656 priv->prof->tx_ppp,
1657 priv->prof->rx_pause,
1658 priv->prof->rx_ppp);
c27a02cd 1659 if (err) {
48e551ff
YB		 1660 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1661 priv->port, err);
c27a02cd
YP		 1662 goto tx_err;
1663 }
1664 /* Set default qp number */
1665 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1666 if (err) {
453a6082 1667 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP		 1668 goto tx_err;
1669 }
c27a02cd 1670
837052d0 1671 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 1672 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 1673 if (err) {
1674 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1675 err);
1676 goto tx_err;
1677 }
1678 }
1679
c27a02cd 1680 /* Init port */
453a6082 1681 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP		 1682 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1683 if (err) {
453a6082 1684 en_err(priv, "Failed Initializing port\n");
1679200f 1685 goto tx_err;
c27a02cd
YP		 1686 }
1687
1679200f 1688 /* Attach rx QP to bradcast address */
c7bf7169 1689 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1690 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1691 if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ		 1692 priv->port, 0, MLX4_PROT_ETH,
1693 &priv->broadcast_id))
1679200f
YP		 1694 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1695
b5845f98
HX		 1696 /* Must redo promiscuous mode setup. */
1697 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1698
c27a02cd 1699 /* Schedule multicast task to populate multicast list */
0eb74fdd 1700 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1701
a66132f3 1702#ifdef CONFIG_MLX4_EN_VXLAN
9737c6ab 1703 if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1 1704 vxlan_get_rx_port(dev);
a66132f3 1705#endif
c27a02cd 1706 priv->port_up = true;
a11faac7 1707 netif_tx_start_all_queues(dev);
3484aac1
AV		 1708 netif_device_attach(dev);
1709
c27a02cd
YP		 1710 return 0;
1711
c27a02cd
YP		 1712tx_err:
1713 while (tx_index--) {
41d942d5
EE		 1714 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]);
1715 mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]);
c27a02cd 1716 }
cabdc8ee
HHZ		 1717 mlx4_en_destroy_drop_qp(priv);
1718rss_err:
c27a02cd 1719 mlx4_en_release_rss_steer(priv);
1679200f 1720mac_err:
16a10ffd 1721 mlx4_en_put_qp(priv);
c27a02cd 1722cq_err:
9e311e77 1723 while (rx_index--) {
41d942d5 1724 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
f94813f3 1725 mlx4_en_free_affinity_hint(priv, rx_index);
9e311e77 1726 }
38aab07c 1727 for (i = 0; i < priv->rx_ring_num; i++)
41d942d5 1728 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
c27a02cd
YP		 1729
1730 return err; /* need to close devices */
1731}
1732
1733
3484aac1 1734void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP		 1735{
1736 struct mlx4_en_priv *priv = netdev_priv(dev);
1737 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1738 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1739 struct ethtool_flow_id *flow, *tmp_flow;
c27a02cd 1740 int i;
1679200f 1741 u8 mc_list[16] = {0};
c27a02cd
YP		 1742
1743 if (!priv->port_up) {
453a6082 1744 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP		 1745 return;
1746 }
c27a02cd 1747
0cc5c8bf
EE		 1748 /* close port*/
1749 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1750
c27a02cd
YP		 1751 /* Synchronize with tx routine */
1752 netif_tx_lock_bh(dev);
3484aac1
AV		 1753 if (detach)
1754 netif_device_detach(dev);
3c05f5ef 1755 netif_tx_stop_all_queues(dev);
c27a02cd
YP		 1756 netif_tx_unlock_bh(dev);
1757
3484aac1
AV		 1758 netif_tx_disable(dev);
1759
7c287380 1760 /* Set port as not active */
3c05f5ef 1761 priv->port_up = false;
c27a02cd 1762
db0e7cba
AY		 1763 /* Promsicuous mode */
1764 if (mdev->dev->caps.steering_mode ==
1765 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1766 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1767 MLX4_EN_FLAG_MC_PROMISC);
1768 mlx4_flow_steer_promisc_remove(mdev->dev,
1769 priv->port,
f9162539 1770 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY		 1771 mlx4_flow_steer_promisc_remove(mdev->dev,
1772 priv->port,
f9162539 1773 MLX4_FS_MC_DEFAULT);
db0e7cba
AY		 1774 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1775 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1776
1777 /* Disable promiscouos mode */
1778 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1779 priv->port);
1780
1781 /* Disable Multicast promisc */
1782 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1783 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1784 priv->port);
1785 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1786 }
1787 }
1788
1679200f 1789 /* Detach All multicasts */
c7bf7169 1790 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1791 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1792 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65 1793 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP		 1794 list_for_each_entry(mclist, &priv->curr_list, list) {
1795 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f
YP		 1796 mc_list[5] = priv->port;
1797 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp,
0ff1fb65 1798 mc_list, MLX4_PROT_ETH, mclist->reg_id);
de123268
OG		 1799 if (mclist->tunnel_reg_id)
1800 mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id);
1679200f
YP		 1801 }
1802 mlx4_en_clear_list(dev);
6d199937
YP		 1803 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1804 list_del(&mclist->list);
1805 kfree(mclist);
1806 }
1807
1679200f
YP		 1808 /* Flush multicast filter */
1809 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1810
6efb5fac
HHZ		 1811 /* Remove flow steering rules for the port*/
1812 if (mdev->dev->caps.steering_mode ==
1813 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1814 ASSERT_RTNL();
1815 list_for_each_entry_safe(flow, tmp_flow,
1816 &priv->ethtool_list, list) {
1817 mlx4_flow_detach(mdev->dev, flow->id);
1818 list_del(&flow->list);
1819 }
1820 }
1821
cabdc8ee
HHZ		 1822 mlx4_en_destroy_drop_qp(priv);
1823
c27a02cd
YP		 1824 /* Free TX Rings */
1825 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1826 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]);
1827 mlx4_en_deactivate_cq(priv, priv->tx_cq[i]);
c27a02cd
YP		 1828 }
1829 msleep(10);
1830
1831 for (i = 0; i < priv->tx_ring_num; i++)
41d942d5 1832 mlx4_en_free_tx_buf(dev, priv->tx_ring[i]);
c27a02cd
YP		 1833
1834 /* Free RSS qps */
1835 mlx4_en_release_rss_steer(priv);
1836
ffe455ad 1837 /* Unregister Mac address for the port */
16a10ffd 1838 mlx4_en_put_qp(priv);
5930e8d0 1839 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1840 mdev->mac_removed[priv->port] = 1;
ffe455ad 1841
c27a02cd
YP		 1842 /* Free RX Rings */
1843 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1844 struct mlx4_en_cq *cq = priv->rx_cq[i];
9e77a2b8
AV		 1845
1846 local_bh_disable();
1847 while (!mlx4_en_cq_lock_napi(cq)) {
1848 pr_info("CQ %d locked\n", i);
1849 mdelay(1);
1850 }
1851 local_bh_enable();
1852
f4a36751 1853 napi_synchronize(&cq->napi);
41d942d5 1854 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
9e77a2b8 1855 mlx4_en_deactivate_cq(priv, cq);
9e311e77
YA		 1856
1857 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1858 }
1859}
1860
1861static void mlx4_en_restart(struct work_struct *work)
1862{
1863 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1864 watchdog_task);
1865 struct mlx4_en_dev *mdev = priv->mdev;
1866 struct net_device *dev = priv->dev;
1867
453a6082 1868 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5
YP		 1869
1870 mutex_lock(&mdev->state_lock);
1871 if (priv->port_up) {
3484aac1 1872 mlx4_en_stop_port(dev, 1);
1e338db5 1873 if (mlx4_en_start_port(dev))
453a6082 1874 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP		 1875 }
1876 mutex_unlock(&mdev->state_lock);
c27a02cd
YP		 1877}
1878
b477ba62 1879static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP		 1880{
1881 struct mlx4_en_priv *priv = netdev_priv(dev);
1882 struct mlx4_en_dev *mdev = priv->mdev;
1883 int i;
c27a02cd 1884
c27a02cd 1885 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
453a6082 1886 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd
YP		 1887
1888 memset(&priv->stats, 0, sizeof(priv->stats));
1889 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE		 1890 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
1891 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
0b131561
MB		 1892 memset(&priv->rx_flowstats, 0, sizeof(priv->rx_flowstats));
1893 memset(&priv->tx_flowstats, 0, sizeof(priv->tx_flowstats));
1894 memset(&priv->rx_priority_flowstats, 0,
1895 sizeof(priv->rx_priority_flowstats));
1896 memset(&priv->tx_priority_flowstats, 0,
1897 sizeof(priv->tx_priority_flowstats));
c27a02cd
YP		 1898
1899 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1900 priv->tx_ring[i]->bytes = 0;
1901 priv->tx_ring[i]->packets = 0;
1902 priv->tx_ring[i]->tx_csum = 0;
c27a02cd
YP		 1903 }
1904 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 1905 priv->rx_ring[i]->bytes = 0;
1906 priv->rx_ring[i]->packets = 0;
1907 priv->rx_ring[i]->csum_ok = 0;
1908 priv->rx_ring[i]->csum_none = 0;
f8c6455b 1909 priv->rx_ring[i]->csum_complete = 0;
c27a02cd 1910 }
b477ba62
EE		 1911}
1912
1913static int mlx4_en_open(struct net_device *dev)
1914{
1915 struct mlx4_en_priv *priv = netdev_priv(dev);
1916 struct mlx4_en_dev *mdev = priv->mdev;
1917 int err = 0;
1918
1919 mutex_lock(&mdev->state_lock);
1920
1921 if (!mdev->device_up) {
1922 en_err(priv, "Cannot open - device down/disabled\n");
1923 err = -EBUSY;
1924 goto out;
1925 }
1926
1927 /* Reset HW statistics and SW counters */
1928 mlx4_en_clear_stats(dev);
c27a02cd 1929
c27a02cd
YP		 1930 err = mlx4_en_start_port(dev);
1931 if (err)
453a6082 1932 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP		 1933
1934out:
1935 mutex_unlock(&mdev->state_lock);
1936 return err;
1937}
1938
1939
1940static int mlx4_en_close(struct net_device *dev)
1941{
1942 struct mlx4_en_priv *priv = netdev_priv(dev);
1943 struct mlx4_en_dev *mdev = priv->mdev;
1944
453a6082 1945 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP		 1946
1947 mutex_lock(&mdev->state_lock);
1948
3484aac1 1949 mlx4_en_stop_port(dev, 0);
c27a02cd
YP		 1950 netif_carrier_off(dev);
1951
1952 mutex_unlock(&mdev->state_lock);
1953 return 0;
1954}
1955
fe0af03c 1956void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd
YP		 1957{
1958 int i;
1959
1eb8c695
AV		 1960#ifdef CONFIG_RFS_ACCEL
1961 free_irq_cpu_rmap(priv->dev->rx_cpu_rmap);
1962 priv->dev->rx_cpu_rmap = NULL;
1963#endif
1964
c27a02cd 1965 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1966 if (priv->tx_ring && priv->tx_ring[i])
c27a02cd 1967 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
41d942d5 1968 if (priv->tx_cq && priv->tx_cq[i])
fe0af03c 1969 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
c27a02cd
YP		 1970 }
1971
1972 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1973 if (priv->rx_ring[i])
68355f71
TLSC		 1974 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
1975 priv->prof->rx_ring_size, priv->stride);
41d942d5 1976 if (priv->rx_cq[i])
fe0af03c 1977 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 1978 }
044ca2a5
YP		 1979
1980 if (priv->base_tx_qpn) {
1981 mlx4_qp_release_range(priv->mdev->dev, priv->base_tx_qpn, priv->tx_ring_num);
1982 priv->base_tx_qpn = 0;
1983 }
c27a02cd
YP		 1984}
1985
18cc42a3 1986int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 1987{
c27a02cd
YP		 1988 struct mlx4_en_port_profile *prof = priv->prof;
1989 int i;
163561a4 1990 int node;
87a5c389 1991
c27a02cd
YP		 1992 /* Create tx Rings */
1993 for (i = 0; i < priv->tx_ring_num; i++) {
163561a4 1994 node = cpu_to_node(i % num_online_cpus());
c27a02cd 1995 if (mlx4_en_create_cq(priv, &priv->tx_cq[i],
163561a4 1996 prof->tx_ring_size, i, TX, node))
c27a02cd
YP		 1997 goto err;
1998
d03a68f8 1999 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i],
d03a68f8
IS		 2000 prof->tx_ring_size, TXBB_SIZE,
2001 node, i))
c27a02cd
YP		 2002 goto err;
2003 }
2004
2005 /* Create rx Rings */
2006 for (i = 0; i < priv->rx_ring_num; i++) {
163561a4 2007 node = cpu_to_node(i % num_online_cpus());
c27a02cd 2008 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
163561a4 2009 prof->rx_ring_size, i, RX, node))
c27a02cd
YP		 2010 goto err;
2011
2012 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
163561a4
EE		 2013 prof->rx_ring_size, priv->stride,
2014 node))
c27a02cd
YP		 2015 goto err;
2016 }
2017
1eb8c695 2018#ifdef CONFIG_RFS_ACCEL
a229e488
AV		 2019 if (priv->mdev->dev->caps.comp_pool) {
2020 priv->dev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->mdev->dev->caps.comp_pool);
2021 if (!priv->dev->rx_cpu_rmap)
2022 goto err;
2023 }
1eb8c695
AV		 2024#endif
2025
c27a02cd
YP		 2026 return 0;
2027
2028err:
453a6082 2029 en_err(priv, "Failed to allocate NIC resources\n");
41d942d5
EE		 2030 for (i = 0; i < priv->rx_ring_num; i++) {
2031 if (priv->rx_ring[i])
2032 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2033 prof->rx_ring_size,
2034 priv->stride);
2035 if (priv->rx_cq[i])
2036 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2037 }
2038 for (i = 0; i < priv->tx_ring_num; i++) {
2039 if (priv->tx_ring[i])
2040 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
2041 if (priv->tx_cq[i])
2042 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
2043 }
c27a02cd
YP		 2044 return -ENOMEM;
2045}
2046
2047
2048void mlx4_en_destroy_netdev(struct net_device *dev)
2049{
2050 struct mlx4_en_priv *priv = netdev_priv(dev);
2051 struct mlx4_en_dev *mdev = priv->mdev;
2052
453a6082 2053 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP		 2054
2055 /* Unregister device - this will close the port if it was up */
2056 if (priv->registered)
2057 unregister_netdev(dev);
2058
2059 if (priv->allocated)
2060 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2061
2062 cancel_delayed_work(&priv->stats_task);
b6c39bfc 2063 cancel_delayed_work(&priv->service_task);
c27a02cd
YP		 2064 /* flush any pending task for this netdev */
2065 flush_workqueue(mdev->workqueue);
2066
2067 /* Detach the netdev so tasks would not attempt to access it */
2068 mutex_lock(&mdev->state_lock);
2069 mdev->pndev[priv->port] = NULL;
5da03547 2070 mdev->upper[priv->port] = NULL;
c27a02cd
YP		 2071 mutex_unlock(&mdev->state_lock);
2072
fe0af03c 2073 mlx4_en_free_resources(priv);
564c274c 2074
bc6a4744
AV		 2075 kfree(priv->tx_ring);
2076 kfree(priv->tx_cq);
2077
c27a02cd
YP		 2078 free_netdev(dev);
2079}
2080
2081static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2082{
2083 struct mlx4_en_priv *priv = netdev_priv(dev);
2084 struct mlx4_en_dev *mdev = priv->mdev;
2085 int err = 0;
2086
453a6082 2087 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP		 2088 dev->mtu, new_mtu);
2089
2090 if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) {
453a6082 2091 en_err(priv, "Bad MTU size:%d.\n", new_mtu);
c27a02cd
YP		 2092 return -EPERM;
2093 }
2094 dev->mtu = new_mtu;
2095
2096 if (netif_running(dev)) {
2097 mutex_lock(&mdev->state_lock);
2098 if (!mdev->device_up) {
2099 /* NIC is probably restarting - let watchdog task reset
2100 * the port */
453a6082 2101 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 2102 } else {
3484aac1 2103 mlx4_en_stop_port(dev, 1);
c27a02cd
YP		 2104 err = mlx4_en_start_port(dev);
2105 if (err) {
453a6082 2106 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP		 2107 priv->port);
2108 queue_work(mdev->workqueue, &priv->watchdog_task);
2109 }
2110 }
2111 mutex_unlock(&mdev->state_lock);
2112 }
2113 return 0;
2114}
2115
100dbda8 2116static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
ec693d47
AV		 2117{
2118 struct mlx4_en_priv *priv = netdev_priv(dev);
2119 struct mlx4_en_dev *mdev = priv->mdev;
2120 struct hwtstamp_config config;
2121
2122 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2123 return -EFAULT;
2124
2125 /* reserved for future extensions */
2126 if (config.flags)
2127 return -EINVAL;
2128
2129 /* device doesn't support time stamping */
2130 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2131 return -EINVAL;
2132
2133 /* TX HW timestamp */
2134 switch (config.tx_type) {
2135 case HWTSTAMP_TX_OFF:
2136 case HWTSTAMP_TX_ON:
2137 break;
2138 default:
2139 return -ERANGE;
2140 }
2141
2142 /* RX HW timestamp */
2143 switch (config.rx_filter) {
2144 case HWTSTAMP_FILTER_NONE:
2145 break;
2146 case HWTSTAMP_FILTER_ALL:
2147 case HWTSTAMP_FILTER_SOME:
2148 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2149 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2150 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2151 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2152 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2153 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2154 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2155 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2156 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2157 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2158 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2159 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2160 config.rx_filter = HWTSTAMP_FILTER_ALL;
2161 break;
2162 default:
2163 return -ERANGE;
2164 }
2165
7787fa66 2166 if (mlx4_en_reset_config(dev, config, dev->features)) {
ec693d47
AV		 2167 config.tx_type = HWTSTAMP_TX_OFF;
2168 config.rx_filter = HWTSTAMP_FILTER_NONE;
2169 }
2170
2171 return copy_to_user(ifr->ifr_data, &config,
2172 sizeof(config)) ? -EFAULT : 0;
2173}
2174
100dbda8
BH		 2175static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2176{
2177 struct mlx4_en_priv *priv = netdev_priv(dev);
2178
2179 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2180 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2181}
2182
ec693d47
AV		 2183static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2184{
2185 switch (cmd) {
2186 case SIOCSHWTSTAMP:
100dbda8
BH		 2187 return mlx4_en_hwtstamp_set(dev, ifr);
2188 case SIOCGHWTSTAMP:
2189 return mlx4_en_hwtstamp_get(dev, ifr);
ec693d47
AV		 2190 default:
2191 return -EOPNOTSUPP;
2192 }
2193}
2194
60d6fe99
AV		 2195static int mlx4_en_set_features(struct net_device *netdev,
2196 netdev_features_t features)
2197{
2198 struct mlx4_en_priv *priv = netdev_priv(netdev);
f0df3503 2199 bool reset = false;
537f6f95
SM		 2200 int ret = 0;
2201
f0df3503
MM		 2202 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXFCS)) {
2203 en_info(priv, "Turn %s RX-FCS\n",
2204 (features & NETIF_F_RXFCS) ? "ON" : "OFF");
2205 reset = true;
2206 }
2207
78500b8c
MM		 2208 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXALL)) {
2209 u8 ignore_fcs_value = (features & NETIF_F_RXALL) ? 1 : 0;
2210
2211 en_info(priv, "Turn %s RX-ALL\n",
2212 ignore_fcs_value ? "ON" : "OFF");
2213 ret = mlx4_SET_PORT_fcs_check(priv->mdev->dev,
2214 priv->port, ignore_fcs_value);
2215 if (ret)
2216 return ret;
2217 }
2218
537f6f95
SM		 2219 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
2220 en_info(priv, "Turn %s RX vlan strip offload\n",
2221 (features & NETIF_F_HW_VLAN_CTAG_RX) ? "ON" : "OFF");
f0df3503 2222 reset = true;
537f6f95 2223 }
60d6fe99 2224
cfb53f36
IS		 2225 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_TX))
2226 en_info(priv, "Turn %s TX vlan strip offload\n",
2227 (features & NETIF_F_HW_VLAN_CTAG_TX) ? "ON" : "OFF");
2228
241a08c3
IS		 2229 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_LOOPBACK)) {
2230 en_info(priv, "Turn %s loopback\n",
2231 (features & NETIF_F_LOOPBACK) ? "ON" : "OFF");
2232 mlx4_en_update_loopback_state(netdev, features);
2233 }
79aeaccd 2234
f0df3503
MM		 2235 if (reset) {
2236 ret = mlx4_en_reset_config(netdev, priv->hwtstamp_config,
2237 features);
2238 if (ret)
2239 return ret;
2240 }
60d6fe99 2241
f0df3503 2242 return 0;
60d6fe99
AV		 2243}
2244
8f7ba3ca
RE		 2245static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2246{
2247 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2248 struct mlx4_en_dev *mdev = en_priv->mdev;
9813337a 2249 u64 mac_u64 = mlx4_mac_to_u64(mac);
8f7ba3ca
RE		 2250
2251 if (!is_valid_ether_addr(mac))
2252 return -EINVAL;
2253
2254 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64);
2255}
2256
3f7fb021
RE		 2257static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2258{
2259 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2260 struct mlx4_en_dev *mdev = en_priv->mdev;
2261
2262 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos);
2263}
2264
cda373f4
IS		 2265static int mlx4_en_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2266 int max_tx_rate)
2267{
2268 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2269 struct mlx4_en_dev *mdev = en_priv->mdev;
2270
2271 return mlx4_set_vf_rate(mdev->dev, en_priv->port, vf, min_tx_rate,
2272 max_tx_rate);
2273}
2274
e6b6a231
RE		 2275static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2276{
2277 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2278 struct mlx4_en_dev *mdev = en_priv->mdev;
2279
2280 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2281}
2282
2cccb9e4
RE		 2283static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2284{
2285 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2286 struct mlx4_en_dev *mdev = en_priv->mdev;
2287
2288 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2289}
8f7ba3ca 2290
948e306d
RE		 2291static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2292{
2293 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2294 struct mlx4_en_dev *mdev = en_priv->mdev;
2295
2296 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2297}
84c86403
HHZ		 2298
2299#define PORT_ID_BYTE_LEN 8
2300static int mlx4_en_get_phys_port_id(struct net_device *dev,
02637fce 2301 struct netdev_phys_item_id *ppid)
84c86403
HHZ		 2302{
2303 struct mlx4_en_priv *priv = netdev_priv(dev);
2304 struct mlx4_dev *mdev = priv->mdev->dev;
2305 int i;
2306 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2307
2308 if (!phys_port_id)
2309 return -EOPNOTSUPP;
2310
2311 ppid->id_len = sizeof(phys_port_id);
2312 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2313 ppid->id[i] = phys_port_id & 0xff;
2314 phys_port_id >>= 8;
2315 }
2316 return 0;
2317}
2318
a66132f3 2319#ifdef CONFIG_MLX4_EN_VXLAN
1b136de1
OG		 2320static void mlx4_en_add_vxlan_offloads(struct work_struct *work)
2321{
2322 int ret;
2323 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2324 vxlan_add_task);
2325
2326 ret = mlx4_config_vxlan_port(priv->mdev->dev, priv->vxlan_port);
2327 if (ret)
2328 goto out;
2329
2330 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2331 VXLAN_STEER_BY_OUTER_MAC, 1);
2332out:
f4a1edd5 2333 if (ret) {
1b136de1 2334 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
f4a1edd5
OG		 2335 return;
2336 }
2337
2338 /* set offloads */
2339 priv->dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2340 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL;
2341 priv->dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2342 priv->dev->features |= NETIF_F_GSO_UDP_TUNNEL;
1b136de1
OG		 2343}
2344
2345static void mlx4_en_del_vxlan_offloads(struct work_struct *work)
2346{
2347 int ret;
2348 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2349 vxlan_del_task);
f4a1edd5
OG		 2350 /* unset offloads */
2351 priv->dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2352 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL);
2353 priv->dev->hw_features &= ~NETIF_F_GSO_UDP_TUNNEL;
2354 priv->dev->features &= ~NETIF_F_GSO_UDP_TUNNEL;
1b136de1
OG		 2355
2356 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2357 VXLAN_STEER_BY_OUTER_MAC, 0);
2358 if (ret)
2359 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
2360
2361 priv->vxlan_port = 0;
2362}
2363
2364static void mlx4_en_add_vxlan_port(struct net_device *dev,
2365 sa_family_t sa_family, __be16 port)
2366{
2367 struct mlx4_en_priv *priv = netdev_priv(dev);
2368 __be16 current_port;
2369
e326f2f1 2370 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1
OG		 2371 return;
2372
2373 if (sa_family == AF_INET6)
2374 return;
2375
2376 current_port = priv->vxlan_port;
2377 if (current_port && current_port != port) {
2378 en_warn(priv, "vxlan port %d configured, can't add port %d\n",
2379 ntohs(current_port), ntohs(port));
2380 return;
2381 }
2382
2383 priv->vxlan_port = port;
2384 queue_work(priv->mdev->workqueue, &priv->vxlan_add_task);
2385}
2386
2387static void mlx4_en_del_vxlan_port(struct net_device *dev,
2388 sa_family_t sa_family, __be16 port)
2389{
2390 struct mlx4_en_priv *priv = netdev_priv(dev);
2391 __be16 current_port;
2392
2393 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
2394 return;
2395
2396 if (sa_family == AF_INET6)
2397 return;
2398
2399 current_port = priv->vxlan_port;
2400 if (current_port != port) {
2401 en_dbg(DRV, priv, "vxlan port %d isn't configured, ignoring\n", ntohs(port));
2402 return;
2403 }
2404
2405 queue_work(priv->mdev->workqueue, &priv->vxlan_del_task);
2406}
956bdab2 2407
5f35227e
JG		 2408static netdev_features_t mlx4_en_features_check(struct sk_buff *skb,
2409 struct net_device *dev,
2410 netdev_features_t features)
956bdab2 2411{
8cb65d00 2412 features = vlan_features_check(skb, features);
5f35227e 2413 return vxlan_features_check(skb, features);
956bdab2 2414}
a66132f3 2415#endif
1b136de1 2416
de1cf8a7 2417static int mlx4_en_set_tx_maxrate(struct net_device *dev, int queue_index, u32 maxrate)
c10e4fc6
OG		 2418{
2419 struct mlx4_en_priv *priv = netdev_priv(dev);
2420 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[queue_index];
2421 struct mlx4_update_qp_params params;
2422 int err;
2423
2424 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT))
2425 return -EOPNOTSUPP;
2426
2427 /* rate provided to us in Mbs, check if it fits into 12 bits, if not use Gbs */
2428 if (maxrate >> 12) {
2429 params.rate_unit = MLX4_QP_RATE_LIMIT_GBS;
2430 params.rate_val = maxrate / 1000;
2431 } else if (maxrate) {
2432 params.rate_unit = MLX4_QP_RATE_LIMIT_MBS;
2433 params.rate_val = maxrate;
2434 } else { /* zero serves to revoke the QP rate-limitation */
2435 params.rate_unit = 0;
2436 params.rate_val = 0;
2437 }
2438
2439 err = mlx4_update_qp(priv->mdev->dev, tx_ring->qpn, MLX4_UPDATE_QP_RATE_LIMIT,
2440 &params);
2441 return err;
2442}
2443
3addc568
SH		 2444static const struct net_device_ops mlx4_netdev_ops = {
2445 .ndo_open = mlx4_en_open,
2446 .ndo_stop = mlx4_en_close,
2447 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2448 .ndo_select_queue = mlx4_en_select_queue,
3addc568 2449 .ndo_get_stats = mlx4_en_get_stats,
0eb74fdd 2450 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2451 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2452 .ndo_validate_addr = eth_validate_addr,
3addc568 2453 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2454 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2455 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH		 2456 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2457 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2458#ifdef CONFIG_NET_POLL_CONTROLLER
2459 .ndo_poll_controller = mlx4_en_netpoll,
2460#endif
60d6fe99 2461 .ndo_set_features = mlx4_en_set_features,
897d7846 2462 .ndo_setup_tc = mlx4_en_setup_tc,
1eb8c695
AV		 2463#ifdef CONFIG_RFS_ACCEL
2464 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2465#endif
e0d1095a 2466#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 2467 .ndo_busy_poll = mlx4_en_low_latency_recv,
9e77a2b8 2468#endif
84c86403 2469 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
a66132f3 2470#ifdef CONFIG_MLX4_EN_VXLAN
1b136de1
OG		 2471 .ndo_add_vxlan_port = mlx4_en_add_vxlan_port,
2472 .ndo_del_vxlan_port = mlx4_en_del_vxlan_port,
5f35227e 2473 .ndo_features_check = mlx4_en_features_check,
a66132f3 2474#endif
c10e4fc6 2475 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
3addc568
SH		 2476};
2477
8f7ba3ca
RE		 2478static const struct net_device_ops mlx4_netdev_ops_master = {
2479 .ndo_open = mlx4_en_open,
2480 .ndo_stop = mlx4_en_close,
2481 .ndo_start_xmit = mlx4_en_xmit,
2482 .ndo_select_queue = mlx4_en_select_queue,
2483 .ndo_get_stats = mlx4_en_get_stats,
2484 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2485 .ndo_set_mac_address = mlx4_en_set_mac,
2486 .ndo_validate_addr = eth_validate_addr,
2487 .ndo_change_mtu = mlx4_en_change_mtu,
2488 .ndo_tx_timeout = mlx4_en_tx_timeout,
2489 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2490 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2491 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2492 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
cda373f4 2493 .ndo_set_vf_rate = mlx4_en_set_vf_rate,
e6b6a231 2494 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2495 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
2cccb9e4 2496 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE		 2497#ifdef CONFIG_NET_POLL_CONTROLLER
2498 .ndo_poll_controller = mlx4_en_netpoll,
2499#endif
2500 .ndo_set_features = mlx4_en_set_features,
2501 .ndo_setup_tc = mlx4_en_setup_tc,
2502#ifdef CONFIG_RFS_ACCEL
2503 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2504#endif
84c86403 2505 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
9737c6ab
OG		 2506#ifdef CONFIG_MLX4_EN_VXLAN
2507 .ndo_add_vxlan_port = mlx4_en_add_vxlan_port,
2508 .ndo_del_vxlan_port = mlx4_en_del_vxlan_port,
5f35227e 2509 .ndo_features_check = mlx4_en_features_check,
9737c6ab 2510#endif
c10e4fc6 2511 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
8f7ba3ca
RE		 2512};
2513
5da03547
MS		 2514struct mlx4_en_bond {
2515 struct work_struct work;
2516 struct mlx4_en_priv *priv;
2517 int is_bonded;
2518 struct mlx4_port_map port_map;
2519};
2520
2521static void mlx4_en_bond_work(struct work_struct *work)
2522{
2523 struct mlx4_en_bond *bond = container_of(work,
2524 struct mlx4_en_bond,
2525 work);
2526 int err = 0;
2527 struct mlx4_dev *dev = bond->priv->mdev->dev;
2528
2529 if (bond->is_bonded) {
2530 if (!mlx4_is_bonded(dev)) {
2531 err = mlx4_bond(dev);
2532 if (err)
2533 en_err(bond->priv, "Fail to bond device\n");
2534 }
2535 if (!err) {
2536 err = mlx4_port_map_set(dev, &bond->port_map);
2537 if (err)
2538 en_err(bond->priv, "Fail to set port map [%d][%d]: %d\n",
2539 bond->port_map.port1,
2540 bond->port_map.port2,
2541 err);
2542 }
2543 } else if (mlx4_is_bonded(dev)) {
2544 err = mlx4_unbond(dev);
2545 if (err)
2546 en_err(bond->priv, "Fail to unbond device\n");
2547 }
2548 dev_put(bond->priv->dev);
2549 kfree(bond);
2550}
2551
2552static int mlx4_en_queue_bond_work(struct mlx4_en_priv *priv, int is_bonded,
2553 u8 v2p_p1, u8 v2p_p2)
2554{
2555 struct mlx4_en_bond *bond = NULL;
2556
2557 bond = kzalloc(sizeof(*bond), GFP_ATOMIC);
2558 if (!bond)
2559 return -ENOMEM;
2560
2561 INIT_WORK(&bond->work, mlx4_en_bond_work);
2562 bond->priv = priv;
2563 bond->is_bonded = is_bonded;
2564 bond->port_map.port1 = v2p_p1;
2565 bond->port_map.port2 = v2p_p2;
2566 dev_hold(priv->dev);
2567 queue_work(priv->mdev->workqueue, &bond->work);
2568 return 0;
2569}
2570
2571int mlx4_en_netdev_event(struct notifier_block *this,
2572 unsigned long event, void *ptr)
2573{
2574 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2575 u8 port = 0;
2576 struct mlx4_en_dev *mdev;
2577 struct mlx4_dev *dev;
2578 int i, num_eth_ports = 0;
2579 bool do_bond = true;
2580 struct mlx4_en_priv *priv;
2581 u8 v2p_port1 = 0;
2582 u8 v2p_port2 = 0;
2583
2584 if (!net_eq(dev_net(ndev), &init_net))
2585 return NOTIFY_DONE;
2586
2587 mdev = container_of(this, struct mlx4_en_dev, nb);
2588 dev = mdev->dev;
2589
2590 /* Go into this mode only when two network devices set on two ports
2591 * of the same mlx4 device are slaves of the same bonding master
2592 */
2593 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
2594 ++num_eth_ports;
2595 if (!port && (mdev->pndev[i] == ndev))
2596 port = i;
2597 mdev->upper[i] = mdev->pndev[i] ?
2598 netdev_master_upper_dev_get(mdev->pndev[i]) : NULL;
2599 /* condition not met: network device is a slave */
2600 if (!mdev->upper[i])
2601 do_bond = false;
2602 if (num_eth_ports < 2)
2603 continue;
2604 /* condition not met: same master */
2605 if (mdev->upper[i] != mdev->upper[i-1])
2606 do_bond = false;
2607 }
2608 /* condition not met: 2 salves */
2609 do_bond = (num_eth_ports == 2) ? do_bond : false;
2610
2611 /* handle only events that come with enough info */
2612 if ((do_bond && (event != NETDEV_BONDING_INFO)) || !port)
2613 return NOTIFY_DONE;
2614
2615 priv = netdev_priv(ndev);
2616 if (do_bond) {
2617 struct netdev_notifier_bonding_info *notifier_info = ptr;
2618 struct netdev_bonding_info *bonding_info =
2619 &notifier_info->bonding_info;
2620
2621 /* required mode 1, 2 or 4 */
2622 if ((bonding_info->master.bond_mode != BOND_MODE_ACTIVEBACKUP) &&
2623 (bonding_info->master.bond_mode != BOND_MODE_XOR) &&
2624 (bonding_info->master.bond_mode != BOND_MODE_8023AD))
2625 do_bond = false;
2626
2627 /* require exactly 2 slaves */
2628 if (bonding_info->master.num_slaves != 2)
2629 do_bond = false;
2630
2631 /* calc v2p */
2632 if (do_bond) {
2633 if (bonding_info->master.bond_mode ==
2634 BOND_MODE_ACTIVEBACKUP) {
2635 /* in active-backup mode virtual ports are
2636 * mapped to the physical port of the active
2637 * slave */
2638 if (bonding_info->slave.state ==
2639 BOND_STATE_BACKUP) {
2640 if (port == 1) {
2641 v2p_port1 = 2;
2642 v2p_port2 = 2;
2643 } else {
2644 v2p_port1 = 1;
2645 v2p_port2 = 1;
2646 }
2647 } else { /* BOND_STATE_ACTIVE */
2648 if (port == 1) {
2649 v2p_port1 = 1;
2650 v2p_port2 = 1;
2651 } else {
2652 v2p_port1 = 2;
2653 v2p_port2 = 2;
2654 }
2655 }
2656 } else { /* Active-Active */
2657 /* in active-active mode a virtual port is
2658 * mapped to the native physical port if and only
2659 * if the physical port is up */
2660 __s8 link = bonding_info->slave.link;
2661
2662 if (port == 1)
2663 v2p_port2 = 2;
2664 else
2665 v2p_port1 = 1;
2666 if ((link == BOND_LINK_UP) ||
2667 (link == BOND_LINK_FAIL)) {
2668 if (port == 1)
2669 v2p_port1 = 1;
2670 else
2671 v2p_port2 = 2;
2672 } else { /* BOND_LINK_DOWN || BOND_LINK_BACK */
2673 if (port == 1)
2674 v2p_port1 = 2;
2675 else
2676 v2p_port2 = 1;
2677 }
2678 }
2679 }
2680 }
2681
2682 mlx4_en_queue_bond_work(priv, do_bond,
2683 v2p_port1, v2p_port2);
2684
2685 return NOTIFY_DONE;
2686}
2687
0b131561
MB		 2688void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
2689 struct mlx4_en_stats_bitmap *stats_bitmap,
2690 u8 rx_ppp, u8 rx_pause,
2691 u8 tx_ppp, u8 tx_pause)
2692{
2693 int last_i = NUM_MAIN_STATS + NUM_PORT_STATS;
2694
2695 if (!mlx4_is_slave(dev) &&
2696 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN)) {
2697 mutex_lock(&stats_bitmap->mutex);
2698 bitmap_clear(stats_bitmap->bitmap, last_i, NUM_FLOW_STATS);
2699
2700 if (rx_ppp)
2701 bitmap_set(stats_bitmap->bitmap, last_i,
2702 NUM_FLOW_PRIORITY_STATS_RX);
2703 last_i += NUM_FLOW_PRIORITY_STATS_RX;
2704
2705 if (rx_pause && !(rx_ppp))
2706 bitmap_set(stats_bitmap->bitmap, last_i,
2707 NUM_FLOW_STATS_RX);
2708 last_i += NUM_FLOW_STATS_RX;
2709
2710 if (tx_ppp)
2711 bitmap_set(stats_bitmap->bitmap, last_i,
2712 NUM_FLOW_PRIORITY_STATS_TX);
2713 last_i += NUM_FLOW_PRIORITY_STATS_TX;
2714
2715 if (tx_pause && !(tx_ppp))
2716 bitmap_set(stats_bitmap->bitmap, last_i,
2717 NUM_FLOW_STATS_TX);
2718 last_i += NUM_FLOW_STATS_TX;
2719
2720 mutex_unlock(&stats_bitmap->mutex);
2721 }
2722}
2723
6fcd2735 2724void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
0b131561
MB		 2725 struct mlx4_en_stats_bitmap *stats_bitmap,
2726 u8 rx_ppp, u8 rx_pause,
2727 u8 tx_ppp, u8 tx_pause)
ffa88f37 2728{
6fcd2735
EBE		 2729 int last_i = 0;
2730
3da8a36c
EBE		 2731 mutex_init(&stats_bitmap->mutex);
2732 bitmap_zero(stats_bitmap->bitmap, NUM_ALL_STATS);
6fcd2735
EBE		 2733
2734 if (mlx4_is_slave(dev)) {
3da8a36c 2735 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2736 MLX4_FIND_NETDEV_STAT(rx_packets), 1);
3da8a36c 2737 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2738 MLX4_FIND_NETDEV_STAT(tx_packets), 1);
3da8a36c 2739 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2740 MLX4_FIND_NETDEV_STAT(rx_bytes), 1);
3da8a36c 2741 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2742 MLX4_FIND_NETDEV_STAT(tx_bytes), 1);
3da8a36c 2743 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2744 MLX4_FIND_NETDEV_STAT(rx_dropped), 1);
3da8a36c 2745 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735
EBE		 2746 MLX4_FIND_NETDEV_STAT(tx_dropped), 1);
2747 } else {
3da8a36c 2748 bitmap_set(stats_bitmap->bitmap, last_i, NUM_MAIN_STATS);
ffa88f37 2749 }
6fcd2735 2750 last_i += NUM_MAIN_STATS;
ffa88f37 2751
3da8a36c 2752 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PORT_STATS);
6fcd2735 2753 last_i += NUM_PORT_STATS;
ffa88f37 2754
0b131561
MB		 2755 mlx4_en_update_pfc_stats_bitmap(dev, stats_bitmap,
2756 rx_ppp, rx_pause,
2757 tx_ppp, tx_pause);
2758 last_i += NUM_FLOW_STATS;
2759
6fcd2735 2760 if (!mlx4_is_slave(dev))
3da8a36c 2761 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PKT_STATS);
ffa88f37
EBE		 2762}
2763
c27a02cd
YP		 2764int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
2765 struct mlx4_en_port_profile *prof)
2766{
2767 struct net_device *dev;
2768 struct mlx4_en_priv *priv;
c07cb4b0 2769 int i;
c27a02cd 2770 int err;
ef96f7d4 2771 u64 mac_u64;
c27a02cd 2772
f1593d22 2773 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 2774 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 2775 if (dev == NULL)
c27a02cd 2776 return -ENOMEM;
c27a02cd 2777
d317966b
AV		 2778 netif_set_real_num_tx_queues(dev, prof->tx_ring_num);
2779 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
2780
872bf2fb 2781 SET_NETDEV_DEV(dev, &mdev->dev->persist->pdev->dev);
76a066f2 2782 dev->dev_port = port - 1;
c27a02cd
YP		 2783
2784 /*
2785 * Initialize driver private data
2786 */
2787
2788 priv = netdev_priv(dev);
2789 memset(priv, 0, sizeof(struct mlx4_en_priv));
207af6c5
EE		 2790 spin_lock_init(&priv->stats_lock);
2791 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
2792 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
2793 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
2794 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
2795 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
2796#ifdef CONFIG_MLX4_EN_VXLAN
2797 INIT_WORK(&priv->vxlan_add_task, mlx4_en_add_vxlan_offloads);
2798 INIT_WORK(&priv->vxlan_del_task, mlx4_en_del_vxlan_offloads);
2799#endif
2800#ifdef CONFIG_RFS_ACCEL
2801 INIT_LIST_HEAD(&priv->filters);
2802 spin_lock_init(&priv->filters_lock);
2803#endif
2804
c27a02cd
YP		 2805 priv->dev = dev;
2806 priv->mdev = mdev;
ebf8c9aa 2807 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP		 2808 priv->prof = prof;
2809 priv->port = port;
2810 priv->port_up = false;
c27a02cd 2811 priv->flags = prof->flags;
0fef9d03 2812 priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME;
60d6fe99
AV		 2813 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
2814 MLX4_WQE_CTRL_SOLICITED);
d317966b 2815 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
c27a02cd 2816 priv->tx_ring_num = prof->tx_ring_num;
fbc6daf1 2817 priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK;
bd635c35 2818 netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key));
d317966b 2819
41d942d5 2820 priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS,
d317966b 2821 GFP_KERNEL);
bc6a4744
AV		 2822 if (!priv->tx_ring) {
2823 err = -ENOMEM;
2824 goto out;
2825 }
41d942d5 2826 priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS,
d317966b 2827 GFP_KERNEL);
bc6a4744
AV		 2828 if (!priv->tx_cq) {
2829 err = -ENOMEM;
2830 goto out;
2831 }
c27a02cd 2832 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 2833 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
b1b6b4da 2834 priv->cqe_size = mdev->dev->caps.cqe_size;
c27a02cd
YP		 2835 priv->mac_index = -1;
2836 priv->msg_enable = MLX4_EN_MSG_LEVEL;
564c274c 2837#ifdef CONFIG_MLX4_EN_DCB
540b3a39 2838 if (!mlx4_is_slave(priv->mdev->dev)) {
3742cc65 2839 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) {
540b3a39
OG		 2840 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
2841 } else {
2842 en_info(priv, "enabling only PFC DCB ops\n");
2843 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
2844 }
2845 }
564c274c 2846#endif
c27a02cd 2847
c07cb4b0
YB		 2848 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
2849 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 2850
c27a02cd
YP		 2851 /* Query for default mac and max mtu */
2852 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99 2853
f8c6455b
SM		 2854 if (mdev->dev->caps.rx_checksum_flags_port[priv->port] &
2855 MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP)
2856 priv->flags |= MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP;
2857
6bbb6d99
YB		 2858 /* Set default MAC */
2859 dev->addr_len = ETH_ALEN;
2860 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
2861 if (!is_valid_ether_addr(dev->dev_addr)) {
ef96f7d4
OG		 2862 if (mlx4_is_slave(priv->mdev->dev)) {
2863 eth_hw_addr_random(dev);
2864 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
9813337a 2865 mac_u64 = mlx4_mac_to_u64(dev->dev_addr);
ef96f7d4
OG		 2866 mdev->dev->caps.def_mac[priv->port] = mac_u64;
2867 } else {
2868 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
2869 priv->port, dev->dev_addr);
2870 err = -EINVAL;
2871 goto out;
2872 }
c27a02cd
YP		 2873 }
2874
2695bab2 2875 memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac));
6bbb6d99 2876
c27a02cd
YP		 2877 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2878 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2879 err = mlx4_en_alloc_resources(priv);
2880 if (err)
2881 goto out;
2882
ec693d47
AV		 2883 /* Initialize time stamping config */
2884 priv->hwtstamp_config.flags = 0;
2885 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
2886 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2887
c27a02cd
YP		 2888 /* Allocate page for receive rings */
2889 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
2890 MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE);
2891 if (err) {
453a6082 2892 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP		 2893 goto out;
2894 }
2895 priv->allocated = 1;
2896
c27a02cd
YP		 2897 /*
2898 * Initialize netdev entry points
2899 */
8f7ba3ca
RE		 2900 if (mlx4_is_master(priv->mdev->dev))
2901 dev->netdev_ops = &mlx4_netdev_ops_master;
2902 else
2903 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 2904 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
1eb63a28
BH		 2905 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
2906 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 2907
7ad24ea4 2908 dev->ethtool_ops = &mlx4_en_ethtool_ops;
c27a02cd 2909
c27a02cd
YP		 2910 /*
2911 * Set driver features
2912 */
c8c64cff
MM		 2913 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2914 if (mdev->LSO_support)
2915 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
2916
2917 dev->vlan_features = dev->hw_features;
2918
ad86107f 2919 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 2920 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM		 2921 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2922 NETIF_F_HW_VLAN_CTAG_FILTER;
537f6f95
SM		 2923 dev->hw_features |= NETIF_F_LOOPBACK |
2924 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c27a02cd 2925
f0df3503
MM		 2926 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
2927 dev->hw_features |= NETIF_F_RXFCS;
2928
78500b8c
MM		 2929 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)
2930 dev->hw_features |= NETIF_F_RXALL;
2931
1eb8c695 2932 if (mdev->dev->caps.steering_mode ==
7d077cd3
MB		 2933 MLX4_STEERING_MODE_DEVICE_MANAGED &&
2934 mdev->dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
1eb8c695
AV		 2935 dev->hw_features |= NETIF_F_NTUPLE;
2936
cc5387f7
YB		 2937 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
2938 dev->priv_flags |= IFF_UNICAST_FLT;
2939
947cbb0a
EP		 2940 /* Setting a default hash function value */
2941 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) {
2942 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
2943 } else if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR) {
2944 priv->rss_hash_fn = ETH_RSS_HASH_XOR;
2945 } else {
2946 en_warn(priv,
2947 "No RSS hash capabilities exposed, using Toeplitz\n");
2948 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
2949 }
2950
c27a02cd 2951 mdev->pndev[port] = dev;
5da03547 2952 mdev->upper[port] = NULL;
c27a02cd
YP		 2953
2954 netif_carrier_off(dev);
4801ae70
EE		 2955 mlx4_en_set_default_moderation(priv);
2956
453a6082
YP		 2957 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num);
2958 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
2959
79aeaccd
YB		 2960 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
2961
90822265 2962 /* Configure port */
5c8e9046 2963 mlx4_en_calc_rx_buf(dev);
90822265 2964 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP		 2965 priv->rx_skb_size + ETH_FCS_LEN,
2966 prof->tx_pause, prof->tx_ppp,
2967 prof->rx_pause, prof->rx_ppp);
90822265 2968 if (err) {
1a91de28
JP		 2969 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
2970 priv->port, err);
90822265
YP		 2971 goto out;
2972 }
2973
837052d0 2974 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 2975 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 2976 if (err) {
2977 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
2978 err);
2979 goto out;
2980 }
2981 }
2982
90822265
YP		 2983 /* Init port */
2984 en_warn(priv, "Initializing port\n");
2985 err = mlx4_INIT_PORT(mdev->dev, priv->port);
2986 if (err) {
2987 en_err(priv, "Failed Initializing port\n");
2988 goto out;
2989 }
c27a02cd 2990 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea
AV		 2991
2992 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2993 queue_delayed_work(mdev->workqueue, &priv->service_task,
2994 SERVICE_TASK_DELAY);
2995
0b131561
MB		 2996 mlx4_en_set_stats_bitmap(mdev->dev, &priv->stats_bitmap,
2997 mdev->profile.prof[priv->port].rx_ppp,
2998 mdev->profile.prof[priv->port].rx_pause,
2999 mdev->profile.prof[priv->port].tx_ppp,
3000 mdev->profile.prof[priv->port].tx_pause);
39de961a 3001
e5eda89d
IS		 3002 err = register_netdev(dev);
3003 if (err) {
3004 en_err(priv, "Netdev registration failed for port %d\n", port);
3005 goto out;
3006 }
3007
3008 priv->registered = 1;
3009
c27a02cd
YP		 3010 return 0;
3011
3012out:
3013 mlx4_en_destroy_netdev(dev);
3014 return err;
3015}
3016
537f6f95
SM		 3017int mlx4_en_reset_config(struct net_device *dev,
3018 struct hwtstamp_config ts_config,
3019 netdev_features_t features)
3020{
3021 struct mlx4_en_priv *priv = netdev_priv(dev);
3022 struct mlx4_en_dev *mdev = priv->mdev;
3023 int port_up = 0;
3024 int err = 0;
3025
3026 if (priv->hwtstamp_config.tx_type == ts_config.tx_type &&
3027 priv->hwtstamp_config.rx_filter == ts_config.rx_filter &&
f0df3503
MM		 3028 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3029 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS))
537f6f95
SM		 3030 return 0; /* Nothing to change */
3031
3032 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3033 (features & NETIF_F_HW_VLAN_CTAG_RX) &&
3034 (priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE)) {
3035 en_warn(priv, "Can't turn ON rx vlan offload while time-stamping rx filter is ON\n");
3036 return -EINVAL;
3037 }
3038
3039 mutex_lock(&mdev->state_lock);
3040 if (priv->port_up) {
3041 port_up = 1;
3042 mlx4_en_stop_port(dev, 1);
3043 }
3044
3045 mlx4_en_free_resources(priv);
3046
3047 en_warn(priv, "Changing device configuration rx filter(%x) rx vlan(%x)\n",
3048 ts_config.rx_filter, !!(features & NETIF_F_HW_VLAN_CTAG_RX));
3049
3050 priv->hwtstamp_config.tx_type = ts_config.tx_type;
3051 priv->hwtstamp_config.rx_filter = ts_config.rx_filter;
3052
3053 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
3054 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3055 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3056 else
3057 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3058 } else if (ts_config.rx_filter == HWTSTAMP_FILTER_NONE) {
3059 /* RX time-stamping is OFF, update the RX vlan offload
3060 * to the latest wanted state
3061 */
3062 if (dev->wanted_features & NETIF_F_HW_VLAN_CTAG_RX)
3063 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3064 else
3065 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3066 }
3067
f0df3503
MM		 3068 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS)) {
3069 if (features & NETIF_F_RXFCS)
3070 dev->features |= NETIF_F_RXFCS;
3071 else
3072 dev->features &= ~NETIF_F_RXFCS;
3073 }
3074
537f6f95
SM		 3075 /* RX vlan offload and RX time-stamping can't co-exist !
3076 * Regardless of the caller's choice,
3077 * Turn Off RX vlan offload in case of time-stamping is ON
3078 */
3079 if (ts_config.rx_filter != HWTSTAMP_FILTER_NONE) {
3080 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
3081 en_warn(priv, "Turning off RX vlan offload since RX time-stamping is ON\n");
3082 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3083 }
3084
3085 err = mlx4_en_alloc_resources(priv);
3086 if (err) {
3087 en_err(priv, "Failed reallocating port resources\n");
3088 goto out;
3089 }
3090 if (port_up) {
3091 err = mlx4_en_start_port(dev);
3092 if (err)
3093 en_err(priv, "Failed starting port\n");
3094 }
3095
3096out:
3097 mutex_unlock(&mdev->state_lock);
3098 netdev_features_change(dev);
3099 return err;
3100}
Linux 6.x block layer and io_uring tree(s)