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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
434c5e39 | 4 | Copyright(c) 1999 - 2013 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #ifndef _IXGBE_H_ | |
30 | #define _IXGBE_H_ | |
31 | ||
f62bbb5e | 32 | #include <linux/bitops.h> |
9a799d71 AK |
33 | #include <linux/types.h> |
34 | #include <linux/pci.h> | |
35 | #include <linux/netdevice.h> | |
b25ebfd2 | 36 | #include <linux/cpumask.h> |
6fabd715 | 37 | #include <linux/aer.h> |
f62bbb5e | 38 | #include <linux/if_vlan.h> |
6cb562d6 | 39 | #include <linux/jiffies.h> |
9a799d71 | 40 | |
74d23cc7 | 41 | #include <linux/timecounter.h> |
3a6a4eda JK |
42 | #include <linux/net_tstamp.h> |
43 | #include <linux/ptp_clock_kernel.h> | |
3a6a4eda | 44 | |
9a799d71 AK |
45 | #include "ixgbe_type.h" |
46 | #include "ixgbe_common.h" | |
2f90b865 | 47 | #include "ixgbe_dcb.h" |
eacd73f7 YZ |
48 | #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) |
49 | #define IXGBE_FCOE | |
50 | #include "ixgbe_fcoe.h" | |
51 | #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ | |
5dd2d332 | 52 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
53 | #include <linux/dca.h> |
54 | #endif | |
9a799d71 | 55 | |
076bb0c8 | 56 | #include <net/busy_poll.h> |
5a85e737 | 57 | |
e0d1095a | 58 | #ifdef CONFIG_NET_RX_BUSY_POLL |
b4640030 | 59 | #define BP_EXTENDED_STATS |
7e15b90f | 60 | #endif |
849c4542 ET |
61 | /* common prefix used by pr_<> macros */ |
62 | #undef pr_fmt | |
63 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9a799d71 AK |
64 | |
65 | /* TX/RX descriptor defines */ | |
6bacb300 | 66 | #define IXGBE_DEFAULT_TXD 512 |
59224555 | 67 | #define IXGBE_DEFAULT_TX_WORK 256 |
9a799d71 AK |
68 | #define IXGBE_MAX_TXD 4096 |
69 | #define IXGBE_MIN_TXD 64 | |
70 | ||
fb44519d | 71 | #if (PAGE_SIZE < 8192) |
6bacb300 | 72 | #define IXGBE_DEFAULT_RXD 512 |
fb44519d AB |
73 | #else |
74 | #define IXGBE_DEFAULT_RXD 128 | |
75 | #endif | |
9a799d71 AK |
76 | #define IXGBE_MAX_RXD 4096 |
77 | #define IXGBE_MIN_RXD 64 | |
78 | ||
5b7f000f DS |
79 | #define IXGBE_ETH_P_LLDP 0x88CC |
80 | ||
9a799d71 | 81 | /* flow control */ |
2b9ade93 | 82 | #define IXGBE_MIN_FCRTL 0x40 |
9a799d71 | 83 | #define IXGBE_MAX_FCRTL 0x7FF80 |
2b9ade93 | 84 | #define IXGBE_MIN_FCRTH 0x600 |
9a799d71 | 85 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
2b9ade93 | 86 | #define IXGBE_DEFAULT_FCPAUSE 0xFFFF |
9a799d71 AK |
87 | #define IXGBE_MIN_FCPAUSE 0 |
88 | #define IXGBE_MAX_FCPAUSE 0xFFFF | |
89 | ||
90 | /* Supported Rx Buffer Sizes */ | |
252562c2 | 91 | #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ |
09816fbe AD |
92 | #define IXGBE_RXBUFFER_2K 2048 |
93 | #define IXGBE_RXBUFFER_3K 3072 | |
94 | #define IXGBE_RXBUFFER_4K 4096 | |
919e78a6 | 95 | #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ |
9a799d71 | 96 | |
13958070 | 97 | /* |
252562c2 AD |
98 | * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we |
99 | * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, | |
100 | * this adds up to 448 bytes of extra data. | |
101 | * | |
102 | * Since netdev_alloc_skb now allocates a page fragment we can use a value | |
103 | * of 256 and the resultant skb will have a truesize of 960 or less. | |
13958070 | 104 | */ |
252562c2 | 105 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 |
9a799d71 | 106 | |
9a799d71 AK |
107 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
108 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
109 | ||
472148c3 AD |
110 | enum ixgbe_tx_flags { |
111 | /* cmd_type flags */ | |
112 | IXGBE_TX_FLAGS_HW_VLAN = 0x01, | |
113 | IXGBE_TX_FLAGS_TSO = 0x02, | |
114 | IXGBE_TX_FLAGS_TSTAMP = 0x04, | |
115 | ||
116 | /* olinfo flags */ | |
117 | IXGBE_TX_FLAGS_CC = 0x08, | |
118 | IXGBE_TX_FLAGS_IPV4 = 0x10, | |
119 | IXGBE_TX_FLAGS_CSUM = 0x20, | |
120 | ||
121 | /* software defined flags */ | |
122 | IXGBE_TX_FLAGS_SW_VLAN = 0x40, | |
123 | IXGBE_TX_FLAGS_FCOE = 0x80, | |
124 | }; | |
125 | ||
126 | /* VLAN info */ | |
9a799d71 | 127 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
66f32a8b AD |
128 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 |
129 | #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 | |
9a799d71 AK |
130 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
131 | ||
7f870475 GR |
132 | #define IXGBE_MAX_VF_MC_ENTRIES 30 |
133 | #define IXGBE_MAX_VF_FUNCTIONS 64 | |
134 | #define IXGBE_MAX_VFTA_ENTRIES 128 | |
135 | #define MAX_EMULATION_MAC_ADDRS 16 | |
a1cbb15c | 136 | #define IXGBE_MAX_PF_MACVLANS 15 |
1d9c0bfd | 137 | #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) |
83c61fa9 GR |
138 | #define IXGBE_82599_VF_DEVICE_ID 0x10ED |
139 | #define IXGBE_X540_VF_DEVICE_ID 0x1515 | |
7f870475 GR |
140 | |
141 | struct vf_data_storage { | |
988d1307 | 142 | struct pci_dev *vfdev; |
7f870475 GR |
143 | unsigned char vf_mac_addresses[ETH_ALEN]; |
144 | u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
145 | u16 num_vf_mc_hashes; | |
146 | u16 default_vf_vlan_id; | |
147 | u16 vlans_enabled; | |
7f870475 | 148 | bool clear_to_send; |
7f01648a | 149 | bool pf_set_mac; |
7f01648a GR |
150 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
151 | u16 pf_qos; | |
ff4ab206 | 152 | u16 tx_rate; |
de4c7f65 GR |
153 | u16 vlan_count; |
154 | u8 spoofchk_enabled; | |
e65ce0d3 | 155 | bool rss_query_enabled; |
54011e4d | 156 | u8 trusted; |
8443c1a4 | 157 | int xcast_mode; |
374c65d6 | 158 | unsigned int vf_api; |
7f870475 GR |
159 | }; |
160 | ||
8443c1a4 HS |
161 | enum ixgbevf_xcast_modes { |
162 | IXGBEVF_XCAST_MODE_NONE = 0, | |
163 | IXGBEVF_XCAST_MODE_MULTI, | |
164 | IXGBEVF_XCAST_MODE_ALLMULTI, | |
165 | }; | |
166 | ||
a1cbb15c GR |
167 | struct vf_macvlans { |
168 | struct list_head l; | |
169 | int vf; | |
a1cbb15c GR |
170 | bool free; |
171 | bool is_macvlan; | |
172 | u8 vf_macvlan[ETH_ALEN]; | |
173 | }; | |
174 | ||
a535c30e AD |
175 | #define IXGBE_MAX_TXD_PWR 14 |
176 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
177 | ||
178 | /* Tx Descriptors needed, worst case */ | |
179 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) | |
990a3158 | 180 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
a535c30e | 181 | |
9a799d71 AK |
182 | /* wrapper around a pointer to a socket buffer, |
183 | * so a DMA handle can be stored along with the buffer */ | |
184 | struct ixgbe_tx_buffer { | |
d3d00239 | 185 | union ixgbe_adv_tx_desc *next_to_watch; |
9a799d71 | 186 | unsigned long time_stamp; |
fd0db0ed AD |
187 | struct sk_buff *skb; |
188 | unsigned int bytecount; | |
189 | unsigned short gso_segs; | |
244e27ad | 190 | __be16 protocol; |
729739b7 AD |
191 | DEFINE_DMA_UNMAP_ADDR(dma); |
192 | DEFINE_DMA_UNMAP_LEN(len); | |
d3d00239 | 193 | u32 tx_flags; |
9a799d71 AK |
194 | }; |
195 | ||
196 | struct ixgbe_rx_buffer { | |
197 | struct sk_buff *skb; | |
198 | dma_addr_t dma; | |
199 | struct page *page; | |
762f4c57 | 200 | unsigned int page_offset; |
9a799d71 AK |
201 | }; |
202 | ||
203 | struct ixgbe_queue_stats { | |
204 | u64 packets; | |
205 | u64 bytes; | |
b4640030 | 206 | #ifdef BP_EXTENDED_STATS |
7e15b90f ET |
207 | u64 yields; |
208 | u64 misses; | |
209 | u64 cleaned; | |
b4640030 | 210 | #endif /* BP_EXTENDED_STATS */ |
9a799d71 AK |
211 | }; |
212 | ||
5b7da515 AD |
213 | struct ixgbe_tx_queue_stats { |
214 | u64 restart_queue; | |
215 | u64 tx_busy; | |
c84d324c | 216 | u64 tx_done_old; |
5b7da515 AD |
217 | }; |
218 | ||
219 | struct ixgbe_rx_queue_stats { | |
220 | u64 rsc_count; | |
221 | u64 rsc_flush; | |
222 | u64 non_eop_descs; | |
223 | u64 alloc_rx_page_failed; | |
224 | u64 alloc_rx_buff_failed; | |
8a0da21b | 225 | u64 csum_err; |
5b7da515 AD |
226 | }; |
227 | ||
a9763f3c MR |
228 | #define IXGBE_TS_HDR_LEN 8 |
229 | ||
f800326d | 230 | enum ixgbe_ring_state_t { |
7d637bcc | 231 | __IXGBE_TX_FDIR_INIT_DONE, |
fd786b7b | 232 | __IXGBE_TX_XPS_INIT_DONE, |
7d637bcc | 233 | __IXGBE_TX_DETECT_HANG, |
c84d324c | 234 | __IXGBE_HANG_CHECK_ARMED, |
7d637bcc | 235 | __IXGBE_RX_RSC_ENABLED, |
8a0da21b | 236 | __IXGBE_RX_CSUM_UDP_ZERO_ERR, |
57efd44c | 237 | __IXGBE_RX_FCOE, |
7d637bcc AD |
238 | }; |
239 | ||
2a47fa45 JF |
240 | struct ixgbe_fwd_adapter { |
241 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
242 | struct net_device *netdev; | |
243 | struct ixgbe_adapter *real_adapter; | |
244 | unsigned int tx_base_queue; | |
245 | unsigned int rx_base_queue; | |
246 | int pool; | |
247 | }; | |
248 | ||
7d637bcc AD |
249 | #define check_for_tx_hang(ring) \ |
250 | test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
251 | #define set_check_for_tx_hang(ring) \ | |
252 | set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
253 | #define clear_check_for_tx_hang(ring) \ | |
254 | clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
255 | #define ring_is_rsc_enabled(ring) \ | |
256 | test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
257 | #define set_ring_rsc_enabled(ring) \ | |
258 | set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
259 | #define clear_ring_rsc_enabled(ring) \ | |
260 | clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
9a799d71 | 261 | struct ixgbe_ring { |
efe3d3c8 | 262 | struct ixgbe_ring *next; /* pointer to next ring in q_vector */ |
d3ee4294 AD |
263 | struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ |
264 | struct net_device *netdev; /* netdev ring belongs to */ | |
265 | struct device *dev; /* device for DMA mapping */ | |
2a47fa45 | 266 | struct ixgbe_fwd_adapter *l2_accel_priv; |
9a799d71 | 267 | void *desc; /* descriptor ring memory */ |
9a799d71 AK |
268 | union { |
269 | struct ixgbe_tx_buffer *tx_buffer_info; | |
270 | struct ixgbe_rx_buffer *rx_buffer_info; | |
271 | }; | |
7d637bcc | 272 | unsigned long state; |
bd198058 | 273 | u8 __iomem *tail; |
d3ee4294 AD |
274 | dma_addr_t dma; /* phys. address of descriptor ring */ |
275 | unsigned int size; /* length in bytes */ | |
bd198058 | 276 | |
ae540af1 | 277 | u16 count; /* amount of descriptors */ |
ae540af1 JB |
278 | |
279 | u8 queue_index; /* needed for multiqueue queue management */ | |
7d637bcc AD |
280 | u8 reg_idx; /* holds the special value that gets |
281 | * the hardware register offset | |
282 | * associated with this ring, which is | |
283 | * different for DCB and RSS modes | |
284 | */ | |
d3ee4294 AD |
285 | u16 next_to_use; |
286 | u16 next_to_clean; | |
287 | ||
a9763f3c MR |
288 | unsigned long last_rx_timestamp; |
289 | ||
f800326d | 290 | union { |
d3ee4294 | 291 | u16 next_to_alloc; |
f800326d AD |
292 | struct { |
293 | u8 atr_sample_rate; | |
294 | u8 atr_count; | |
295 | }; | |
f800326d | 296 | }; |
9a799d71 | 297 | |
bd198058 | 298 | u8 dcb_tc; |
9a799d71 | 299 | struct ixgbe_queue_stats stats; |
de1036b1 | 300 | struct u64_stats_sync syncp; |
5b7da515 AD |
301 | union { |
302 | struct ixgbe_tx_queue_stats tx_stats; | |
303 | struct ixgbe_rx_queue_stats rx_stats; | |
304 | }; | |
7ca3bc58 | 305 | } ____cacheline_internodealigned_in_smp; |
9a799d71 | 306 | |
c7e4358a SN |
307 | enum ixgbe_ring_f_enum { |
308 | RING_F_NONE = 0, | |
7f870475 | 309 | RING_F_VMDQ, /* SR-IOV uses the same ring feature */ |
c7e4358a | 310 | RING_F_RSS, |
c4cf55e5 | 311 | RING_F_FDIR, |
0331a832 YZ |
312 | #ifdef IXGBE_FCOE |
313 | RING_F_FCOE, | |
314 | #endif /* IXGBE_FCOE */ | |
c7e4358a SN |
315 | |
316 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
317 | }; | |
318 | ||
0f9b232b | 319 | #define IXGBE_MAX_RSS_INDICES 16 |
e9ee3238 | 320 | #define IXGBE_MAX_RSS_INDICES_X550 63 |
0f9b232b DS |
321 | #define IXGBE_MAX_VMDQ_INDICES 64 |
322 | #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ | |
323 | #define IXGBE_MAX_FCOE_INDICES 8 | |
324 | #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) | |
325 | #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) | |
326 | #define IXGBE_MAX_L2A_QUEUES 4 | |
327 | #define IXGBE_BAD_L2A_QUEUE 3 | |
328 | #define IXGBE_MAX_MACVLANS 31 | |
329 | #define IXGBE_MAX_DCBMACVLANS 8 | |
2a47fa45 | 330 | |
021230d4 | 331 | struct ixgbe_ring_feature { |
c087663e AD |
332 | u16 limit; /* upper limit on feature indices */ |
333 | u16 indices; /* current value of indices */ | |
e4b317e9 AD |
334 | u16 mask; /* Mask used for feature to ring mapping */ |
335 | u16 offset; /* offset to start of feature */ | |
7ca3bc58 | 336 | } ____cacheline_internodealigned_in_smp; |
021230d4 | 337 | |
73079ea0 AD |
338 | #define IXGBE_82599_VMDQ_8Q_MASK 0x78 |
339 | #define IXGBE_82599_VMDQ_4Q_MASK 0x7C | |
340 | #define IXGBE_82599_VMDQ_2Q_MASK 0x7E | |
341 | ||
f800326d AD |
342 | /* |
343 | * FCoE requires that all Rx buffers be over 2200 bytes in length. Since | |
344 | * this is twice the size of a half page we need to double the page order | |
345 | * for FCoE enabled Rx queues. | |
346 | */ | |
09816fbe | 347 | static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) |
f800326d | 348 | { |
09816fbe AD |
349 | #ifdef IXGBE_FCOE |
350 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
351 | return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : | |
352 | IXGBE_RXBUFFER_3K; | |
353 | #endif | |
354 | return IXGBE_RXBUFFER_2K; | |
f800326d | 355 | } |
09816fbe AD |
356 | |
357 | static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) | |
358 | { | |
359 | #ifdef IXGBE_FCOE | |
360 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
361 | return (PAGE_SIZE < 8192) ? 1 : 0; | |
f800326d | 362 | #endif |
09816fbe AD |
363 | return 0; |
364 | } | |
f800326d | 365 | #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) |
f800326d | 366 | |
08c8833b | 367 | struct ixgbe_ring_container { |
efe3d3c8 | 368 | struct ixgbe_ring *ring; /* pointer to linked list of rings */ |
bd198058 AD |
369 | unsigned int total_bytes; /* total bytes processed this int */ |
370 | unsigned int total_packets; /* total packets processed this int */ | |
371 | u16 work_limit; /* total work allowed per interrupt */ | |
08c8833b AD |
372 | u8 count; /* total number of rings in vector */ |
373 | u8 itr; /* current ITR setting for ring */ | |
374 | }; | |
021230d4 | 375 | |
a557928e AD |
376 | /* iterator for handling rings in ring container */ |
377 | #define ixgbe_for_each_ring(pos, head) \ | |
378 | for (pos = (head).ring; pos != NULL; pos = pos->next) | |
379 | ||
2f90b865 | 380 | #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ |
e7cf745b | 381 | ? 8 : 1) |
2f90b865 AD |
382 | #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS |
383 | ||
49c7ffbe | 384 | /* MAX_Q_VECTORS of these are allocated, |
021230d4 AV |
385 | * but we only use one per queue-specific vector. |
386 | */ | |
387 | struct ixgbe_q_vector { | |
388 | struct ixgbe_adapter *adapter; | |
33cf09c9 AD |
389 | #ifdef CONFIG_IXGBE_DCA |
390 | int cpu; /* CPU for DCA */ | |
391 | #endif | |
d5bf4f67 ET |
392 | u16 v_idx; /* index of q_vector within array, also used for |
393 | * finding the bit in EICR and friends that | |
394 | * represents the vector for this ring */ | |
395 | u16 itr; /* Interrupt throttle rate written to EITR */ | |
08c8833b | 396 | struct ixgbe_ring_container rx, tx; |
d5bf4f67 ET |
397 | |
398 | struct napi_struct napi; | |
de88eeeb AD |
399 | cpumask_t affinity_mask; |
400 | int numa_node; | |
401 | struct rcu_head rcu; /* to avoid race with update stats on free */ | |
d0759ebb | 402 | char name[IFNAMSIZ + 9]; |
de88eeeb | 403 | |
e0d1095a | 404 | #ifdef CONFIG_NET_RX_BUSY_POLL |
adc81090 | 405 | atomic_t state; |
e0d1095a | 406 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 407 | |
de88eeeb AD |
408 | /* for dynamic allocation of rings associated with this q_vector */ |
409 | struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; | |
021230d4 | 410 | }; |
adc81090 | 411 | |
e0d1095a | 412 | #ifdef CONFIG_NET_RX_BUSY_POLL |
adc81090 AD |
413 | enum ixgbe_qv_state_t { |
414 | IXGBE_QV_STATE_IDLE = 0, | |
415 | IXGBE_QV_STATE_NAPI, | |
416 | IXGBE_QV_STATE_POLL, | |
417 | IXGBE_QV_STATE_DISABLE | |
418 | }; | |
419 | ||
5a85e737 ET |
420 | static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) |
421 | { | |
adc81090 AD |
422 | /* reset state to idle */ |
423 | atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); | |
5a85e737 ET |
424 | } |
425 | ||
426 | /* called from the device poll routine to get ownership of a q_vector */ | |
427 | static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) | |
428 | { | |
adc81090 AD |
429 | int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, |
430 | IXGBE_QV_STATE_NAPI); | |
b4640030 | 431 | #ifdef BP_EXTENDED_STATS |
adc81090 | 432 | if (rc != IXGBE_QV_STATE_IDLE) |
7e15b90f ET |
433 | q_vector->tx.ring->stats.yields++; |
434 | #endif | |
adc81090 AD |
435 | |
436 | return rc == IXGBE_QV_STATE_IDLE; | |
5a85e737 ET |
437 | } |
438 | ||
439 | /* returns true is someone tried to get the qv while napi had it */ | |
adc81090 | 440 | static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) |
5a85e737 | 441 | { |
adc81090 AD |
442 | WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI); |
443 | ||
444 | /* flush any outstanding Rx frames */ | |
445 | if (q_vector->napi.gro_list) | |
446 | napi_gro_flush(&q_vector->napi, false); | |
447 | ||
448 | /* reset state to idle */ | |
449 | atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); | |
5a85e737 ET |
450 | } |
451 | ||
452 | /* called from ixgbe_low_latency_poll() */ | |
453 | static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) | |
454 | { | |
adc81090 AD |
455 | int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, |
456 | IXGBE_QV_STATE_POLL); | |
b4640030 | 457 | #ifdef BP_EXTENDED_STATS |
adc81090 AD |
458 | if (rc != IXGBE_QV_STATE_IDLE) |
459 | q_vector->tx.ring->stats.yields++; | |
7e15b90f | 460 | #endif |
adc81090 | 461 | return rc == IXGBE_QV_STATE_IDLE; |
5a85e737 ET |
462 | } |
463 | ||
464 | /* returns true if someone tried to get the qv while it was locked */ | |
adc81090 | 465 | static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) |
5a85e737 | 466 | { |
adc81090 AD |
467 | WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL); |
468 | ||
469 | /* reset state to idle */ | |
470 | atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); | |
5a85e737 ET |
471 | } |
472 | ||
473 | /* true if a socket is polling, even if it did not get the lock */ | |
b4640030 | 474 | static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) |
5a85e737 | 475 | { |
adc81090 | 476 | return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL; |
5a85e737 | 477 | } |
27d9ce4f JK |
478 | |
479 | /* false if QV is currently owned */ | |
480 | static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) | |
481 | { | |
adc81090 AD |
482 | int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, |
483 | IXGBE_QV_STATE_DISABLE); | |
484 | ||
485 | return rc == IXGBE_QV_STATE_IDLE; | |
27d9ce4f JK |
486 | } |
487 | ||
e0d1095a | 488 | #else /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 ET |
489 | static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) |
490 | { | |
491 | } | |
492 | ||
493 | static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) | |
494 | { | |
495 | return true; | |
496 | } | |
497 | ||
498 | static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) | |
499 | { | |
500 | return false; | |
501 | } | |
502 | ||
503 | static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) | |
504 | { | |
505 | return false; | |
506 | } | |
507 | ||
508 | static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) | |
509 | { | |
510 | return false; | |
511 | } | |
512 | ||
b4640030 | 513 | static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) |
5a85e737 ET |
514 | { |
515 | return false; | |
516 | } | |
27d9ce4f JK |
517 | |
518 | static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) | |
519 | { | |
520 | return true; | |
521 | } | |
522 | ||
e0d1095a | 523 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 524 | |
3ca8bc6d DS |
525 | #ifdef CONFIG_IXGBE_HWMON |
526 | ||
527 | #define IXGBE_HWMON_TYPE_LOC 0 | |
528 | #define IXGBE_HWMON_TYPE_TEMP 1 | |
529 | #define IXGBE_HWMON_TYPE_CAUTION 2 | |
530 | #define IXGBE_HWMON_TYPE_MAX 3 | |
531 | ||
532 | struct hwmon_attr { | |
533 | struct device_attribute dev_attr; | |
534 | struct ixgbe_hw *hw; | |
535 | struct ixgbe_thermal_diode_data *sensor; | |
536 | char name[12]; | |
537 | }; | |
538 | ||
539 | struct hwmon_buff { | |
03b77d81 GR |
540 | struct attribute_group group; |
541 | const struct attribute_group *groups[2]; | |
542 | struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; | |
543 | struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; | |
3ca8bc6d DS |
544 | unsigned int n_hwmon; |
545 | }; | |
546 | #endif /* CONFIG_IXGBE_HWMON */ | |
021230d4 | 547 | |
d5bf4f67 ET |
548 | /* |
549 | * microsecond values for various ITR rates shifted by 2 to fit itr register | |
550 | * with the first 3 bits reserved 0 | |
9a799d71 | 551 | */ |
d5bf4f67 ET |
552 | #define IXGBE_MIN_RSC_ITR 24 |
553 | #define IXGBE_100K_ITR 40 | |
554 | #define IXGBE_20K_ITR 200 | |
8ac34f10 | 555 | #define IXGBE_12K_ITR 336 |
9a799d71 | 556 | |
f56e0cb1 AD |
557 | /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ |
558 | static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, | |
559 | const u32 stat_err_bits) | |
560 | { | |
561 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); | |
562 | } | |
563 | ||
7d4987de AD |
564 | static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) |
565 | { | |
566 | u16 ntc = ring->next_to_clean; | |
567 | u16 ntu = ring->next_to_use; | |
568 | ||
569 | return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; | |
570 | } | |
9a799d71 | 571 | |
e4f74028 | 572 | #define IXGBE_RX_DESC(R, i) \ |
31f05a2d | 573 | (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) |
e4f74028 | 574 | #define IXGBE_TX_DESC(R, i) \ |
31f05a2d | 575 | (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) |
e4f74028 | 576 | #define IXGBE_TX_CTXTDESC(R, i) \ |
31f05a2d | 577 | (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) |
9a799d71 | 578 | |
c88887e0 | 579 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ |
63f39bd1 YZ |
580 | #ifdef IXGBE_FCOE |
581 | /* Use 3K as the baby jumbo frame size for FCoE */ | |
582 | #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 | |
583 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 584 | |
021230d4 AV |
585 | #define OTHER_VECTOR 1 |
586 | #define NON_Q_VECTORS (OTHER_VECTOR) | |
587 | ||
e8e26350 | 588 | #define MAX_MSIX_VECTORS_82599 64 |
49c7ffbe | 589 | #define MAX_Q_VECTORS_82599 64 |
eb7f139c | 590 | #define MAX_MSIX_VECTORS_82598 18 |
49c7ffbe | 591 | #define MAX_Q_VECTORS_82598 16 |
eb7f139c | 592 | |
5d7daa35 JK |
593 | struct ixgbe_mac_addr { |
594 | u8 addr[ETH_ALEN]; | |
c9f53e63 | 595 | u16 pool; |
5d7daa35 JK |
596 | u16 state; /* bitmask */ |
597 | }; | |
c9f53e63 | 598 | |
5d7daa35 JK |
599 | #define IXGBE_MAC_STATE_DEFAULT 0x1 |
600 | #define IXGBE_MAC_STATE_MODIFIED 0x2 | |
601 | #define IXGBE_MAC_STATE_IN_USE 0x4 | |
602 | ||
49c7ffbe | 603 | #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 |
e8e26350 | 604 | #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 |
eb7f139c | 605 | |
8f15486d | 606 | #define MIN_MSIX_Q_VECTORS 1 |
021230d4 AV |
607 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
608 | ||
46646e61 AD |
609 | /* default to trying for four seconds */ |
610 | #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) | |
58e7cd24 | 611 | #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ |
46646e61 | 612 | |
9a799d71 AK |
613 | /* board specific private data structure */ |
614 | struct ixgbe_adapter { | |
46646e61 AD |
615 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
616 | /* OS defined structs */ | |
617 | struct net_device *netdev; | |
618 | struct pci_dev *pdev; | |
619 | ||
e606bfe7 AD |
620 | unsigned long state; |
621 | ||
622 | /* Some features need tri-state capability, | |
623 | * thus the additional *_CAPABLE flags. | |
624 | */ | |
625 | u32 flags; | |
a16a0d2f | 626 | #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) |
a16a0d2f AD |
627 | #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) |
628 | #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) | |
629 | #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) | |
630 | #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) | |
a16a0d2f AD |
631 | #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) |
632 | #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) | |
633 | #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) | |
634 | #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) | |
635 | #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) | |
636 | #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) | |
637 | #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) | |
638 | #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) | |
639 | #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) | |
640 | #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) | |
641 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) | |
642 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) | |
643 | #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) | |
644 | #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) | |
645 | #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) | |
646 | #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) | |
67359c3c | 647 | #define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24) |
a9763f3c MR |
648 | #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) |
649 | #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) | |
e606bfe7 AD |
650 | |
651 | u32 flags2; | |
a16a0d2f | 652 | #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) |
e606bfe7 AD |
653 | #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) |
654 | #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) | |
f0f9778d | 655 | #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) |
7086400d AD |
656 | #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) |
657 | #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) | |
c83c6cbd | 658 | #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) |
d034acf1 | 659 | #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) |
ef6afc0c AD |
660 | #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) |
661 | #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) | |
8fecf67c | 662 | #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10) |
597f22d6 | 663 | #define IXGBE_FLAG2_PHY_INTERRUPT (u32)(1 << 11) |
67359c3c | 664 | #define IXGBE_FLAG2_VXLAN_REREG_NEEDED BIT(12) |
16369564 | 665 | #define IXGBE_FLAG2_VLAN_PROMISC BIT(13) |
d033d526 | 666 | |
46646e61 AD |
667 | /* Tx fast path data */ |
668 | int num_tx_queues; | |
669 | u16 tx_itr_setting; | |
bd198058 AD |
670 | u16 tx_work_limit; |
671 | ||
46646e61 AD |
672 | /* Rx fast path data */ |
673 | int num_rx_queues; | |
674 | u16 rx_itr_setting; | |
675 | ||
9f12df90 AD |
676 | /* Port number used to identify VXLAN traffic */ |
677 | __be16 vxlan_port; | |
678 | ||
9a799d71 | 679 | /* TX */ |
4a0b9ca0 | 680 | struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; |
9a799d71 | 681 | |
7ca3bc58 JB |
682 | u64 restart_queue; |
683 | u64 lsc_int; | |
46646e61 | 684 | u32 tx_timeout_count; |
7ca3bc58 | 685 | |
9a799d71 | 686 | /* RX */ |
46646e61 | 687 | struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; |
7f870475 GR |
688 | int num_rx_pools; /* == num_rx_queues in 82598 */ |
689 | int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ | |
9a799d71 | 690 | u64 hw_csum_rx_error; |
e8e26350 | 691 | u64 hw_rx_no_dma_resources; |
46646e61 AD |
692 | u64 rsc_total_count; |
693 | u64 rsc_total_flush; | |
9a799d71 | 694 | u64 non_eop_descs; |
9a799d71 AK |
695 | u32 alloc_rx_page_failed; |
696 | u32 alloc_rx_buff_failed; | |
697 | ||
49c7ffbe | 698 | struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; |
9a799d71 | 699 | |
46646e61 AD |
700 | /* DCB parameters */ |
701 | struct ieee_pfc *ixgbe_ieee_pfc; | |
702 | struct ieee_ets *ixgbe_ieee_ets; | |
703 | struct ixgbe_dcb_config dcb_cfg; | |
704 | struct ixgbe_dcb_config temp_dcb_cfg; | |
705 | u8 dcb_set_bitmap; | |
706 | u8 dcbx_cap; | |
707 | enum ixgbe_fc_mode last_lfc_mode; | |
708 | ||
49c7ffbe AD |
709 | int num_q_vectors; /* current number of q_vectors for device */ |
710 | int max_q_vectors; /* true count of q_vectors for device */ | |
46646e61 AD |
711 | struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
712 | struct msix_entry *msix_entries; | |
9a799d71 | 713 | |
da4dd0f7 PWJ |
714 | u32 test_icr; |
715 | struct ixgbe_ring test_tx_ring; | |
716 | struct ixgbe_ring test_rx_ring; | |
717 | ||
9a799d71 AK |
718 | /* structs defined in ixgbe_hw.h */ |
719 | struct ixgbe_hw hw; | |
720 | u16 msg_enable; | |
721 | struct ixgbe_hw_stats stats; | |
021230d4 | 722 | |
9a799d71 | 723 | u64 tx_busy; |
30efa5a3 JB |
724 | unsigned int tx_ring_count; |
725 | unsigned int rx_ring_count; | |
cf8280ee JB |
726 | |
727 | u32 link_speed; | |
728 | bool link_up; | |
58e7cd24 | 729 | unsigned long sfp_poll_time; |
cf8280ee JB |
730 | unsigned long link_check_timeout; |
731 | ||
7086400d | 732 | struct timer_list service_timer; |
46646e61 AD |
733 | struct work_struct service_task; |
734 | ||
735 | struct hlist_head fdir_filter_list; | |
736 | unsigned long fdir_overflow; /* number of times ATR was backed off */ | |
737 | union ixgbe_atr_input fdir_mask; | |
738 | int fdir_filter_count; | |
c4cf55e5 PWJ |
739 | u32 fdir_pballoc; |
740 | u32 atr_sample_rate; | |
741 | spinlock_t fdir_perfect_lock; | |
46646e61 | 742 | |
d0ed8937 YZ |
743 | #ifdef IXGBE_FCOE |
744 | struct ixgbe_fcoe fcoe; | |
745 | #endif /* IXGBE_FCOE */ | |
2a1a091c | 746 | u8 __iomem *io_addr; /* Mainly for iounmap use */ |
e8e26350 | 747 | u32 wol; |
46646e61 | 748 | |
aa2bacb6 DS |
749 | u16 bridge_mode; |
750 | ||
15e5209f ET |
751 | u16 eeprom_verh; |
752 | u16 eeprom_verl; | |
c23f5b6b | 753 | u16 eeprom_cap; |
7f870475 | 754 | |
119fc60a | 755 | u32 interrupt_event; |
46646e61 | 756 | u32 led_reg; |
1a6c14a2 | 757 | |
3a6a4eda JK |
758 | struct ptp_clock *ptp_clock; |
759 | struct ptp_clock_info ptp_caps; | |
891dc082 JK |
760 | struct work_struct ptp_tx_work; |
761 | struct sk_buff *ptp_tx_skb; | |
93501d48 | 762 | struct hwtstamp_config tstamp_config; |
891dc082 | 763 | unsigned long ptp_tx_start; |
3a6a4eda | 764 | unsigned long last_overflow_check; |
6cb562d6 | 765 | unsigned long last_rx_ptp_check; |
eda183c2 | 766 | unsigned long last_rx_timestamp; |
3a6a4eda | 767 | spinlock_t tmreg_lock; |
a9763f3c MR |
768 | struct cyclecounter hw_cc; |
769 | struct timecounter hw_tc; | |
3a6a4eda | 770 | u32 base_incval; |
a9763f3c MR |
771 | u32 tx_hwtstamp_timeouts; |
772 | u32 rx_hwtstamp_cleared; | |
773 | void (*ptp_setup_sdp)(struct ixgbe_adapter *); | |
3a6a4eda | 774 | |
7f870475 GR |
775 | /* SR-IOV */ |
776 | DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); | |
777 | unsigned int num_vfs; | |
778 | struct vf_data_storage *vfinfo; | |
ff4ab206 | 779 | int vf_rate_link_speed; |
a1cbb15c GR |
780 | struct vf_macvlans vf_mvs; |
781 | struct vf_macvlans *mv_list; | |
3e05334f | 782 | |
83c61fa9 GR |
783 | u32 timer_event_accumulator; |
784 | u32 vferr_refcount; | |
5d7daa35 | 785 | struct ixgbe_mac_addr *mac_table; |
3ca8bc6d DS |
786 | struct kobject *info_kobj; |
787 | #ifdef CONFIG_IXGBE_HWMON | |
03b77d81 | 788 | struct hwmon_buff *ixgbe_hwmon_buff; |
3ca8bc6d | 789 | #endif /* CONFIG_IXGBE_HWMON */ |
00949167 CS |
790 | #ifdef CONFIG_DEBUG_FS |
791 | struct dentry *ixgbe_dbg_adapter; | |
792 | #endif /*CONFIG_DEBUG_FS*/ | |
107d3018 AD |
793 | |
794 | u8 default_up; | |
2a47fa45 | 795 | unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ |
dfaf891d | 796 | |
b82b17d9 JF |
797 | #define IXGBE_MAX_LINK_HANDLE 10 |
798 | struct ixgbe_mat_field *jump_tables[IXGBE_MAX_LINK_HANDLE]; | |
db956ae8 | 799 | unsigned long tables; |
b82b17d9 | 800 | |
dfaf891d VZ |
801 | /* maximum number of RETA entries among all devices supported by ixgbe |
802 | * driver: currently it's x550 device in non-SRIOV mode | |
803 | */ | |
804 | #define IXGBE_MAX_RETA_ENTRIES 512 | |
805 | u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; | |
806 | ||
807 | #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ | |
808 | u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)]; | |
3e05334f AD |
809 | }; |
810 | ||
0f9b232b DS |
811 | static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) |
812 | { | |
813 | switch (adapter->hw.mac.type) { | |
814 | case ixgbe_mac_82598EB: | |
815 | case ixgbe_mac_82599EB: | |
816 | case ixgbe_mac_X540: | |
817 | return IXGBE_MAX_RSS_INDICES; | |
818 | case ixgbe_mac_X550: | |
819 | case ixgbe_mac_X550EM_x: | |
820 | return IXGBE_MAX_RSS_INDICES_X550; | |
821 | default: | |
822 | return 0; | |
823 | } | |
824 | } | |
825 | ||
3e05334f AD |
826 | struct ixgbe_fdir_filter { |
827 | struct hlist_node fdir_node; | |
828 | union ixgbe_atr_input filter; | |
829 | u16 sw_idx; | |
830 | u16 action; | |
9a799d71 AK |
831 | }; |
832 | ||
70e5576c | 833 | enum ixgbe_state_t { |
9a799d71 AK |
834 | __IXGBE_TESTING, |
835 | __IXGBE_RESETTING, | |
c4900be0 | 836 | __IXGBE_DOWN, |
41c62843 | 837 | __IXGBE_DISABLED, |
09f40aed | 838 | __IXGBE_REMOVING, |
7086400d | 839 | __IXGBE_SERVICE_SCHED, |
58cf663f | 840 | __IXGBE_SERVICE_INITED, |
7086400d | 841 | __IXGBE_IN_SFP_INIT, |
8fecf67c | 842 | __IXGBE_PTP_RUNNING, |
151b260c | 843 | __IXGBE_PTP_TX_IN_PROGRESS, |
9a799d71 AK |
844 | }; |
845 | ||
4c1975d7 AD |
846 | struct ixgbe_cb { |
847 | union { /* Union defining head/tail partner */ | |
848 | struct sk_buff *head; | |
849 | struct sk_buff *tail; | |
850 | }; | |
aa80175a | 851 | dma_addr_t dma; |
4c1975d7 | 852 | u16 append_cnt; |
f800326d | 853 | bool page_released; |
aa80175a | 854 | }; |
4c1975d7 | 855 | #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) |
aa80175a | 856 | |
9a799d71 | 857 | enum ixgbe_boards { |
3957d63d | 858 | board_82598, |
e8e26350 | 859 | board_82599, |
fe15e8e1 | 860 | board_X540, |
6a14ee0c DS |
861 | board_X550, |
862 | board_X550EM_x, | |
9a799d71 AK |
863 | }; |
864 | ||
3957d63d | 865 | extern struct ixgbe_info ixgbe_82598_info; |
e8e26350 | 866 | extern struct ixgbe_info ixgbe_82599_info; |
fe15e8e1 | 867 | extern struct ixgbe_info ixgbe_X540_info; |
6a14ee0c DS |
868 | extern struct ixgbe_info ixgbe_X550_info; |
869 | extern struct ixgbe_info ixgbe_X550EM_x_info; | |
7a6b6f51 | 870 | #ifdef CONFIG_IXGBE_DCB |
32953543 | 871 | extern const struct dcbnl_rtnl_ops dcbnl_ops; |
2f90b865 | 872 | #endif |
9a799d71 AK |
873 | |
874 | extern char ixgbe_driver_name[]; | |
9c8eb720 | 875 | extern const char ixgbe_driver_version[]; |
8af3c33f | 876 | #ifdef IXGBE_FCOE |
ea81875a | 877 | extern char ixgbe_default_device_descr[]; |
8af3c33f | 878 | #endif /* IXGBE_FCOE */ |
9a799d71 | 879 | |
6c211fe1 SA |
880 | int ixgbe_open(struct net_device *netdev); |
881 | int ixgbe_close(struct net_device *netdev); | |
5ccc921a JP |
882 | void ixgbe_up(struct ixgbe_adapter *adapter); |
883 | void ixgbe_down(struct ixgbe_adapter *adapter); | |
884 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); | |
885 | void ixgbe_reset(struct ixgbe_adapter *adapter); | |
886 | void ixgbe_set_ethtool_ops(struct net_device *netdev); | |
887 | int ixgbe_setup_rx_resources(struct ixgbe_ring *); | |
888 | int ixgbe_setup_tx_resources(struct ixgbe_ring *); | |
889 | void ixgbe_free_rx_resources(struct ixgbe_ring *); | |
890 | void ixgbe_free_tx_resources(struct ixgbe_ring *); | |
891 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
892 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
893 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); | |
894 | void ixgbe_update_stats(struct ixgbe_adapter *adapter); | |
895 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); | |
896 | int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, | |
8e2813f5 | 897 | u16 subdevice_id); |
5d7daa35 JK |
898 | #ifdef CONFIG_PCI_IOV |
899 | void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); | |
900 | #endif | |
901 | int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, | |
c9f53e63 | 902 | const u8 *addr, u16 queue); |
5d7daa35 | 903 | int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, |
c9f53e63 | 904 | const u8 *addr, u16 queue); |
e1d0a2af | 905 | void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid); |
5ccc921a JP |
906 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); |
907 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, | |
908 | struct ixgbe_ring *); | |
909 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, | |
910 | struct ixgbe_tx_buffer *); | |
911 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); | |
912 | void ixgbe_write_eitr(struct ixgbe_q_vector *); | |
913 | int ixgbe_poll(struct napi_struct *napi, int budget); | |
914 | int ethtool_ioctl(struct ifreq *ifr); | |
915 | s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); | |
916 | s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
917 | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
918 | s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, | |
919 | union ixgbe_atr_hash_dword input, | |
920 | union ixgbe_atr_hash_dword common, | |
921 | u8 queue); | |
922 | s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, | |
923 | union ixgbe_atr_input *input_mask); | |
924 | s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, | |
925 | union ixgbe_atr_input *input, | |
926 | u16 soft_id, u8 queue); | |
927 | s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, | |
928 | union ixgbe_atr_input *input, | |
929 | u16 soft_id); | |
930 | void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, | |
931 | union ixgbe_atr_input *mask); | |
b82b17d9 JF |
932 | int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, |
933 | struct ixgbe_fdir_filter *input, | |
934 | u16 sw_idx); | |
5ccc921a | 935 | void ixgbe_set_rx_mode(struct net_device *netdev); |
8af3c33f | 936 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a | 937 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); |
8af3c33f | 938 | #endif |
5ccc921a JP |
939 | int ixgbe_setup_tc(struct net_device *dev, u8 tc); |
940 | void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); | |
941 | void ixgbe_do_reset(struct net_device *netdev); | |
1210982b | 942 | #ifdef CONFIG_IXGBE_HWMON |
5ccc921a JP |
943 | void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); |
944 | int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); | |
1210982b | 945 | #endif /* CONFIG_IXGBE_HWMON */ |
eacd73f7 | 946 | #ifdef IXGBE_FCOE |
5ccc921a JP |
947 | void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); |
948 | int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, | |
949 | u8 *hdr_len); | |
950 | int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
951 | union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); | |
952 | int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, | |
953 | struct scatterlist *sgl, unsigned int sgc); | |
954 | int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, | |
955 | struct scatterlist *sgl, unsigned int sgc); | |
956 | int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); | |
957 | int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
958 | void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
959 | int ixgbe_fcoe_enable(struct net_device *netdev); | |
960 | int ixgbe_fcoe_disable(struct net_device *netdev); | |
6ee16520 | 961 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a JP |
962 | u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); |
963 | u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); | |
6ee16520 | 964 | #endif /* CONFIG_IXGBE_DCB */ |
5ccc921a JP |
965 | int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); |
966 | int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, | |
967 | struct netdev_fcoe_hbainfo *info); | |
968 | u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); | |
eacd73f7 | 969 | #endif /* IXGBE_FCOE */ |
00949167 | 970 | #ifdef CONFIG_DEBUG_FS |
5ccc921a JP |
971 | void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); |
972 | void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); | |
973 | void ixgbe_dbg_init(void); | |
974 | void ixgbe_dbg_exit(void); | |
33243fb0 JP |
975 | #else |
976 | static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} | |
977 | static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} | |
978 | static inline void ixgbe_dbg_init(void) {} | |
979 | static inline void ixgbe_dbg_exit(void) {} | |
00949167 | 980 | #endif /* CONFIG_DEBUG_FS */ |
b2d96e0a AD |
981 | static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) |
982 | { | |
983 | return netdev_get_tx_queue(ring->netdev, ring->queue_index); | |
984 | } | |
985 | ||
5ccc921a | 986 | void ixgbe_ptp_init(struct ixgbe_adapter *adapter); |
9966d1ee | 987 | void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); |
5ccc921a JP |
988 | void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); |
989 | void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); | |
990 | void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); | |
a9763f3c MR |
991 | void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); |
992 | void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); | |
993 | static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, | |
994 | union ixgbe_adv_rx_desc *rx_desc, | |
995 | struct sk_buff *skb) | |
996 | { | |
997 | if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { | |
998 | ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); | |
999 | return; | |
1000 | } | |
1001 | ||
1002 | if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) | |
1003 | return; | |
1004 | ||
1005 | ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); | |
1006 | ||
1007 | /* Update the last_rx_timestamp timer in order to enable watchdog check | |
1008 | * for error case of latched timestamp on a dropped packet. | |
1009 | */ | |
1010 | rx_ring->last_rx_timestamp = jiffies; | |
1011 | } | |
1012 | ||
93501d48 JK |
1013 | int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); |
1014 | int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); | |
5ccc921a JP |
1015 | void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); |
1016 | void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); | |
a9763f3c | 1017 | void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); |
da36b647 GR |
1018 | #ifdef CONFIG_PCI_IOV |
1019 | void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); | |
1020 | #endif | |
3a6a4eda | 1021 | |
2a47fa45 JF |
1022 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
1023 | struct ixgbe_adapter *adapter, | |
1024 | struct ixgbe_ring *tx_ring); | |
7f276efb | 1025 | u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); |
1c7cf078 | 1026 | void ixgbe_store_reta(struct ixgbe_adapter *adapter); |
9a799d71 | 1027 | #endif /* _IXGBE_H_ */ |