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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
[linux-2.6-block.git] / drivers / net / ethernet / brocade / bna / bnad.c
CommitLineData
8b230ed8 1/*
2732ba56 2 * Linux network driver for QLogic BR-series Converged Network Adapter.
8b230ed8
RM		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
2732ba56
RM		 14 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
15 * Copyright (c) 2014-2015 QLogic Corporation
8b230ed8 16 * All rights reserved
2732ba56 17 * www.qlogic.com
8b230ed8 18 */
f859d7cb 19#include <linux/bitops.h>
8b230ed8
RM		 20#include <linux/netdevice.h>
21#include <linux/skbuff.h>
22#include <linux/etherdevice.h>
23#include <linux/in.h>
24#include <linux/ethtool.h>
25#include <linux/if_vlan.h>
26#include <linux/if_ether.h>
27#include <linux/ip.h>
70c71606 28#include <linux/prefetch.h>
9d9779e7 29#include <linux/module.h>
8b230ed8
RM		 30
31#include "bnad.h"
32#include "bna.h"
33#include "cna.h"
34
b7ee31c5 35static DEFINE_MUTEX(bnad_fwimg_mutex);
8b230ed8
RM		 36
37/*
38 * Module params
39 */
40static uint bnad_msix_disable;
41module_param(bnad_msix_disable, uint, 0444);
42MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
43
44static uint bnad_ioc_auto_recover = 1;
45module_param(bnad_ioc_auto_recover, uint, 0444);
46MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
47
7afc5dbd
KG		 48static uint bna_debugfs_enable = 1;
49module_param(bna_debugfs_enable, uint, S_IRUGO | S_IWUSR);
50MODULE_PARM_DESC(bna_debugfs_enable, "Enables debugfs feature, default=1,"
51 " Range[false:0|true:1]");
52
8b230ed8
RM		 53/*
54 * Global variables
55 */
482da0fa 56static u32 bnad_rxqs_per_cq = 2;
e1e0918f 57static u32 bna_id;
58static struct mutex bnad_list_mutex;
59static LIST_HEAD(bnad_list);
e2f9ecfc
IV		 60static const u8 bnad_bcast_addr[] __aligned(2) =
61 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
8b230ed8
RM		 62
63/*
64 * Local MACROS
65 */
8b230ed8
RM		 66#define BNAD_GET_MBOX_IRQ(_bnad) \
67 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
8811e267 68 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
8b230ed8
RM		 69 ((_bnad)->pcidev->irq))
70
5216562a 71#define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _size) \
8b230ed8
RM		 72do { \
73 (_res_info)->res_type = BNA_RES_T_MEM; \
74 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
75 (_res_info)->res_u.mem_info.num = (_num); \
5216562a 76 (_res_info)->res_u.mem_info.len = (_size); \
8b230ed8
RM		 77} while (0)
78
72a9730b
KG		 79static void
80bnad_add_to_list(struct bnad *bnad)
81{
82 mutex_lock(&bnad_list_mutex);
83 list_add_tail(&bnad->list_entry, &bnad_list);
84 bnad->id = bna_id++;
85 mutex_unlock(&bnad_list_mutex);
86}
87
88static void
89bnad_remove_from_list(struct bnad *bnad)
90{
91 mutex_lock(&bnad_list_mutex);
92 list_del(&bnad->list_entry);
93 mutex_unlock(&bnad_list_mutex);
94}
95
8b230ed8
RM		 96/*
97 * Reinitialize completions in CQ, once Rx is taken down
98 */
99static void
b3cc6e88 100bnad_cq_cleanup(struct bnad *bnad, struct bna_ccb *ccb)
8b230ed8 101{
5216562a 102 struct bna_cq_entry *cmpl;
8b230ed8
RM		 103 int i;
104
8b230ed8 105 for (i = 0; i < ccb->q_depth; i++) {
5216562a 106 cmpl = &((struct bna_cq_entry *)ccb->sw_q)[i];
8b230ed8 107 cmpl->valid = 0;
8b230ed8
RM		 108 }
109}
110
5216562a
RM		 111/* Tx Datapath functions */
112
113
114/* Caller should ensure that the entry at unmap_q[index] is valid */
271e8b79 115static u32
5216562a
RM		 116bnad_tx_buff_unmap(struct bnad *bnad,
117 struct bnad_tx_unmap *unmap_q,
118 u32 q_depth, u32 index)
271e8b79 119{
5216562a
RM		 120 struct bnad_tx_unmap *unmap;
121 struct sk_buff *skb;
122 int vector, nvecs;
123
124 unmap = &unmap_q[index];
125 nvecs = unmap->nvecs;
126
127 skb = unmap->skb;
128 unmap->skb = NULL;
129 unmap->nvecs = 0;
130 dma_unmap_single(&bnad->pcidev->dev,
131 dma_unmap_addr(&unmap->vectors[0], dma_addr),
132 skb_headlen(skb), DMA_TO_DEVICE);
133 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, 0);
134 nvecs--;
135
136 vector = 0;
137 while (nvecs) {
138 vector++;
139 if (vector == BFI_TX_MAX_VECTORS_PER_WI) {
140 vector = 0;
141 BNA_QE_INDX_INC(index, q_depth);
142 unmap = &unmap_q[index];
143 }
271e8b79 144
5216562a
RM		 145 dma_unmap_page(&bnad->pcidev->dev,
146 dma_unmap_addr(&unmap->vectors[vector], dma_addr),
24f5d33d
RM		 147 dma_unmap_len(&unmap->vectors[vector], dma_len),
148 DMA_TO_DEVICE);
5216562a
RM		 149 dma_unmap_addr_set(&unmap->vectors[vector], dma_addr, 0);
150 nvecs--;
271e8b79
RM		 151 }
152
5216562a
RM		 153 BNA_QE_INDX_INC(index, q_depth);
154
271e8b79
RM		 155 return index;
156}
157
8b230ed8
RM		 158/*
159 * Frees all pending Tx Bufs
160 * At this point no activity is expected on the Q,
161 * so DMA unmap & freeing is fine.
162 */
163static void
5216562a 164bnad_txq_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
8b230ed8 165{
5216562a
RM		 166 struct bnad_tx_unmap *unmap_q = tcb->unmap_q;
167 struct sk_buff *skb;
168 int i;
8b230ed8 169
5216562a
RM		 170 for (i = 0; i < tcb->q_depth; i++) {
171 skb = unmap_q[i].skb;
938fa488 172 if (!skb)
8b230ed8 173 continue;
5216562a 174 bnad_tx_buff_unmap(bnad, unmap_q, tcb->q_depth, i);
938fa488 175
8b230ed8
RM		 176 dev_kfree_skb_any(skb);
177 }
178}
179
8b230ed8 180/*
b3cc6e88 181 * bnad_txcmpl_process : Frees the Tx bufs on Tx completion
8b230ed8
RM		 182 * Can be called in a) Interrupt context
183 * b) Sending context
8b230ed8
RM		 184 */
185static u32
5216562a 186bnad_txcmpl_process(struct bnad *bnad, struct bna_tcb *tcb)
8b230ed8 187{
5216562a
RM		 188 u32 sent_packets = 0, sent_bytes = 0;
189 u32 wis, unmap_wis, hw_cons, cons, q_depth;
190 struct bnad_tx_unmap *unmap_q = tcb->unmap_q;
191 struct bnad_tx_unmap *unmap;
192 struct sk_buff *skb;
8b230ed8 193
d95d1081 194 /* Just return if TX is stopped */
be7fa326 195 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
8b230ed8
RM		 196 return 0;
197
5216562a
RM		 198 hw_cons = *(tcb->hw_consumer_index);
199 cons = tcb->consumer_index;
200 q_depth = tcb->q_depth;
8b230ed8 201
5216562a 202 wis = BNA_Q_INDEX_CHANGE(cons, hw_cons, q_depth);
8b230ed8
RM		 203 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
204
8b230ed8 205 while (wis) {
5216562a
RM		 206 unmap = &unmap_q[cons];
207
208 skb = unmap->skb;
8b230ed8 209
8b230ed8
RM		 210 sent_packets++;
211 sent_bytes += skb->len;
8b230ed8 212
5216562a
RM		 213 unmap_wis = BNA_TXQ_WI_NEEDED(unmap->nvecs);
214 wis -= unmap_wis;
8b230ed8 215
5216562a 216 cons = bnad_tx_buff_unmap(bnad, unmap_q, q_depth, cons);
8b230ed8
RM		 217 dev_kfree_skb_any(skb);
218 }
219
220 /* Update consumer pointers. */
5216562a 221 tcb->consumer_index = hw_cons;
8b230ed8
RM		 222
223 tcb->txq->tx_packets += sent_packets;
224 tcb->txq->tx_bytes += sent_bytes;
225
226 return sent_packets;
227}
228
8b230ed8 229static u32
b3cc6e88 230bnad_tx_complete(struct bnad *bnad, struct bna_tcb *tcb)
8b230ed8
RM		 231{
232 struct net_device *netdev = bnad->netdev;
be7fa326 233 u32 sent = 0;
8b230ed8
RM		 234
235 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
236 return 0;
237
b3cc6e88 238 sent = bnad_txcmpl_process(bnad, tcb);
8b230ed8
RM		 239 if (sent) {
240 if (netif_queue_stopped(netdev) &&
241 netif_carrier_ok(netdev) &&
242 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
243 BNAD_NETIF_WAKE_THRESHOLD) {
be7fa326
RM		 244 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
245 netif_wake_queue(netdev);
246 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
247 }
8b230ed8 248 }
be7fa326
RM		 249 }
250
251 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
8b230ed8 252 bna_ib_ack(tcb->i_dbell, sent);
8b230ed8 253
4e857c58 254 smp_mb__before_atomic();
8b230ed8
RM		 255 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
256
257 return sent;
258}
259
260/* MSIX Tx Completion Handler */
261static irqreturn_t
262bnad_msix_tx(int irq, void *data)
263{
264 struct bna_tcb *tcb = (struct bna_tcb *)data;
265 struct bnad *bnad = tcb->bnad;
266
b3cc6e88 267 bnad_tx_complete(bnad, tcb);
8b230ed8
RM		 268
269 return IRQ_HANDLED;
270}
271
30f9fc94
RM		 272static inline void
273bnad_rxq_alloc_uninit(struct bnad *bnad, struct bna_rcb *rcb)
274{
275 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
276
277 unmap_q->reuse_pi = -1;
278 unmap_q->alloc_order = -1;
279 unmap_q->map_size = 0;
280 unmap_q->type = BNAD_RXBUF_NONE;
281}
282
283/* Default is page-based allocation. Multi-buffer support - TBD */
284static int
285bnad_rxq_alloc_init(struct bnad *bnad, struct bna_rcb *rcb)
286{
287 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
e29aa339 288 int order;
30f9fc94
RM		 289
290 bnad_rxq_alloc_uninit(bnad, rcb);
291
e29aa339
RM		 292 order = get_order(rcb->rxq->buffer_size);
293
294 unmap_q->type = BNAD_RXBUF_PAGE;
30f9fc94
RM		 295
296 if (bna_is_small_rxq(rcb->id)) {
297 unmap_q->alloc_order = 0;
298 unmap_q->map_size = rcb->rxq->buffer_size;
299 } else {
e29aa339
RM		 300 if (rcb->rxq->multi_buffer) {
301 unmap_q->alloc_order = 0;
302 unmap_q->map_size = rcb->rxq->buffer_size;
303 unmap_q->type = BNAD_RXBUF_MULTI_BUFF;
304 } else {
305 unmap_q->alloc_order = order;
306 unmap_q->map_size =
307 (rcb->rxq->buffer_size > 2048) ?
308 PAGE_SIZE << order : 2048;
309 }
30f9fc94
RM		 310 }
311
ebb56d37 312 BUG_ON((PAGE_SIZE << order) % unmap_q->map_size);
30f9fc94 313
30f9fc94
RM		 314 return 0;
315}
316
317static inline void
318bnad_rxq_cleanup_page(struct bnad *bnad, struct bnad_rx_unmap *unmap)
319{
320 if (!unmap->page)
321 return;
322
323 dma_unmap_page(&bnad->pcidev->dev,
324 dma_unmap_addr(&unmap->vector, dma_addr),
325 unmap->vector.len, DMA_FROM_DEVICE);
326 put_page(unmap->page);
327 unmap->page = NULL;
328 dma_unmap_addr_set(&unmap->vector, dma_addr, 0);
329 unmap->vector.len = 0;
330}
331
332static inline void
333bnad_rxq_cleanup_skb(struct bnad *bnad, struct bnad_rx_unmap *unmap)
334{
335 if (!unmap->skb)
336 return;
337
338 dma_unmap_single(&bnad->pcidev->dev,
339 dma_unmap_addr(&unmap->vector, dma_addr),
340 unmap->vector.len, DMA_FROM_DEVICE);
341 dev_kfree_skb_any(unmap->skb);
342 unmap->skb = NULL;
343 dma_unmap_addr_set(&unmap->vector, dma_addr, 0);
344 unmap->vector.len = 0;
345}
346
8b230ed8 347static void
b3cc6e88 348bnad_rxq_cleanup(struct bnad *bnad, struct bna_rcb *rcb)
8b230ed8 349{
30f9fc94 350 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
5216562a
RM		 351 int i;
352
353 for (i = 0; i < rcb->q_depth; i++) {
30f9fc94 354 struct bnad_rx_unmap *unmap = &unmap_q->unmap[i];
8b230ed8 355
e29aa339 356 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
30f9fc94 357 bnad_rxq_cleanup_skb(bnad, unmap);
e29aa339
RM		 358 else
359 bnad_rxq_cleanup_page(bnad, unmap);
30f9fc94
RM		 360 }
361 bnad_rxq_alloc_uninit(bnad, rcb);
362}
5216562a 363
30f9fc94
RM		 364static u32
365bnad_rxq_refill_page(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc)
366{
367 u32 alloced, prod, q_depth;
368 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
369 struct bnad_rx_unmap *unmap, *prev;
370 struct bna_rxq_entry *rxent;
371 struct page *page;
372 u32 page_offset, alloc_size;
373 dma_addr_t dma_addr;
374
375 prod = rcb->producer_index;
376 q_depth = rcb->q_depth;
377
378 alloc_size = PAGE_SIZE << unmap_q->alloc_order;
379 alloced = 0;
380
381 while (nalloc--) {
382 unmap = &unmap_q->unmap[prod];
383
384 if (unmap_q->reuse_pi < 0) {
385 page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
386 unmap_q->alloc_order);
387 page_offset = 0;
388 } else {
389 prev = &unmap_q->unmap[unmap_q->reuse_pi];
390 page = prev->page;
391 page_offset = prev->page_offset + unmap_q->map_size;
392 get_page(page);
393 }
394
395 if (unlikely(!page)) {
396 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
397 rcb->rxq->rxbuf_alloc_failed++;
398 goto finishing;
399 }
400
401 dma_addr = dma_map_page(&bnad->pcidev->dev, page, page_offset,
402 unmap_q->map_size, DMA_FROM_DEVICE);
403
404 unmap->page = page;
405 unmap->page_offset = page_offset;
406 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr);
407 unmap->vector.len = unmap_q->map_size;
408 page_offset += unmap_q->map_size;
409
410 if (page_offset < alloc_size)
411 unmap_q->reuse_pi = prod;
412 else
413 unmap_q->reuse_pi = -1;
414
415 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod];
416 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
417 BNA_QE_INDX_INC(prod, q_depth);
418 alloced++;
419 }
420
421finishing:
422 if (likely(alloced)) {
423 rcb->producer_index = prod;
424 smp_mb();
425 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
426 bna_rxq_prod_indx_doorbell(rcb);
8b230ed8 427 }
30f9fc94
RM		 428
429 return alloced;
8b230ed8
RM		 430}
431
30f9fc94
RM		 432static u32
433bnad_rxq_refill_skb(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc)
8b230ed8 434{
30f9fc94
RM		 435 u32 alloced, prod, q_depth, buff_sz;
436 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
5216562a 437 struct bnad_rx_unmap *unmap;
8b230ed8
RM		 438 struct bna_rxq_entry *rxent;
439 struct sk_buff *skb;
440 dma_addr_t dma_addr;
441
5216562a 442 buff_sz = rcb->rxq->buffer_size;
5216562a
RM		 443 prod = rcb->producer_index;
444 q_depth = rcb->q_depth;
8b230ed8 445
30f9fc94
RM		 446 alloced = 0;
447 while (nalloc--) {
448 unmap = &unmap_q->unmap[prod];
449
450 skb = netdev_alloc_skb_ip_align(bnad->netdev, buff_sz);
451
8b230ed8
RM		 452 if (unlikely(!skb)) {
453 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
3caa1e95 454 rcb->rxq->rxbuf_alloc_failed++;
8b230ed8
RM		 455 goto finishing;
456 }
5ea74318 457 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
5216562a 458 buff_sz, DMA_FROM_DEVICE);
8b230ed8 459
5216562a
RM		 460 unmap->skb = skb;
461 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr);
462 unmap->vector.len = buff_sz;
30f9fc94
RM		 463
464 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod];
465 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
5216562a 466 BNA_QE_INDX_INC(prod, q_depth);
8b230ed8
RM		 467 alloced++;
468 }
469
470finishing:
471 if (likely(alloced)) {
5216562a 472 rcb->producer_index = prod;
8b230ed8 473 smp_mb();
5bcf6ac0 474 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
be7fa326 475 bna_rxq_prod_indx_doorbell(rcb);
8b230ed8 476 }
30f9fc94
RM		 477
478 return alloced;
479}
480
481static inline void
482bnad_rxq_post(struct bnad *bnad, struct bna_rcb *rcb)
483{
484 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
485 u32 to_alloc;
486
487 to_alloc = BNA_QE_FREE_CNT(rcb, rcb->q_depth);
488 if (!(to_alloc >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT))
489 return;
490
e29aa339 491 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
30f9fc94 492 bnad_rxq_refill_skb(bnad, rcb, to_alloc);
e29aa339
RM		 493 else
494 bnad_rxq_refill_page(bnad, rcb, to_alloc);
8b230ed8
RM		 495}
496
5e46631f
RM		 497#define flags_cksum_prot_mask (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
498 BNA_CQ_EF_IPV6 | \
499 BNA_CQ_EF_TCP | BNA_CQ_EF_UDP | \
500 BNA_CQ_EF_L4_CKSUM_OK)
501
502#define flags_tcp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
503 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
504#define flags_tcp6 (BNA_CQ_EF_IPV6 | \
505 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
506#define flags_udp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
507 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
508#define flags_udp6 (BNA_CQ_EF_IPV6 | \
509 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
510
e29aa339
RM		 511static void
512bnad_cq_drop_packet(struct bnad *bnad, struct bna_rcb *rcb,
513 u32 sop_ci, u32 nvecs)
30f9fc94 514{
e29aa339
RM		 515 struct bnad_rx_unmap_q *unmap_q;
516 struct bnad_rx_unmap *unmap;
517 u32 ci, vec;
30f9fc94 518
e29aa339
RM		 519 unmap_q = rcb->unmap_q;
520 for (vec = 0, ci = sop_ci; vec < nvecs; vec++) {
521 unmap = &unmap_q->unmap[ci];
522 BNA_QE_INDX_INC(ci, rcb->q_depth);
523
524 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
525 bnad_rxq_cleanup_skb(bnad, unmap);
526 else
527 bnad_rxq_cleanup_page(bnad, unmap);
528 }
529}
530
531static void
532bnad_cq_setup_skb_frags(struct bna_rcb *rcb, struct sk_buff *skb,
533 u32 sop_ci, u32 nvecs, u32 last_fraglen)
534{
535 struct bnad *bnad;
536 u32 ci, vec, len, totlen = 0;
537 struct bnad_rx_unmap_q *unmap_q;
538 struct bnad_rx_unmap *unmap;
539
540 unmap_q = rcb->unmap_q;
541 bnad = rcb->bnad;
66f9513a
RM		 542
543 /* prefetch header */
544 prefetch(page_address(unmap_q->unmap[sop_ci].page) +
545 unmap_q->unmap[sop_ci].page_offset);
546
e29aa339
RM		 547 for (vec = 1, ci = sop_ci; vec <= nvecs; vec++) {
548 unmap = &unmap_q->unmap[ci];
549 BNA_QE_INDX_INC(ci, rcb->q_depth);
30f9fc94
RM		 550
551 dma_unmap_page(&bnad->pcidev->dev,
552 dma_unmap_addr(&unmap->vector, dma_addr),
553 unmap->vector.len, DMA_FROM_DEVICE);
e29aa339
RM		 554
555 len = (vec == nvecs) ?
556 last_fraglen : unmap->vector.len;
f2d9da1a 557 skb->truesize += unmap->vector.len;
e29aa339
RM		 558 totlen += len;
559
30f9fc94 560 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e29aa339 561 unmap->page, unmap->page_offset, len);
30f9fc94
RM		 562
563 unmap->page = NULL;
564 unmap->vector.len = 0;
30f9fc94
RM		 565 }
566
e29aa339
RM		 567 skb->len += totlen;
568 skb->data_len += totlen;
e29aa339
RM		 569}
570
571static inline void
572bnad_cq_setup_skb(struct bnad *bnad, struct sk_buff *skb,
573 struct bnad_rx_unmap *unmap, u32 len)
574{
575 prefetch(skb->data);
30f9fc94
RM		 576
577 dma_unmap_single(&bnad->pcidev->dev,
578 dma_unmap_addr(&unmap->vector, dma_addr),
579 unmap->vector.len, DMA_FROM_DEVICE);
580
e29aa339 581 skb_put(skb, len);
30f9fc94
RM		 582 skb->protocol = eth_type_trans(skb, bnad->netdev);
583
584 unmap->skb = NULL;
585 unmap->vector.len = 0;
30f9fc94
RM		 586}
587
8b230ed8 588static u32
b3cc6e88 589bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget)
8b230ed8 590{
e29aa339 591 struct bna_cq_entry *cq, *cmpl, *next_cmpl;
8b230ed8 592 struct bna_rcb *rcb = NULL;
30f9fc94 593 struct bnad_rx_unmap_q *unmap_q;
e29aa339
RM		 594 struct bnad_rx_unmap *unmap = NULL;
595 struct sk_buff *skb = NULL;
8b230ed8 596 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
30f9fc94 597 struct bnad_rx_ctrl *rx_ctrl = ccb->ctrl;
e29aa339
RM		 598 u32 packets = 0, len = 0, totlen = 0;
599 u32 pi, vec, sop_ci = 0, nvecs = 0;
600 u32 flags, masked_flags;
078086f3 601
8b230ed8 602 prefetch(bnad->netdev);
5216562a
RM		 603
604 cq = ccb->sw_q;
5216562a 605
17a30a14 606 while (packets < budget) {
c36c9d50 607 cmpl = &cq[ccb->producer_index];
17a30a14
RM		 608 if (!cmpl->valid)
609 break;
610 /* The 'valid' field is set by the adapter, only after writing
611 * the other fields of completion entry. Hence, do not load
612 * other fields of completion entry *before* the 'valid' is
613 * loaded. Adding the rmb() here prevents the compiler and/or
614 * CPU from reordering the reads which would potentially result
615 * in reading stale values in completion entry.
616 */
617 rmb();
618
8b230ed8
RM		 619 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
620
078086f3 621 if (bna_is_small_rxq(cmpl->rxq_id))
8b230ed8 622 rcb = ccb->rcb[1];
078086f3
RM		 623 else
624 rcb = ccb->rcb[0];
8b230ed8
RM		 625
626 unmap_q = rcb->unmap_q;
627
e29aa339
RM		 628 /* start of packet ci */
629 sop_ci = rcb->consumer_index;
630
631 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) {
632 unmap = &unmap_q->unmap[sop_ci];
633 skb = unmap->skb;
634 } else {
635 skb = napi_get_frags(&rx_ctrl->napi);
636 if (unlikely(!skb))
637 break;
638 }
639 prefetch(skb);
640
641 flags = ntohl(cmpl->flags);
642 len = ntohs(cmpl->length);
643 totlen = len;
644 nvecs = 1;
645
646 /* Check all the completions for this frame.
647 * busy-wait doesn't help much, break here.
648 */
649 if (BNAD_RXBUF_IS_MULTI_BUFF(unmap_q->type) &&
650 (flags & BNA_CQ_EF_EOP) == 0) {
651 pi = ccb->producer_index;
652 do {
653 BNA_QE_INDX_INC(pi, ccb->q_depth);
654 next_cmpl = &cq[pi];
655
656 if (!next_cmpl->valid)
657 break;
17a30a14
RM		 658 /* The 'valid' field is set by the adapter, only
659 * after writing the other fields of completion
660 * entry. Hence, do not load other fields of
661 * completion entry *before* the 'valid' is
662 * loaded. Adding the rmb() here prevents the
663 * compiler and/or CPU from reordering the reads
664 * which would potentially result in reading
665 * stale values in completion entry.
666 */
667 rmb();
5216562a 668
e29aa339
RM		 669 len = ntohs(next_cmpl->length);
670 flags = ntohl(next_cmpl->flags);
671
672 nvecs++;
673 totlen += len;
674 } while ((flags & BNA_CQ_EF_EOP) == 0);
675
676 if (!next_cmpl->valid)
677 break;
678 }
ade4dc3e 679 packets++;
e29aa339
RM		 680
681 /* TODO: BNA_CQ_EF_LOCAL ? */
682 if (unlikely(flags & (BNA_CQ_EF_MAC_ERROR |
683 BNA_CQ_EF_FCS_ERROR |
684 BNA_CQ_EF_TOO_LONG))) {
685 bnad_cq_drop_packet(bnad, rcb, sop_ci, nvecs);
8b230ed8 686 rcb->rxq->rx_packets_with_error++;
e29aa339 687
8b230ed8
RM		 688 goto next;
689 }
690
e29aa339
RM		 691 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
692 bnad_cq_setup_skb(bnad, skb, unmap, len);
693 else
694 bnad_cq_setup_skb_frags(rcb, skb, sop_ci, nvecs, len);
30f9fc94 695
e29aa339
RM		 696 rcb->rxq->rx_packets++;
697 rcb->rxq->rx_bytes += totlen;
698 ccb->bytes_per_intr += totlen;
5e46631f
RM		 699
700 masked_flags = flags & flags_cksum_prot_mask;
701
8b230ed8 702 if (likely
e5ee20e7 703 ((bnad->netdev->features & NETIF_F_RXCSUM) &&
5e46631f
RM		 704 ((masked_flags == flags_tcp4) ||
705 (masked_flags == flags_udp4) ||
706 (masked_flags == flags_tcp6) ||
707 (masked_flags == flags_udp6))))
8b230ed8
RM		 708 skb->ip_summed = CHECKSUM_UNNECESSARY;
709 else
bc8acf2c 710 skb_checksum_none_assert(skb);
8b230ed8 711
877767dc
IV		 712 if ((flags & BNA_CQ_EF_VLAN) &&
713 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX))
86a9bad3 714 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(cmpl->vlan_tag));
f859d7cb 715
e29aa339 716 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
f859d7cb 717 netif_receive_skb(skb);
e29aa339
RM		 718 else
719 napi_gro_frags(&rx_ctrl->napi);
8b230ed8
RM		 720
721next:
e29aa339
RM		 722 BNA_QE_INDX_ADD(rcb->consumer_index, nvecs, rcb->q_depth);
723 for (vec = 0; vec < nvecs; vec++) {
724 cmpl = &cq[ccb->producer_index];
725 cmpl->valid = 0;
726 BNA_QE_INDX_INC(ccb->producer_index, ccb->q_depth);
727 }
8b230ed8
RM		 728 }
729
30f9fc94 730 napi_gro_flush(&rx_ctrl->napi, false);
2be67144 731 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
271e8b79
RM		 732 bna_ib_ack_disable_irq(ccb->i_dbell, packets);
733
5216562a 734 bnad_rxq_post(bnad, ccb->rcb[0]);
2be67144 735 if (ccb->rcb[1])
5216562a 736 bnad_rxq_post(bnad, ccb->rcb[1]);
078086f3 737
8b230ed8
RM		 738 return packets;
739}
740
8b230ed8
RM		 741static void
742bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
743{
744 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
be7fa326
RM		 745 struct napi_struct *napi = &rx_ctrl->napi;
746
747 if (likely(napi_schedule_prep(napi))) {
be7fa326 748 __napi_schedule(napi);
271e8b79 749 rx_ctrl->rx_schedule++;
8b230ed8 750 }
8b230ed8
RM		 751}
752
753/* MSIX Rx Path Handler */
754static irqreturn_t
755bnad_msix_rx(int irq, void *data)
756{
757 struct bna_ccb *ccb = (struct bna_ccb *)data;
8b230ed8 758
271e8b79 759 if (ccb) {
ebb56d37 760 ((struct bnad_rx_ctrl *)ccb->ctrl)->rx_intr_ctr++;
2be67144 761 bnad_netif_rx_schedule_poll(ccb->bnad, ccb);
271e8b79 762 }
8b230ed8
RM		 763
764 return IRQ_HANDLED;
765}
766
767/* Interrupt handlers */
768
769/* Mbox Interrupt Handlers */
770static irqreturn_t
771bnad_msix_mbox_handler(int irq, void *data)
772{
773 u32 intr_status;
e2fa6f2e 774 unsigned long flags;
be7fa326 775 struct bnad *bnad = (struct bnad *)data;
8b230ed8 776
8b230ed8 777 spin_lock_irqsave(&bnad->bna_lock, flags);
dfee325a
RM		 778 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
779 spin_unlock_irqrestore(&bnad->bna_lock, flags);
780 return IRQ_HANDLED;
781 }
8b230ed8
RM		 782
783 bna_intr_status_get(&bnad->bna, intr_status);
784
078086f3 785 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
8b230ed8
RM		 786 bna_mbox_handler(&bnad->bna, intr_status);
787
788 spin_unlock_irqrestore(&bnad->bna_lock, flags);
789
8b230ed8
RM		 790 return IRQ_HANDLED;
791}
792
793static irqreturn_t
794bnad_isr(int irq, void *data)
795{
796 int i, j;
797 u32 intr_status;
798 unsigned long flags;
be7fa326 799 struct bnad *bnad = (struct bnad *)data;
8b230ed8
RM		 800 struct bnad_rx_info *rx_info;
801 struct bnad_rx_ctrl *rx_ctrl;
078086f3 802 struct bna_tcb *tcb = NULL;
8b230ed8 803
dfee325a
RM		 804 spin_lock_irqsave(&bnad->bna_lock, flags);
805 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
806 spin_unlock_irqrestore(&bnad->bna_lock, flags);
e2fa6f2e 807 return IRQ_NONE;
dfee325a 808 }
8b230ed8
RM		 809
810 bna_intr_status_get(&bnad->bna, intr_status);
e2fa6f2e 811
dfee325a
RM		 812 if (unlikely(!intr_status)) {
813 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 814 return IRQ_NONE;
dfee325a 815 }
8b230ed8 816
078086f3 817 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
8b230ed8 818 bna_mbox_handler(&bnad->bna, intr_status);
be7fa326 819
8b230ed8
RM		 820 spin_unlock_irqrestore(&bnad->bna_lock, flags);
821
be7fa326
RM		 822 if (!BNA_IS_INTX_DATA_INTR(intr_status))
823 return IRQ_HANDLED;
824
8b230ed8 825 /* Process data interrupts */
be7fa326
RM		 826 /* Tx processing */
827 for (i = 0; i < bnad->num_tx; i++) {
078086f3
RM		 828 for (j = 0; j < bnad->num_txq_per_tx; j++) {
829 tcb = bnad->tx_info[i].tcb[j];
830 if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
b3cc6e88 831 bnad_tx_complete(bnad, bnad->tx_info[i].tcb[j]);
078086f3 832 }
be7fa326
RM		 833 }
834 /* Rx processing */
8b230ed8
RM		 835 for (i = 0; i < bnad->num_rx; i++) {
836 rx_info = &bnad->rx_info[i];
837 if (!rx_info->rx)
838 continue;
839 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
840 rx_ctrl = &rx_info->rx_ctrl[j];
841 if (rx_ctrl->ccb)
842 bnad_netif_rx_schedule_poll(bnad,
843 rx_ctrl->ccb);
844 }
845 }
8b230ed8
RM		 846 return IRQ_HANDLED;
847}
848
849/*
850 * Called in interrupt / callback context
851 * with bna_lock held, so cfg_flags access is OK
852 */
853static void
854bnad_enable_mbox_irq(struct bnad *bnad)
855{
be7fa326 856 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
e2fa6f2e 857
8b230ed8
RM		 858 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
859}
860
861/*
862 * Called with bnad->bna_lock held b'cos of
863 * bnad->cfg_flags access.
864 */
b7ee31c5 865static void
8b230ed8
RM		 866bnad_disable_mbox_irq(struct bnad *bnad)
867{
be7fa326 868 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
8b230ed8 869
be7fa326
RM		 870 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
871}
8b230ed8 872
be7fa326
RM		 873static void
874bnad_set_netdev_perm_addr(struct bnad *bnad)
875{
876 struct net_device *netdev = bnad->netdev;
e2fa6f2e 877
d6b30598 878 ether_addr_copy(netdev->perm_addr, bnad->perm_addr);
be7fa326 879 if (is_zero_ether_addr(netdev->dev_addr))
d6b30598 880 ether_addr_copy(netdev->dev_addr, bnad->perm_addr);
8b230ed8
RM		 881}
882
883/* Control Path Handlers */
884
885/* Callbacks */
886void
078086f3 887bnad_cb_mbox_intr_enable(struct bnad *bnad)
8b230ed8
RM		 888{
889 bnad_enable_mbox_irq(bnad);
890}
891
892void
078086f3 893bnad_cb_mbox_intr_disable(struct bnad *bnad)
8b230ed8
RM		 894{
895 bnad_disable_mbox_irq(bnad);
896}
897
898void
078086f3
RM		 899bnad_cb_ioceth_ready(struct bnad *bnad)
900{
901 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
902 complete(&bnad->bnad_completions.ioc_comp);
903}
904
905void
906bnad_cb_ioceth_failed(struct bnad *bnad)
8b230ed8 907{
078086f3 908 bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL;
8b230ed8 909 complete(&bnad->bnad_completions.ioc_comp);
8b230ed8
RM		 910}
911
912void
078086f3 913bnad_cb_ioceth_disabled(struct bnad *bnad)
8b230ed8 914{
078086f3 915 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
8b230ed8 916 complete(&bnad->bnad_completions.ioc_comp);
8b230ed8
RM		 917}
918
919static void
078086f3 920bnad_cb_enet_disabled(void *arg)
8b230ed8
RM		 921{
922 struct bnad *bnad = (struct bnad *)arg;
923
8b230ed8 924 netif_carrier_off(bnad->netdev);
078086f3 925 complete(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 926}
927
928void
078086f3 929bnad_cb_ethport_link_status(struct bnad *bnad,
8b230ed8
RM		 930 enum bna_link_status link_status)
931{
3db1cd5c 932 bool link_up = false;
8b230ed8
RM		 933
934 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
935
936 if (link_status == BNA_CEE_UP) {
078086f3
RM		 937 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
938 BNAD_UPDATE_CTR(bnad, cee_toggle);
8b230ed8 939 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
078086f3
RM		 940 } else {
941 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
942 BNAD_UPDATE_CTR(bnad, cee_toggle);
8b230ed8 943 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
078086f3 944 }
8b230ed8
RM		 945
946 if (link_up) {
947 if (!netif_carrier_ok(bnad->netdev)) {
078086f3 948 uint tx_id, tcb_id;
ecc46789 949 netdev_info(bnad->netdev, "link up\n");
8b230ed8
RM		 950 netif_carrier_on(bnad->netdev);
951 BNAD_UPDATE_CTR(bnad, link_toggle);
078086f3
RM		 952 for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) {
953 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx;
954 tcb_id++) {
955 struct bna_tcb *tcb =
956 bnad->tx_info[tx_id].tcb[tcb_id];
957 u32 txq_id;
958 if (!tcb)
959 continue;
960
961 txq_id = tcb->id;
962
963 if (test_bit(BNAD_TXQ_TX_STARTED,
964 &tcb->flags)) {
965 /*
966 * Force an immediate
967 * Transmit Schedule */
078086f3
RM		 968 netif_wake_subqueue(
969 bnad->netdev,
970 txq_id);
971 BNAD_UPDATE_CTR(bnad,
972 netif_queue_wakeup);
973 } else {
974 netif_stop_subqueue(
975 bnad->netdev,
976 txq_id);
977 BNAD_UPDATE_CTR(bnad,
978 netif_queue_stop);
979 }
980 }
8b230ed8
RM		 981 }
982 }
983 } else {
984 if (netif_carrier_ok(bnad->netdev)) {
ecc46789 985 netdev_info(bnad->netdev, "link down\n");
8b230ed8
RM		 986 netif_carrier_off(bnad->netdev);
987 BNAD_UPDATE_CTR(bnad, link_toggle);
988 }
989 }
990}
991
992static void
078086f3 993bnad_cb_tx_disabled(void *arg, struct bna_tx *tx)
8b230ed8
RM		 994{
995 struct bnad *bnad = (struct bnad *)arg;
996
997 complete(&bnad->bnad_completions.tx_comp);
998}
999
1000static void
1001bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
1002{
1003 struct bnad_tx_info *tx_info =
1004 (struct bnad_tx_info *)tcb->txq->tx->priv;
8b230ed8 1005
5216562a 1006 tcb->priv = tcb;
8b230ed8 1007 tx_info->tcb[tcb->id] = tcb;
8b230ed8
RM		 1008}
1009
1010static void
1011bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
1012{
1013 struct bnad_tx_info *tx_info =
1014 (struct bnad_tx_info *)tcb->txq->tx->priv;
1015
1016 tx_info->tcb[tcb->id] = NULL;
01b54b14 1017 tcb->priv = NULL;
8b230ed8
RM		 1018}
1019
8b230ed8
RM		 1020static void
1021bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
1022{
1023 struct bnad_rx_info *rx_info =
1024 (struct bnad_rx_info *)ccb->cq->rx->priv;
1025
1026 rx_info->rx_ctrl[ccb->id].ccb = ccb;
1027 ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
1028}
1029
1030static void
1031bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
1032{
1033 struct bnad_rx_info *rx_info =
1034 (struct bnad_rx_info *)ccb->cq->rx->priv;
1035
1036 rx_info->rx_ctrl[ccb->id].ccb = NULL;
1037}
1038
1039static void
078086f3 1040bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx)
8b230ed8
RM		 1041{
1042 struct bnad_tx_info *tx_info =
078086f3
RM		 1043 (struct bnad_tx_info *)tx->priv;
1044 struct bna_tcb *tcb;
1045 u32 txq_id;
1046 int i;
8b230ed8 1047
078086f3
RM		 1048 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1049 tcb = tx_info->tcb[i];
1050 if (!tcb)
1051 continue;
1052 txq_id = tcb->id;
1053 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
1054 netif_stop_subqueue(bnad->netdev, txq_id);
078086f3 1055 }
8b230ed8
RM		 1056}
1057
1058static void
078086f3 1059bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx)
8b230ed8 1060{
078086f3
RM		 1061 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
1062 struct bna_tcb *tcb;
078086f3
RM		 1063 u32 txq_id;
1064 int i;
8b230ed8 1065
078086f3
RM		 1066 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1067 tcb = tx_info->tcb[i];
1068 if (!tcb)
1069 continue;
1070 txq_id = tcb->id;
8b230ed8 1071
01b54b14 1072 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags));
078086f3 1073 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
01b54b14 1074 BUG_ON(*(tcb->hw_consumer_index) != 0);
078086f3
RM		 1075
1076 if (netif_carrier_ok(bnad->netdev)) {
078086f3
RM		 1077 netif_wake_subqueue(bnad->netdev, txq_id);
1078 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
1079 }
1080 }
be7fa326
RM		 1081
1082 /*
078086f3 1083 * Workaround for first ioceth enable failure & we
be7fa326
RM		 1084 * get a 0 MAC address. We try to get the MAC address
1085 * again here.
1086 */
d6b30598
IV		 1087 if (is_zero_ether_addr(bnad->perm_addr)) {
1088 bna_enet_perm_mac_get(&bnad->bna.enet, bnad->perm_addr);
be7fa326
RM		 1089 bnad_set_netdev_perm_addr(bnad);
1090 }
be7fa326
RM		 1091}
1092
01b54b14
JH		 1093/*
1094 * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm.
1095 */
1096static void
1097bnad_tx_cleanup(struct delayed_work *work)
1098{
1099 struct bnad_tx_info *tx_info =
1100 container_of(work, struct bnad_tx_info, tx_cleanup_work);
1101 struct bnad *bnad = NULL;
01b54b14
JH		 1102 struct bna_tcb *tcb;
1103 unsigned long flags;
5216562a 1104 u32 i, pending = 0;
01b54b14
JH		 1105
1106 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1107 tcb = tx_info->tcb[i];
1108 if (!tcb)
1109 continue;
1110
1111 bnad = tcb->bnad;
1112
1113 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
1114 pending++;
1115 continue;
1116 }
1117
b3cc6e88 1118 bnad_txq_cleanup(bnad, tcb);
01b54b14 1119
4e857c58 1120 smp_mb__before_atomic();
01b54b14
JH		 1121 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
1122 }
1123
1124 if (pending) {
1125 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work,
1126 msecs_to_jiffies(1));
1127 return;
1128 }
1129
1130 spin_lock_irqsave(&bnad->bna_lock, flags);
1131 bna_tx_cleanup_complete(tx_info->tx);
1132 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1133}
1134
be7fa326 1135static void
078086f3 1136bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx)
be7fa326 1137{
078086f3
RM		 1138 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
1139 struct bna_tcb *tcb;
1140 int i;
1141
1142 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1143 tcb = tx_info->tcb[i];
1144 if (!tcb)
1145 continue;
1146 }
1147
01b54b14 1148 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0);
8b230ed8
RM		 1149}
1150
5bcf6ac0
RM		 1151static void
1152bnad_cb_rx_stall(struct bnad *bnad, struct bna_rx *rx)
1153{
1154 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1155 struct bna_ccb *ccb;
1156 struct bnad_rx_ctrl *rx_ctrl;
1157 int i;
1158
1159 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1160 rx_ctrl = &rx_info->rx_ctrl[i];
1161 ccb = rx_ctrl->ccb;
1162 if (!ccb)
1163 continue;
1164
1165 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[0]->flags);
1166
1167 if (ccb->rcb[1])
1168 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[1]->flags);
1169 }
1170}
1171
01b54b14
JH		 1172/*
1173 * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm.
1174 */
1175static void
1176bnad_rx_cleanup(void *work)
1177{
1178 struct bnad_rx_info *rx_info =
1179 container_of(work, struct bnad_rx_info, rx_cleanup_work);
1180 struct bnad_rx_ctrl *rx_ctrl;
1181 struct bnad *bnad = NULL;
1182 unsigned long flags;
5216562a 1183 u32 i;
01b54b14
JH		 1184
1185 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1186 rx_ctrl = &rx_info->rx_ctrl[i];
1187
1188 if (!rx_ctrl->ccb)
1189 continue;
1190
1191 bnad = rx_ctrl->ccb->bnad;
1192
1193 /*
1194 * Wait till the poll handler has exited
1195 * and nothing can be scheduled anymore
1196 */
1197 napi_disable(&rx_ctrl->napi);
1198
b3cc6e88
JH		 1199 bnad_cq_cleanup(bnad, rx_ctrl->ccb);
1200 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[0]);
01b54b14 1201 if (rx_ctrl->ccb->rcb[1])
b3cc6e88 1202 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[1]);
01b54b14
JH		 1203 }
1204
1205 spin_lock_irqsave(&bnad->bna_lock, flags);
1206 bna_rx_cleanup_complete(rx_info->rx);
1207 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1208}
1209
8b230ed8 1210static void
078086f3 1211bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1212{
078086f3
RM		 1213 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1214 struct bna_ccb *ccb;
1215 struct bnad_rx_ctrl *rx_ctrl;
1216 int i;
1217
772b5235 1218 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
078086f3
RM		 1219 rx_ctrl = &rx_info->rx_ctrl[i];
1220 ccb = rx_ctrl->ccb;
1221 if (!ccb)
1222 continue;
1223
1224 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
1225
1226 if (ccb->rcb[1])
1227 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
078086f3 1228 }
be7fa326 1229
01b54b14 1230 queue_work(bnad->work_q, &rx_info->rx_cleanup_work);
8b230ed8
RM		 1231}
1232
1233static void
078086f3 1234bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1235{
078086f3
RM		 1236 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1237 struct bna_ccb *ccb;
1238 struct bna_rcb *rcb;
1239 struct bnad_rx_ctrl *rx_ctrl;
30f9fc94 1240 int i, j;
be7fa326 1241
772b5235 1242 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
078086f3
RM		 1243 rx_ctrl = &rx_info->rx_ctrl[i];
1244 ccb = rx_ctrl->ccb;
1245 if (!ccb)
1246 continue;
be7fa326 1247
01b54b14 1248 napi_enable(&rx_ctrl->napi);
8b230ed8 1249
078086f3
RM		 1250 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) {
1251 rcb = ccb->rcb[j];
1252 if (!rcb)
1253 continue;
078086f3 1254
30f9fc94 1255 bnad_rxq_alloc_init(bnad, rcb);
078086f3 1256 set_bit(BNAD_RXQ_STARTED, &rcb->flags);
5bcf6ac0 1257 set_bit(BNAD_RXQ_POST_OK, &rcb->flags);
5216562a 1258 bnad_rxq_post(bnad, rcb);
078086f3 1259 }
8b230ed8
RM		 1260 }
1261}
1262
1263static void
078086f3 1264bnad_cb_rx_disabled(void *arg, struct bna_rx *rx)
8b230ed8
RM		 1265{
1266 struct bnad *bnad = (struct bnad *)arg;
1267
1268 complete(&bnad->bnad_completions.rx_comp);
1269}
1270
1271static void
078086f3 1272bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx)
8b230ed8 1273{
078086f3 1274 bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS;
8b230ed8
RM		 1275 complete(&bnad->bnad_completions.mcast_comp);
1276}
1277
1278void
1279bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
1280 struct bna_stats *stats)
1281{
1282 if (status == BNA_CB_SUCCESS)
1283 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
1284
1285 if (!netif_running(bnad->netdev) ||
1286 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1287 return;
1288
1289 mod_timer(&bnad->stats_timer,
1290 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1291}
1292
078086f3
RM		 1293static void
1294bnad_cb_enet_mtu_set(struct bnad *bnad)
1295{
1296 bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS;
1297 complete(&bnad->bnad_completions.mtu_comp);
1298}
1299
72a9730b
KG		 1300void
1301bnad_cb_completion(void *arg, enum bfa_status status)
1302{
1303 struct bnad_iocmd_comp *iocmd_comp =
1304 (struct bnad_iocmd_comp *)arg;
1305
1306 iocmd_comp->comp_status = (u32) status;
1307 complete(&iocmd_comp->comp);
1308}
1309
8b230ed8
RM		 1310/* Resource allocation, free functions */
1311
1312static void
1313bnad_mem_free(struct bnad *bnad,
1314 struct bna_mem_info *mem_info)
1315{
1316 int i;
1317 dma_addr_t dma_pa;
1318
1319 if (mem_info->mdl == NULL)
1320 return;
1321
1322 for (i = 0; i < mem_info->num; i++) {
1323 if (mem_info->mdl[i].kva != NULL) {
1324 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1325 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
1326 dma_pa);
5ea74318
IV		 1327 dma_free_coherent(&bnad->pcidev->dev,
1328 mem_info->mdl[i].len,
1329 mem_info->mdl[i].kva, dma_pa);
8b230ed8
RM		 1330 } else
1331 kfree(mem_info->mdl[i].kva);
1332 }
1333 }
1334 kfree(mem_info->mdl);
1335 mem_info->mdl = NULL;
1336}
1337
1338static int
1339bnad_mem_alloc(struct bnad *bnad,
1340 struct bna_mem_info *mem_info)
1341{
1342 int i;
1343 dma_addr_t dma_pa;
1344
1345 if ((mem_info->num == 0) || (mem_info->len == 0)) {
1346 mem_info->mdl = NULL;
1347 return 0;
1348 }
1349
1350 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1351 GFP_KERNEL);
1352 if (mem_info->mdl == NULL)
1353 return -ENOMEM;
1354
1355 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1356 for (i = 0; i < mem_info->num; i++) {
1357 mem_info->mdl[i].len = mem_info->len;
1358 mem_info->mdl[i].kva =
5ea74318 1359 dma_alloc_coherent(&bnad->pcidev->dev,
1f9061d2
JP		 1360 mem_info->len, &dma_pa,
1361 GFP_KERNEL);
8b230ed8
RM		 1362 if (mem_info->mdl[i].kva == NULL)
1363 goto err_return;
1364
1365 BNA_SET_DMA_ADDR(dma_pa,
1366 &(mem_info->mdl[i].dma));
1367 }
1368 } else {
1369 for (i = 0; i < mem_info->num; i++) {
1370 mem_info->mdl[i].len = mem_info->len;
1371 mem_info->mdl[i].kva = kzalloc(mem_info->len,
1372 GFP_KERNEL);
1373 if (mem_info->mdl[i].kva == NULL)
1374 goto err_return;
1375 }
1376 }
1377
1378 return 0;
1379
1380err_return:
1381 bnad_mem_free(bnad, mem_info);
1382 return -ENOMEM;
1383}
1384
1385/* Free IRQ for Mailbox */
1386static void
078086f3 1387bnad_mbox_irq_free(struct bnad *bnad)
8b230ed8
RM		 1388{
1389 int irq;
1390 unsigned long flags;
1391
8b230ed8 1392 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 1393 bnad_disable_mbox_irq(bnad);
e2fa6f2e 1394 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1395
1396 irq = BNAD_GET_MBOX_IRQ(bnad);
be7fa326 1397 free_irq(irq, bnad);
8b230ed8
RM		 1398}
1399
1400/*
1401 * Allocates IRQ for Mailbox, but keep it disabled
1402 * This will be enabled once we get the mbox enable callback
1403 * from bna
1404 */
1405static int
078086f3 1406bnad_mbox_irq_alloc(struct bnad *bnad)
8b230ed8 1407{
0120b99c
RM		 1408 int err = 0;
1409 unsigned long irq_flags, flags;
8b230ed8 1410 u32 irq;
0120b99c 1411 irq_handler_t irq_handler;
8b230ed8 1412
8b230ed8
RM		 1413 spin_lock_irqsave(&bnad->bna_lock, flags);
1414 if (bnad->cfg_flags & BNAD_CF_MSIX) {
1415 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
8811e267 1416 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
8279171a 1417 irq_flags = 0;
8b230ed8
RM		 1418 } else {
1419 irq_handler = (irq_handler_t)bnad_isr;
1420 irq = bnad->pcidev->irq;
5f77898d 1421 irq_flags = IRQF_SHARED;
8b230ed8 1422 }
8811e267 1423
8b230ed8 1424 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1425 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1426
e2fa6f2e
RM		 1427 /*
1428 * Set the Mbox IRQ disable flag, so that the IRQ handler
1429 * called from request_irq() for SHARED IRQs do not execute
1430 */
1431 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
1432
be7fa326
RM		 1433 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
1434
8279171a 1435 err = request_irq(irq, irq_handler, irq_flags,
be7fa326 1436 bnad->mbox_irq_name, bnad);
e2fa6f2e 1437
be7fa326 1438 return err;
8b230ed8
RM		 1439}
1440
1441static void
1442bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1443{
1444 kfree(intr_info->idl);
1445 intr_info->idl = NULL;
1446}
1447
1448/* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1449static int
1450bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
078086f3 1451 u32 txrx_id, struct bna_intr_info *intr_info)
8b230ed8
RM		 1452{
1453 int i, vector_start = 0;
1454 u32 cfg_flags;
1455 unsigned long flags;
1456
1457 spin_lock_irqsave(&bnad->bna_lock, flags);
1458 cfg_flags = bnad->cfg_flags;
1459 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1460
1461 if (cfg_flags & BNAD_CF_MSIX) {
1462 intr_info->intr_type = BNA_INTR_T_MSIX;
1463 intr_info->idl = kcalloc(intr_info->num,
1464 sizeof(struct bna_intr_descr),
1465 GFP_KERNEL);
1466 if (!intr_info->idl)
1467 return -ENOMEM;
1468
1469 switch (src) {
1470 case BNAD_INTR_TX:
8811e267 1471 vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id;
8b230ed8
RM		 1472 break;
1473
1474 case BNAD_INTR_RX:
8811e267
RM		 1475 vector_start = BNAD_MAILBOX_MSIX_VECTORS +
1476 (bnad->num_tx * bnad->num_txq_per_tx) +
8b230ed8
RM		 1477 txrx_id;
1478 break;
1479
1480 default:
1481 BUG();
1482 }
1483
1484 for (i = 0; i < intr_info->num; i++)
1485 intr_info->idl[i].vector = vector_start + i;
1486 } else {
1487 intr_info->intr_type = BNA_INTR_T_INTX;
1488 intr_info->num = 1;
1489 intr_info->idl = kcalloc(intr_info->num,
1490 sizeof(struct bna_intr_descr),
1491 GFP_KERNEL);
1492 if (!intr_info->idl)
1493 return -ENOMEM;
1494
1495 switch (src) {
1496 case BNAD_INTR_TX:
8811e267 1497 intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK;
8b230ed8
RM		 1498 break;
1499
1500 case BNAD_INTR_RX:
8811e267 1501 intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK;
8b230ed8
RM		 1502 break;
1503 }
1504 }
1505 return 0;
1506}
1507
1aa8b471 1508/* NOTE: Should be called for MSIX only
8b230ed8
RM		 1509 * Unregisters Tx MSIX vector(s) from the kernel
1510 */
1511static void
1512bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1513 int num_txqs)
1514{
1515 int i;
1516 int vector_num;
1517
1518 for (i = 0; i < num_txqs; i++) {
1519 if (tx_info->tcb[i] == NULL)
1520 continue;
1521
1522 vector_num = tx_info->tcb[i]->intr_vector;
1523 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1524 }
1525}
1526
1aa8b471 1527/* NOTE: Should be called for MSIX only
8b230ed8
RM		 1528 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1529 */
1530static int
1531bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
078086f3 1532 u32 tx_id, int num_txqs)
8b230ed8
RM		 1533{
1534 int i;
1535 int err;
1536 int vector_num;
1537
1538 for (i = 0; i < num_txqs; i++) {
1539 vector_num = tx_info->tcb[i]->intr_vector;
1540 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1541 tx_id + tx_info->tcb[i]->id);
1542 err = request_irq(bnad->msix_table[vector_num].vector,
1543 (irq_handler_t)bnad_msix_tx, 0,
1544 tx_info->tcb[i]->name,
1545 tx_info->tcb[i]);
1546 if (err)
1547 goto err_return;
1548 }
1549
1550 return 0;
1551
1552err_return:
1553 if (i > 0)
1554 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1555 return -1;
1556}
1557
1aa8b471 1558/* NOTE: Should be called for MSIX only
8b230ed8
RM		 1559 * Unregisters Rx MSIX vector(s) from the kernel
1560 */
1561static void
1562bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1563 int num_rxps)
1564{
1565 int i;
1566 int vector_num;
1567
1568 for (i = 0; i < num_rxps; i++) {
1569 if (rx_info->rx_ctrl[i].ccb == NULL)
1570 continue;
1571
1572 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1573 free_irq(bnad->msix_table[vector_num].vector,
1574 rx_info->rx_ctrl[i].ccb);
1575 }
1576}
1577
1aa8b471 1578/* NOTE: Should be called for MSIX only
8b230ed8
RM		 1579 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1580 */
1581static int
1582bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
078086f3 1583 u32 rx_id, int num_rxps)
8b230ed8
RM		 1584{
1585 int i;
1586 int err;
1587 int vector_num;
1588
1589 for (i = 0; i < num_rxps; i++) {
1590 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1591 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1592 bnad->netdev->name,
1593 rx_id + rx_info->rx_ctrl[i].ccb->id);
1594 err = request_irq(bnad->msix_table[vector_num].vector,
1595 (irq_handler_t)bnad_msix_rx, 0,
1596 rx_info->rx_ctrl[i].ccb->name,
1597 rx_info->rx_ctrl[i].ccb);
1598 if (err)
1599 goto err_return;
1600 }
1601
1602 return 0;
1603
1604err_return:
1605 if (i > 0)
1606 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1607 return -1;
1608}
1609
1610/* Free Tx object Resources */
1611static void
1612bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1613{
1614 int i;
1615
1616 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1617 if (res_info[i].res_type == BNA_RES_T_MEM)
1618 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1619 else if (res_info[i].res_type == BNA_RES_T_INTR)
1620 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1621 }
1622}
1623
1624/* Allocates memory and interrupt resources for Tx object */
1625static int
1626bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
078086f3 1627 u32 tx_id)
8b230ed8
RM		 1628{
1629 int i, err = 0;
1630
1631 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1632 if (res_info[i].res_type == BNA_RES_T_MEM)
1633 err = bnad_mem_alloc(bnad,
1634 &res_info[i].res_u.mem_info);
1635 else if (res_info[i].res_type == BNA_RES_T_INTR)
1636 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1637 &res_info[i].res_u.intr_info);
1638 if (err)
1639 goto err_return;
1640 }
1641 return 0;
1642
1643err_return:
1644 bnad_tx_res_free(bnad, res_info);
1645 return err;
1646}
1647
1648/* Free Rx object Resources */
1649static void
1650bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1651{
1652 int i;
1653
1654 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1655 if (res_info[i].res_type == BNA_RES_T_MEM)
1656 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1657 else if (res_info[i].res_type == BNA_RES_T_INTR)
1658 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1659 }
1660}
1661
1662/* Allocates memory and interrupt resources for Rx object */
1663static int
1664bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1665 uint rx_id)
1666{
1667 int i, err = 0;
1668
1669 /* All memory needs to be allocated before setup_ccbs */
1670 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1671 if (res_info[i].res_type == BNA_RES_T_MEM)
1672 err = bnad_mem_alloc(bnad,
1673 &res_info[i].res_u.mem_info);
1674 else if (res_info[i].res_type == BNA_RES_T_INTR)
1675 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1676 &res_info[i].res_u.intr_info);
1677 if (err)
1678 goto err_return;
1679 }
1680 return 0;
1681
1682err_return:
1683 bnad_rx_res_free(bnad, res_info);
1684 return err;
1685}
1686
1687/* Timer callbacks */
1688/* a) IOC timer */
1689static void
1690bnad_ioc_timeout(unsigned long data)
1691{
1692 struct bnad *bnad = (struct bnad *)data;
1693 unsigned long flags;
1694
1695 spin_lock_irqsave(&bnad->bna_lock, flags);
ad24d6f0 1696 bfa_nw_ioc_timeout(&bnad->bna.ioceth.ioc);
8b230ed8
RM		 1697 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1698}
1699
1700static void
1701bnad_ioc_hb_check(unsigned long data)
1702{
1703 struct bnad *bnad = (struct bnad *)data;
1704 unsigned long flags;
1705
1706 spin_lock_irqsave(&bnad->bna_lock, flags);
ad24d6f0 1707 bfa_nw_ioc_hb_check(&bnad->bna.ioceth.ioc);
8b230ed8
RM		 1708 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1709}
1710
1711static void
1d32f769 1712bnad_iocpf_timeout(unsigned long data)
8b230ed8
RM		 1713{
1714 struct bnad *bnad = (struct bnad *)data;
1715 unsigned long flags;
1716
1717 spin_lock_irqsave(&bnad->bna_lock, flags);
ad24d6f0 1718 bfa_nw_iocpf_timeout(&bnad->bna.ioceth.ioc);
1d32f769
RM		 1719 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1720}
1721
1722static void
1723bnad_iocpf_sem_timeout(unsigned long data)
1724{
1725 struct bnad *bnad = (struct bnad *)data;
1726 unsigned long flags;
1727
1728 spin_lock_irqsave(&bnad->bna_lock, flags);
ad24d6f0 1729 bfa_nw_iocpf_sem_timeout(&bnad->bna.ioceth.ioc);
8b230ed8
RM		 1730 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1731}
1732
1733/*
1734 * All timer routines use bnad->bna_lock to protect against
1735 * the following race, which may occur in case of no locking:
0120b99c 1736 * Time CPU m CPU n
8b230ed8
RM		 1737 * 0 1 = test_bit
1738 * 1 clear_bit
1739 * 2 del_timer_sync
1740 * 3 mod_timer
1741 */
1742
1743/* b) Dynamic Interrupt Moderation Timer */
1744static void
1745bnad_dim_timeout(unsigned long data)
1746{
1747 struct bnad *bnad = (struct bnad *)data;
1748 struct bnad_rx_info *rx_info;
1749 struct bnad_rx_ctrl *rx_ctrl;
1750 int i, j;
1751 unsigned long flags;
1752
1753 if (!netif_carrier_ok(bnad->netdev))
1754 return;
1755
1756 spin_lock_irqsave(&bnad->bna_lock, flags);
1757 for (i = 0; i < bnad->num_rx; i++) {
1758 rx_info = &bnad->rx_info[i];
1759 if (!rx_info->rx)
1760 continue;
1761 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1762 rx_ctrl = &rx_info->rx_ctrl[j];
1763 if (!rx_ctrl->ccb)
1764 continue;
1765 bna_rx_dim_update(rx_ctrl->ccb);
1766 }
1767 }
1768
1769 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1770 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1771 mod_timer(&bnad->dim_timer,
1772 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1773 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1774}
1775
1776/* c) Statistics Timer */
1777static void
1778bnad_stats_timeout(unsigned long data)
1779{
1780 struct bnad *bnad = (struct bnad *)data;
1781 unsigned long flags;
1782
1783 if (!netif_running(bnad->netdev) ||
1784 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1785 return;
1786
1787 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3 1788 bna_hw_stats_get(&bnad->bna);
8b230ed8
RM		 1789 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1790}
1791
1792/*
1793 * Set up timer for DIM
1794 * Called with bnad->bna_lock held
1795 */
1796void
1797bnad_dim_timer_start(struct bnad *bnad)
1798{
1799 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1800 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1801 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1802 (unsigned long)bnad);
1803 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1804 mod_timer(&bnad->dim_timer,
1805 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1806 }
1807}
1808
1809/*
1810 * Set up timer for statistics
1811 * Called with mutex_lock(&bnad->conf_mutex) held
1812 */
1813static void
1814bnad_stats_timer_start(struct bnad *bnad)
1815{
1816 unsigned long flags;
1817
1818 spin_lock_irqsave(&bnad->bna_lock, flags);
1819 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1820 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1821 (unsigned long)bnad);
1822 mod_timer(&bnad->stats_timer,
1823 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1824 }
1825 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 1826}
1827
1828/*
1829 * Stops the stats timer
1830 * Called with mutex_lock(&bnad->conf_mutex) held
1831 */
1832static void
1833bnad_stats_timer_stop(struct bnad *bnad)
1834{
1835 int to_del = 0;
1836 unsigned long flags;
1837
1838 spin_lock_irqsave(&bnad->bna_lock, flags);
1839 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1840 to_del = 1;
1841 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1842 if (to_del)
1843 del_timer_sync(&bnad->stats_timer);
1844}
1845
1846/* Utilities */
1847
1848static void
1849bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1850{
1851 int i = 1; /* Index 0 has broadcast address */
1852 struct netdev_hw_addr *mc_addr;
1853
1854 netdev_for_each_mc_addr(mc_addr, netdev) {
e2f9ecfc 1855 ether_addr_copy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0]);
8b230ed8
RM		 1856 i++;
1857 }
1858}
1859
1860static int
1861bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1862{
1863 struct bnad_rx_ctrl *rx_ctrl =
1864 container_of(napi, struct bnad_rx_ctrl, napi);
2be67144 1865 struct bnad *bnad = rx_ctrl->bnad;
8b230ed8
RM		 1866 int rcvd = 0;
1867
271e8b79 1868 rx_ctrl->rx_poll_ctr++;
8b230ed8
RM		 1869
1870 if (!netif_carrier_ok(bnad->netdev))
1871 goto poll_exit;
1872
b3cc6e88 1873 rcvd = bnad_cq_process(bnad, rx_ctrl->ccb, budget);
271e8b79 1874 if (rcvd >= budget)
8b230ed8
RM		 1875 return rcvd;
1876
1877poll_exit:
19dbff9f 1878 napi_complete(napi);
8b230ed8 1879
271e8b79 1880 rx_ctrl->rx_complete++;
2be67144
RM		 1881
1882 if (rx_ctrl->ccb)
271e8b79
RM		 1883 bnad_enable_rx_irq_unsafe(rx_ctrl->ccb);
1884
8b230ed8
RM		 1885 return rcvd;
1886}
1887
2be67144 1888#define BNAD_NAPI_POLL_QUOTA 64
8b230ed8 1889static void
01b54b14 1890bnad_napi_add(struct bnad *bnad, u32 rx_id)
8b230ed8 1891{
8b230ed8
RM		 1892 struct bnad_rx_ctrl *rx_ctrl;
1893 int i;
8b230ed8
RM		 1894
1895 /* Initialize & enable NAPI */
1896 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1897 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
1898 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
2be67144
RM		 1899 bnad_napi_poll_rx, BNAD_NAPI_POLL_QUOTA);
1900 }
1901}
1902
1903static void
01b54b14 1904bnad_napi_delete(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 1905{
1906 int i;
1907
1908 /* First disable and then clean up */
01b54b14 1909 for (i = 0; i < bnad->num_rxp_per_rx; i++)
8b230ed8 1910 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
8b230ed8
RM		 1911}
1912
1913/* Should be held with conf_lock held */
1914void
b3cc6e88 1915bnad_destroy_tx(struct bnad *bnad, u32 tx_id)
8b230ed8
RM		 1916{
1917 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1918 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1919 unsigned long flags;
1920
1921 if (!tx_info->tx)
1922 return;
1923
1924 init_completion(&bnad->bnad_completions.tx_comp);
1925 spin_lock_irqsave(&bnad->bna_lock, flags);
1926 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1927 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1928 wait_for_completion(&bnad->bnad_completions.tx_comp);
1929
1930 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1931 bnad_tx_msix_unregister(bnad, tx_info,
1932 bnad->num_txq_per_tx);
1933
1934 spin_lock_irqsave(&bnad->bna_lock, flags);
1935 bna_tx_destroy(tx_info->tx);
1936 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1937
1938 tx_info->tx = NULL;
078086f3 1939 tx_info->tx_id = 0;
8b230ed8 1940
8b230ed8
RM		 1941 bnad_tx_res_free(bnad, res_info);
1942}
1943
1944/* Should be held with conf_lock held */
1945int
078086f3 1946bnad_setup_tx(struct bnad *bnad, u32 tx_id)
8b230ed8
RM		 1947{
1948 int err;
1949 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1950 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1951 struct bna_intr_info *intr_info =
1952 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1953 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
d91d25d5 1954 static const struct bna_tx_event_cbfn tx_cbfn = {
1955 .tcb_setup_cbfn = bnad_cb_tcb_setup,
1956 .tcb_destroy_cbfn = bnad_cb_tcb_destroy,
1957 .tx_stall_cbfn = bnad_cb_tx_stall,
1958 .tx_resume_cbfn = bnad_cb_tx_resume,
1959 .tx_cleanup_cbfn = bnad_cb_tx_cleanup,
1960 };
1961
8b230ed8
RM		 1962 struct bna_tx *tx;
1963 unsigned long flags;
1964
078086f3
RM		 1965 tx_info->tx_id = tx_id;
1966
8b230ed8
RM		 1967 /* Initialize the Tx object configuration */
1968 tx_config->num_txq = bnad->num_txq_per_tx;
1969 tx_config->txq_depth = bnad->txq_depth;
1970 tx_config->tx_type = BNA_TX_T_REGULAR;
078086f3 1971 tx_config->coalescing_timeo = bnad->tx_coalescing_timeo;
8b230ed8 1972
8b230ed8
RM		 1973 /* Get BNA's resource requirement for one tx object */
1974 spin_lock_irqsave(&bnad->bna_lock, flags);
1975 bna_tx_res_req(bnad->num_txq_per_tx,
1976 bnad->txq_depth, res_info);
1977 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1978
1979 /* Fill Unmap Q memory requirements */
5216562a
RM		 1980 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1981 bnad->num_txq_per_tx, (sizeof(struct bnad_tx_unmap) *
1982 bnad->txq_depth));
8b230ed8
RM		 1983
1984 /* Allocate resources */
1985 err = bnad_tx_res_alloc(bnad, res_info, tx_id);
1986 if (err)
1987 return err;
1988
1989 /* Ask BNA to create one Tx object, supplying required resources */
1990 spin_lock_irqsave(&bnad->bna_lock, flags);
1991 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
1992 tx_info);
1993 spin_unlock_irqrestore(&bnad->bna_lock, flags);
f29eeb79
RM		 1994 if (!tx) {
1995 err = -ENOMEM;
8b230ed8 1996 goto err_return;
f29eeb79 1997 }
8b230ed8
RM		 1998 tx_info->tx = tx;
1999
01b54b14
JH		 2000 INIT_DELAYED_WORK(&tx_info->tx_cleanup_work,
2001 (work_func_t)bnad_tx_cleanup);
2002
8b230ed8
RM		 2003 /* Register ISR for the Tx object */
2004 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
2005 err = bnad_tx_msix_register(bnad, tx_info,
2006 tx_id, bnad->num_txq_per_tx);
2007 if (err)
f29eeb79 2008 goto cleanup_tx;
8b230ed8
RM		 2009 }
2010
2011 spin_lock_irqsave(&bnad->bna_lock, flags);
2012 bna_tx_enable(tx);
2013 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2014
2015 return 0;
2016
f29eeb79
RM		 2017cleanup_tx:
2018 spin_lock_irqsave(&bnad->bna_lock, flags);
2019 bna_tx_destroy(tx_info->tx);
2020 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2021 tx_info->tx = NULL;
2022 tx_info->tx_id = 0;
8b230ed8
RM		 2023err_return:
2024 bnad_tx_res_free(bnad, res_info);
2025 return err;
2026}
2027
2028/* Setup the rx config for bna_rx_create */
2029/* bnad decides the configuration */
2030static void
2031bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
2032{
e29aa339 2033 memset(rx_config, 0, sizeof(*rx_config));
8b230ed8
RM		 2034 rx_config->rx_type = BNA_RX_T_REGULAR;
2035 rx_config->num_paths = bnad->num_rxp_per_rx;
078086f3 2036 rx_config->coalescing_timeo = bnad->rx_coalescing_timeo;
8b230ed8
RM		 2037
2038 if (bnad->num_rxp_per_rx > 1) {
2039 rx_config->rss_status = BNA_STATUS_T_ENABLED;
2040 rx_config->rss_config.hash_type =
078086f3
RM		 2041 (BFI_ENET_RSS_IPV6 |
2042 BFI_ENET_RSS_IPV6_TCP |
2043 BFI_ENET_RSS_IPV4 |
2044 BFI_ENET_RSS_IPV4_TCP);
8b230ed8
RM		 2045 rx_config->rss_config.hash_mask =
2046 bnad->num_rxp_per_rx - 1;
0fa6aa4a 2047 netdev_rss_key_fill(rx_config->rss_config.toeplitz_hash_key,
8b230ed8
RM		 2048 sizeof(rx_config->rss_config.toeplitz_hash_key));
2049 } else {
2050 rx_config->rss_status = BNA_STATUS_T_DISABLED;
2051 memset(&rx_config->rss_config, 0,
2052 sizeof(rx_config->rss_config));
2053 }
e29aa339
RM		 2054
2055 rx_config->frame_size = BNAD_FRAME_SIZE(bnad->netdev->mtu);
2056 rx_config->q0_multi_buf = BNA_STATUS_T_DISABLED;
2057
2058 /* BNA_RXP_SINGLE - one data-buffer queue
2059 * BNA_RXP_SLR - one small-buffer and one large-buffer queues
2060 * BNA_RXP_HDS - one header-buffer and one data-buffer queues
2061 */
2062 /* TODO: configurable param for queue type */
8b230ed8 2063 rx_config->rxp_type = BNA_RXP_SLR;
8b230ed8 2064
e29aa339
RM		 2065 if (BNAD_PCI_DEV_IS_CAT2(bnad) &&
2066 rx_config->frame_size > 4096) {
2067 /* though size_routing_enable is set in SLR,
2068 * small packets may get routed to same rxq.
2069 * set buf_size to 2048 instead of PAGE_SIZE.
2070 */
2071 rx_config->q0_buf_size = 2048;
2072 /* this should be in multiples of 2 */
2073 rx_config->q0_num_vecs = 4;
2074 rx_config->q0_depth = bnad->rxq_depth * rx_config->q0_num_vecs;
2075 rx_config->q0_multi_buf = BNA_STATUS_T_ENABLED;
2076 } else {
2077 rx_config->q0_buf_size = rx_config->frame_size;
2078 rx_config->q0_num_vecs = 1;
2079 rx_config->q0_depth = bnad->rxq_depth;
2080 }
2081
2082 /* initialize for q1 for BNA_RXP_SLR/BNA_RXP_HDS */
2083 if (rx_config->rxp_type == BNA_RXP_SLR) {
2084 rx_config->q1_depth = bnad->rxq_depth;
2085 rx_config->q1_buf_size = BFI_SMALL_RXBUF_SIZE;
2086 }
8b230ed8 2087
877767dc
IV		 2088 rx_config->vlan_strip_status =
2089 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) ?
2090 BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED;
8b230ed8
RM		 2091}
2092
2be67144
RM		 2093static void
2094bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id)
2095{
2096 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2097 int i;
2098
2099 for (i = 0; i < bnad->num_rxp_per_rx; i++)
2100 rx_info->rx_ctrl[i].bnad = bnad;
2101}
2102
8b230ed8 2103/* Called with mutex_lock(&bnad->conf_mutex) held */
2fd888a5 2104static u32
e29aa339
RM		 2105bnad_reinit_rx(struct bnad *bnad)
2106{
2107 struct net_device *netdev = bnad->netdev;
2108 u32 err = 0, current_err = 0;
2109 u32 rx_id = 0, count = 0;
2110 unsigned long flags;
2111
2112 /* destroy and create new rx objects */
2113 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) {
2114 if (!bnad->rx_info[rx_id].rx)
2115 continue;
2116 bnad_destroy_rx(bnad, rx_id);
2117 }
2118
2119 spin_lock_irqsave(&bnad->bna_lock, flags);
2120 bna_enet_mtu_set(&bnad->bna.enet,
2121 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
2122 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2123
2124 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) {
2125 count++;
2126 current_err = bnad_setup_rx(bnad, rx_id);
2127 if (current_err && !err) {
2128 err = current_err;
ecc46789 2129 netdev_err(netdev, "RXQ:%u setup failed\n", rx_id);
e29aa339
RM		 2130 }
2131 }
2132
2133 /* restore rx configuration */
2134 if (bnad->rx_info[0].rx && !err) {
2135 bnad_restore_vlans(bnad, 0);
2136 bnad_enable_default_bcast(bnad);
2137 spin_lock_irqsave(&bnad->bna_lock, flags);
2138 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2139 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2140 bnad_set_rx_mode(netdev);
2141 }
2142
2143 return count;
2144}
2145
2146/* Called with bnad_conf_lock() held */
8b230ed8 2147void
b3cc6e88 2148bnad_destroy_rx(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 2149{
2150 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2151 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
2152 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
2153 unsigned long flags;
271e8b79 2154 int to_del = 0;
8b230ed8
RM		 2155
2156 if (!rx_info->rx)
2157 return;
2158
2159 if (0 == rx_id) {
2160 spin_lock_irqsave(&bnad->bna_lock, flags);
271e8b79
RM		 2161 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
2162 test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
8b230ed8 2163 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
271e8b79
RM		 2164 to_del = 1;
2165 }
8b230ed8 2166 spin_unlock_irqrestore(&bnad->bna_lock, flags);
271e8b79 2167 if (to_del)
8b230ed8
RM		 2168 del_timer_sync(&bnad->dim_timer);
2169 }
2170
8b230ed8
RM		 2171 init_completion(&bnad->bnad_completions.rx_comp);
2172 spin_lock_irqsave(&bnad->bna_lock, flags);
2173 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
2174 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2175 wait_for_completion(&bnad->bnad_completions.rx_comp);
2176
2177 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
2178 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
2179
01b54b14 2180 bnad_napi_delete(bnad, rx_id);
2be67144 2181
8b230ed8
RM		 2182 spin_lock_irqsave(&bnad->bna_lock, flags);
2183 bna_rx_destroy(rx_info->rx);
8b230ed8
RM		 2184
2185 rx_info->rx = NULL;
3caa1e95 2186 rx_info->rx_id = 0;
b9fa1fbf 2187 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 2188
2189 bnad_rx_res_free(bnad, res_info);
2190}
2191
2192/* Called with mutex_lock(&bnad->conf_mutex) held */
2193int
078086f3 2194bnad_setup_rx(struct bnad *bnad, u32 rx_id)
8b230ed8
RM		 2195{
2196 int err;
2197 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2198 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
2199 struct bna_intr_info *intr_info =
2200 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
2201 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
d91d25d5 2202 static const struct bna_rx_event_cbfn rx_cbfn = {
5216562a 2203 .rcb_setup_cbfn = NULL,
01b54b14 2204 .rcb_destroy_cbfn = NULL,
d91d25d5 2205 .ccb_setup_cbfn = bnad_cb_ccb_setup,
2206 .ccb_destroy_cbfn = bnad_cb_ccb_destroy,
5bcf6ac0 2207 .rx_stall_cbfn = bnad_cb_rx_stall,
d91d25d5 2208 .rx_cleanup_cbfn = bnad_cb_rx_cleanup,
2209 .rx_post_cbfn = bnad_cb_rx_post,
2210 };
8b230ed8
RM		 2211 struct bna_rx *rx;
2212 unsigned long flags;
2213
078086f3
RM		 2214 rx_info->rx_id = rx_id;
2215
8b230ed8
RM		 2216 /* Initialize the Rx object configuration */
2217 bnad_init_rx_config(bnad, rx_config);
2218
8b230ed8
RM		 2219 /* Get BNA's resource requirement for one Rx object */
2220 spin_lock_irqsave(&bnad->bna_lock, flags);
2221 bna_rx_res_req(rx_config, res_info);
2222 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2223
2224 /* Fill Unmap Q memory requirements */
e29aa339
RM		 2225 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPDQ],
2226 rx_config->num_paths,
2227 (rx_config->q0_depth *
2228 sizeof(struct bnad_rx_unmap)) +
2229 sizeof(struct bnad_rx_unmap_q));
2230
2231 if (rx_config->rxp_type != BNA_RXP_SINGLE) {
2232 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPHQ],
2233 rx_config->num_paths,
2234 (rx_config->q1_depth *
2235 sizeof(struct bnad_rx_unmap) +
2236 sizeof(struct bnad_rx_unmap_q)));
2237 }
8b230ed8
RM		 2238 /* Allocate resource */
2239 err = bnad_rx_res_alloc(bnad, res_info, rx_id);
2240 if (err)
2241 return err;
2242
2be67144
RM		 2243 bnad_rx_ctrl_init(bnad, rx_id);
2244
8b230ed8
RM		 2245 /* Ask BNA to create one Rx object, supplying required resources */
2246 spin_lock_irqsave(&bnad->bna_lock, flags);
2247 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
2248 rx_info);
3caa1e95
RM		 2249 if (!rx) {
2250 err = -ENOMEM;
b9fa1fbf 2251 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 2252 goto err_return;
3caa1e95 2253 }
8b230ed8 2254 rx_info->rx = rx;
b9fa1fbf 2255 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 2256
01b54b14
JH		 2257 INIT_WORK(&rx_info->rx_cleanup_work,
2258 (work_func_t)(bnad_rx_cleanup));
2259
2be67144
RM		 2260 /*
2261 * Init NAPI, so that state is set to NAPI_STATE_SCHED,
2262 * so that IRQ handler cannot schedule NAPI at this point.
2263 */
01b54b14 2264 bnad_napi_add(bnad, rx_id);
2be67144 2265
8b230ed8
RM		 2266 /* Register ISR for the Rx object */
2267 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
2268 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
2269 rx_config->num_paths);
2270 if (err)
2271 goto err_return;
2272 }
2273
8b230ed8
RM		 2274 spin_lock_irqsave(&bnad->bna_lock, flags);
2275 if (0 == rx_id) {
2276 /* Set up Dynamic Interrupt Moderation Vector */
2277 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
2278 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
2279
2280 /* Enable VLAN filtering only on the default Rx */
2281 bna_rx_vlanfilter_enable(rx);
2282
2283 /* Start the DIM timer */
2284 bnad_dim_timer_start(bnad);
2285 }
2286
2287 bna_rx_enable(rx);
2288 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2289
2290 return 0;
2291
2292err_return:
b3cc6e88 2293 bnad_destroy_rx(bnad, rx_id);
8b230ed8
RM		 2294 return err;
2295}
2296
2297/* Called with conf_lock & bnad->bna_lock held */
2298void
2299bnad_tx_coalescing_timeo_set(struct bnad *bnad)
2300{
2301 struct bnad_tx_info *tx_info;
2302
2303 tx_info = &bnad->tx_info[0];
2304 if (!tx_info->tx)
2305 return;
2306
2307 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
2308}
2309
2310/* Called with conf_lock & bnad->bna_lock held */
2311void
2312bnad_rx_coalescing_timeo_set(struct bnad *bnad)
2313{
2314 struct bnad_rx_info *rx_info;
0120b99c 2315 int i;
8b230ed8
RM		 2316
2317 for (i = 0; i < bnad->num_rx; i++) {
2318 rx_info = &bnad->rx_info[i];
2319 if (!rx_info->rx)
2320 continue;
2321 bna_rx_coalescing_timeo_set(rx_info->rx,
2322 bnad->rx_coalescing_timeo);
2323 }
2324}
2325
2326/*
2327 * Called with bnad->bna_lock held
2328 */
a2122d95 2329int
558caad7 2330bnad_mac_addr_set_locked(struct bnad *bnad, const u8 *mac_addr)
8b230ed8
RM		 2331{
2332 int ret;
2333
2334 if (!is_valid_ether_addr(mac_addr))
2335 return -EADDRNOTAVAIL;
2336
2337 /* If datapath is down, pretend everything went through */
2338 if (!bnad->rx_info[0].rx)
2339 return 0;
2340
1f9883e0 2341 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr);
8b230ed8
RM		 2342 if (ret != BNA_CB_SUCCESS)
2343 return -EADDRNOTAVAIL;
2344
2345 return 0;
2346}
2347
2348/* Should be called with conf_lock held */
a2122d95 2349int
8b230ed8
RM		 2350bnad_enable_default_bcast(struct bnad *bnad)
2351{
2352 struct bnad_rx_info *rx_info = &bnad->rx_info[0];
2353 int ret;
2354 unsigned long flags;
2355
2356 init_completion(&bnad->bnad_completions.mcast_comp);
2357
2358 spin_lock_irqsave(&bnad->bna_lock, flags);
558caad7
IV		 2359 ret = bna_rx_mcast_add(rx_info->rx, bnad_bcast_addr,
2360 bnad_cb_rx_mcast_add);
8b230ed8
RM		 2361 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2362
2363 if (ret == BNA_CB_SUCCESS)
2364 wait_for_completion(&bnad->bnad_completions.mcast_comp);
2365 else
2366 return -ENODEV;
2367
2368 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
2369 return -ENODEV;
2370
2371 return 0;
2372}
2373
19dbff9f 2374/* Called with mutex_lock(&bnad->conf_mutex) held */
a2122d95 2375void
aad75b66
RM		 2376bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
2377{
f859d7cb 2378 u16 vid;
aad75b66
RM		 2379 unsigned long flags;
2380
f859d7cb 2381 for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) {
aad75b66 2382 spin_lock_irqsave(&bnad->bna_lock, flags);
f859d7cb 2383 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid);
aad75b66
RM		 2384 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2385 }
2386}
2387
8b230ed8
RM		 2388/* Statistics utilities */
2389void
250e061e 2390bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
8b230ed8 2391{
8b230ed8
RM		 2392 int i, j;
2393
2394 for (i = 0; i < bnad->num_rx; i++) {
2395 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2396 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
250e061e 2397 stats->rx_packets += bnad->rx_info[i].
8b230ed8 2398 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
250e061e 2399 stats->rx_bytes += bnad->rx_info[i].
8b230ed8
RM		 2400 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
2401 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
2402 bnad->rx_info[i].rx_ctrl[j].ccb->
2403 rcb[1]->rxq) {
250e061e 2404 stats->rx_packets +=
8b230ed8
RM		 2405 bnad->rx_info[i].rx_ctrl[j].
2406 ccb->rcb[1]->rxq->rx_packets;
250e061e 2407 stats->rx_bytes +=
8b230ed8
RM		 2408 bnad->rx_info[i].rx_ctrl[j].
2409 ccb->rcb[1]->rxq->rx_bytes;
2410 }
2411 }
2412 }
2413 }
2414 for (i = 0; i < bnad->num_tx; i++) {
2415 for (j = 0; j < bnad->num_txq_per_tx; j++) {
2416 if (bnad->tx_info[i].tcb[j]) {
250e061e 2417 stats->tx_packets +=
8b230ed8 2418 bnad->tx_info[i].tcb[j]->txq->tx_packets;
250e061e 2419 stats->tx_bytes +=
8b230ed8
RM		 2420 bnad->tx_info[i].tcb[j]->txq->tx_bytes;
2421 }
2422 }
2423 }
2424}
2425
2426/*
2427 * Must be called with the bna_lock held.
2428 */
2429void
250e061e 2430bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
8b230ed8 2431{
078086f3
RM		 2432 struct bfi_enet_stats_mac *mac_stats;
2433 u32 bmap;
8b230ed8
RM		 2434 int i;
2435
078086f3 2436 mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats;
250e061e 2437 stats->rx_errors =
8b230ed8
RM		 2438 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2439 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2440 mac_stats->rx_undersize;
250e061e 2441 stats->tx_errors = mac_stats->tx_fcs_error +
8b230ed8 2442 mac_stats->tx_undersize;
250e061e
ED		 2443 stats->rx_dropped = mac_stats->rx_drop;
2444 stats->tx_dropped = mac_stats->tx_drop;
2445 stats->multicast = mac_stats->rx_multicast;
2446 stats->collisions = mac_stats->tx_total_collision;
8b230ed8 2447
250e061e 2448 stats->rx_length_errors = mac_stats->rx_frame_length_error;
8b230ed8
RM		 2449
2450 /* receive ring buffer overflow ?? */
2451
250e061e
ED		 2452 stats->rx_crc_errors = mac_stats->rx_fcs_error;
2453 stats->rx_frame_errors = mac_stats->rx_alignment_error;
8b230ed8 2454 /* recv'r fifo overrun */
078086f3
RM		 2455 bmap = bna_rx_rid_mask(&bnad->bna);
2456 for (i = 0; bmap; i++) {
8b230ed8 2457 if (bmap & 1) {
250e061e 2458 stats->rx_fifo_errors +=
8b230ed8 2459 bnad->stats.bna_stats->
078086f3 2460 hw_stats.rxf_stats[i].frame_drops;
8b230ed8
RM		 2461 break;
2462 }
2463 bmap >>= 1;
2464 }
2465}
2466
2467static void
2468bnad_mbox_irq_sync(struct bnad *bnad)
2469{
2470 u32 irq;
2471 unsigned long flags;
2472
2473 spin_lock_irqsave(&bnad->bna_lock, flags);
2474 if (bnad->cfg_flags & BNAD_CF_MSIX)
8811e267 2475 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
8b230ed8
RM		 2476 else
2477 irq = bnad->pcidev->irq;
2478 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2479
2480 synchronize_irq(irq);
2481}
2482
2483/* Utility used by bnad_start_xmit, for doing TSO */
2484static int
2485bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2486{
2487 int err;
2488
b13a8a99 2489 err = skb_cow_head(skb, 0);
2490 if (err < 0) {
2491 BNAD_UPDATE_CTR(bnad, tso_err);
2492 return err;
8b230ed8
RM		 2493 }
2494
2495 /*
2496 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2497 * excluding the length field.
2498 */
1c53730a 2499 if (vlan_get_protocol(skb) == htons(ETH_P_IP)) {
8b230ed8
RM		 2500 struct iphdr *iph = ip_hdr(skb);
2501
2502 /* Do we really need these? */
2503 iph->tot_len = 0;
2504 iph->check = 0;
2505
2506 tcp_hdr(skb)->check =
2507 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2508 IPPROTO_TCP, 0);
2509 BNAD_UPDATE_CTR(bnad, tso4);
2510 } else {
2511 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2512
8b230ed8
RM		 2513 ipv6h->payload_len = 0;
2514 tcp_hdr(skb)->check =
2515 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2516 IPPROTO_TCP, 0);
2517 BNAD_UPDATE_CTR(bnad, tso6);
2518 }
2519
2520 return 0;
2521}
2522
2523/*
2524 * Initialize Q numbers depending on Rx Paths
2525 * Called with bnad->bna_lock held, because of cfg_flags
2526 * access.
2527 */
2528static void
2529bnad_q_num_init(struct bnad *bnad)
2530{
2531 int rxps;
2532
2533 rxps = min((uint)num_online_cpus(),
772b5235 2534 (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX));
8b230ed8
RM		 2535
2536 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2537 rxps = 1; /* INTx */
2538
2539 bnad->num_rx = 1;
2540 bnad->num_tx = 1;
2541 bnad->num_rxp_per_rx = rxps;
2542 bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2543}
2544
2545/*
2546 * Adjusts the Q numbers, given a number of msix vectors
2547 * Give preference to RSS as opposed to Tx priority Queues,
2548 * in such a case, just use 1 Tx Q
2549 * Called with bnad->bna_lock held b'cos of cfg_flags access
2550 */
2551static void
078086f3 2552bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp)
8b230ed8
RM		 2553{
2554 bnad->num_txq_per_tx = 1;
2555 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
2556 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2557 (bnad->cfg_flags & BNAD_CF_MSIX)) {
2558 bnad->num_rxp_per_rx = msix_vectors -
2559 (bnad->num_tx * bnad->num_txq_per_tx) -
2560 BNAD_MAILBOX_MSIX_VECTORS;
2561 } else
2562 bnad->num_rxp_per_rx = 1;
2563}
2564
078086f3
RM		 2565/* Enable / disable ioceth */
2566static int
2567bnad_ioceth_disable(struct bnad *bnad)
8b230ed8
RM		 2568{
2569 unsigned long flags;
078086f3 2570 int err = 0;
8b230ed8
RM		 2571
2572 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2573 init_completion(&bnad->bnad_completions.ioc_comp);
2574 bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP);
8b230ed8
RM		 2575 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2576
078086f3
RM		 2577 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2578 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2579
2580 err = bnad->bnad_completions.ioc_comp_status;
2581 return err;
8b230ed8
RM		 2582}
2583
2584static int
078086f3 2585bnad_ioceth_enable(struct bnad *bnad)
8b230ed8
RM		 2586{
2587 int err = 0;
2588 unsigned long flags;
2589
8b230ed8 2590 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2591 init_completion(&bnad->bnad_completions.ioc_comp);
2592 bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING;
2593 bna_ioceth_enable(&bnad->bna.ioceth);
8b230ed8
RM		 2594 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2595
078086f3
RM		 2596 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2597 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
8b230ed8 2598
078086f3 2599 err = bnad->bnad_completions.ioc_comp_status;
8b230ed8
RM		 2600
2601 return err;
2602}
2603
2604/* Free BNA resources */
2605static void
078086f3
RM		 2606bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info,
2607 u32 res_val_max)
8b230ed8
RM		 2608{
2609 int i;
8b230ed8 2610
078086f3
RM		 2611 for (i = 0; i < res_val_max; i++)
2612 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
8b230ed8
RM		 2613}
2614
2615/* Allocates memory and interrupt resources for BNA */
2616static int
078086f3
RM		 2617bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
2618 u32 res_val_max)
8b230ed8
RM		 2619{
2620 int i, err;
8b230ed8 2621
078086f3
RM		 2622 for (i = 0; i < res_val_max; i++) {
2623 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
8b230ed8
RM		 2624 if (err)
2625 goto err_return;
2626 }
2627 return 0;
2628
2629err_return:
078086f3 2630 bnad_res_free(bnad, res_info, res_val_max);
8b230ed8
RM		 2631 return err;
2632}
2633
2634/* Interrupt enable / disable */
2635static void
2636bnad_enable_msix(struct bnad *bnad)
2637{
2638 int i, ret;
8b230ed8
RM		 2639 unsigned long flags;
2640
2641 spin_lock_irqsave(&bnad->bna_lock, flags);
2642 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2643 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2644 return;
2645 }
2646 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2647
2648 if (bnad->msix_table)
2649 return;
2650
8b230ed8 2651 bnad->msix_table =
b7ee31c5 2652 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
8b230ed8
RM		 2653
2654 if (!bnad->msix_table)
2655 goto intx_mode;
2656
b7ee31c5 2657 for (i = 0; i < bnad->msix_num; i++)
8b230ed8
RM		 2658 bnad->msix_table[i].entry = i;
2659
43c20200
AG		 2660 ret = pci_enable_msix_range(bnad->pcidev, bnad->msix_table,
2661 1, bnad->msix_num);
2662 if (ret < 0) {
2663 goto intx_mode;
2664 } else if (ret < bnad->msix_num) {
ecc46789
IV		 2665 dev_warn(&bnad->pcidev->dev,
2666 "%d MSI-X vectors allocated < %d requested\n",
2667 ret, bnad->msix_num);
8b230ed8
RM		 2668
2669 spin_lock_irqsave(&bnad->bna_lock, flags);
2670 /* ret = #of vectors that we got */
271e8b79
RM		 2671 bnad_q_num_adjust(bnad, (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2,
2672 (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2);
8b230ed8
RM		 2673 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2674
271e8b79 2675 bnad->msix_num = BNAD_NUM_TXQ + BNAD_NUM_RXP +
8b230ed8 2676 BNAD_MAILBOX_MSIX_VECTORS;
8b230ed8 2677
43c20200
AG		 2678 if (bnad->msix_num > ret) {
2679 pci_disable_msix(bnad->pcidev);
8b230ed8 2680 goto intx_mode;
43c20200
AG		 2681 }
2682 }
078086f3
RM		 2683
2684 pci_intx(bnad->pcidev, 0);
2685
8b230ed8
RM		 2686 return;
2687
2688intx_mode:
ecc46789
IV		 2689 dev_warn(&bnad->pcidev->dev,
2690 "MSI-X enable failed - operating in INTx mode\n");
8b230ed8
RM		 2691
2692 kfree(bnad->msix_table);
2693 bnad->msix_table = NULL;
2694 bnad->msix_num = 0;
8b230ed8
RM		 2695 spin_lock_irqsave(&bnad->bna_lock, flags);
2696 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2697 bnad_q_num_init(bnad);
2698 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2699}
2700
2701static void
2702bnad_disable_msix(struct bnad *bnad)
2703{
2704 u32 cfg_flags;
2705 unsigned long flags;
2706
2707 spin_lock_irqsave(&bnad->bna_lock, flags);
2708 cfg_flags = bnad->cfg_flags;
2709 if (bnad->cfg_flags & BNAD_CF_MSIX)
2710 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2711 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2712
2713 if (cfg_flags & BNAD_CF_MSIX) {
2714 pci_disable_msix(bnad->pcidev);
2715 kfree(bnad->msix_table);
2716 bnad->msix_table = NULL;
2717 }
2718}
2719
2720/* Netdev entry points */
2721static int
2722bnad_open(struct net_device *netdev)
2723{
2724 int err;
2725 struct bnad *bnad = netdev_priv(netdev);
2726 struct bna_pause_config pause_config;
8b230ed8
RM		 2727 unsigned long flags;
2728
2729 mutex_lock(&bnad->conf_mutex);
2730
2731 /* Tx */
2732 err = bnad_setup_tx(bnad, 0);
2733 if (err)
2734 goto err_return;
2735
2736 /* Rx */
2737 err = bnad_setup_rx(bnad, 0);
2738 if (err)
2739 goto cleanup_tx;
2740
2741 /* Port */
2742 pause_config.tx_pause = 0;
2743 pause_config.rx_pause = 0;
2744
8b230ed8 2745 spin_lock_irqsave(&bnad->bna_lock, flags);
e29aa339
RM		 2746 bna_enet_mtu_set(&bnad->bna.enet,
2747 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
1f9883e0 2748 bna_enet_pause_config(&bnad->bna.enet, &pause_config);
078086f3 2749 bna_enet_enable(&bnad->bna.enet);
8b230ed8
RM		 2750 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2751
2752 /* Enable broadcast */
2753 bnad_enable_default_bcast(bnad);
2754
aad75b66
RM		 2755 /* Restore VLANs, if any */
2756 bnad_restore_vlans(bnad, 0);
2757
8b230ed8
RM		 2758 /* Set the UCAST address */
2759 spin_lock_irqsave(&bnad->bna_lock, flags);
2760 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2761 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2762
2763 /* Start the stats timer */
2764 bnad_stats_timer_start(bnad);
2765
2766 mutex_unlock(&bnad->conf_mutex);
2767
2768 return 0;
2769
2770cleanup_tx:
b3cc6e88 2771 bnad_destroy_tx(bnad, 0);
8b230ed8
RM		 2772
2773err_return:
2774 mutex_unlock(&bnad->conf_mutex);
2775 return err;
2776}
2777
2778static int
2779bnad_stop(struct net_device *netdev)
2780{
2781 struct bnad *bnad = netdev_priv(netdev);
2782 unsigned long flags;
2783
2784 mutex_lock(&bnad->conf_mutex);
2785
2786 /* Stop the stats timer */
2787 bnad_stats_timer_stop(bnad);
2788
078086f3 2789 init_completion(&bnad->bnad_completions.enet_comp);
8b230ed8
RM		 2790
2791 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 2792 bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP,
2793 bnad_cb_enet_disabled);
8b230ed8
RM		 2794 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2795
078086f3 2796 wait_for_completion(&bnad->bnad_completions.enet_comp);
8b230ed8 2797
b3cc6e88
JH		 2798 bnad_destroy_tx(bnad, 0);
2799 bnad_destroy_rx(bnad, 0);
8b230ed8
RM		 2800
2801 /* Synchronize mailbox IRQ */
2802 bnad_mbox_irq_sync(bnad);
2803
2804 mutex_unlock(&bnad->conf_mutex);
2805
2806 return 0;
2807}
2808
2809/* TX */
5216562a
RM		 2810/* Returns 0 for success */
2811static int
2812bnad_txq_wi_prepare(struct bnad *bnad, struct bna_tcb *tcb,
2813 struct sk_buff *skb, struct bna_txq_entry *txqent)
8b230ed8 2814{
5216562a
RM		 2815 u16 flags = 0;
2816 u32 gso_size;
2817 u16 vlan_tag = 0;
8b230ed8 2818
df8a39de
JP		 2819 if (skb_vlan_tag_present(skb)) {
2820 vlan_tag = (u16)skb_vlan_tag_get(skb);
8b230ed8
RM		 2821 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2822 }
2823 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
5216562a
RM		 2824 vlan_tag = ((tcb->priority & 0x7) << VLAN_PRIO_SHIFT)
2825 | (vlan_tag & 0x1fff);
8b230ed8
RM		 2826 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2827 }
8b230ed8
RM		 2828 txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2829
2830 if (skb_is_gso(skb)) {
271e8b79 2831 gso_size = skb_shinfo(skb)->gso_size;
5216562a 2832 if (unlikely(gso_size > bnad->netdev->mtu)) {
271e8b79 2833 BNAD_UPDATE_CTR(bnad, tx_skb_mss_too_long);
5216562a 2834 return -EINVAL;
271e8b79
RM		 2835 }
2836 if (unlikely((gso_size + skb_transport_offset(skb) +
5216562a 2837 tcp_hdrlen(skb)) >= skb->len)) {
b779d0af 2838 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND);
271e8b79
RM		 2839 txqent->hdr.wi.lso_mss = 0;
2840 BNAD_UPDATE_CTR(bnad, tx_skb_tso_too_short);
2841 } else {
b779d0af 2842 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND_LSO);
271e8b79
RM		 2843 txqent->hdr.wi.lso_mss = htons(gso_size);
2844 }
2845
5216562a 2846 if (bnad_tso_prepare(bnad, skb)) {
271e8b79 2847 BNAD_UPDATE_CTR(bnad, tx_skb_tso_prepare);
5216562a 2848 return -EINVAL;
8b230ed8 2849 }
5216562a 2850
8b230ed8
RM		 2851 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2852 txqent->hdr.wi.l4_hdr_size_n_offset =
5216562a
RM		 2853 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET(
2854 tcp_hdrlen(skb) >> 2, skb_transport_offset(skb)));
2855 } else {
b779d0af 2856 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND);
8b230ed8
RM		 2857 txqent->hdr.wi.lso_mss = 0;
2858
6654cf60 2859 if (unlikely(skb->len > (bnad->netdev->mtu + VLAN_ETH_HLEN))) {
271e8b79 2860 BNAD_UPDATE_CTR(bnad, tx_skb_non_tso_too_long);
5216562a 2861 return -EINVAL;
8b230ed8 2862 }
8b230ed8 2863
271e8b79 2864 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1c53730a 2865 __be16 net_proto = vlan_get_protocol(skb);
271e8b79 2866 u8 proto = 0;
8b230ed8 2867
1c53730a 2868 if (net_proto == htons(ETH_P_IP))
271e8b79 2869 proto = ip_hdr(skb)->protocol;
5216562a 2870#ifdef NETIF_F_IPV6_CSUM
1c53730a 2871 else if (net_proto == htons(ETH_P_IPV6)) {
271e8b79
RM		 2872 /* nexthdr may not be TCP immediately. */
2873 proto = ipv6_hdr(skb)->nexthdr;
2874 }
5216562a 2875#endif
271e8b79
RM		 2876 if (proto == IPPROTO_TCP) {
2877 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2878 txqent->hdr.wi.l4_hdr_size_n_offset =
2879 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2880 (0, skb_transport_offset(skb)));
2881
2882 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2883
2884 if (unlikely(skb_headlen(skb) <
5216562a
RM		 2885 skb_transport_offset(skb) +
2886 tcp_hdrlen(skb))) {
271e8b79 2887 BNAD_UPDATE_CTR(bnad, tx_skb_tcp_hdr);
5216562a 2888 return -EINVAL;
271e8b79 2889 }
271e8b79
RM		 2890 } else if (proto == IPPROTO_UDP) {
2891 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2892 txqent->hdr.wi.l4_hdr_size_n_offset =
2893 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2894 (0, skb_transport_offset(skb)));
2895
2896 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2897 if (unlikely(skb_headlen(skb) <
5216562a 2898 skb_transport_offset(skb) +
271e8b79 2899 sizeof(struct udphdr))) {
271e8b79 2900 BNAD_UPDATE_CTR(bnad, tx_skb_udp_hdr);
5216562a 2901 return -EINVAL;
271e8b79
RM		 2902 }
2903 } else {
5216562a 2904
271e8b79 2905 BNAD_UPDATE_CTR(bnad, tx_skb_csum_err);
5216562a 2906 return -EINVAL;
8b230ed8 2907 }
5216562a 2908 } else
271e8b79 2909 txqent->hdr.wi.l4_hdr_size_n_offset = 0;
8b230ed8
RM		 2910 }
2911
2912 txqent->hdr.wi.flags = htons(flags);
8b230ed8
RM		 2913 txqent->hdr.wi.frame_length = htonl(skb->len);
2914
5216562a
RM		 2915 return 0;
2916}
2917
2918/*
2919 * bnad_start_xmit : Netdev entry point for Transmit
2920 * Called under lock held by net_device
2921 */
2922static netdev_tx_t
2923bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2924{
2925 struct bnad *bnad = netdev_priv(netdev);
2926 u32 txq_id = 0;
2927 struct bna_tcb *tcb = NULL;
2928 struct bnad_tx_unmap *unmap_q, *unmap, *head_unmap;
2929 u32 prod, q_depth, vect_id;
2930 u32 wis, vectors, len;
2931 int i;
2932 dma_addr_t dma_addr;
2933 struct bna_txq_entry *txqent;
2934
271e8b79 2935 len = skb_headlen(skb);
8b230ed8 2936
5216562a
RM		 2937 /* Sanity checks for the skb */
2938
2939 if (unlikely(skb->len <= ETH_HLEN)) {
27400df8 2940 dev_kfree_skb_any(skb);
5216562a
RM		 2941 BNAD_UPDATE_CTR(bnad, tx_skb_too_short);
2942 return NETDEV_TX_OK;
2943 }
2944 if (unlikely(len > BFI_TX_MAX_DATA_PER_VECTOR)) {
27400df8 2945 dev_kfree_skb_any(skb);
5216562a
RM		 2946 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2947 return NETDEV_TX_OK;
2948 }
2949 if (unlikely(len == 0)) {
27400df8 2950 dev_kfree_skb_any(skb);
5216562a
RM		 2951 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2952 return NETDEV_TX_OK;
2953 }
2954
2955 tcb = bnad->tx_info[0].tcb[txq_id];
271e8b79 2956
5216562a
RM		 2957 /*
2958 * Takes care of the Tx that is scheduled between clearing the flag
2959 * and the netif_tx_stop_all_queues() call.
2960 */
96e31adf 2961 if (unlikely(!tcb || !test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
27400df8 2962 dev_kfree_skb_any(skb);
5216562a
RM		 2963 BNAD_UPDATE_CTR(bnad, tx_skb_stopping);
2964 return NETDEV_TX_OK;
2965 }
2966
96e31adf
RM		 2967 q_depth = tcb->q_depth;
2968 prod = tcb->producer_index;
2969 unmap_q = tcb->unmap_q;
2970
5216562a
RM		 2971 vectors = 1 + skb_shinfo(skb)->nr_frags;
2972 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
2973
2974 if (unlikely(vectors > BFI_TX_MAX_VECTORS_PER_PKT)) {
27400df8 2975 dev_kfree_skb_any(skb);
5216562a
RM		 2976 BNAD_UPDATE_CTR(bnad, tx_skb_max_vectors);
2977 return NETDEV_TX_OK;
2978 }
2979
2980 /* Check for available TxQ resources */
2981 if (unlikely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) {
2982 if ((*tcb->hw_consumer_index != tcb->consumer_index) &&
2983 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
2984 u32 sent;
2985 sent = bnad_txcmpl_process(bnad, tcb);
2986 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2987 bna_ib_ack(tcb->i_dbell, sent);
4e857c58 2988 smp_mb__before_atomic();
5216562a
RM		 2989 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
2990 } else {
2991 netif_stop_queue(netdev);
2992 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2993 }
2994
2995 smp_mb();
2996 /*
2997 * Check again to deal with race condition between
2998 * netif_stop_queue here, and netif_wake_queue in
2999 * interrupt handler which is not inside netif tx lock.
3000 */
3001 if (likely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) {
3002 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
3003 return NETDEV_TX_BUSY;
3004 } else {
3005 netif_wake_queue(netdev);
3006 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
3007 }
3008 }
3009
3010 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod];
3011 head_unmap = &unmap_q[prod];
3012
3013 /* Program the opcode, flags, frame_len, num_vectors in WI */
3014 if (bnad_txq_wi_prepare(bnad, tcb, skb, txqent)) {
27400df8 3015 dev_kfree_skb_any(skb);
5216562a
RM		 3016 return NETDEV_TX_OK;
3017 }
3018 txqent->hdr.wi.reserved = 0;
3019 txqent->hdr.wi.num_vectors = vectors;
3020
3021 head_unmap->skb = skb;
3022 head_unmap->nvecs = 0;
3023
3024 /* Program the vectors */
3025 unmap = head_unmap;
3026 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
3027 len, DMA_TO_DEVICE);
3028 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[0].host_addr);
3029 txqent->vector[0].length = htons(len);
3030 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, dma_addr);
3031 head_unmap->nvecs++;
3032
3033 for (i = 0, vect_id = 0; i < vectors - 1; i++) {
9e903e08 3034 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
24f5d33d 3035 u32 size = skb_frag_size(frag);
8b230ed8 3036
271e8b79 3037 if (unlikely(size == 0)) {
5216562a
RM		 3038 /* Undo the changes starting at tcb->producer_index */
3039 bnad_tx_buff_unmap(bnad, unmap_q, q_depth,
3040 tcb->producer_index);
27400df8 3041 dev_kfree_skb_any(skb);
271e8b79
RM		 3042 BNAD_UPDATE_CTR(bnad, tx_skb_frag_zero);
3043 return NETDEV_TX_OK;
3044 }
3045
3046 len += size;
3047
5216562a
RM		 3048 vect_id++;
3049 if (vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
8b230ed8 3050 vect_id = 0;
5216562a
RM		 3051 BNA_QE_INDX_INC(prod, q_depth);
3052 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod];
b779d0af 3053 txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION);
5216562a 3054 unmap = &unmap_q[prod];
8b230ed8
RM		 3055 }
3056
4d5b1a67
IC		 3057 dma_addr = skb_frag_dma_map(&bnad->pcidev->dev, frag,
3058 0, size, DMA_TO_DEVICE);
ecca6a96 3059 dma_unmap_len_set(&unmap->vectors[vect_id], dma_len, size);
8b230ed8 3060 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
5216562a
RM		 3061 txqent->vector[vect_id].length = htons(size);
3062 dma_unmap_addr_set(&unmap->vectors[vect_id], dma_addr,
ecca6a96 3063 dma_addr);
5216562a 3064 head_unmap->nvecs++;
8b230ed8
RM		 3065 }
3066
271e8b79 3067 if (unlikely(len != skb->len)) {
5216562a
RM		 3068 /* Undo the changes starting at tcb->producer_index */
3069 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, tcb->producer_index);
27400df8 3070 dev_kfree_skb_any(skb);
271e8b79
RM		 3071 BNAD_UPDATE_CTR(bnad, tx_skb_len_mismatch);
3072 return NETDEV_TX_OK;
3073 }
3074
5216562a
RM		 3075 BNA_QE_INDX_INC(prod, q_depth);
3076 tcb->producer_index = prod;
8b230ed8
RM		 3077
3078 smp_mb();
be7fa326
RM		 3079
3080 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
3081 return NETDEV_TX_OK;
3082
fee1253e
RM		 3083 skb_tx_timestamp(skb);
3084
8b230ed8 3085 bna_txq_prod_indx_doorbell(tcb);
271e8b79 3086 smp_mb();
8b230ed8 3087
8b230ed8
RM		 3088 return NETDEV_TX_OK;
3089}
3090
3091/*
3092 * Used spin_lock to synchronize reading of stats structures, which
3093 * is written by BNA under the same lock.
3094 */
250e061e
ED		 3095static struct rtnl_link_stats64 *
3096bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
8b230ed8
RM		 3097{
3098 struct bnad *bnad = netdev_priv(netdev);
3099 unsigned long flags;
3100
3101 spin_lock_irqsave(&bnad->bna_lock, flags);
3102
250e061e
ED		 3103 bnad_netdev_qstats_fill(bnad, stats);
3104 bnad_netdev_hwstats_fill(bnad, stats);
8b230ed8
RM		 3105
3106 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3107
250e061e 3108 return stats;
8b230ed8
RM		 3109}
3110
fe1624cf
RM		 3111static void
3112bnad_set_rx_ucast_fltr(struct bnad *bnad)
3113{
3114 struct net_device *netdev = bnad->netdev;
3115 int uc_count = netdev_uc_count(netdev);
3116 enum bna_cb_status ret;
3117 u8 *mac_list;
3118 struct netdev_hw_addr *ha;
3119 int entry;
3120
3121 if (netdev_uc_empty(bnad->netdev)) {
1f9883e0 3122 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL);
fe1624cf
RM		 3123 return;
3124 }
3125
3126 if (uc_count > bna_attr(&bnad->bna)->num_ucmac)
3127 goto mode_default;
3128
3129 mac_list = kzalloc(uc_count * ETH_ALEN, GFP_ATOMIC);
3130 if (mac_list == NULL)
3131 goto mode_default;
3132
3133 entry = 0;
3134 netdev_for_each_uc_addr(ha, netdev) {
e2f9ecfc 3135 ether_addr_copy(&mac_list[entry * ETH_ALEN], &ha->addr[0]);
fe1624cf
RM		 3136 entry++;
3137 }
3138
1f9883e0 3139 ret = bna_rx_ucast_listset(bnad->rx_info[0].rx, entry, mac_list);
fe1624cf
RM		 3140 kfree(mac_list);
3141
3142 if (ret != BNA_CB_SUCCESS)
3143 goto mode_default;
3144
3145 return;
3146
3147 /* ucast packets not in UCAM are routed to default function */
3148mode_default:
3149 bnad->cfg_flags |= BNAD_CF_DEFAULT;
1f9883e0 3150 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL);
fe1624cf
RM		 3151}
3152
3153static void
3154bnad_set_rx_mcast_fltr(struct bnad *bnad)
3155{
3156 struct net_device *netdev = bnad->netdev;
3157 int mc_count = netdev_mc_count(netdev);
3158 enum bna_cb_status ret;
3159 u8 *mac_list;
3160
3161 if (netdev->flags & IFF_ALLMULTI)
3162 goto mode_allmulti;
3163
3164 if (netdev_mc_empty(netdev))
3165 return;
3166
3167 if (mc_count > bna_attr(&bnad->bna)->num_mcmac)
3168 goto mode_allmulti;
3169
3170 mac_list = kzalloc((mc_count + 1) * ETH_ALEN, GFP_ATOMIC);
3171
3172 if (mac_list == NULL)
3173 goto mode_allmulti;
3174
e2f9ecfc 3175 ether_addr_copy(&mac_list[0], &bnad_bcast_addr[0]);
fe1624cf
RM		 3176
3177 /* copy rest of the MCAST addresses */
3178 bnad_netdev_mc_list_get(netdev, mac_list);
1f9883e0 3179 ret = bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1, mac_list);
fe1624cf
RM		 3180 kfree(mac_list);
3181
3182 if (ret != BNA_CB_SUCCESS)
3183 goto mode_allmulti;
3184
3185 return;
3186
3187mode_allmulti:
3188 bnad->cfg_flags |= BNAD_CF_ALLMULTI;
1f9883e0 3189 bna_rx_mcast_delall(bnad->rx_info[0].rx);
fe1624cf
RM		 3190}
3191
a2122d95 3192void
8b230ed8
RM		 3193bnad_set_rx_mode(struct net_device *netdev)
3194{
3195 struct bnad *bnad = netdev_priv(netdev);
fe1624cf 3196 enum bna_rxmode new_mode, mode_mask;
8b230ed8
RM		 3197 unsigned long flags;
3198
3199 spin_lock_irqsave(&bnad->bna_lock, flags);
3200
fe1624cf
RM		 3201 if (bnad->rx_info[0].rx == NULL) {
3202 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3203 return;
8b230ed8
RM		 3204 }
3205
fe1624cf
RM		 3206 /* clear bnad flags to update it with new settings */
3207 bnad->cfg_flags &= ~(BNAD_CF_PROMISC | BNAD_CF_DEFAULT |
3208 BNAD_CF_ALLMULTI);
271e8b79 3209
fe1624cf
RM		 3210 new_mode = 0;
3211 if (netdev->flags & IFF_PROMISC) {
3212 new_mode |= BNAD_RXMODE_PROMISC_DEFAULT;
3213 bnad->cfg_flags |= BNAD_CF_PROMISC;
3214 } else {
3215 bnad_set_rx_mcast_fltr(bnad);
8b230ed8 3216
fe1624cf
RM		 3217 if (bnad->cfg_flags & BNAD_CF_ALLMULTI)
3218 new_mode |= BNA_RXMODE_ALLMULTI;
8b230ed8 3219
fe1624cf 3220 bnad_set_rx_ucast_fltr(bnad);
8b230ed8 3221
fe1624cf
RM		 3222 if (bnad->cfg_flags & BNAD_CF_DEFAULT)
3223 new_mode |= BNA_RXMODE_DEFAULT;
3224 }
8b230ed8 3225
fe1624cf
RM		 3226 mode_mask = BNA_RXMODE_PROMISC | BNA_RXMODE_DEFAULT |
3227 BNA_RXMODE_ALLMULTI;
1f9883e0 3228 bna_rx_mode_set(bnad->rx_info[0].rx, new_mode, mode_mask);
8b230ed8 3229
8b230ed8
RM		 3230 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3231}
3232
3233/*
3234 * bna_lock is used to sync writes to netdev->addr
3235 * conf_lock cannot be used since this call may be made
3236 * in a non-blocking context.
3237 */
3238static int
e2f9ecfc 3239bnad_set_mac_address(struct net_device *netdev, void *addr)
8b230ed8
RM		 3240{
3241 int err;
3242 struct bnad *bnad = netdev_priv(netdev);
e2f9ecfc 3243 struct sockaddr *sa = (struct sockaddr *)addr;
8b230ed8
RM		 3244 unsigned long flags;
3245
3246 spin_lock_irqsave(&bnad->bna_lock, flags);
3247
3248 err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
8b230ed8 3249 if (!err)
e2f9ecfc 3250 ether_addr_copy(netdev->dev_addr, sa->sa_data);
8b230ed8
RM		 3251
3252 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3253
3254 return err;
3255}
3256
3257static int
e29aa339 3258bnad_mtu_set(struct bnad *bnad, int frame_size)
8b230ed8 3259{
8b230ed8
RM		 3260 unsigned long flags;
3261
078086f3
RM		 3262 init_completion(&bnad->bnad_completions.mtu_comp);
3263
3264 spin_lock_irqsave(&bnad->bna_lock, flags);
e29aa339 3265 bna_enet_mtu_set(&bnad->bna.enet, frame_size, bnad_cb_enet_mtu_set);
078086f3
RM		 3266 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3267
3268 wait_for_completion(&bnad->bnad_completions.mtu_comp);
3269
3270 return bnad->bnad_completions.mtu_comp_status;
3271}
3272
3273static int
3274bnad_change_mtu(struct net_device *netdev, int new_mtu)
3275{
e29aa339 3276 int err, mtu;
8b230ed8 3277 struct bnad *bnad = netdev_priv(netdev);
e29aa339 3278 u32 rx_count = 0, frame, new_frame;
8b230ed8
RM		 3279
3280 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
3281 return -EINVAL;
3282
3283 mutex_lock(&bnad->conf_mutex);
3284
e29aa339 3285 mtu = netdev->mtu;
8b230ed8
RM		 3286 netdev->mtu = new_mtu;
3287
e29aa339
RM		 3288 frame = BNAD_FRAME_SIZE(mtu);
3289 new_frame = BNAD_FRAME_SIZE(new_mtu);
3290
3291 /* check if multi-buffer needs to be enabled */
3292 if (BNAD_PCI_DEV_IS_CAT2(bnad) &&
3293 netif_running(bnad->netdev)) {
3294 /* only when transition is over 4K */
3295 if ((frame <= 4096 && new_frame > 4096) ||
3296 (frame > 4096 && new_frame <= 4096))
3297 rx_count = bnad_reinit_rx(bnad);
3298 }
3299
3300 /* rx_count > 0 - new rx created
3301 * - Linux set err = 0 and return
3302 */
3303 err = bnad_mtu_set(bnad, new_frame);
078086f3
RM		 3304 if (err)
3305 err = -EBUSY;
8b230ed8
RM		 3306
3307 mutex_unlock(&bnad->conf_mutex);
3308 return err;
3309}
3310
8e586137 3311static int
80d5c368 3312bnad_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
8b230ed8
RM		 3313{
3314 struct bnad *bnad = netdev_priv(netdev);
3315 unsigned long flags;
3316
3317 if (!bnad->rx_info[0].rx)
8e586137 3318 return 0;
8b230ed8
RM		 3319
3320 mutex_lock(&bnad->conf_mutex);
3321
3322 spin_lock_irqsave(&bnad->bna_lock, flags);
3323 bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
f859d7cb 3324 set_bit(vid, bnad->active_vlans);
8b230ed8
RM		 3325 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3326
3327 mutex_unlock(&bnad->conf_mutex);
8e586137
JP		 3328
3329 return 0;
8b230ed8
RM		 3330}
3331
8e586137 3332static int
80d5c368 3333bnad_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
8b230ed8
RM		 3334{
3335 struct bnad *bnad = netdev_priv(netdev);
3336 unsigned long flags;
3337
3338 if (!bnad->rx_info[0].rx)
8e586137 3339 return 0;
8b230ed8
RM		 3340
3341 mutex_lock(&bnad->conf_mutex);
3342
3343 spin_lock_irqsave(&bnad->bna_lock, flags);
f859d7cb 3344 clear_bit(vid, bnad->active_vlans);
8b230ed8
RM		 3345 bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
3346 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3347
3348 mutex_unlock(&bnad->conf_mutex);
8e586137
JP		 3349
3350 return 0;
8b230ed8
RM		 3351}
3352
877767dc
IV		 3353static int bnad_set_features(struct net_device *dev, netdev_features_t features)
3354{
3355 struct bnad *bnad = netdev_priv(dev);
3356 netdev_features_t changed = features ^ dev->features;
3357
3358 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(dev)) {
3359 unsigned long flags;
3360
3361 spin_lock_irqsave(&bnad->bna_lock, flags);
3362
3363 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3364 bna_rx_vlan_strip_enable(bnad->rx_info[0].rx);
3365 else
3366 bna_rx_vlan_strip_disable(bnad->rx_info[0].rx);
3367
3368 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3369 }
3370
3371 return 0;
3372}
3373
8b230ed8
RM		 3374#ifdef CONFIG_NET_POLL_CONTROLLER
3375static void
3376bnad_netpoll(struct net_device *netdev)
3377{
3378 struct bnad *bnad = netdev_priv(netdev);
3379 struct bnad_rx_info *rx_info;
3380 struct bnad_rx_ctrl *rx_ctrl;
3381 u32 curr_mask;
3382 int i, j;
3383
3384 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
3385 bna_intx_disable(&bnad->bna, curr_mask);
3386 bnad_isr(bnad->pcidev->irq, netdev);
3387 bna_intx_enable(&bnad->bna, curr_mask);
3388 } else {
19dbff9f
RM		 3389 /*
3390 * Tx processing may happen in sending context, so no need
3391 * to explicitly process completions here
3392 */
3393
3394 /* Rx processing */
8b230ed8
RM		 3395 for (i = 0; i < bnad->num_rx; i++) {
3396 rx_info = &bnad->rx_info[i];
3397 if (!rx_info->rx)
3398 continue;
3399 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
3400 rx_ctrl = &rx_info->rx_ctrl[j];
271e8b79 3401 if (rx_ctrl->ccb)
8b230ed8
RM		 3402 bnad_netif_rx_schedule_poll(bnad,
3403 rx_ctrl->ccb);
8b230ed8
RM		 3404 }
3405 }
3406 }
3407}
3408#endif
3409
3410static const struct net_device_ops bnad_netdev_ops = {
3411 .ndo_open = bnad_open,
3412 .ndo_stop = bnad_stop,
3413 .ndo_start_xmit = bnad_start_xmit,
250e061e 3414 .ndo_get_stats64 = bnad_get_stats64,
8b230ed8 3415 .ndo_set_rx_mode = bnad_set_rx_mode,
8b230ed8
RM		 3416 .ndo_validate_addr = eth_validate_addr,
3417 .ndo_set_mac_address = bnad_set_mac_address,
3418 .ndo_change_mtu = bnad_change_mtu,
8b230ed8
RM		 3419 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
3420 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
877767dc 3421 .ndo_set_features = bnad_set_features,
8b230ed8
RM		 3422#ifdef CONFIG_NET_POLL_CONTROLLER
3423 .ndo_poll_controller = bnad_netpoll
3424#endif
3425};
3426
3427static void
3428bnad_netdev_init(struct bnad *bnad, bool using_dac)
3429{
3430 struct net_device *netdev = bnad->netdev;
3431
e5ee20e7
MM		 3432 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3433 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
877767dc
IV		 3434 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_TX |
3435 NETIF_F_HW_VLAN_CTAG_RX;
8b230ed8 3436
e5ee20e7
MM		 3437 netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA |
3438 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3439 NETIF_F_TSO | NETIF_F_TSO6;
8b230ed8 3440
877767dc 3441 netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
8b230ed8
RM		 3442
3443 if (using_dac)
3444 netdev->features |= NETIF_F_HIGHDMA;
3445
8b230ed8
RM		 3446 netdev->mem_start = bnad->mmio_start;
3447 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
3448
3449 netdev->netdev_ops = &bnad_netdev_ops;
3450 bnad_set_ethtool_ops(netdev);
3451}
3452
3453/*
3454 * 1. Initialize the bnad structure
3455 * 2. Setup netdev pointer in pci_dev
d95d1081
JH		 3456 * 3. Initialize no. of TxQ & CQs & MSIX vectors
3457 * 4. Initialize work queue.
8b230ed8
RM		 3458 */
3459static int
3460bnad_init(struct bnad *bnad,
3461 struct pci_dev *pdev, struct net_device *netdev)
3462{
3463 unsigned long flags;
3464
3465 SET_NETDEV_DEV(netdev, &pdev->dev);
3466 pci_set_drvdata(pdev, netdev);
3467
3468 bnad->netdev = netdev;
3469 bnad->pcidev = pdev;
3470 bnad->mmio_start = pci_resource_start(pdev, 0);
3471 bnad->mmio_len = pci_resource_len(pdev, 0);
3472 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
3473 if (!bnad->bar0) {
3474 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
8b230ed8
RM		 3475 return -ENOMEM;
3476 }
ecc46789
IV		 3477 dev_info(&pdev->dev, "bar0 mapped to %p, len %llu\n", bnad->bar0,
3478 (unsigned long long) bnad->mmio_len);
8b230ed8
RM		 3479
3480 spin_lock_irqsave(&bnad->bna_lock, flags);
3481 if (!bnad_msix_disable)
3482 bnad->cfg_flags = BNAD_CF_MSIX;
3483
3484 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
3485
3486 bnad_q_num_init(bnad);
3487 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3488
3489 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
3490 (bnad->num_rx * bnad->num_rxp_per_rx) +
3491 BNAD_MAILBOX_MSIX_VECTORS;
8b230ed8
RM		 3492
3493 bnad->txq_depth = BNAD_TXQ_DEPTH;
3494 bnad->rxq_depth = BNAD_RXQ_DEPTH;
8b230ed8
RM		 3495
3496 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3497 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
3498
01b54b14
JH		 3499 sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id);
3500 bnad->work_q = create_singlethread_workqueue(bnad->wq_name);
ba21fc69
WY		 3501 if (!bnad->work_q) {
3502 iounmap(bnad->bar0);
01b54b14 3503 return -ENOMEM;
ba21fc69 3504 }
01b54b14 3505
8b230ed8
RM		 3506 return 0;
3507}
3508
3509/*
3510 * Must be called after bnad_pci_uninit()
3511 * so that iounmap() and pci_set_drvdata(NULL)
3512 * happens only after PCI uninitialization.
3513 */
3514static void
3515bnad_uninit(struct bnad *bnad)
3516{
01b54b14
JH		 3517 if (bnad->work_q) {
3518 flush_workqueue(bnad->work_q);
3519 destroy_workqueue(bnad->work_q);
3520 bnad->work_q = NULL;
3521 }
3522
8b230ed8
RM		 3523 if (bnad->bar0)
3524 iounmap(bnad->bar0);
8b230ed8
RM		 3525}
3526
3527/*
3528 * Initialize locks
078086f3 3529 a) Per ioceth mutes used for serializing configuration
8b230ed8
RM		 3530 changes from OS interface
3531 b) spin lock used to protect bna state machine
3532 */
3533static void
3534bnad_lock_init(struct bnad *bnad)
3535{
3536 spin_lock_init(&bnad->bna_lock);
3537 mutex_init(&bnad->conf_mutex);
72a9730b 3538 mutex_init(&bnad_list_mutex);
8b230ed8
RM		 3539}
3540
3541static void
3542bnad_lock_uninit(struct bnad *bnad)
3543{
3544 mutex_destroy(&bnad->conf_mutex);
72a9730b 3545 mutex_destroy(&bnad_list_mutex);
8b230ed8
RM		 3546}
3547
3548/* PCI Initialization */
3549static int
3550bnad_pci_init(struct bnad *bnad,
3551 struct pci_dev *pdev, bool *using_dac)
3552{
3553 int err;
3554
3555 err = pci_enable_device(pdev);
3556 if (err)
3557 return err;
3558 err = pci_request_regions(pdev, BNAD_NAME);
3559 if (err)
3560 goto disable_device;
3e548079 3561 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
3db1cd5c 3562 *using_dac = true;
8b230ed8 3563 } else {
3e548079
RK		 3564 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3565 if (err)
3566 goto release_regions;
3db1cd5c 3567 *using_dac = false;
8b230ed8
RM		 3568 }
3569 pci_set_master(pdev);
3570 return 0;
3571
3572release_regions:
3573 pci_release_regions(pdev);
3574disable_device:
3575 pci_disable_device(pdev);
3576
3577 return err;
3578}
3579
3580static void
3581bnad_pci_uninit(struct pci_dev *pdev)
3582{
3583 pci_release_regions(pdev);
3584 pci_disable_device(pdev);
3585}
3586
c4eef189 3587static int
8b230ed8
RM		 3588bnad_pci_probe(struct pci_dev *pdev,
3589 const struct pci_device_id *pcidev_id)
3590{
3caa1e95 3591 bool using_dac;
0120b99c 3592 int err;
8b230ed8
RM		 3593 struct bnad *bnad;
3594 struct bna *bna;
3595 struct net_device *netdev;
3596 struct bfa_pcidev pcidev_info;
3597 unsigned long flags;
3598
8b230ed8
RM		 3599 mutex_lock(&bnad_fwimg_mutex);
3600 if (!cna_get_firmware_buf(pdev)) {
3601 mutex_unlock(&bnad_fwimg_mutex);
ecc46789 3602 dev_err(&pdev->dev, "failed to load firmware image!\n");
8b230ed8
RM		 3603 return -ENODEV;
3604 }
3605 mutex_unlock(&bnad_fwimg_mutex);
3606
3607 /*
3608 * Allocates sizeof(struct net_device + struct bnad)
3609 * bnad = netdev->priv
3610 */
3611 netdev = alloc_etherdev(sizeof(struct bnad));
3612 if (!netdev) {
8b230ed8
RM		 3613 err = -ENOMEM;
3614 return err;
3615 }
3616 bnad = netdev_priv(netdev);
078086f3 3617 bnad_lock_init(bnad);
72a9730b 3618 bnad_add_to_list(bnad);
078086f3
RM		 3619
3620 mutex_lock(&bnad->conf_mutex);
8b230ed8
RM		 3621 /*
3622 * PCI initialization
0120b99c 3623 * Output : using_dac = 1 for 64 bit DMA
be7fa326 3624 * = 0 for 32 bit DMA
8b230ed8 3625 */
e905ed57 3626 using_dac = false;
8b230ed8
RM		 3627 err = bnad_pci_init(bnad, pdev, &using_dac);
3628 if (err)
44861f44 3629 goto unlock_mutex;
8b230ed8 3630
8b230ed8
RM		 3631 /*
3632 * Initialize bnad structure
3633 * Setup relation between pci_dev & netdev
8b230ed8
RM		 3634 */
3635 err = bnad_init(bnad, pdev, netdev);
3636 if (err)
3637 goto pci_uninit;
078086f3 3638
8b230ed8
RM		 3639 /* Initialize netdev structure, set up ethtool ops */
3640 bnad_netdev_init(bnad, using_dac);
3641
815f41e7
RM		 3642 /* Set link to down state */
3643 netif_carrier_off(netdev);
3644
7afc5dbd
KG		 3645 /* Setup the debugfs node for this bfad */
3646 if (bna_debugfs_enable)
3647 bnad_debugfs_init(bnad);
3648
8b230ed8 3649 /* Get resource requirement form bna */
078086f3 3650 spin_lock_irqsave(&bnad->bna_lock, flags);
8b230ed8 3651 bna_res_req(&bnad->res_info[0]);
078086f3 3652 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 3653
3654 /* Allocate resources from bna */
078086f3 3655 err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
8b230ed8 3656 if (err)
078086f3 3657 goto drv_uninit;
8b230ed8
RM		 3658
3659 bna = &bnad->bna;
3660
3661 /* Setup pcidev_info for bna_init() */
3662 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3663 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3664 pcidev_info.device_id = bnad->pcidev->device;
3665 pcidev_info.pci_bar_kva = bnad->bar0;
3666
8b230ed8
RM		 3667 spin_lock_irqsave(&bnad->bna_lock, flags);
3668 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
8b230ed8
RM		 3669 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3670
3671 bnad->stats.bna_stats = &bna->stats;
3672
078086f3
RM		 3673 bnad_enable_msix(bnad);
3674 err = bnad_mbox_irq_alloc(bnad);
3675 if (err)
3676 goto res_free;
3677
8b230ed8 3678 /* Set up timers */
078086f3 3679 setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout,
ebb56d37 3680 (unsigned long)bnad);
078086f3 3681 setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check,
ebb56d37 3682 (unsigned long)bnad);
078086f3 3683 setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout,
ebb56d37 3684 (unsigned long)bnad);
078086f3 3685 setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout,
ebb56d37 3686 (unsigned long)bnad);
8b230ed8 3687
8b230ed8
RM		 3688 /*
3689 * Start the chip
078086f3
RM		 3690 * If the call back comes with error, we bail out.
3691 * This is a catastrophic error.
8b230ed8 3692 */
078086f3
RM		 3693 err = bnad_ioceth_enable(bnad);
3694 if (err) {
ecc46789 3695 dev_err(&pdev->dev, "initialization failed err=%d\n", err);
078086f3
RM		 3696 goto probe_success;
3697 }
3698
3699 spin_lock_irqsave(&bnad->bna_lock, flags);
3700 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3701 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) {
3702 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1,
3703 bna_attr(bna)->num_rxp - 1);
3704 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3705 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1))
3706 err = -EIO;
3707 }
3caa1e95
RM		 3708 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3709 if (err)
3710 goto disable_ioceth;
3711
3712 spin_lock_irqsave(&bnad->bna_lock, flags);
078086f3
RM		 3713 bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]);
3714 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3715
3716 err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
0caa9aae
RM		 3717 if (err) {
3718 err = -EIO;
078086f3 3719 goto disable_ioceth;
0caa9aae 3720 }
078086f3
RM		 3721
3722 spin_lock_irqsave(&bnad->bna_lock, flags);
3723 bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]);
3724 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8
RM		 3725
3726 /* Get the burnt-in mac */
3727 spin_lock_irqsave(&bnad->bna_lock, flags);
d6b30598 3728 bna_enet_perm_mac_get(&bna->enet, bnad->perm_addr);
8b230ed8
RM		 3729 bnad_set_netdev_perm_addr(bnad);
3730 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3731
0caa9aae
RM		 3732 mutex_unlock(&bnad->conf_mutex);
3733
8b230ed8
RM		 3734 /* Finally, reguister with net_device layer */
3735 err = register_netdev(netdev);
3736 if (err) {
ecc46789 3737 dev_err(&pdev->dev, "registering net device failed\n");
078086f3 3738 goto probe_uninit;
8b230ed8 3739 }
078086f3 3740 set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags);
8b230ed8 3741
0caa9aae
RM		 3742 return 0;
3743
078086f3
RM		 3744probe_success:
3745 mutex_unlock(&bnad->conf_mutex);
8b230ed8
RM		 3746 return 0;
3747
078086f3 3748probe_uninit:
3fc72370 3749 mutex_lock(&bnad->conf_mutex);
078086f3
RM		 3750 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3751disable_ioceth:
3752 bnad_ioceth_disable(bnad);
3753 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3754 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3755 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
8b230ed8
RM		 3756 spin_lock_irqsave(&bnad->bna_lock, flags);
3757 bna_uninit(bna);
3758 spin_unlock_irqrestore(&bnad->bna_lock, flags);
078086f3 3759 bnad_mbox_irq_free(bnad);
8b230ed8 3760 bnad_disable_msix(bnad);
078086f3
RM		 3761res_free:
3762 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3763drv_uninit:
7afc5dbd
KG		 3764 /* Remove the debugfs node for this bnad */
3765 kfree(bnad->regdata);
3766 bnad_debugfs_uninit(bnad);
078086f3 3767 bnad_uninit(bnad);
8b230ed8
RM		 3768pci_uninit:
3769 bnad_pci_uninit(pdev);
44861f44 3770unlock_mutex:
078086f3 3771 mutex_unlock(&bnad->conf_mutex);
72a9730b 3772 bnad_remove_from_list(bnad);
8b230ed8 3773 bnad_lock_uninit(bnad);
8b230ed8
RM		 3774 free_netdev(netdev);
3775 return err;
3776}
3777
c4eef189 3778static void
8b230ed8
RM		 3779bnad_pci_remove(struct pci_dev *pdev)
3780{
3781 struct net_device *netdev = pci_get_drvdata(pdev);
3782 struct bnad *bnad;
3783 struct bna *bna;
3784 unsigned long flags;
3785
3786 if (!netdev)
3787 return;
3788
8b230ed8
RM		 3789 bnad = netdev_priv(netdev);
3790 bna = &bnad->bna;
3791
078086f3
RM		 3792 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags))
3793 unregister_netdev(netdev);
8b230ed8
RM		 3794
3795 mutex_lock(&bnad->conf_mutex);
078086f3
RM		 3796 bnad_ioceth_disable(bnad);
3797 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3798 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3799 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
8b230ed8
RM		 3800 spin_lock_irqsave(&bnad->bna_lock, flags);
3801 bna_uninit(bna);
3802 spin_unlock_irqrestore(&bnad->bna_lock, flags);
8b230ed8 3803
078086f3
RM		 3804 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3805 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3806 bnad_mbox_irq_free(bnad);
8b230ed8
RM		 3807 bnad_disable_msix(bnad);
3808 bnad_pci_uninit(pdev);
078086f3 3809 mutex_unlock(&bnad->conf_mutex);
72a9730b 3810 bnad_remove_from_list(bnad);
8b230ed8 3811 bnad_lock_uninit(bnad);
7afc5dbd
KG		 3812 /* Remove the debugfs node for this bnad */
3813 kfree(bnad->regdata);
3814 bnad_debugfs_uninit(bnad);
8b230ed8
RM		 3815 bnad_uninit(bnad);
3816 free_netdev(netdev);
3817}
3818
9baa3c34 3819static const struct pci_device_id bnad_pci_id_table[] = {
8b230ed8
RM		 3820 {
3821 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3822 PCI_DEVICE_ID_BROCADE_CT),
3823 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3824 .class_mask = 0xffff00
586b2816
RM		 3825 },
3826 {
3827 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3828 BFA_PCI_DEVICE_ID_CT2),
3829 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3830 .class_mask = 0xffff00
3831 },
3832 {0, },
8b230ed8
RM		 3833};
3834
3835MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3836
3837static struct pci_driver bnad_pci_driver = {
3838 .name = BNAD_NAME,
3839 .id_table = bnad_pci_id_table,
3840 .probe = bnad_pci_probe,
c4eef189 3841 .remove = bnad_pci_remove,
8b230ed8
RM		 3842};
3843
3844static int __init
3845bnad_module_init(void)
3846{
3847 int err;
3848
ecc46789
IV		 3849 pr_info("bna: QLogic BR-series 10G Ethernet driver - version: %s\n",
3850 BNAD_VERSION);
8b230ed8 3851
8a891429 3852 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
8b230ed8
RM		 3853
3854 err = pci_register_driver(&bnad_pci_driver);
3855 if (err < 0) {
ecc46789 3856 pr_err("bna: PCI driver registration failed err=%d\n", err);
8b230ed8
RM		 3857 return err;
3858 }
3859
3860 return 0;
3861}
3862
3863static void __exit
3864bnad_module_exit(void)
3865{
3866 pci_unregister_driver(&bnad_pci_driver);
294ca868 3867 release_firmware(bfi_fw);
8b230ed8
RM		 3868}
3869
3870module_init(bnad_module_init);
3871module_exit(bnad_module_exit);
3872
3873MODULE_AUTHOR("Brocade");
3874MODULE_LICENSE("GPL");
2732ba56 3875MODULE_DESCRIPTION("QLogic BR-series 10G PCIe Ethernet driver");
8b230ed8
RM		 3876MODULE_VERSION(BNAD_VERSION);
3877MODULE_FIRMWARE(CNA_FW_FILE_CT);
1bf9fd70 3878MODULE_FIRMWARE(CNA_FW_FILE_CT2);
Linux 6.x block layer and io_uring tree(s)