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Merge branches 'acpi-resources', 'acpi-battery', 'acpi-doc' and 'acpi-pnp'
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
08f6dd89 9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
de0c62db
DK		 10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
de0c62db
DK		 25#include "bnx2x.h"
26#include "bnx2x_cmn.h"
27#include "bnx2x_dump.h"
4a33bc03 28#include "bnx2x_init.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
c96bdc0c
DK		 65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
67 4, "[%s]: driver_filtered_tx_pkt" }
ec6ba945
VZ		 68};
69
70#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
71
72static const struct {
73 long offset;
74 int size;
75 u32 flags;
76#define STATS_FLAGS_PORT 1
77#define STATS_FLAGS_FUNC 2
78#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
79 char string[ETH_GSTRING_LEN];
80} bnx2x_stats_arr[] = {
81/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_bytes" },
83 { STATS_OFFSET32(error_bytes_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
85 { STATS_OFFSET32(total_unicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
87 { STATS_OFFSET32(total_multicast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
89 { STATS_OFFSET32(total_broadcast_packets_received_hi),
90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
92 8, STATS_FLAGS_PORT, "rx_crc_errors" },
93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
94 8, STATS_FLAGS_PORT, "rx_align_errors" },
95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
98 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
99/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
100 8, STATS_FLAGS_PORT, "rx_fragments" },
101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
102 8, STATS_FLAGS_PORT, "rx_jabbers" },
103 { STATS_OFFSET32(no_buff_discard_hi),
104 8, STATS_FLAGS_BOTH, "rx_discards" },
105 { STATS_OFFSET32(mac_filter_discard),
106 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 107 { STATS_OFFSET32(mf_tag_discard),
108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 109 { STATS_OFFSET32(pfc_frames_received_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_received" },
111 { STATS_OFFSET32(pfc_frames_sent_hi),
112 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 113 { STATS_OFFSET32(brb_drop_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_discard" },
115 { STATS_OFFSET32(brb_truncate_hi),
116 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
117 { STATS_OFFSET32(pause_frames_received_hi),
118 8, STATS_FLAGS_PORT, "rx_pause_frames" },
119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
121 { STATS_OFFSET32(nig_timer_max),
122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
123/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
125 { STATS_OFFSET32(rx_skb_alloc_failed),
126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
127 { STATS_OFFSET32(hw_csum_err),
128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
129
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, STATS_FLAGS_PORT, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, STATS_FLAGS_PORT, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
144/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, STATS_FLAGS_PORT, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, STATS_FLAGS_PORT, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
164/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 171 8, STATS_FLAGS_PORT, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 177 8, STATS_FLAGS_FUNC, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, STATS_FLAGS_FUNC, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
c96bdc0c
DK		 182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
e9939c80
YM		 184 { STATS_OFFSET32(eee_tx_lpi),
185 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
ec6ba945
VZ		 186};
187
188#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
07ba6af4 189
1ac9e428
YR		 190static int bnx2x_get_port_type(struct bnx2x *bp)
191{
192 int port_type;
193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 switch (bp->link_params.phy[phy_idx].media_type) {
dbef807e
YM		 195 case ETH_PHY_SFPP_10G_FIBER:
196 case ETH_PHY_SFP_1G_FIBER:
1ac9e428
YR		 197 case ETH_PHY_XFP_FIBER:
198 case ETH_PHY_KR:
199 case ETH_PHY_CX4:
200 port_type = PORT_FIBRE;
201 break;
202 case ETH_PHY_DA_TWINAX:
203 port_type = PORT_DA;
204 break;
205 case ETH_PHY_BASE_T:
206 port_type = PORT_TP;
207 break;
208 case ETH_PHY_NOT_PRESENT:
209 port_type = PORT_NONE;
210 break;
211 case ETH_PHY_UNSPECIFIED:
212 default:
213 port_type = PORT_OTHER;
214 break;
215 }
216 return port_type;
217}
ec6ba945 218
6495d15a
DK		 219static int bnx2x_get_vf_settings(struct net_device *dev,
220 struct ethtool_cmd *cmd)
221{
222 struct bnx2x *bp = netdev_priv(dev);
223
224 if (bp->state == BNX2X_STATE_OPEN) {
225 if (test_bit(BNX2X_LINK_REPORT_FD,
226 &bp->vf_link_vars.link_report_flags))
227 cmd->duplex = DUPLEX_FULL;
228 else
229 cmd->duplex = DUPLEX_HALF;
230
231 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed);
232 } else {
233 cmd->duplex = DUPLEX_UNKNOWN;
234 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
235 }
236
237 cmd->port = PORT_OTHER;
238 cmd->phy_address = 0;
239 cmd->transceiver = XCVR_INTERNAL;
240 cmd->autoneg = AUTONEG_DISABLE;
241 cmd->maxtxpkt = 0;
242 cmd->maxrxpkt = 0;
243
244 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
245 " supported 0x%x advertising 0x%x speed %u\n"
246 " duplex %d port %d phy_address %d transceiver %d\n"
247 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
248 cmd->cmd, cmd->supported, cmd->advertising,
249 ethtool_cmd_speed(cmd),
250 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
251 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
252
253 return 0;
254}
255
de0c62db
DK		 256static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
257{
258 struct bnx2x *bp = netdev_priv(dev);
a22f0788 259 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 260
a22f0788
YR		 261 /* Dual Media boards present all available port types */
262 cmd->supported = bp->port.supported[cfg_idx] |
263 (bp->port.supported[cfg_idx ^ 1] &
264 (SUPPORTED_TP | SUPPORTED_FIBRE));
265 cmd->advertising = bp->port.advertising[cfg_idx];
dbef807e
YM		 266 if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
267 ETH_PHY_SFP_1G_FIBER) {
268 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
269 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
270 }
de0c62db 271
59694f00
YM		 272 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
273 !(bp->flags & MF_FUNC_DIS)) {
2de67439 274 cmd->duplex = bp->link_vars.duplex;
38298461
YM		 275
276 if (IS_MF(bp) && !BP_NOMCP(bp))
277 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
59694f00
YM		 278 else
279 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
de0c62db 280 } else {
38298461
YM		 281 cmd->duplex = DUPLEX_UNKNOWN;
282 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
de0c62db 283 }
f2e0899f 284
1ac9e428 285 cmd->port = bnx2x_get_port_type(bp);
a22f0788 286
de0c62db
DK		 287 cmd->phy_address = bp->mdio.prtad;
288 cmd->transceiver = XCVR_INTERNAL;
289
a22f0788 290 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 291 cmd->autoneg = AUTONEG_ENABLE;
292 else
293 cmd->autoneg = AUTONEG_DISABLE;
294
9e7e8399
MY		 295 /* Publish LP advertised speeds and FC */
296 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
297 u32 status = bp->link_vars.link_status;
298
299 cmd->lp_advertising |= ADVERTISED_Autoneg;
300 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
301 cmd->lp_advertising |= ADVERTISED_Pause;
302 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
303 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
304
305 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
306 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
307 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
308 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
309 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
310 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
311 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
312 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
313 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
314 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
315 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
316 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
317 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
318 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
319 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
320 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
be94bea7
YR		 321 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
322 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
9e7e8399
MY		 323 }
324
de0c62db
DK		 325 cmd->maxtxpkt = 0;
326 cmd->maxrxpkt = 0;
327
51c1a580 328 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 329 " supported 0x%x advertising 0x%x speed %u\n"
330 " duplex %d port %d phy_address %d transceiver %d\n"
331 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 332 cmd->cmd, cmd->supported, cmd->advertising,
333 ethtool_cmd_speed(cmd),
de0c62db
DK		 334 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
335 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
336
337 return 0;
338}
339
340static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
341{
342 struct bnx2x *bp = netdev_priv(dev);
a22f0788 343 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
dbef807e 344 u32 speed, phy_idx;
de0c62db 345
0793f83f 346 if (IS_MF_SD(bp))
de0c62db
DK		 347 return 0;
348
51c1a580 349 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
b3337e4c 350 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 351 " duplex %d port %d phy_address %d transceiver %d\n"
352 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 353 cmd->cmd, cmd->supported, cmd->advertising,
354 ethtool_cmd_speed(cmd),
de0c62db
DK		 355 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
356 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
357
b3337e4c 358 speed = ethtool_cmd_speed(cmd);
0793f83f 359
16a5fd92 360 /* If received a request for an unknown duplex, assume full*/
38298461
YM		 361 if (cmd->duplex == DUPLEX_UNKNOWN)
362 cmd->duplex = DUPLEX_FULL;
363
0793f83f 364 if (IS_MF_SI(bp)) {
e3835b99 365 u32 part;
0793f83f
DK		 366 u32 line_speed = bp->link_vars.line_speed;
367
368 /* use 10G if no link detected */
369 if (!line_speed)
370 line_speed = 10000;
371
372 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
51c1a580
MS		 373 DP(BNX2X_MSG_ETHTOOL,
374 "To set speed BC %X or higher is required, please upgrade BC\n",
375 REQ_BC_VER_4_SET_MF_BW);
0793f83f
DK		 376 return -EINVAL;
377 }
e3835b99 378
faa6fcbb 379 part = (speed * 100) / line_speed;
e3835b99 380
faa6fcbb 381 if (line_speed < speed || !part) {
51c1a580
MS		 382 DP(BNX2X_MSG_ETHTOOL,
383 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
0793f83f
DK		 384 return -EINVAL;
385 }
0793f83f 386
e3835b99
DK		 387 if (bp->state != BNX2X_STATE_OPEN)
388 /* store value for following "load" */
389 bp->pending_max = part;
390 else
391 bnx2x_update_max_mf_config(bp, part);
0793f83f 392
0793f83f
DK		 393 return 0;
394 }
395
a22f0788
YR		 396 cfg_idx = bnx2x_get_link_cfg_idx(bp);
397 old_multi_phy_config = bp->link_params.multi_phy_config;
33f9e6f5
YR		 398 if (cmd->port != bnx2x_get_port_type(bp)) {
399 switch (cmd->port) {
400 case PORT_TP:
401 if (!(bp->port.supported[0] & SUPPORTED_TP ||
402 bp->port.supported[1] & SUPPORTED_TP)) {
403 DP(BNX2X_MSG_ETHTOOL,
404 "Unsupported port type\n");
405 return -EINVAL;
406 }
407 bp->link_params.multi_phy_config &=
408 ~PORT_HW_CFG_PHY_SELECTION_MASK;
409 if (bp->link_params.multi_phy_config &
410 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
411 bp->link_params.multi_phy_config |=
412 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
413 else
414 bp->link_params.multi_phy_config |=
415 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
416 break;
417 case PORT_FIBRE:
418 case PORT_DA:
042d7654 419 case PORT_NONE:
33f9e6f5
YR		 420 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
421 bp->port.supported[1] & SUPPORTED_FIBRE)) {
422 DP(BNX2X_MSG_ETHTOOL,
423 "Unsupported port type\n");
424 return -EINVAL;
425 }
426 bp->link_params.multi_phy_config &=
427 ~PORT_HW_CFG_PHY_SELECTION_MASK;
428 if (bp->link_params.multi_phy_config &
429 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
430 bp->link_params.multi_phy_config |=
431 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
432 else
433 bp->link_params.multi_phy_config |=
434 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
435 break;
436 default:
51c1a580 437 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 438 return -EINVAL;
439 }
a22f0788 440 }
2de67439 441 /* Save new config in case command complete successfully */
a22f0788
YR		 442 new_multi_phy_config = bp->link_params.multi_phy_config;
443 /* Get the new cfg_idx */
444 cfg_idx = bnx2x_get_link_cfg_idx(bp);
445 /* Restore old config in case command failed */
446 bp->link_params.multi_phy_config = old_multi_phy_config;
51c1a580 447 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
a22f0788 448
de0c62db 449 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 450 u32 an_supported_speed = bp->port.supported[cfg_idx];
451 if (bp->link_params.phy[EXT_PHY1].type ==
452 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
453 an_supported_speed |= (SUPPORTED_100baseT_Half |
454 SUPPORTED_100baseT_Full);
a22f0788 455 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 456 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
de0c62db
DK		 457 return -EINVAL;
458 }
459
460 /* advertise the requested speed and duplex if supported */
75318327 461 if (cmd->advertising & ~an_supported_speed) {
51c1a580
MS		 462 DP(BNX2X_MSG_ETHTOOL,
463 "Advertisement parameters are not supported\n");
8d661637
YR		 464 return -EINVAL;
465 }
de0c62db 466
a22f0788 467 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 468 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
469 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 470 cmd->advertising);
8d661637
YR		 471 if (cmd->advertising) {
472
473 bp->link_params.speed_cap_mask[cfg_idx] = 0;
474 if (cmd->advertising & ADVERTISED_10baseT_Half) {
475 bp->link_params.speed_cap_mask[cfg_idx] |=
476 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
477 }
478 if (cmd->advertising & ADVERTISED_10baseT_Full)
479 bp->link_params.speed_cap_mask[cfg_idx] |=
480 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 481
8d661637
YR		 482 if (cmd->advertising & ADVERTISED_100baseT_Full)
483 bp->link_params.speed_cap_mask[cfg_idx] |=
484 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
485
486 if (cmd->advertising & ADVERTISED_100baseT_Half) {
487 bp->link_params.speed_cap_mask[cfg_idx] |=
488 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
489 }
490 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
491 bp->link_params.speed_cap_mask[cfg_idx] |=
492 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
493 }
494 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
495 ADVERTISED_1000baseKX_Full))
496 bp->link_params.speed_cap_mask[cfg_idx] |=
497 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
498
499 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
500 ADVERTISED_10000baseKX4_Full |
501 ADVERTISED_10000baseKR_Full))
502 bp->link_params.speed_cap_mask[cfg_idx] |=
503 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
be94bea7
YR		 504
505 if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
506 bp->link_params.speed_cap_mask[cfg_idx] |=
507 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
8d661637 508 }
de0c62db
DK		 509 } else { /* forced speed */
510 /* advertise the requested speed and duplex if supported */
a22f0788 511 switch (speed) {
de0c62db
DK		 512 case SPEED_10:
513 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 514 if (!(bp->port.supported[cfg_idx] &
de0c62db 515 SUPPORTED_10baseT_Full)) {
51c1a580 516 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 517 "10M full not supported\n");
518 return -EINVAL;
519 }
520
521 advertising = (ADVERTISED_10baseT_Full |
522 ADVERTISED_TP);
523 } else {
a22f0788 524 if (!(bp->port.supported[cfg_idx] &
de0c62db 525 SUPPORTED_10baseT_Half)) {
51c1a580 526 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 527 "10M half not supported\n");
528 return -EINVAL;
529 }
530
531 advertising = (ADVERTISED_10baseT_Half |
532 ADVERTISED_TP);
533 }
534 break;
535
536 case SPEED_100:
537 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 538 if (!(bp->port.supported[cfg_idx] &
de0c62db 539 SUPPORTED_100baseT_Full)) {
51c1a580 540 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 541 "100M full not supported\n");
542 return -EINVAL;
543 }
544
545 advertising = (ADVERTISED_100baseT_Full |
546 ADVERTISED_TP);
547 } else {
a22f0788 548 if (!(bp->port.supported[cfg_idx] &
de0c62db 549 SUPPORTED_100baseT_Half)) {
51c1a580 550 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 551 "100M half not supported\n");
552 return -EINVAL;
553 }
554
555 advertising = (ADVERTISED_100baseT_Half |
556 ADVERTISED_TP);
557 }
558 break;
559
560 case SPEED_1000:
561 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 562 DP(BNX2X_MSG_ETHTOOL,
563 "1G half not supported\n");
de0c62db
DK		 564 return -EINVAL;
565 }
566
a22f0788
YR		 567 if (!(bp->port.supported[cfg_idx] &
568 SUPPORTED_1000baseT_Full)) {
51c1a580
MS		 569 DP(BNX2X_MSG_ETHTOOL,
570 "1G full not supported\n");
de0c62db
DK		 571 return -EINVAL;
572 }
573
574 advertising = (ADVERTISED_1000baseT_Full |
575 ADVERTISED_TP);
576 break;
577
578 case SPEED_2500:
579 if (cmd->duplex != DUPLEX_FULL) {
51c1a580 580 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 581 "2.5G half not supported\n");
582 return -EINVAL;
583 }
584
a22f0788
YR		 585 if (!(bp->port.supported[cfg_idx]
586 & SUPPORTED_2500baseX_Full)) {
51c1a580 587 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 588 "2.5G full not supported\n");
589 return -EINVAL;
590 }
591
592 advertising = (ADVERTISED_2500baseX_Full |
593 ADVERTISED_TP);
594 break;
595
596 case SPEED_10000:
597 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 598 DP(BNX2X_MSG_ETHTOOL,
599 "10G half not supported\n");
de0c62db
DK		 600 return -EINVAL;
601 }
dbef807e 602 phy_idx = bnx2x_get_cur_phy_idx(bp);
a22f0788 603 if (!(bp->port.supported[cfg_idx]
dbef807e
YM		 604 & SUPPORTED_10000baseT_Full) ||
605 (bp->link_params.phy[phy_idx].media_type ==
606 ETH_PHY_SFP_1G_FIBER)) {
51c1a580
MS		 607 DP(BNX2X_MSG_ETHTOOL,
608 "10G full not supported\n");
de0c62db
DK		 609 return -EINVAL;
610 }
611
612 advertising = (ADVERTISED_10000baseT_Full |
613 ADVERTISED_FIBRE);
614 break;
615
616 default:
51c1a580 617 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
de0c62db
DK		 618 return -EINVAL;
619 }
620
a22f0788
YR		 621 bp->link_params.req_line_speed[cfg_idx] = speed;
622 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
623 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 624 }
625
51c1a580 626 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
f1deab50 627 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 628 bp->link_params.req_line_speed[cfg_idx],
629 bp->link_params.req_duplex[cfg_idx],
630 bp->port.advertising[cfg_idx]);
de0c62db 631
a22f0788
YR		 632 /* Set new config */
633 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 634 if (netif_running(dev)) {
635 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
636 bnx2x_link_set(bp);
637 }
638
639 return 0;
640}
641
07ba6af4
MS		 642#define DUMP_ALL_PRESETS 0x1FFF
643#define DUMP_MAX_PRESETS 13
0fea29c1 644
07ba6af4 645static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
0fea29c1
VZ		 646{
647 if (CHIP_IS_E1(bp))
07ba6af4 648 return dump_num_registers[0][preset-1];
0fea29c1 649 else if (CHIP_IS_E1H(bp))
07ba6af4 650 return dump_num_registers[1][preset-1];
0fea29c1 651 else if (CHIP_IS_E2(bp))
07ba6af4 652 return dump_num_registers[2][preset-1];
0fea29c1 653 else if (CHIP_IS_E3A0(bp))
07ba6af4 654 return dump_num_registers[3][preset-1];
0fea29c1 655 else if (CHIP_IS_E3B0(bp))
07ba6af4 656 return dump_num_registers[4][preset-1];
0fea29c1 657 else
07ba6af4
MS		 658 return 0;
659}
660
661static int __bnx2x_get_regs_len(struct bnx2x *bp)
662{
663 u32 preset_idx;
664 int regdump_len = 0;
665
666 /* Calculate the total preset regs length */
667 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
668 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
669
670 return regdump_len;
671}
672
673static int bnx2x_get_regs_len(struct net_device *dev)
674{
675 struct bnx2x *bp = netdev_priv(dev);
676 int regdump_len = 0;
677
75543741
YM		 678 if (IS_VF(bp))
679 return 0;
680
07ba6af4
MS		 681 regdump_len = __bnx2x_get_regs_len(bp);
682 regdump_len *= 4;
683 regdump_len += sizeof(struct dump_header);
684
685 return regdump_len;
0fea29c1
VZ		 686}
687
07ba6af4
MS		 688#define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
689#define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
690#define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
691#define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
692#define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
693
694#define IS_REG_IN_PRESET(presets, idx) \
695 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
696
0fea29c1 697/******* Paged registers info selectors ********/
1191cb83 698static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
0fea29c1
VZ		 699{
700 if (CHIP_IS_E2(bp))
701 return page_vals_e2;
702 else if (CHIP_IS_E3(bp))
703 return page_vals_e3;
704 else
705 return NULL;
706}
707
1191cb83 708static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
0fea29c1
VZ		 709{
710 if (CHIP_IS_E2(bp))
711 return PAGE_MODE_VALUES_E2;
712 else if (CHIP_IS_E3(bp))
713 return PAGE_MODE_VALUES_E3;
714 else
715 return 0;
716}
717
1191cb83 718static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
0fea29c1
VZ		 719{
720 if (CHIP_IS_E2(bp))
721 return page_write_regs_e2;
722 else if (CHIP_IS_E3(bp))
723 return page_write_regs_e3;
724 else
725 return NULL;
726}
727
1191cb83 728static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
0fea29c1
VZ		 729{
730 if (CHIP_IS_E2(bp))
731 return PAGE_WRITE_REGS_E2;
732 else if (CHIP_IS_E3(bp))
733 return PAGE_WRITE_REGS_E3;
734 else
735 return 0;
736}
737
1191cb83 738static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
0fea29c1
VZ		 739{
740 if (CHIP_IS_E2(bp))
741 return page_read_regs_e2;
742 else if (CHIP_IS_E3(bp))
743 return page_read_regs_e3;
744 else
745 return NULL;
746}
747
1191cb83 748static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
0fea29c1
VZ		 749{
750 if (CHIP_IS_E2(bp))
751 return PAGE_READ_REGS_E2;
752 else if (CHIP_IS_E3(bp))
753 return PAGE_READ_REGS_E3;
754 else
755 return 0;
756}
757
07ba6af4
MS		 758static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
759 const struct reg_addr *reg_info)
0fea29c1 760{
07ba6af4
MS		 761 if (CHIP_IS_E1(bp))
762 return IS_E1_REG(reg_info->chips);
763 else if (CHIP_IS_E1H(bp))
764 return IS_E1H_REG(reg_info->chips);
765 else if (CHIP_IS_E2(bp))
766 return IS_E2_REG(reg_info->chips);
767 else if (CHIP_IS_E3A0(bp))
768 return IS_E3A0_REG(reg_info->chips);
769 else if (CHIP_IS_E3B0(bp))
770 return IS_E3B0_REG(reg_info->chips);
771 else
772 return false;
0fea29c1 773}
de0c62db 774
07ba6af4
MS		 775static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
776 const struct wreg_addr *wreg_info)
777{
778 if (CHIP_IS_E1(bp))
779 return IS_E1_REG(wreg_info->chips);
780 else if (CHIP_IS_E1H(bp))
781 return IS_E1H_REG(wreg_info->chips);
782 else if (CHIP_IS_E2(bp))
783 return IS_E2_REG(wreg_info->chips);
784 else if (CHIP_IS_E3A0(bp))
785 return IS_E3A0_REG(wreg_info->chips);
786 else if (CHIP_IS_E3B0(bp))
787 return IS_E3B0_REG(wreg_info->chips);
788 else
789 return false;
de0c62db
DK		 790}
791
0fea29c1
VZ		 792/**
793 * bnx2x_read_pages_regs - read "paged" registers
794 *
795 * @bp device handle
796 * @p output buffer
797 *
2de67439
YM		 798 * Reads "paged" memories: memories that may only be read by first writing to a
799 * specific address ("write address") and then reading from a specific address
800 * ("read address"). There may be more than one write address per "page" and
801 * more than one read address per write address.
0fea29c1 802 */
07ba6af4 803static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
f2e0899f
DK		 804{
805 u32 i, j, k, n;
07ba6af4 806
0fea29c1
VZ		 807 /* addresses of the paged registers */
808 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
809 /* number of paged registers */
810 int num_pages = __bnx2x_get_page_reg_num(bp);
811 /* write addresses */
812 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
813 /* number of write addresses */
814 int write_num = __bnx2x_get_page_write_num(bp);
815 /* read addresses info */
816 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
817 /* number of read addresses */
818 int read_num = __bnx2x_get_page_read_num(bp);
07ba6af4 819 u32 addr, size;
0fea29c1
VZ		 820
821 for (i = 0; i < num_pages; i++) {
822 for (j = 0; j < write_num; j++) {
823 REG_WR(bp, write_addr[j], page_addr[i]);
07ba6af4
MS		 824
825 for (k = 0; k < read_num; k++) {
826 if (IS_REG_IN_PRESET(read_addr[k].presets,
827 preset)) {
828 size = read_addr[k].size;
829 for (n = 0; n < size; n++) {
830 addr = read_addr[k].addr + n*4;
831 *p++ = REG_RD(bp, addr);
832 }
833 }
834 }
f2e0899f
DK		 835 }
836 }
837}
838
07ba6af4 839static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
0fea29c1 840{
07ba6af4
MS		 841 u32 i, j, addr;
842 const struct wreg_addr *wreg_addr_p = NULL;
843
844 if (CHIP_IS_E1(bp))
845 wreg_addr_p = &wreg_addr_e1;
846 else if (CHIP_IS_E1H(bp))
847 wreg_addr_p = &wreg_addr_e1h;
848 else if (CHIP_IS_E2(bp))
849 wreg_addr_p = &wreg_addr_e2;
850 else if (CHIP_IS_E3A0(bp))
851 wreg_addr_p = &wreg_addr_e3;
852 else if (CHIP_IS_E3B0(bp))
853 wreg_addr_p = &wreg_addr_e3b0;
854
855 /* Read the idle_chk registers */
856 for (i = 0; i < IDLE_REGS_COUNT; i++) {
857 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
858 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
859 for (j = 0; j < idle_reg_addrs[i].size; j++)
860 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
861 }
862 }
0fea29c1
VZ		 863
864 /* Read the regular registers */
07ba6af4
MS		 865 for (i = 0; i < REGS_COUNT; i++) {
866 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
867 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
0fea29c1
VZ		 868 for (j = 0; j < reg_addrs[i].size; j++)
869 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
07ba6af4
MS		 870 }
871 }
872
873 /* Read the CAM registers */
874 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
875 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
876 for (i = 0; i < wreg_addr_p->size; i++) {
877 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
878
879 /* In case of wreg_addr register, read additional
880 registers from read_regs array
881 */
882 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
883 addr = *(wreg_addr_p->read_regs);
884 *p++ = REG_RD(bp, addr + j*4);
885 }
886 }
887 }
888
889 /* Paged registers are supported in E2 & E3 only */
890 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
16a5fd92 891 /* Read "paged" registers */
07ba6af4
MS		 892 bnx2x_read_pages_regs(bp, p, preset);
893 }
894
895 return 0;
896}
897
898static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
899{
900 u32 preset_idx;
0fea29c1 901
07ba6af4
MS		 902 /* Read all registers, by reading all preset registers */
903 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
904 /* Skip presets with IOR */
905 if ((preset_idx == 2) ||
906 (preset_idx == 5) ||
907 (preset_idx == 8) ||
908 (preset_idx == 11))
909 continue;
910 __bnx2x_get_preset_regs(bp, p, preset_idx);
911 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
912 }
0fea29c1
VZ		 913}
914
de0c62db
DK		 915static void bnx2x_get_regs(struct net_device *dev,
916 struct ethtool_regs *regs, void *_p)
917{
0fea29c1 918 u32 *p = _p;
de0c62db 919 struct bnx2x *bp = netdev_priv(dev);
07ba6af4 920 struct dump_header dump_hdr = {0};
de0c62db 921
07ba6af4 922 regs->version = 2;
de0c62db
DK		 923 memset(p, 0, regs->len);
924
925 if (!netif_running(bp->dev))
926 return;
927
4a33bc03
VZ		 928 /* Disable parity attentions as long as following dump may
929 * cause false alarms by reading never written registers. We
930 * will re-enable parity attentions right after the dump.
931 */
07ba6af4 932
4a33bc03
VZ		 933 bnx2x_disable_blocks_parity(bp);
934
07ba6af4
MS		 935 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
936 dump_hdr.preset = DUMP_ALL_PRESETS;
937 dump_hdr.version = BNX2X_DUMP_VERSION;
938
939 /* dump_meta_data presents OR of CHIP and PATH. */
940 if (CHIP_IS_E1(bp)) {
941 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
942 } else if (CHIP_IS_E1H(bp)) {
943 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
944 } else if (CHIP_IS_E2(bp)) {
945 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
946 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
947 } else if (CHIP_IS_E3A0(bp)) {
948 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
949 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
950 } else if (CHIP_IS_E3B0(bp)) {
951 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
952 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
953 }
954
955 memcpy(p, &dump_hdr, sizeof(struct dump_header));
956 p += dump_hdr.header_size + 1;
de0c62db 957
0fea29c1
VZ		 958 /* Actually read the registers */
959 __bnx2x_get_regs(bp, p);
960
4293b9f5 961 /* Re-enable parity attentions */
07ba6af4
MS		 962 bnx2x_clear_blocks_parity(bp);
963 bnx2x_enable_blocks_parity(bp);
07ba6af4
MS		 964}
965
966static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
967{
968 struct bnx2x *bp = netdev_priv(dev);
969 int regdump_len = 0;
970
971 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
972 regdump_len *= 4;
973 regdump_len += sizeof(struct dump_header);
974
975 return regdump_len;
976}
977
978static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
979{
980 struct bnx2x *bp = netdev_priv(dev);
981
982 /* Use the ethtool_dump "flag" field as the dump preset index */
5bb680d6
MS		 983 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
984 return -EINVAL;
985
07ba6af4
MS		 986 bp->dump_preset_idx = val->flag;
987 return 0;
988}
989
990static int bnx2x_get_dump_flag(struct net_device *dev,
991 struct ethtool_dump *dump)
992{
993 struct bnx2x *bp = netdev_priv(dev);
994
8cc2d927
MS		 995 dump->version = BNX2X_DUMP_VERSION;
996 dump->flag = bp->dump_preset_idx;
07ba6af4
MS		 997 /* Calculate the requested preset idx length */
998 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
999 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1000 bp->dump_preset_idx, dump->len);
07ba6af4
MS		 1001 return 0;
1002}
1003
1004static int bnx2x_get_dump_data(struct net_device *dev,
1005 struct ethtool_dump *dump,
1006 void *buffer)
1007{
1008 u32 *p = buffer;
1009 struct bnx2x *bp = netdev_priv(dev);
1010 struct dump_header dump_hdr = {0};
1011
07ba6af4
MS		 1012 /* Disable parity attentions as long as following dump may
1013 * cause false alarms by reading never written registers. We
1014 * will re-enable parity attentions right after the dump.
1015 */
1016
07ba6af4
MS		 1017 bnx2x_disable_blocks_parity(bp);
1018
07ba6af4
MS		 1019 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1020 dump_hdr.preset = bp->dump_preset_idx;
1021 dump_hdr.version = BNX2X_DUMP_VERSION;
1022
1023 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1024
1025 /* dump_meta_data presents OR of CHIP and PATH. */
1026 if (CHIP_IS_E1(bp)) {
1027 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1028 } else if (CHIP_IS_E1H(bp)) {
1029 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1030 } else if (CHIP_IS_E2(bp)) {
1031 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1032 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1033 } else if (CHIP_IS_E3A0(bp)) {
1034 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1035 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1036 } else if (CHIP_IS_E3B0(bp)) {
1037 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1038 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1039 }
1040
1041 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1042 p += dump_hdr.header_size + 1;
1043
1044 /* Actually read the registers */
1045 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1046
4293b9f5 1047 /* Re-enable parity attentions */
07ba6af4
MS		 1048 bnx2x_clear_blocks_parity(bp);
1049 bnx2x_enable_blocks_parity(bp);
1050
07ba6af4 1051 return 0;
de0c62db
DK		 1052}
1053
de0c62db
DK		 1054static void bnx2x_get_drvinfo(struct net_device *dev,
1055 struct ethtool_drvinfo *info)
1056{
1057 struct bnx2x *bp = netdev_priv(dev);
de0c62db 1058
68aad78c
RJ		 1059 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1060 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db 1061
8ca5e17e
AE		 1062 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1063
68aad78c 1064 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db 1065 info->n_stats = BNX2X_NUM_STATS;
cf2c1df6 1066 info->testinfo_len = BNX2X_NUM_TESTS(bp);
de0c62db
DK		 1067 info->eedump_len = bp->common.flash_size;
1068 info->regdump_len = bnx2x_get_regs_len(dev);
1069}
1070
1071static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1072{
1073 struct bnx2x *bp = netdev_priv(dev);
1074
1075 if (bp->flags & NO_WOL_FLAG) {
1076 wol->supported = 0;
1077 wol->wolopts = 0;
1078 } else {
1079 wol->supported = WAKE_MAGIC;
1080 if (bp->wol)
1081 wol->wolopts = WAKE_MAGIC;
1082 else
1083 wol->wolopts = 0;
1084 }
1085 memset(&wol->sopass, 0, sizeof(wol->sopass));
1086}
1087
1088static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1089{
1090 struct bnx2x *bp = netdev_priv(dev);
1091
51c1a580 1092 if (wol->wolopts & ~WAKE_MAGIC) {
2de67439 1093 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
de0c62db 1094 return -EINVAL;
51c1a580 1095 }
de0c62db
DK		 1096
1097 if (wol->wolopts & WAKE_MAGIC) {
51c1a580 1098 if (bp->flags & NO_WOL_FLAG) {
2de67439 1099 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
de0c62db 1100 return -EINVAL;
51c1a580 1101 }
de0c62db
DK		 1102 bp->wol = 1;
1103 } else
1104 bp->wol = 0;
1105
1106 return 0;
1107}
1108
1109static u32 bnx2x_get_msglevel(struct net_device *dev)
1110{
1111 struct bnx2x *bp = netdev_priv(dev);
1112
1113 return bp->msg_enable;
1114}
1115
1116static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1117{
1118 struct bnx2x *bp = netdev_priv(dev);
1119
7a25cc73
DK		 1120 if (capable(CAP_NET_ADMIN)) {
1121 /* dump MCP trace */
ad5afc89 1122 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
7a25cc73 1123 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 1124 bp->msg_enable = level;
7a25cc73 1125 }
de0c62db
DK		 1126}
1127
1128static int bnx2x_nway_reset(struct net_device *dev)
1129{
1130 struct bnx2x *bp = netdev_priv(dev);
1131
1132 if (!bp->port.pmf)
1133 return 0;
1134
1135 if (netif_running(dev)) {
1136 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 1137 bnx2x_force_link_reset(bp);
de0c62db
DK		 1138 bnx2x_link_set(bp);
1139 }
1140
1141 return 0;
1142}
1143
1144static u32 bnx2x_get_link(struct net_device *dev)
1145{
1146 struct bnx2x *bp = netdev_priv(dev);
1147
f2e0899f 1148 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 1149 return 0;
1150
6495d15a
DK		 1151 if (IS_VF(bp))
1152 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1153 &bp->vf_link_vars.link_report_flags);
1154
de0c62db
DK		 1155 return bp->link_vars.link_up;
1156}
1157
1158static int bnx2x_get_eeprom_len(struct net_device *dev)
1159{
1160 struct bnx2x *bp = netdev_priv(dev);
1161
1162 return bp->common.flash_size;
1163}
1164
16a5fd92
YM		 1165/* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1166 * had we done things the other way around, if two pfs from the same port would
f16da43b
AE		 1167 * attempt to access nvram at the same time, we could run into a scenario such
1168 * as:
1169 * pf A takes the port lock.
1170 * pf B succeeds in taking the same lock since they are from the same port.
1171 * pf A takes the per pf misc lock. Performs eeprom access.
1172 * pf A finishes. Unlocks the per pf misc lock.
1173 * Pf B takes the lock and proceeds to perform it's own access.
1174 * pf A unlocks the per port lock, while pf B is still working (!).
1175 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
2de67439 1176 * access corrupted by pf B)
f16da43b 1177 */
de0c62db
DK		 1178static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1179{
1180 int port = BP_PORT(bp);
1181 int count, i;
f16da43b
AE		 1182 u32 val;
1183
1184 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1185 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1186
1187 /* adjust timeout for emulation/FPGA */
754a2f52 1188 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1189 if (CHIP_REV_IS_SLOW(bp))
1190 count *= 100;
1191
1192 /* request access to nvram interface */
1193 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1194 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1195
1196 for (i = 0; i < count*10; i++) {
1197 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1198 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1199 break;
1200
1201 udelay(5);
1202 }
1203
1204 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
51c1a580
MS		 1205 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1206 "cannot get access to nvram interface\n");
de0c62db
DK		 1207 return -EBUSY;
1208 }
1209
1210 return 0;
1211}
1212
1213static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1214{
1215 int port = BP_PORT(bp);
1216 int count, i;
f16da43b 1217 u32 val;
de0c62db
DK		 1218
1219 /* adjust timeout for emulation/FPGA */
754a2f52 1220 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1221 if (CHIP_REV_IS_SLOW(bp))
1222 count *= 100;
1223
1224 /* relinquish nvram interface */
1225 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1226 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1227
1228 for (i = 0; i < count*10; i++) {
1229 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1230 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1231 break;
1232
1233 udelay(5);
1234 }
1235
1236 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
51c1a580
MS		 1237 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1238 "cannot free access to nvram interface\n");
de0c62db
DK		 1239 return -EBUSY;
1240 }
1241
f16da43b
AE		 1242 /* release HW lock: protect against other PFs in PF Direct Assignment */
1243 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1244 return 0;
1245}
1246
1247static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1248{
1249 u32 val;
1250
1251 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1252
1253 /* enable both bits, even on read */
1254 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1255 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1256 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1257}
1258
1259static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1260{
1261 u32 val;
1262
1263 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1264
1265 /* disable both bits, even after read */
1266 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1267 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1268 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1269}
1270
1271static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1272 u32 cmd_flags)
1273{
1274 int count, i, rc;
1275 u32 val;
1276
1277 /* build the command word */
1278 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1279
1280 /* need to clear DONE bit separately */
1281 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1282
1283 /* address of the NVRAM to read from */
1284 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1285 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1286
1287 /* issue a read command */
1288 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1289
1290 /* adjust timeout for emulation/FPGA */
754a2f52 1291 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1292 if (CHIP_REV_IS_SLOW(bp))
1293 count *= 100;
1294
1295 /* wait for completion */
1296 *ret_val = 0;
1297 rc = -EBUSY;
1298 for (i = 0; i < count; i++) {
1299 udelay(5);
1300 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1301
1302 if (val & MCPR_NVM_COMMAND_DONE) {
1303 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1304 /* we read nvram data in cpu order
1305 * but ethtool sees it as an array of bytes
07ba6af4
MS		 1306 * converting to big-endian will do the work
1307 */
de0c62db
DK		 1308 *ret_val = cpu_to_be32(val);
1309 rc = 0;
1310 break;
1311 }
1312 }
51c1a580
MS		 1313 if (rc == -EBUSY)
1314 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1315 "nvram read timeout expired\n");
de0c62db
DK		 1316 return rc;
1317}
1318
1319static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1320 int buf_size)
1321{
1322 int rc;
1323 u32 cmd_flags;
1324 __be32 val;
1325
1326 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1327 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1328 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1329 offset, buf_size);
1330 return -EINVAL;
1331 }
1332
1333 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1334 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1335 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1336 offset, buf_size, bp->common.flash_size);
1337 return -EINVAL;
1338 }
1339
1340 /* request access to nvram interface */
1341 rc = bnx2x_acquire_nvram_lock(bp);
1342 if (rc)
1343 return rc;
1344
1345 /* enable access to nvram interface */
1346 bnx2x_enable_nvram_access(bp);
1347
1348 /* read the first word(s) */
1349 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1350 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1351 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1352 memcpy(ret_buf, &val, 4);
1353
1354 /* advance to the next dword */
1355 offset += sizeof(u32);
1356 ret_buf += sizeof(u32);
1357 buf_size -= sizeof(u32);
1358 cmd_flags = 0;
1359 }
1360
1361 if (rc == 0) {
1362 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1363 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1364 memcpy(ret_buf, &val, 4);
1365 }
1366
1367 /* disable access to nvram interface */
1368 bnx2x_disable_nvram_access(bp);
1369 bnx2x_release_nvram_lock(bp);
1370
1371 return rc;
1372}
1373
85640952
DK		 1374static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1375 int buf_size)
1376{
1377 int rc;
1378
1379 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1380
1381 if (!rc) {
1382 __be32 *be = (__be32 *)buf;
1383
1384 while ((buf_size -= 4) >= 0)
1385 *buf++ = be32_to_cpu(*be++);
1386 }
1387
1388 return rc;
1389}
1390
3fb43eb2
YM		 1391static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1392{
1393 int rc = 1;
1394 u16 pm = 0;
1395 struct net_device *dev = pci_get_drvdata(bp->pdev);
1396
29ed74c3 1397 if (bp->pdev->pm_cap)
3fb43eb2 1398 rc = pci_read_config_word(bp->pdev,
29ed74c3 1399 bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
3fb43eb2 1400
829a5071 1401 if ((rc && !netif_running(dev)) ||
c957d09f 1402 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
3fb43eb2
YM		 1403 return false;
1404
1405 return true;
1406}
1407
de0c62db
DK		 1408static int bnx2x_get_eeprom(struct net_device *dev,
1409 struct ethtool_eeprom *eeprom, u8 *eebuf)
1410{
1411 struct bnx2x *bp = netdev_priv(dev);
de0c62db 1412
3fb43eb2 1413 if (!bnx2x_is_nvm_accessible(bp)) {
51c1a580
MS		 1414 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1415 "cannot access eeprom when the interface is down\n");
de0c62db 1416 return -EAGAIN;
51c1a580 1417 }
de0c62db 1418
51c1a580 1419 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1420 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1421 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1422 eeprom->len, eeprom->len);
1423
1424 /* parameters already validated in ethtool_get_eeprom */
1425
f1691dc6 1426 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
de0c62db
DK		 1427}
1428
24ea818e
YM		 1429static int bnx2x_get_module_eeprom(struct net_device *dev,
1430 struct ethtool_eeprom *ee,
1431 u8 *data)
1432{
1433 struct bnx2x *bp = netdev_priv(dev);
669d6996 1434 int rc = -EINVAL, phy_idx;
24ea818e 1435 u8 *user_data = data;
669d6996 1436 unsigned int start_addr = ee->offset, xfer_size = 0;
24ea818e 1437
3fb43eb2 1438 if (!bnx2x_is_nvm_accessible(bp)) {
24ea818e
YM		 1439 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1440 "cannot access eeprom when the interface is down\n");
1441 return -EAGAIN;
1442 }
1443
1444 phy_idx = bnx2x_get_cur_phy_idx(bp);
669d6996
YR		 1445
1446 /* Read A0 section */
1447 if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1448 /* Limit transfer size to the A0 section boundary */
1449 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1450 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1451 else
1452 xfer_size = ee->len;
1453 bnx2x_acquire_phy_lock(bp);
24ea818e
YM		 1454 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1455 &bp->link_params,
669d6996
YR		 1456 I2C_DEV_ADDR_A0,
1457 start_addr,
24ea818e
YM		 1458 xfer_size,
1459 user_data);
669d6996
YR		 1460 bnx2x_release_phy_lock(bp);
1461 if (rc) {
1462 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1463
1464 return -EINVAL;
1465 }
24ea818e 1466 user_data += xfer_size;
669d6996 1467 start_addr += xfer_size;
24ea818e
YM		 1468 }
1469
669d6996
YR		 1470 /* Read A2 section */
1471 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1472 (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1473 xfer_size = ee->len - xfer_size;
1474 /* Limit transfer size to the A2 section boundary */
1475 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1476 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1477 start_addr -= ETH_MODULE_SFF_8079_LEN;
1478 bnx2x_acquire_phy_lock(bp);
1479 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1480 &bp->link_params,
1481 I2C_DEV_ADDR_A2,
1482 start_addr,
1483 xfer_size,
1484 user_data);
1485 bnx2x_release_phy_lock(bp);
1486 if (rc) {
1487 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1488 return -EINVAL;
1489 }
1490 }
24ea818e
YM		 1491 return rc;
1492}
1493
1494static int bnx2x_get_module_info(struct net_device *dev,
1495 struct ethtool_modinfo *modinfo)
1496{
1497 struct bnx2x *bp = netdev_priv(dev);
669d6996
YR		 1498 int phy_idx, rc;
1499 u8 sff8472_comp, diag_type;
1500
3fb43eb2 1501 if (!bnx2x_is_nvm_accessible(bp)) {
669d6996 1502 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
24ea818e
YM		 1503 "cannot access eeprom when the interface is down\n");
1504 return -EAGAIN;
1505 }
24ea818e 1506 phy_idx = bnx2x_get_cur_phy_idx(bp);
669d6996
YR		 1507 bnx2x_acquire_phy_lock(bp);
1508 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1509 &bp->link_params,
1510 I2C_DEV_ADDR_A0,
1511 SFP_EEPROM_SFF_8472_COMP_ADDR,
1512 SFP_EEPROM_SFF_8472_COMP_SIZE,
1513 &sff8472_comp);
1514 bnx2x_release_phy_lock(bp);
1515 if (rc) {
1516 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1517 return -EINVAL;
1518 }
1519
1520 bnx2x_acquire_phy_lock(bp);
1521 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1522 &bp->link_params,
1523 I2C_DEV_ADDR_A0,
1524 SFP_EEPROM_DIAG_TYPE_ADDR,
1525 SFP_EEPROM_DIAG_TYPE_SIZE,
1526 &diag_type);
1527 bnx2x_release_phy_lock(bp);
1528 if (rc) {
1529 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1530 return -EINVAL;
1531 }
1532
1533 if (!sff8472_comp ||
1534 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
24ea818e
YM		 1535 modinfo->type = ETH_MODULE_SFF_8079;
1536 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
669d6996
YR		 1537 } else {
1538 modinfo->type = ETH_MODULE_SFF_8472;
1539 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
24ea818e 1540 }
669d6996 1541 return 0;
24ea818e
YM		 1542}
1543
de0c62db
DK		 1544static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1545 u32 cmd_flags)
1546{
1547 int count, i, rc;
1548
1549 /* build the command word */
1550 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1551
1552 /* need to clear DONE bit separately */
1553 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1554
1555 /* write the data */
1556 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1557
1558 /* address of the NVRAM to write to */
1559 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1560 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1561
1562 /* issue the write command */
1563 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1564
1565 /* adjust timeout for emulation/FPGA */
754a2f52 1566 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1567 if (CHIP_REV_IS_SLOW(bp))
1568 count *= 100;
1569
1570 /* wait for completion */
1571 rc = -EBUSY;
1572 for (i = 0; i < count; i++) {
1573 udelay(5);
1574 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1575 if (val & MCPR_NVM_COMMAND_DONE) {
1576 rc = 0;
1577 break;
1578 }
1579 }
1580
51c1a580
MS		 1581 if (rc == -EBUSY)
1582 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1583 "nvram write timeout expired\n");
de0c62db
DK		 1584 return rc;
1585}
1586
1587#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1588
1589static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1590 int buf_size)
1591{
1592 int rc;
30c20b67
DK		 1593 u32 cmd_flags, align_offset, val;
1594 __be32 val_be;
de0c62db
DK		 1595
1596 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1597 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1598 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1599 offset, buf_size, bp->common.flash_size);
1600 return -EINVAL;
1601 }
1602
1603 /* request access to nvram interface */
1604 rc = bnx2x_acquire_nvram_lock(bp);
1605 if (rc)
1606 return rc;
1607
1608 /* enable access to nvram interface */
1609 bnx2x_enable_nvram_access(bp);
1610
1611 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1612 align_offset = (offset & ~0x03);
30c20b67 1613 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
de0c62db
DK		 1614
1615 if (rc == 0) {
de0c62db 1616 /* nvram data is returned as an array of bytes
07ba6af4
MS		 1617 * convert it back to cpu order
1618 */
30c20b67
DK		 1619 val = be32_to_cpu(val_be);
1620
c957d09f
YM		 1621 val &= ~le32_to_cpu((__force __le32)
1622 (0xff << BYTE_OFFSET(offset)));
1623 val |= le32_to_cpu((__force __le32)
1624 (*data_buf << BYTE_OFFSET(offset)));
de0c62db
DK		 1625
1626 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1627 cmd_flags);
1628 }
1629
1630 /* disable access to nvram interface */
1631 bnx2x_disable_nvram_access(bp);
1632 bnx2x_release_nvram_lock(bp);
1633
1634 return rc;
1635}
1636
1637static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1638 int buf_size)
1639{
1640 int rc;
1641 u32 cmd_flags;
1642 u32 val;
1643 u32 written_so_far;
1644
1645 if (buf_size == 1) /* ethtool */
1646 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1647
1648 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1649 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1650 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1651 offset, buf_size);
1652 return -EINVAL;
1653 }
1654
1655 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1656 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1657 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1658 offset, buf_size, bp->common.flash_size);
1659 return -EINVAL;
1660 }
1661
1662 /* request access to nvram interface */
1663 rc = bnx2x_acquire_nvram_lock(bp);
1664 if (rc)
1665 return rc;
1666
1667 /* enable access to nvram interface */
1668 bnx2x_enable_nvram_access(bp);
1669
1670 written_so_far = 0;
1671 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1672 while ((written_so_far < buf_size) && (rc == 0)) {
1673 if (written_so_far == (buf_size - sizeof(u32)))
1674 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1675 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1676 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1677 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1678 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1679
1680 memcpy(&val, data_buf, 4);
1681
68bf5a10
YM		 1682 /* Notice unlike bnx2x_nvram_read_dword() this will not
1683 * change val using be32_to_cpu(), which causes data to flip
1684 * if the eeprom is read and then written back. This is due
1685 * to tools utilizing this functionality that would break
1686 * if this would be resolved.
1687 */
de0c62db
DK		 1688 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1689
1690 /* advance to the next dword */
1691 offset += sizeof(u32);
1692 data_buf += sizeof(u32);
1693 written_so_far += sizeof(u32);
1694 cmd_flags = 0;
1695 }
1696
1697 /* disable access to nvram interface */
1698 bnx2x_disable_nvram_access(bp);
1699 bnx2x_release_nvram_lock(bp);
1700
1701 return rc;
1702}
1703
1704static int bnx2x_set_eeprom(struct net_device *dev,
1705 struct ethtool_eeprom *eeprom, u8 *eebuf)
1706{
1707 struct bnx2x *bp = netdev_priv(dev);
1708 int port = BP_PORT(bp);
1709 int rc = 0;
e10bc84d 1710 u32 ext_phy_config;
3fb43eb2
YM		 1711
1712 if (!bnx2x_is_nvm_accessible(bp)) {
51c1a580
MS		 1713 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1714 "cannot access eeprom when the interface is down\n");
de0c62db 1715 return -EAGAIN;
51c1a580 1716 }
de0c62db 1717
51c1a580 1718 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1719 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1720 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1721 eeprom->len, eeprom->len);
1722
1723 /* parameters already validated in ethtool_set_eeprom */
1724
1725 /* PHY eeprom can be accessed only by the PMF */
1726 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
51c1a580
MS		 1727 !bp->port.pmf) {
1728 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1729 "wrong magic or interface is not pmf\n");
de0c62db 1730 return -EINVAL;
51c1a580 1731 }
de0c62db 1732
e10bc84d
YR		 1733 ext_phy_config =
1734 SHMEM_RD(bp,
1735 dev_info.port_hw_config[port].external_phy_config);
1736
de0c62db
DK		 1737 if (eeprom->magic == 0x50485950) {
1738 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1739 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1740
1741 bnx2x_acquire_phy_lock(bp);
1742 rc |= bnx2x_link_reset(&bp->link_params,
1743 &bp->link_vars, 0);
e10bc84d 1744 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1745 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1746 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1747 MISC_REGISTERS_GPIO_HIGH, port);
1748 bnx2x_release_phy_lock(bp);
1749 bnx2x_link_report(bp);
1750
1751 } else if (eeprom->magic == 0x50485952) {
1752 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1753 if (bp->state == BNX2X_STATE_OPEN) {
1754 bnx2x_acquire_phy_lock(bp);
1755 rc |= bnx2x_link_reset(&bp->link_params,
1756 &bp->link_vars, 1);
1757
1758 rc |= bnx2x_phy_init(&bp->link_params,
1759 &bp->link_vars);
1760 bnx2x_release_phy_lock(bp);
1761 bnx2x_calc_fc_adv(bp);
1762 }
1763 } else if (eeprom->magic == 0x53985943) {
1764 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1765 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1766 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1767
1768 /* DSP Remove Download Mode */
1769 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1770 MISC_REGISTERS_GPIO_LOW, port);
1771
1772 bnx2x_acquire_phy_lock(bp);
1773
e10bc84d
YR		 1774 bnx2x_sfx7101_sp_sw_reset(bp,
1775 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1776
1777 /* wait 0.5 sec to allow it to run */
1778 msleep(500);
1779 bnx2x_ext_phy_hw_reset(bp, port);
1780 msleep(500);
1781 bnx2x_release_phy_lock(bp);
1782 }
1783 } else
1784 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1785
1786 return rc;
1787}
f85582f8 1788
de0c62db
DK		 1789static int bnx2x_get_coalesce(struct net_device *dev,
1790 struct ethtool_coalesce *coal)
1791{
1792 struct bnx2x *bp = netdev_priv(dev);
1793
1794 memset(coal, 0, sizeof(struct ethtool_coalesce));
1795
1796 coal->rx_coalesce_usecs = bp->rx_ticks;
1797 coal->tx_coalesce_usecs = bp->tx_ticks;
1798
1799 return 0;
1800}
1801
1802static int bnx2x_set_coalesce(struct net_device *dev,
1803 struct ethtool_coalesce *coal)
1804{
1805 struct bnx2x *bp = netdev_priv(dev);
1806
1807 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1808 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1809 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1810
1811 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1812 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1813 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1814
1815 if (netif_running(dev))
1816 bnx2x_update_coalesce(bp);
1817
1818 return 0;
1819}
1820
1821static void bnx2x_get_ringparam(struct net_device *dev,
1822 struct ethtool_ringparam *ering)
1823{
1824 struct bnx2x *bp = netdev_priv(dev);
1825
1826 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1827
25141580
DK		 1828 if (bp->rx_ring_size)
1829 ering->rx_pending = bp->rx_ring_size;
1830 else
c2188952 1831 ering->rx_pending = MAX_RX_AVAIL;
25141580 1832
a3348722 1833 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
de0c62db
DK		 1834 ering->tx_pending = bp->tx_ring_size;
1835}
1836
1837static int bnx2x_set_ringparam(struct net_device *dev,
1838 struct ethtool_ringparam *ering)
1839{
1840 struct bnx2x *bp = netdev_priv(dev);
de0c62db 1841
04c46736
YM		 1842 DP(BNX2X_MSG_ETHTOOL,
1843 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1844 ering->rx_pending, ering->tx_pending);
1845
909d9faa
YM		 1846 if (pci_num_vf(bp->pdev)) {
1847 DP(BNX2X_MSG_IOV,
1848 "VFs are enabled, can not change ring parameters\n");
1849 return -EPERM;
1850 }
1851
de0c62db 1852 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 1853 DP(BNX2X_MSG_ETHTOOL,
1854 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 1855 return -EAGAIN;
1856 }
1857
1858 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1859 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1860 MIN_RX_SIZE_TPA)) ||
2e98ffc2 1861 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
51c1a580
MS		 1862 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1863 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db 1864 return -EINVAL;
51c1a580 1865 }
de0c62db
DK		 1866
1867 bp->rx_ring_size = ering->rx_pending;
1868 bp->tx_ring_size = ering->tx_pending;
1869
a9fccec7 1870 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1871}
1872
1873static void bnx2x_get_pauseparam(struct net_device *dev,
1874 struct ethtool_pauseparam *epause)
1875{
1876 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1877 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1878 int cfg_reg;
1879
a22f0788
YR		 1880 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1881 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1882
9e7e8399 1883 if (!epause->autoneg)
241fb5d2 1884 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
9e7e8399
MY		 1885 else
1886 cfg_reg = bp->link_params.req_fc_auto_adv;
1887
1888 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1889 BNX2X_FLOW_CTRL_RX);
9e7e8399 1890 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1891 BNX2X_FLOW_CTRL_TX);
1892
51c1a580 1893 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1894 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1895 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1896}
1897
1898static int bnx2x_set_pauseparam(struct net_device *dev,
1899 struct ethtool_pauseparam *epause)
1900{
1901 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1902 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1903 if (IS_MF(bp))
de0c62db
DK		 1904 return 0;
1905
51c1a580 1906 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1907 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1908 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1909
a22f0788 1910 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1911
1912 if (epause->rx_pause)
a22f0788 1913 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1914
1915 if (epause->tx_pause)
a22f0788 1916 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1917
a22f0788
YR		 1918 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1919 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1920
1921 if (epause->autoneg) {
a22f0788 1922 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 1923 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
de0c62db
DK		 1924 return -EINVAL;
1925 }
1926
a22f0788
YR		 1927 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1928 bp->link_params.req_flow_ctrl[cfg_idx] =
1929 BNX2X_FLOW_CTRL_AUTO;
1930 }
ba35a0fd 1931 bp->link_params.req_fc_auto_adv = 0;
5cd75f0c
YR		 1932 if (epause->rx_pause)
1933 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1934
1935 if (epause->tx_pause)
1936 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
ba35a0fd
YR		 1937
1938 if (!bp->link_params.req_fc_auto_adv)
1939 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1940 }
1941
51c1a580 1942 DP(BNX2X_MSG_ETHTOOL,
a22f0788 1943 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1944
1945 if (netif_running(dev)) {
1946 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1947 bnx2x_link_set(bp);
1948 }
1949
1950 return 0;
1951}
1952
5889335c 1953static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
cf2c1df6
MS		 1954 "register_test (offline) ",
1955 "memory_test (offline) ",
1956 "int_loopback_test (offline)",
1957 "ext_loopback_test (offline)",
1958 "nvram_test (online) ",
1959 "interrupt_test (online) ",
1960 "link_test (online) "
de0c62db
DK		 1961};
1962
3521b419
YM		 1963enum {
1964 BNX2X_PRI_FLAG_ISCSI,
1965 BNX2X_PRI_FLAG_FCOE,
1966 BNX2X_PRI_FLAG_STORAGE,
1967 BNX2X_PRI_FLAG_LEN,
1968};
1969
1970static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
1971 "iSCSI offload support",
1972 "FCoE offload support",
1973 "Storage only interface"
1974};
1975
e9939c80
YM		 1976static u32 bnx2x_eee_to_adv(u32 eee_adv)
1977{
1978 u32 modes = 0;
1979
1980 if (eee_adv & SHMEM_EEE_100M_ADV)
1981 modes |= ADVERTISED_100baseT_Full;
1982 if (eee_adv & SHMEM_EEE_1G_ADV)
1983 modes |= ADVERTISED_1000baseT_Full;
1984 if (eee_adv & SHMEM_EEE_10G_ADV)
1985 modes |= ADVERTISED_10000baseT_Full;
1986
1987 return modes;
1988}
1989
1990static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1991{
1992 u32 eee_adv = 0;
1993 if (modes & ADVERTISED_100baseT_Full)
1994 eee_adv |= SHMEM_EEE_100M_ADV;
1995 if (modes & ADVERTISED_1000baseT_Full)
1996 eee_adv |= SHMEM_EEE_1G_ADV;
1997 if (modes & ADVERTISED_10000baseT_Full)
1998 eee_adv |= SHMEM_EEE_10G_ADV;
1999
2000 return eee_adv << shift;
2001}
2002
2003static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2004{
2005 struct bnx2x *bp = netdev_priv(dev);
2006 u32 eee_cfg;
2007
2008 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2009 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2010 return -EOPNOTSUPP;
2011 }
2012
08e9acc2 2013 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 2014
2015 edata->supported =
2016 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2017 SHMEM_EEE_SUPPORTED_SHIFT);
2018
2019 edata->advertised =
2020 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2021 SHMEM_EEE_ADV_STATUS_SHIFT);
2022 edata->lp_advertised =
2023 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2024 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2025
2026 /* SHMEM value is in 16u units --> Convert to 1u units. */
2027 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2028
2029 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
2030 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
2031 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2032
2033 return 0;
2034}
2035
2036static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2037{
2038 struct bnx2x *bp = netdev_priv(dev);
2039 u32 eee_cfg;
2040 u32 advertised;
2041
2042 if (IS_MF(bp))
2043 return 0;
2044
2045 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2046 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2047 return -EOPNOTSUPP;
2048 }
2049
08e9acc2 2050 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 2051
2052 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2053 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2054 return -EOPNOTSUPP;
2055 }
2056
2057 advertised = bnx2x_adv_to_eee(edata->advertised,
2058 SHMEM_EEE_ADV_STATUS_SHIFT);
2059 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2060 DP(BNX2X_MSG_ETHTOOL,
efc7ce03 2061 "Direct manipulation of EEE advertisement is not supported\n");
e9939c80
YM		 2062 return -EINVAL;
2063 }
2064
2065 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2066 DP(BNX2X_MSG_ETHTOOL,
2067 "Maximal Tx Lpi timer supported is %x(u)\n",
2068 EEE_MODE_TIMER_MASK);
2069 return -EINVAL;
2070 }
2071 if (edata->tx_lpi_enabled &&
2072 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2073 DP(BNX2X_MSG_ETHTOOL,
2074 "Minimal Tx Lpi timer supported is %d(u)\n",
2075 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2076 return -EINVAL;
2077 }
2078
2079 /* All is well; Apply changes*/
2080 if (edata->eee_enabled)
2081 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2082 else
2083 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2084
2085 if (edata->tx_lpi_enabled)
2086 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2087 else
2088 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2089
2090 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2091 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2092 EEE_MODE_TIMER_MASK) |
2093 EEE_MODE_OVERRIDE_NVRAM |
2094 EEE_MODE_OUTPUT_TIME;
2095
16a5fd92 2096 /* Restart link to propagate changes */
e9939c80
YM		 2097 if (netif_running(dev)) {
2098 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 2099 bnx2x_force_link_reset(bp);
e9939c80
YM		 2100 bnx2x_link_set(bp);
2101 }
2102
2103 return 0;
2104}
2105
619c5cb6
VZ		 2106enum {
2107 BNX2X_CHIP_E1_OFST = 0,
2108 BNX2X_CHIP_E1H_OFST,
2109 BNX2X_CHIP_E2_OFST,
2110 BNX2X_CHIP_E3_OFST,
2111 BNX2X_CHIP_E3B0_OFST,
2112 BNX2X_CHIP_MAX_OFST
2113};
2114
2115#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
2116#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
2117#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
2118#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
2119#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
2120
2121#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2122#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2123
de0c62db
DK		 2124static int bnx2x_test_registers(struct bnx2x *bp)
2125{
2126 int idx, i, rc = -ENODEV;
619c5cb6 2127 u32 wr_val = 0, hw;
de0c62db
DK		 2128 int port = BP_PORT(bp);
2129 static const struct {
619c5cb6 2130 u32 hw;
de0c62db
DK		 2131 u32 offset0;
2132 u32 offset1;
2133 u32 mask;
2134 } reg_tbl[] = {
619c5cb6
VZ		 2135/* 0 */ { BNX2X_CHIP_MASK_ALL,
2136 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2137 { BNX2X_CHIP_MASK_ALL,
2138 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2139 { BNX2X_CHIP_MASK_E1X,
2140 HC_REG_AGG_INT_0, 4, 0x000003ff },
2141 { BNX2X_CHIP_MASK_ALL,
2142 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2143 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2144 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2145 { BNX2X_CHIP_MASK_E3B0,
2146 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2147 { BNX2X_CHIP_MASK_ALL,
2148 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2149 { BNX2X_CHIP_MASK_ALL,
2150 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2151 { BNX2X_CHIP_MASK_ALL,
2152 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2153 { BNX2X_CHIP_MASK_ALL,
2154 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2155/* 10 */ { BNX2X_CHIP_MASK_ALL,
2156 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2157 { BNX2X_CHIP_MASK_ALL,
2158 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2159 { BNX2X_CHIP_MASK_ALL,
2160 QM_REG_CONNNUM_0, 4, 0x000fffff },
2161 { BNX2X_CHIP_MASK_ALL,
2162 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2163 { BNX2X_CHIP_MASK_ALL,
2164 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2165 { BNX2X_CHIP_MASK_ALL,
2166 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2167 { BNX2X_CHIP_MASK_ALL,
2168 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2169 { BNX2X_CHIP_MASK_ALL,
2170 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2171 { BNX2X_CHIP_MASK_ALL,
2172 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2173 { BNX2X_CHIP_MASK_ALL,
2174 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2175/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2176 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2177 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2178 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2179 { BNX2X_CHIP_MASK_ALL,
2180 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2181 { BNX2X_CHIP_MASK_ALL,
2182 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2183 { BNX2X_CHIP_MASK_ALL,
2184 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2185 { BNX2X_CHIP_MASK_ALL,
2186 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2187 { BNX2X_CHIP_MASK_ALL,
2188 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2189 { BNX2X_CHIP_MASK_ALL,
2190 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2191 { BNX2X_CHIP_MASK_ALL,
2192 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2193 { BNX2X_CHIP_MASK_ALL,
2194 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2195/* 30 */ { BNX2X_CHIP_MASK_ALL,
2196 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2197 { BNX2X_CHIP_MASK_ALL,
2198 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2199 { BNX2X_CHIP_MASK_ALL,
2200 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2201 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2202 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2203 { BNX2X_CHIP_MASK_ALL,
2204 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2205 { BNX2X_CHIP_MASK_ALL,
2206 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2207 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2208 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2209 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2210 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2211
2212 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 2213 };
2214
3fb43eb2 2215 if (!bnx2x_is_nvm_accessible(bp)) {
51c1a580
MS		 2216 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2217 "cannot access eeprom when the interface is down\n");
de0c62db 2218 return rc;
51c1a580 2219 }
de0c62db 2220
619c5cb6
VZ		 2221 if (CHIP_IS_E1(bp))
2222 hw = BNX2X_CHIP_MASK_E1;
2223 else if (CHIP_IS_E1H(bp))
2224 hw = BNX2X_CHIP_MASK_E1H;
2225 else if (CHIP_IS_E2(bp))
2226 hw = BNX2X_CHIP_MASK_E2;
2227 else if (CHIP_IS_E3B0(bp))
2228 hw = BNX2X_CHIP_MASK_E3B0;
2229 else /* e3 A0 */
2230 hw = BNX2X_CHIP_MASK_E3;
2231
de0c62db 2232 /* Repeat the test twice:
07ba6af4
MS		 2233 * First by writing 0x00000000, second by writing 0xffffffff
2234 */
de0c62db
DK		 2235 for (idx = 0; idx < 2; idx++) {
2236
2237 switch (idx) {
2238 case 0:
2239 wr_val = 0;
2240 break;
2241 case 1:
2242 wr_val = 0xffffffff;
2243 break;
2244 }
2245
2246 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2247 u32 offset, mask, save_val, val;
619c5cb6 2248 if (!(hw & reg_tbl[i].hw))
f2e0899f 2249 continue;
de0c62db
DK		 2250
2251 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2252 mask = reg_tbl[i].mask;
2253
2254 save_val = REG_RD(bp, offset);
2255
ec6ba945 2256 REG_WR(bp, offset, wr_val & mask);
f85582f8 2257
de0c62db
DK		 2258 val = REG_RD(bp, offset);
2259
2260 /* Restore the original register's value */
2261 REG_WR(bp, offset, save_val);
2262
2263 /* verify value is as expected */
2264 if ((val & mask) != (wr_val & mask)) {
51c1a580 2265 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 2266 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2267 offset, val, wr_val, mask);
2268 goto test_reg_exit;
2269 }
2270 }
2271 }
2272
2273 rc = 0;
2274
2275test_reg_exit:
2276 return rc;
2277}
2278
2279static int bnx2x_test_memory(struct bnx2x *bp)
2280{
2281 int i, j, rc = -ENODEV;
619c5cb6 2282 u32 val, index;
de0c62db
DK		 2283 static const struct {
2284 u32 offset;
2285 int size;
2286 } mem_tbl[] = {
2287 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2288 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2289 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2290 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2291 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2292 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2293 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2294
2295 { 0xffffffff, 0 }
2296 };
619c5cb6 2297
de0c62db
DK		 2298 static const struct {
2299 char *name;
2300 u32 offset;
619c5cb6 2301 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 2302 } prty_tbl[] = {
619c5cb6
VZ		 2303 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2304 {0x3ffc0, 0, 0, 0} },
2305 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2306 {0x2, 0x2, 0, 0} },
2307 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2308 {0, 0, 0, 0} },
2309 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2310 {0x3ffc0, 0, 0, 0} },
2311 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2312 {0x3ffc0, 0, 0, 0} },
2313 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2314 {0x3ffc1, 0, 0, 0} },
2315
2316 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 2317 };
2318
3fb43eb2 2319 if (!bnx2x_is_nvm_accessible(bp)) {
51c1a580
MS		 2320 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2321 "cannot access eeprom when the interface is down\n");
de0c62db 2322 return rc;
51c1a580 2323 }
de0c62db 2324
619c5cb6
VZ		 2325 if (CHIP_IS_E1(bp))
2326 index = BNX2X_CHIP_E1_OFST;
2327 else if (CHIP_IS_E1H(bp))
2328 index = BNX2X_CHIP_E1H_OFST;
2329 else if (CHIP_IS_E2(bp))
2330 index = BNX2X_CHIP_E2_OFST;
2331 else /* e3 */
2332 index = BNX2X_CHIP_E3_OFST;
2333
f2e0899f
DK		 2334 /* pre-Check the parity status */
2335 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2336 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 2337 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 2338 DP(BNX2X_MSG_ETHTOOL,
f2e0899f
DK		 2339 "%s is 0x%x\n", prty_tbl[i].name, val);
2340 goto test_mem_exit;
2341 }
2342 }
2343
de0c62db
DK		 2344 /* Go through all the memories */
2345 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2346 for (j = 0; j < mem_tbl[i].size; j++)
2347 REG_RD(bp, mem_tbl[i].offset + j*4);
2348
2349 /* Check the parity status */
2350 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2351 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 2352 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 2353 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 2354 "%s is 0x%x\n", prty_tbl[i].name, val);
2355 goto test_mem_exit;
2356 }
2357 }
2358
2359 rc = 0;
2360
2361test_mem_exit:
2362 return rc;
2363}
2364
a22f0788 2365static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 2366{
f2e0899f 2367 int cnt = 1400;
de0c62db 2368
619c5cb6 2369 if (link_up) {
a22f0788 2370 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 2371 msleep(20);
2372
2373 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
51c1a580 2374 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
8970b2e4
MS		 2375
2376 cnt = 1400;
2377 while (!bp->link_vars.link_up && cnt--)
2378 msleep(20);
2379
2380 if (cnt <= 0 && !bp->link_vars.link_up)
2381 DP(BNX2X_MSG_ETHTOOL,
2382 "Timeout waiting for link init\n");
619c5cb6 2383 }
de0c62db
DK		 2384}
2385
619c5cb6 2386static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 2387{
2388 unsigned int pkt_size, num_pkts, i;
2389 struct sk_buff *skb;
2390 unsigned char *packet;
2391 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2392 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
65565884 2393 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
de0c62db
DK		 2394 u16 tx_start_idx, tx_idx;
2395 u16 rx_start_idx, rx_idx;
b0700b1e 2396 u16 pkt_prod, bd_prod;
de0c62db
DK		 2397 struct sw_tx_bd *tx_buf;
2398 struct eth_tx_start_bd *tx_start_bd;
de0c62db
DK		 2399 dma_addr_t mapping;
2400 union eth_rx_cqe *cqe;
619c5cb6 2401 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 2402 struct sw_rx_bd *rx_buf;
2403 u16 len;
2404 int rc = -ENODEV;
e52fcb24 2405 u8 *data;
8970b2e4
MS		 2406 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2407 txdata->txq_index);
de0c62db
DK		 2408
2409 /* check the loopback mode */
2410 switch (loopback_mode) {
2411 case BNX2X_PHY_LOOPBACK:
8970b2e4
MS		 2412 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2413 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
de0c62db 2414 return -EINVAL;
8970b2e4 2415 }
de0c62db
DK		 2416 break;
2417 case BNX2X_MAC_LOOPBACK:
32911333
YR		 2418 if (CHIP_IS_E3(bp)) {
2419 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2420 if (bp->port.supported[cfg_idx] &
2421 (SUPPORTED_10000baseT_Full |
2422 SUPPORTED_20000baseMLD2_Full |
2423 SUPPORTED_20000baseKR2_Full))
2424 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2425 else
2426 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2427 } else
2428 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2429
de0c62db
DK		 2430 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2431 break;
8970b2e4
MS		 2432 case BNX2X_EXT_LOOPBACK:
2433 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2434 DP(BNX2X_MSG_ETHTOOL,
2435 "Can't configure external loopback\n");
2436 return -EINVAL;
2437 }
2438 break;
de0c62db 2439 default:
51c1a580 2440 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db
DK		 2441 return -EINVAL;
2442 }
2443
2444 /* prepare the loopback packet */
2445 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2446 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 2447 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db 2448 if (!skb) {
51c1a580 2449 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
de0c62db
DK		 2450 rc = -ENOMEM;
2451 goto test_loopback_exit;
2452 }
2453 packet = skb_put(skb, pkt_size);
2454 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
c7bf7169 2455 eth_zero_addr(packet + ETH_ALEN);
de0c62db
DK		 2456 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2457 for (i = ETH_HLEN; i < pkt_size; i++)
2458 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 2459 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2460 skb_headlen(skb), DMA_TO_DEVICE);
2461 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2462 rc = -ENOMEM;
2463 dev_kfree_skb(skb);
51c1a580 2464 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
619c5cb6
VZ		 2465 goto test_loopback_exit;
2466 }
de0c62db
DK		 2467
2468 /* send the loopback packet */
2469 num_pkts = 0;
6383c0b3 2470 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2471 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2472
73dbb5e1
DK		 2473 netdev_tx_sent_queue(txq, skb->len);
2474
6383c0b3
AE		 2475 pkt_prod = txdata->tx_pkt_prod++;
2476 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2477 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 2478 tx_buf->skb = skb;
2479 tx_buf->flags = 0;
2480
6383c0b3
AE		 2481 bd_prod = TX_BD(txdata->tx_bd_prod);
2482 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 2483 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2484 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2485 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2486 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 2487 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 2488 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 2489 SET_FLAG(tx_start_bd->general_data,
2490 ETH_TX_START_BD_HDR_NBDS,
2491 1);
96bed4b9
YM		 2492 SET_FLAG(tx_start_bd->general_data,
2493 ETH_TX_START_BD_PARSE_NBDS,
2494 0);
de0c62db
DK		 2495
2496 /* turn on parsing and get a BD */
2497 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 2498
96bed4b9
YM		 2499 if (CHIP_IS_E1x(bp)) {
2500 u16 global_data = 0;
2501 struct eth_tx_parse_bd_e1x *pbd_e1x =
2502 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2503 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2504 SET_FLAG(global_data,
2505 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2506 pbd_e1x->global_data = cpu_to_le16(global_data);
2507 } else {
2508 u32 parsing_data = 0;
2509 struct eth_tx_parse_bd_e2 *pbd_e2 =
2510 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2511 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2512 SET_FLAG(parsing_data,
2513 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2514 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2515 }
de0c62db
DK		 2516 wmb();
2517
6383c0b3 2518 txdata->tx_db.data.prod += 2;
de0c62db 2519 barrier();
6383c0b3 2520 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 2521
2522 mmiowb();
619c5cb6 2523 barrier();
de0c62db
DK		 2524
2525 num_pkts++;
6383c0b3 2526 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 2527
2528 udelay(100);
2529
6383c0b3 2530 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2531 if (tx_idx != tx_start_idx + num_pkts)
2532 goto test_loopback_exit;
2533
f2e0899f
DK		 2534 /* Unlike HC IGU won't generate an interrupt for status block
2535 * updates that have been performed while interrupts were
2536 * disabled.
2537 */
e1210d12
ED		 2538 if (bp->common.int_block == INT_BLOCK_IGU) {
2539 /* Disable local BHes to prevent a dead-lock situation between
2540 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2541 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2542 */
2543 local_bh_disable();
6383c0b3 2544 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 2545 local_bh_enable();
2546 }
f2e0899f 2547
de0c62db
DK		 2548 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2549 if (rx_idx != rx_start_idx + num_pkts)
2550 goto test_loopback_exit;
2551
b0700b1e 2552 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 2553 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 2554 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2555 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 2556 goto test_loopback_rx_exit;
2557
621b4d66 2558 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
de0c62db
DK		 2559 if (len != pkt_size)
2560 goto test_loopback_rx_exit;
2561
2562 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 2563 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 2564 dma_unmap_addr(rx_buf, mapping),
2565 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 2566 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 2567 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 2568 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 2569 goto test_loopback_rx_exit;
2570
2571 rc = 0;
2572
2573test_loopback_rx_exit:
2574
2575 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2576 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2577 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2578 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2579
2580 /* Update producers */
2581 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2582 fp_rx->rx_sge_prod);
2583
2584test_loopback_exit:
2585 bp->link_params.loopback_mode = LOOPBACK_NONE;
2586
2587 return rc;
2588}
2589
619c5cb6 2590static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 2591{
2592 int rc = 0, res;
2593
2594 if (BP_NOMCP(bp))
2595 return rc;
2596
2597 if (!netif_running(bp->dev))
2598 return BNX2X_LOOPBACK_FAILED;
2599
2600 bnx2x_netif_stop(bp, 1);
2601 bnx2x_acquire_phy_lock(bp);
2602
619c5cb6 2603 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db 2604 if (res) {
51c1a580 2605 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
de0c62db
DK		 2606 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2607 }
2608
619c5cb6 2609 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db 2610 if (res) {
51c1a580 2611 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
de0c62db
DK		 2612 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2613 }
2614
2615 bnx2x_release_phy_lock(bp);
2616 bnx2x_netif_start(bp);
2617
2618 return rc;
2619}
2620
8970b2e4
MS		 2621static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2622{
2623 int rc;
2624 u8 is_serdes =
2625 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2626
2627 if (BP_NOMCP(bp))
2628 return -ENODEV;
2629
2630 if (!netif_running(bp->dev))
2631 return BNX2X_EXT_LOOPBACK_FAILED;
2632
5d07d868 2633 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
8970b2e4
MS		 2634 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2635 if (rc) {
2636 DP(BNX2X_MSG_ETHTOOL,
2637 "Can't perform self-test, nic_load (for external lb) failed\n");
2638 return -ENODEV;
2639 }
2640 bnx2x_wait_for_link(bp, 1, is_serdes);
2641
2642 bnx2x_netif_stop(bp, 1);
2643
2644 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2645 if (rc)
2646 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2647
2648 bnx2x_netif_start(bp);
2649
2650 return rc;
2651}
2652
edb944d2
DK		 2653struct code_entry {
2654 u32 sram_start_addr;
2655 u32 code_attribute;
2656#define CODE_IMAGE_TYPE_MASK 0xf0800003
2657#define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003
2658#define CODE_IMAGE_LENGTH_MASK 0x007ffffc
2659#define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000
2660 u32 nvm_start_addr;
2661};
2662
2663#define CODE_ENTRY_MAX 16
2664#define CODE_ENTRY_EXTENDED_DIR_IDX 15
2665#define MAX_IMAGES_IN_EXTENDED_DIR 64
2666#define NVRAM_DIR_OFFSET 0x14
2667
2668#define EXTENDED_DIR_EXISTS(code) \
2669 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2670 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2671
de0c62db 2672#define CRC32_RESIDUAL 0xdebb20e3
edb944d2
DK		 2673#define CRC_BUFF_SIZE 256
2674
2675static int bnx2x_nvram_crc(struct bnx2x *bp,
2676 int offset,
2677 int size,
2678 u8 *buff)
2679{
2680 u32 crc = ~0;
2681 int rc = 0, done = 0;
2682
2683 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2684 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2685
2686 while (done < size) {
2687 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2688
2689 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2690
2691 if (rc)
2692 return rc;
2693
2694 crc = crc32_le(crc, buff, count);
2695 done += count;
2696 }
2697
2698 if (crc != CRC32_RESIDUAL)
2699 rc = -EINVAL;
2700
2701 return rc;
2702}
2703
2704static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2705 struct code_entry *entry,
2706 u8 *buff)
2707{
2708 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2709 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2710 int rc;
2711
2712 /* Zero-length images and AFEX profiles do not have CRC */
2713 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2714 return 0;
2715
2716 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2717 if (rc)
2718 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2719 "image %x has failed crc test (rc %d)\n", type, rc);
2720
2721 return rc;
2722}
2723
2724static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2725{
2726 int rc;
2727 struct code_entry entry;
2728
2729 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2730 if (rc)
2731 return rc;
2732
2733 return bnx2x_test_nvram_dir(bp, &entry, buff);
2734}
2735
2736static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2737{
2738 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2739 struct code_entry entry;
2740 int i;
2741
2742 rc = bnx2x_nvram_read32(bp,
2743 dir_offset +
2744 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2745 (u32 *)&entry, sizeof(entry));
2746 if (rc)
2747 return rc;
2748
2749 if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2750 return 0;
2751
2752 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2753 &cnt, sizeof(u32));
2754 if (rc)
2755 return rc;
2756
2757 dir_offset = entry.nvm_start_addr + 8;
2758
2759 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2760 rc = bnx2x_test_dir_entry(bp, dir_offset +
2761 sizeof(struct code_entry) * i,
2762 buff);
2763 if (rc)
2764 return rc;
2765 }
2766
2767 return 0;
2768}
2769
2770static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2771{
2772 u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2773 int i;
2774
2775 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2776
2777 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2778 rc = bnx2x_test_dir_entry(bp, dir_offset +
2779 sizeof(struct code_entry) * i,
2780 buff);
2781 if (rc)
2782 return rc;
2783 }
2784
2785 return bnx2x_test_nvram_ext_dirs(bp, buff);
2786}
2787
2788struct crc_pair {
2789 int offset;
2790 int size;
2791};
2792
2793static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2794 const struct crc_pair *nvram_tbl, u8 *buf)
2795{
2796 int i;
2797
2798 for (i = 0; nvram_tbl[i].size; i++) {
2799 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2800 nvram_tbl[i].size, buf);
2801 if (rc) {
2802 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2803 "nvram_tbl[%d] has failed crc test (rc %d)\n",
2804 i, rc);
2805 return rc;
2806 }
2807 }
2808
2809 return 0;
2810}
de0c62db
DK		 2811
2812static int bnx2x_test_nvram(struct bnx2x *bp)
2813{
edb944d2 2814 const struct crc_pair nvram_tbl[] = {
de0c62db
DK		 2815 { 0, 0x14 }, /* bootstrap */
2816 { 0x14, 0xec }, /* dir */
2817 { 0x100, 0x350 }, /* manuf_info */
2818 { 0x450, 0xf0 }, /* feature_info */
2819 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2820 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2821 { 0, 0 }
2822 };
edb944d2
DK		 2823 const struct crc_pair nvram_tbl2[] = {
2824 { 0x7e8, 0x350 }, /* manuf_info2 */
2825 { 0xb38, 0xf0 }, /* feature_info */
2826 { 0, 0 }
2827 };
2828
85640952 2829 u8 *buf;
edb944d2
DK		 2830 int rc;
2831 u32 magic;
de0c62db
DK		 2832
2833 if (BP_NOMCP(bp))
2834 return 0;
2835
edb944d2 2836 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
afa13b4b 2837 if (!buf) {
51c1a580 2838 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
afa13b4b
MY		 2839 rc = -ENOMEM;
2840 goto test_nvram_exit;
2841 }
afa13b4b 2842
85640952 2843 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
de0c62db 2844 if (rc) {
51c1a580
MS		 2845 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2846 "magic value read (rc %d)\n", rc);
de0c62db
DK		 2847 goto test_nvram_exit;
2848 }
2849
de0c62db 2850 if (magic != 0x669955aa) {
51c1a580
MS		 2851 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2852 "wrong magic value (0x%08x)\n", magic);
de0c62db
DK		 2853 rc = -ENODEV;
2854 goto test_nvram_exit;
2855 }
2856
edb944d2
DK		 2857 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2858 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2859 if (rc)
2860 goto test_nvram_exit;
de0c62db 2861
edb944d2
DK		 2862 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2863 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2864 SHARED_HW_CFG_HIDE_PORT1;
de0c62db 2865
edb944d2 2866 if (!hide) {
51c1a580 2867 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
edb944d2
DK		 2868 "Port 1 CRC test-set\n");
2869 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2870 if (rc)
2871 goto test_nvram_exit;
de0c62db
DK		 2872 }
2873 }
2874
edb944d2
DK		 2875 rc = bnx2x_test_nvram_dirs(bp, buf);
2876
de0c62db 2877test_nvram_exit:
afa13b4b 2878 kfree(buf);
de0c62db
DK		 2879 return rc;
2880}
2881
619c5cb6 2882/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2883static int bnx2x_test_intr(struct bnx2x *bp)
2884{
3b603066 2885 struct bnx2x_queue_state_params params = {NULL};
de0c62db 2886
51c1a580
MS		 2887 if (!netif_running(bp->dev)) {
2888 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2889 "cannot access eeprom when the interface is down\n");
de0c62db 2890 return -ENODEV;
51c1a580 2891 }
de0c62db 2892
15192a8c 2893 params.q_obj = &bp->sp_objs->q_obj;
619c5cb6 2894 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2895
619c5cb6
VZ		 2896 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2897
2898 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2899}
2900
2901static void bnx2x_self_test(struct net_device *dev,
2902 struct ethtool_test *etest, u64 *buf)
2903{
2904 struct bnx2x *bp = netdev_priv(dev);
a336ca7c
YR		 2905 u8 is_serdes, link_up;
2906 int rc, cnt = 0;
cf2c1df6 2907
909d9faa
YM		 2908 if (pci_num_vf(bp->pdev)) {
2909 DP(BNX2X_MSG_IOV,
2910 "VFs are enabled, can not perform self test\n");
2911 return;
2912 }
2913
de0c62db 2914 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 2915 netdev_err(bp->dev,
2916 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 2917 etest->flags |= ETH_TEST_FL_FAILED;
2918 return;
2919 }
2de67439 2920
8970b2e4
MS		 2921 DP(BNX2X_MSG_ETHTOOL,
2922 "Self-test command parameters: offline = %d, external_lb = %d\n",
2923 (etest->flags & ETH_TEST_FL_OFFLINE),
2924 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
de0c62db 2925
cf2c1df6 2926 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
de0c62db 2927
bd8e012b
YM		 2928 if (bnx2x_test_nvram(bp) != 0) {
2929 if (!IS_MF(bp))
2930 buf[4] = 1;
2931 else
2932 buf[0] = 1;
2933 etest->flags |= ETH_TEST_FL_FAILED;
2934 }
2935
cf2c1df6 2936 if (!netif_running(dev)) {
bd8e012b 2937 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
de0c62db 2938 return;
cf2c1df6 2939 }
de0c62db 2940
a22f0788 2941 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
a336ca7c 2942 link_up = bp->link_vars.link_up;
cf2c1df6
MS		 2943 /* offline tests are not supported in MF mode */
2944 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
de0c62db
DK		 2945 int port = BP_PORT(bp);
2946 u32 val;
de0c62db
DK		 2947
2948 /* save current value of input enable for TX port IF */
2949 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2950 /* disable input for TX port IF */
2951 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2952
5d07d868 2953 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
cf2c1df6
MS		 2954 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2955 if (rc) {
2956 etest->flags |= ETH_TEST_FL_FAILED;
2957 DP(BNX2X_MSG_ETHTOOL,
2958 "Can't perform self-test, nic_load (for offline) failed\n");
2959 return;
2960 }
2961
de0c62db 2962 /* wait until link state is restored */
619c5cb6 2963 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2964
2965 if (bnx2x_test_registers(bp) != 0) {
2966 buf[0] = 1;
2967 etest->flags |= ETH_TEST_FL_FAILED;
2968 }
2969 if (bnx2x_test_memory(bp) != 0) {
2970 buf[1] = 1;
2971 etest->flags |= ETH_TEST_FL_FAILED;
2972 }
f85582f8 2973
8970b2e4 2974 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
de0c62db
DK		 2975 if (buf[2] != 0)
2976 etest->flags |= ETH_TEST_FL_FAILED;
2977
8970b2e4
MS		 2978 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2979 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2980 if (buf[3] != 0)
2981 etest->flags |= ETH_TEST_FL_FAILED;
2982 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2983 }
2984
5d07d868 2985 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
de0c62db
DK		 2986
2987 /* restore input for TX port IF */
2988 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
cf2c1df6
MS		 2989 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2990 if (rc) {
2991 etest->flags |= ETH_TEST_FL_FAILED;
2992 DP(BNX2X_MSG_ETHTOOL,
2993 "Can't perform self-test, nic_load (for online) failed\n");
2994 return;
2995 }
de0c62db 2996 /* wait until link state is restored */
a22f0788 2997 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db 2998 }
bd8e012b 2999
de0c62db 3000 if (bnx2x_test_intr(bp) != 0) {
cf2c1df6
MS		 3001 if (!IS_MF(bp))
3002 buf[5] = 1;
3003 else
3004 buf[1] = 1;
de0c62db
DK		 3005 etest->flags |= ETH_TEST_FL_FAILED;
3006 }
633ac363 3007
a336ca7c
YR		 3008 if (link_up) {
3009 cnt = 100;
3010 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3011 msleep(20);
3012 }
3013
3014 if (!cnt) {
cf2c1df6
MS		 3015 if (!IS_MF(bp))
3016 buf[6] = 1;
3017 else
3018 buf[2] = 1;
633ac363
DK		 3019 etest->flags |= ETH_TEST_FL_FAILED;
3020 }
de0c62db
DK		 3021}
3022
de0c62db
DK		 3023#define IS_PORT_STAT(i) \
3024 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
3025#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
d8361051
YM		 3026#define HIDE_PORT_STAT(bp) \
3027 ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \
3028 IS_VF(bp))
de0c62db 3029
619c5cb6
VZ		 3030/* ethtool statistics are displayed for all regular ethernet queues and the
3031 * fcoe L2 queue if not disabled
3032 */
1191cb83 3033static int bnx2x_num_stat_queues(struct bnx2x *bp)
619c5cb6
VZ		 3034{
3035 return BNX2X_NUM_ETH_QUEUES(bp);
3036}
3037
de0c62db
DK		 3038static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3039{
3040 struct bnx2x *bp = netdev_priv(dev);
3521b419 3041 int i, num_strings = 0;
de0c62db
DK		 3042
3043 switch (stringset) {
3044 case ETH_SS_STATS:
3045 if (is_multi(bp)) {
3521b419
YM		 3046 num_strings = bnx2x_num_stat_queues(bp) *
3047 BNX2X_NUM_Q_STATS;
d5e83632 3048 } else
3521b419 3049 num_strings = 0;
d8361051 3050 if (HIDE_PORT_STAT(bp)) {
d5e83632
YM		 3051 for (i = 0; i < BNX2X_NUM_STATS; i++)
3052 if (IS_FUNC_STAT(i))
3521b419 3053 num_strings++;
d5e83632 3054 } else
3521b419 3055 num_strings += BNX2X_NUM_STATS;
d5e83632 3056
3521b419 3057 return num_strings;
de0c62db
DK		 3058
3059 case ETH_SS_TEST:
cf2c1df6 3060 return BNX2X_NUM_TESTS(bp);
de0c62db 3061
3521b419
YM		 3062 case ETH_SS_PRIV_FLAGS:
3063 return BNX2X_PRI_FLAG_LEN;
3064
de0c62db
DK		 3065 default:
3066 return -EINVAL;
3067 }
3068}
3069
3521b419
YM		 3070static u32 bnx2x_get_private_flags(struct net_device *dev)
3071{
3072 struct bnx2x *bp = netdev_priv(dev);
3073 u32 flags = 0;
3074
3075 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3076 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3077 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3078
3079 return flags;
3080}
3081
de0c62db
DK		 3082static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3083{
3084 struct bnx2x *bp = netdev_priv(dev);
5889335c 3085 int i, j, k, start;
ec6ba945 3086 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 3087
3088 switch (stringset) {
3089 case ETH_SS_STATS:
d5e83632 3090 k = 0;
de0c62db 3091 if (is_multi(bp)) {
619c5cb6 3092 for_each_eth_queue(bp, i) {
ec6ba945 3093 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 3094 sprintf(queue_name, "%d", i);
de0c62db 3095 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 3096 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3097 ETH_GSTRING_LEN,
3098 bnx2x_q_stats_arr[j].string,
3099 queue_name);
de0c62db
DK		 3100 k += BNX2X_NUM_Q_STATS;
3101 }
de0c62db 3102 }
d5e83632 3103
d5e83632 3104 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
d8361051 3105 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
d5e83632
YM		 3106 continue;
3107 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3108 bnx2x_stats_arr[i].string);
3109 j++;
3110 }
3111
de0c62db
DK		 3112 break;
3113
3114 case ETH_SS_TEST:
cf2c1df6
MS		 3115 /* First 4 tests cannot be done in MF mode */
3116 if (!IS_MF(bp))
3117 start = 0;
3118 else
3119 start = 4;
5889335c
MS		 3120 memcpy(buf, bnx2x_tests_str_arr + start,
3121 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3521b419
YM		 3122 break;
3123
3124 case ETH_SS_PRIV_FLAGS:
3125 memcpy(buf, bnx2x_private_arr,
3126 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3127 break;
de0c62db
DK		 3128 }
3129}
3130
3131static void bnx2x_get_ethtool_stats(struct net_device *dev,
3132 struct ethtool_stats *stats, u64 *buf)
3133{
3134 struct bnx2x *bp = netdev_priv(dev);
3135 u32 *hw_stats, *offset;
d5e83632 3136 int i, j, k = 0;
de0c62db
DK		 3137
3138 if (is_multi(bp)) {
619c5cb6 3139 for_each_eth_queue(bp, i) {
15192a8c 3140 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
de0c62db
DK		 3141 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3142 if (bnx2x_q_stats_arr[j].size == 0) {
3143 /* skip this counter */
3144 buf[k + j] = 0;
3145 continue;
3146 }
3147 offset = (hw_stats +
3148 bnx2x_q_stats_arr[j].offset);
3149 if (bnx2x_q_stats_arr[j].size == 4) {
3150 /* 4-byte counter */
3151 buf[k + j] = (u64) *offset;
3152 continue;
3153 }
3154 /* 8-byte counter */
3155 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3156 }
3157 k += BNX2X_NUM_Q_STATS;
3158 }
d5e83632
YM		 3159 }
3160
3161 hw_stats = (u32 *)&bp->eth_stats;
3162 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
d8361051 3163 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
d5e83632
YM		 3164 continue;
3165 if (bnx2x_stats_arr[i].size == 0) {
3166 /* skip this counter */
3167 buf[k + j] = 0;
3168 j++;
3169 continue;
de0c62db 3170 }
d5e83632
YM		 3171 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3172 if (bnx2x_stats_arr[i].size == 4) {
3173 /* 4-byte counter */
3174 buf[k + j] = (u64) *offset;
de0c62db 3175 j++;
d5e83632 3176 continue;
de0c62db 3177 }
d5e83632
YM		 3178 /* 8-byte counter */
3179 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3180 j++;
de0c62db
DK		 3181 }
3182}
3183
32d36134 3184static int bnx2x_set_phys_id(struct net_device *dev,
3185 enum ethtool_phys_id_state state)
de0c62db
DK		 3186{
3187 struct bnx2x *bp = netdev_priv(dev);
de0c62db 3188
3fb43eb2 3189 if (!bnx2x_is_nvm_accessible(bp)) {
51c1a580
MS		 3190 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3191 "cannot access eeprom when the interface is down\n");
32d36134 3192 return -EAGAIN;
51c1a580 3193 }
de0c62db 3194
32d36134 3195 switch (state) {
3196 case ETHTOOL_ID_ACTIVE:
fce55922 3197 return 1; /* cycle on/off once per second */
de0c62db 3198
32d36134 3199 case ETHTOOL_ID_ON:
8203c4b6 3200 bnx2x_acquire_phy_lock(bp);
32d36134 3201 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 3202 LED_MODE_ON, SPEED_1000);
8203c4b6 3203 bnx2x_release_phy_lock(bp);
32d36134 3204 break;
de0c62db 3205
32d36134 3206 case ETHTOOL_ID_OFF:
8203c4b6 3207 bnx2x_acquire_phy_lock(bp);
32d36134 3208 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 3209 LED_MODE_FRONT_PANEL_OFF, 0);
8203c4b6 3210 bnx2x_release_phy_lock(bp);
32d36134 3211 break;
3212
3213 case ETHTOOL_ID_INACTIVE:
8203c4b6 3214 bnx2x_acquire_phy_lock(bp);
e1943424
DM		 3215 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3216 LED_MODE_OPER,
3217 bp->link_vars.line_speed);
8203c4b6 3218 bnx2x_release_phy_lock(bp);
32d36134 3219 }
de0c62db
DK		 3220
3221 return 0;
3222}
3223
5d317c6a
MS		 3224static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3225{
5d317c6a
MS		 3226 switch (info->flow_type) {
3227 case TCP_V4_FLOW:
3228 case TCP_V6_FLOW:
3229 info->data = RXH_IP_SRC | RXH_IP_DST |
3230 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3231 break;
3232 case UDP_V4_FLOW:
3233 if (bp->rss_conf_obj.udp_rss_v4)
3234 info->data = RXH_IP_SRC | RXH_IP_DST |
3235 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3236 else
3237 info->data = RXH_IP_SRC | RXH_IP_DST;
3238 break;
3239 case UDP_V6_FLOW:
3240 if (bp->rss_conf_obj.udp_rss_v6)
3241 info->data = RXH_IP_SRC | RXH_IP_DST |
3242 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3243 else
3244 info->data = RXH_IP_SRC | RXH_IP_DST;
3245 break;
3246 case IPV4_FLOW:
3247 case IPV6_FLOW:
3248 info->data = RXH_IP_SRC | RXH_IP_DST;
3249 break;
3250 default:
3251 info->data = 0;
3252 break;
3253 }
3254
3255 return 0;
3256}
3257
ab532cf3 3258static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 3259 u32 *rules __always_unused)
ab532cf3
TH		 3260{
3261 struct bnx2x *bp = netdev_priv(dev);
3262
3263 switch (info->cmd) {
3264 case ETHTOOL_GRXRINGS:
3265 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3266 return 0;
5d317c6a
MS		 3267 case ETHTOOL_GRXFH:
3268 return bnx2x_get_rss_flags(bp, info);
3269 default:
3270 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3271 return -EOPNOTSUPP;
3272 }
3273}
3274
3275static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3276{
3277 int udp_rss_requested;
3278
3279 DP(BNX2X_MSG_ETHTOOL,
3280 "Set rss flags command parameters: flow type = %d, data = %llu\n",
3281 info->flow_type, info->data);
3282
3283 switch (info->flow_type) {
3284 case TCP_V4_FLOW:
3285 case TCP_V6_FLOW:
3286 /* For TCP only 4-tupple hash is supported */
3287 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3288 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3289 DP(BNX2X_MSG_ETHTOOL,
3290 "Command parameters not supported\n");
3291 return -EINVAL;
5d317c6a 3292 }
2de67439 3293 return 0;
5d317c6a
MS		 3294
3295 case UDP_V4_FLOW:
3296 case UDP_V6_FLOW:
3297 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3298 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2de67439 3299 RXH_L4_B_0_1 | RXH_L4_B_2_3))
5d317c6a
MS		 3300 udp_rss_requested = 1;
3301 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3302 udp_rss_requested = 0;
3303 else
3304 return -EINVAL;
3305 if ((info->flow_type == UDP_V4_FLOW) &&
3306 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3307 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3308 DP(BNX2X_MSG_ETHTOOL,
3309 "rss re-configured, UDP 4-tupple %s\n",
3310 udp_rss_requested ? "enabled" : "disabled");
60cad4e6 3311 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
5d317c6a
MS		 3312 } else if ((info->flow_type == UDP_V6_FLOW) &&
3313 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3314 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
5d317c6a
MS		 3315 DP(BNX2X_MSG_ETHTOOL,
3316 "rss re-configured, UDP 4-tupple %s\n",
3317 udp_rss_requested ? "enabled" : "disabled");
60cad4e6 3318 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
5d317c6a 3319 }
924d75ab
YM		 3320 return 0;
3321
5d317c6a
MS		 3322 case IPV4_FLOW:
3323 case IPV6_FLOW:
3324 /* For IP only 2-tupple hash is supported */
3325 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3326 DP(BNX2X_MSG_ETHTOOL,
3327 "Command parameters not supported\n");
3328 return -EINVAL;
5d317c6a 3329 }
924d75ab
YM		 3330 return 0;
3331
5d317c6a
MS		 3332 case SCTP_V4_FLOW:
3333 case AH_ESP_V4_FLOW:
3334 case AH_V4_FLOW:
3335 case ESP_V4_FLOW:
3336 case SCTP_V6_FLOW:
3337 case AH_ESP_V6_FLOW:
3338 case AH_V6_FLOW:
3339 case ESP_V6_FLOW:
3340 case IP_USER_FLOW:
3341 case ETHER_FLOW:
3342 /* RSS is not supported for these protocols */
3343 if (info->data) {
3344 DP(BNX2X_MSG_ETHTOOL,
3345 "Command parameters not supported\n");
3346 return -EINVAL;
5d317c6a 3347 }
924d75ab
YM		 3348 return 0;
3349
5d317c6a
MS		 3350 default:
3351 return -EINVAL;
3352 }
3353}
3354
3355static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3356{
3357 struct bnx2x *bp = netdev_priv(dev);
ab532cf3 3358
5d317c6a
MS		 3359 switch (info->cmd) {
3360 case ETHTOOL_SRXFH:
3361 return bnx2x_set_rss_flags(bp, info);
ab532cf3 3362 default:
51c1a580 3363 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
ab532cf3
TH		 3364 return -EOPNOTSUPP;
3365 }
3366}
3367
7850f63f
BH		 3368static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3369{
96305234 3370 return T_ETH_INDIRECTION_TABLE_SIZE;
7850f63f
BH		 3371}
3372
892311f6
EP		 3373static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3374 u8 *hfunc)
ab532cf3
TH		 3375{
3376 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 3377 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3378 size_t i;
ab532cf3 3379
892311f6
EP		 3380 if (hfunc)
3381 *hfunc = ETH_RSS_HASH_TOP;
3382 if (!indir)
3383 return 0;
3384
619c5cb6
VZ		 3385 /* Get the current configuration of the RSS indirection table */
3386 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3387
3388 /*
3389 * We can't use a memcpy() as an internal storage of an
3390 * indirection table is a u8 array while indir->ring_index
3391 * points to an array of u32.
3392 *
3393 * Indirection table contains the FW Client IDs, so we need to
3394 * align the returned table to the Client ID of the leading RSS
3395 * queue.
3396 */
7850f63f
BH		 3397 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3398 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 3399
ab532cf3
TH		 3400 return 0;
3401}
3402
fe62d001 3403static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
892311f6 3404 const u8 *key, const u8 hfunc)
ab532cf3
TH		 3405{
3406 struct bnx2x *bp = netdev_priv(dev);
3407 size_t i;
619c5cb6 3408
892311f6
EP		 3409 /* We require at least one supported parameter to be changed and no
3410 * change in any of the unsupported parameters
3411 */
3412 if (key ||
3413 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3414 return -EOPNOTSUPP;
3415
3416 if (!indir)
3417 return 0;
3418
619c5cb6 3419 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6 3420 /*
fe62d001 3421 * The same as in bnx2x_get_rxfh: we can't use a memcpy()
619c5cb6
VZ		 3422 * as an internal storage of an indirection table is a u8 array
3423 * while indir->ring_index points to an array of u32.
3424 *
3425 * Indirection table contains the FW Client IDs, so we need to
3426 * align the received table to the Client ID of the leading RSS
3427 * queue
3428 */
5d317c6a 3429 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 3430 }
ab532cf3 3431
5d317c6a 3432 return bnx2x_config_rss_eth(bp, false);
ab532cf3
TH		 3433}
3434
0e8d2ec5
MS		 3435/**
3436 * bnx2x_get_channels - gets the number of RSS queues.
3437 *
3438 * @dev: net device
3439 * @channels: returns the number of max / current queues
3440 */
3441static void bnx2x_get_channels(struct net_device *dev,
3442 struct ethtool_channels *channels)
3443{
3444 struct bnx2x *bp = netdev_priv(dev);
3445
3446 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3447 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3448}
3449
3450/**
3451 * bnx2x_change_num_queues - change the number of RSS queues.
3452 *
3453 * @bp: bnx2x private structure
3454 *
3455 * Re-configure interrupt mode to get the new number of MSI-X
3456 * vectors and re-add NAPI objects.
3457 */
3458static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3459{
0e8d2ec5 3460 bnx2x_disable_msi(bp);
55c11941
MS		 3461 bp->num_ethernet_queues = num_rss;
3462 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3463 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
0e8d2ec5 3464 bnx2x_set_int_mode(bp);
0e8d2ec5
MS		 3465}
3466
3467/**
3468 * bnx2x_set_channels - sets the number of RSS queues.
3469 *
3470 * @dev: net device
3471 * @channels: includes the number of queues requested
3472 */
3473static int bnx2x_set_channels(struct net_device *dev,
3474 struct ethtool_channels *channels)
3475{
3476 struct bnx2x *bp = netdev_priv(dev);
3477
0e8d2ec5
MS		 3478 DP(BNX2X_MSG_ETHTOOL,
3479 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3480 channels->rx_count, channels->tx_count, channels->other_count,
3481 channels->combined_count);
3482
909d9faa
YM		 3483 if (pci_num_vf(bp->pdev)) {
3484 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3485 return -EPERM;
3486 }
3487
0e8d2ec5
MS		 3488 /* We don't support separate rx / tx channels.
3489 * We don't allow setting 'other' channels.
3490 */
3491 if (channels->rx_count || channels->tx_count || channels->other_count
3492 || (channels->combined_count == 0) ||
3493 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3494 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3495 return -EINVAL;
3496 }
3497
3498 /* Check if there was a change in the active parameters */
3499 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3500 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3501 return 0;
3502 }
3503
3504 /* Set the requested number of queues in bp context.
3505 * Note that the actual number of queues created during load may be
3506 * less than requested if memory is low.
3507 */
3508 if (unlikely(!netif_running(dev))) {
3509 bnx2x_change_num_queues(bp, channels->combined_count);
3510 return 0;
3511 }
5d07d868 3512 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
0e8d2ec5
MS		 3513 bnx2x_change_num_queues(bp, channels->combined_count);
3514 return bnx2x_nic_load(bp, LOAD_NORMAL);
3515}
3516
eeed018c
MK		 3517static int bnx2x_get_ts_info(struct net_device *dev,
3518 struct ethtool_ts_info *info)
3519{
3520 struct bnx2x *bp = netdev_priv(dev);
3521
3522 if (bp->flags & PTP_SUPPORTED) {
3523 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3524 SOF_TIMESTAMPING_RX_SOFTWARE |
3525 SOF_TIMESTAMPING_SOFTWARE |
3526 SOF_TIMESTAMPING_TX_HARDWARE |
3527 SOF_TIMESTAMPING_RX_HARDWARE |
3528 SOF_TIMESTAMPING_RAW_HARDWARE;
3529
3530 if (bp->ptp_clock)
3531 info->phc_index = ptp_clock_index(bp->ptp_clock);
3532 else
3533 info->phc_index = -1;
3534
3535 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3536 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3537 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
3538 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
3539 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3540 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
3541 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
3542 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3543 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
3544 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
3545 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
3546 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
3547 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
3548
3549 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3550
3551 return 0;
3552 }
3553
3554 return ethtool_op_get_ts_info(dev, info);
3555}
3556
de0c62db
DK		 3557static const struct ethtool_ops bnx2x_ethtool_ops = {
3558 .get_settings = bnx2x_get_settings,
3559 .set_settings = bnx2x_set_settings,
3560 .get_drvinfo = bnx2x_get_drvinfo,
3561 .get_regs_len = bnx2x_get_regs_len,
3562 .get_regs = bnx2x_get_regs,
07ba6af4
MS		 3563 .get_dump_flag = bnx2x_get_dump_flag,
3564 .get_dump_data = bnx2x_get_dump_data,
3565 .set_dump = bnx2x_set_dump,
de0c62db
DK		 3566 .get_wol = bnx2x_get_wol,
3567 .set_wol = bnx2x_set_wol,
3568 .get_msglevel = bnx2x_get_msglevel,
3569 .set_msglevel = bnx2x_set_msglevel,
3570 .nway_reset = bnx2x_nway_reset,
3571 .get_link = bnx2x_get_link,
3572 .get_eeprom_len = bnx2x_get_eeprom_len,
3573 .get_eeprom = bnx2x_get_eeprom,
3574 .set_eeprom = bnx2x_set_eeprom,
3575 .get_coalesce = bnx2x_get_coalesce,
3576 .set_coalesce = bnx2x_set_coalesce,
3577 .get_ringparam = bnx2x_get_ringparam,
3578 .set_ringparam = bnx2x_set_ringparam,
3579 .get_pauseparam = bnx2x_get_pauseparam,
3580 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 3581 .self_test = bnx2x_self_test,
3582 .get_sset_count = bnx2x_get_sset_count,
3521b419 3583 .get_priv_flags = bnx2x_get_private_flags,
de0c62db 3584 .get_strings = bnx2x_get_strings,
32d36134 3585 .set_phys_id = bnx2x_set_phys_id,
de0c62db 3586 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 3587 .get_rxnfc = bnx2x_get_rxnfc,
5d317c6a 3588 .set_rxnfc = bnx2x_set_rxnfc,
7850f63f 3589 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
fe62d001
BH		 3590 .get_rxfh = bnx2x_get_rxfh,
3591 .set_rxfh = bnx2x_set_rxfh,
0e8d2ec5
MS		 3592 .get_channels = bnx2x_get_channels,
3593 .set_channels = bnx2x_set_channels,
24ea818e
YM		 3594 .get_module_info = bnx2x_get_module_info,
3595 .get_module_eeprom = bnx2x_get_module_eeprom,
e9939c80
YM		 3596 .get_eee = bnx2x_get_eee,
3597 .set_eee = bnx2x_set_eee,
eeed018c 3598 .get_ts_info = bnx2x_get_ts_info,
de0c62db
DK		 3599};
3600
005a07ba 3601static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
6495d15a 3602 .get_settings = bnx2x_get_vf_settings,
005a07ba
AE		 3603 .get_drvinfo = bnx2x_get_drvinfo,
3604 .get_msglevel = bnx2x_get_msglevel,
3605 .set_msglevel = bnx2x_set_msglevel,
3606 .get_link = bnx2x_get_link,
3607 .get_coalesce = bnx2x_get_coalesce,
3608 .get_ringparam = bnx2x_get_ringparam,
3609 .set_ringparam = bnx2x_set_ringparam,
3610 .get_sset_count = bnx2x_get_sset_count,
3611 .get_strings = bnx2x_get_strings,
3612 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3613 .get_rxnfc = bnx2x_get_rxnfc,
3614 .set_rxnfc = bnx2x_set_rxnfc,
3615 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
fe62d001
BH		 3616 .get_rxfh = bnx2x_get_rxfh,
3617 .set_rxfh = bnx2x_set_rxfh,
005a07ba
AE		 3618 .get_channels = bnx2x_get_channels,
3619 .set_channels = bnx2x_set_channels,
3620};
3621
3622void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
de0c62db 3623{
7ad24ea4
WK		 3624 netdev->ethtool_ops = (IS_PF(bp)) ?
3625 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
de0c62db 3626}
Linux 6.x block layer and io_uring tree(s)