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9f6c9258 DK |
1 | /* bnx2x_cmn.h: Broadcom Everest network driver. |
2 | * | |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
9f6c9258 DK |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
08f6dd89 | 9 | * Maintained by: Ariel Elior <ariel.elior@qlogic.com> |
9f6c9258 DK |
10 | * Written by: Eliezer Tamir |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
17 | #ifndef BNX2X_CMN_H | |
18 | #define BNX2X_CMN_H | |
19 | ||
20 | #include <linux/types.h> | |
619c5cb6 | 21 | #include <linux/pci.h> |
9f6c9258 | 22 | #include <linux/netdevice.h> |
614c76df | 23 | #include <linux/etherdevice.h> |
df1efc2d | 24 | #include <linux/irq.h> |
9f6c9258 | 25 | |
9f6c9258 | 26 | #include "bnx2x.h" |
6411280a | 27 | #include "bnx2x_sriov.h" |
9f6c9258 | 28 | |
619c5cb6 | 29 | /* This is used as a replacement for an MCP if it's not present */ |
a8f47eb7 | 30 | extern int bnx2x_load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ |
31 | extern int bnx2x_num_queues; | |
9f6c9258 | 32 | |
b3b83c3f DK |
33 | /************************ Macros ********************************/ |
34 | #define BNX2X_PCI_FREE(x, y, size) \ | |
35 | do { \ | |
36 | if (x) { \ | |
37 | dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ | |
38 | x = NULL; \ | |
39 | y = 0; \ | |
40 | } \ | |
41 | } while (0) | |
42 | ||
43 | #define BNX2X_FREE(x) \ | |
44 | do { \ | |
45 | if (x) { \ | |
46 | kfree((void *)x); \ | |
47 | x = NULL; \ | |
48 | } \ | |
49 | } while (0) | |
50 | ||
cd2b0389 JP |
51 | #define BNX2X_PCI_ALLOC(y, size) \ |
52 | ({ \ | |
53 | void *x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ | |
54 | if (x) \ | |
55 | DP(NETIF_MSG_HW, \ | |
56 | "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \ | |
57 | (unsigned long long)(*y), x); \ | |
58 | x; \ | |
59 | }) | |
60 | #define BNX2X_PCI_FALLOC(y, size) \ | |
61 | ({ \ | |
62 | void *x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ | |
63 | if (x) { \ | |
64 | memset(x, 0xff, size); \ | |
65 | DP(NETIF_MSG_HW, \ | |
66 | "BNX2X_PCI_FALLOC: Physical %Lx Virtual %p\n", \ | |
67 | (unsigned long long)(*y), x); \ | |
68 | } \ | |
69 | x; \ | |
70 | }) | |
b3b83c3f | 71 | |
9f6c9258 DK |
72 | /*********************** Interfaces **************************** |
73 | * Functions that need to be implemented by each driver version | |
74 | */ | |
619c5cb6 VZ |
75 | /* Init */ |
76 | ||
77 | /** | |
78 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
79 | * | |
80 | * @bp: driver handle | |
81 | * @unload_mode: requested function's unload mode | |
82 | * | |
83 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
84 | */ | |
85 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); | |
86 | ||
87 | /** | |
88 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
89 | * | |
90 | * @bp: driver handle | |
5d07d868 | 91 | * @keep_link: true iff link should be kept up |
619c5cb6 | 92 | */ |
5d07d868 | 93 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link); |
619c5cb6 VZ |
94 | |
95 | /** | |
96305234 | 96 | * bnx2x_config_rss_pf - configure RSS parameters in a PF. |
619c5cb6 VZ |
97 | * |
98 | * @bp: driver handle | |
49ce9c2c | 99 | * @rss_obj: RSS object to use |
619c5cb6 VZ |
100 | * @ind_table: indirection table to configure |
101 | * @config_hash: re-configure RSS hash keys configuration | |
60cad4e6 | 102 | * @enable: enabled or disabled configuration |
619c5cb6 | 103 | */ |
60cad4e6 AE |
104 | int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, |
105 | bool config_hash, bool enable); | |
619c5cb6 VZ |
106 | |
107 | /** | |
108 | * bnx2x__init_func_obj - init function object | |
109 | * | |
110 | * @bp: driver handle | |
111 | * | |
112 | * Initializes the Function Object with the appropriate | |
113 | * parameters which include a function slow path driver | |
114 | * interface. | |
115 | */ | |
116 | void bnx2x__init_func_obj(struct bnx2x *bp); | |
117 | ||
118 | /** | |
119 | * bnx2x_setup_queue - setup eth queue. | |
120 | * | |
121 | * @bp: driver handle | |
122 | * @fp: pointer to the fastpath structure | |
123 | * @leading: boolean | |
124 | * | |
125 | */ | |
126 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
127 | bool leading); | |
128 | ||
129 | /** | |
130 | * bnx2x_setup_leading - bring up a leading eth queue. | |
131 | * | |
132 | * @bp: driver handle | |
133 | */ | |
134 | int bnx2x_setup_leading(struct bnx2x *bp); | |
135 | ||
136 | /** | |
137 | * bnx2x_fw_command - send the MCP a request | |
138 | * | |
139 | * @bp: driver handle | |
140 | * @command: request | |
141 | * @param: request's parameter | |
142 | * | |
143 | * block until there is a reply | |
144 | */ | |
145 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); | |
9f6c9258 DK |
146 | |
147 | /** | |
e8920674 | 148 | * bnx2x_initial_phy_init - initialize link parameters structure variables. |
9f6c9258 | 149 | * |
e8920674 DK |
150 | * @bp: driver handle |
151 | * @load_mode: current mode | |
9f6c9258 | 152 | */ |
cd1dfce2 | 153 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); |
9f6c9258 DK |
154 | |
155 | /** | |
e8920674 | 156 | * bnx2x_link_set - configure hw according to link parameters structure. |
9f6c9258 | 157 | * |
e8920674 | 158 | * @bp: driver handle |
9f6c9258 DK |
159 | */ |
160 | void bnx2x_link_set(struct bnx2x *bp); | |
161 | ||
5d07d868 YM |
162 | /** |
163 | * bnx2x_force_link_reset - Forces link reset, and put the PHY | |
164 | * in reset as well. | |
165 | * | |
166 | * @bp: driver handle | |
167 | */ | |
168 | void bnx2x_force_link_reset(struct bnx2x *bp); | |
169 | ||
9f6c9258 | 170 | /** |
e8920674 | 171 | * bnx2x_link_test - query link status. |
9f6c9258 | 172 | * |
e8920674 DK |
173 | * @bp: driver handle |
174 | * @is_serdes: bool | |
9f6c9258 | 175 | * |
e8920674 | 176 | * Returns 0 if link is UP. |
9f6c9258 | 177 | */ |
a22f0788 | 178 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); |
9f6c9258 | 179 | |
619c5cb6 VZ |
180 | /** |
181 | * bnx2x_drv_pulse - write driver pulse to shmem | |
182 | * | |
183 | * @bp: driver handle | |
184 | * | |
185 | * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox | |
186 | * in the shmem. | |
187 | */ | |
188 | void bnx2x_drv_pulse(struct bnx2x *bp); | |
189 | ||
190 | /** | |
191 | * bnx2x_igu_ack_sb - update IGU with current SB value | |
192 | * | |
193 | * @bp: driver handle | |
194 | * @igu_sb_id: SB id | |
195 | * @segment: SB segment | |
196 | * @index: SB index | |
197 | * @op: SB operation | |
198 | * @update: is HW update required | |
199 | */ | |
200 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, | |
201 | u16 index, u8 op, u8 update); | |
202 | ||
c9ee9206 VZ |
203 | /* Disable transactions from chip to host */ |
204 | void bnx2x_pf_disable(struct bnx2x *bp); | |
07ba6af4 | 205 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); |
c9ee9206 | 206 | |
9f6c9258 | 207 | /** |
e8920674 | 208 | * bnx2x__link_status_update - handles link status change. |
9f6c9258 | 209 | * |
e8920674 | 210 | * @bp: driver handle |
9f6c9258 DK |
211 | */ |
212 | void bnx2x__link_status_update(struct bnx2x *bp); | |
213 | ||
f85582f8 | 214 | /** |
e8920674 | 215 | * bnx2x_link_report - report link status to upper layer. |
f85582f8 | 216 | * |
e8920674 | 217 | * @bp: driver handle |
f85582f8 DK |
218 | */ |
219 | void bnx2x_link_report(struct bnx2x *bp); | |
220 | ||
2ae17f66 VZ |
221 | /* None-atomic version of bnx2x_link_report() */ |
222 | void __bnx2x_link_report(struct bnx2x *bp); | |
223 | ||
0793f83f | 224 | /** |
e8920674 | 225 | * bnx2x_get_mf_speed - calculate MF speed. |
0793f83f | 226 | * |
e8920674 | 227 | * @bp: driver handle |
0793f83f | 228 | * |
e8920674 | 229 | * Takes into account current linespeed and MF configuration. |
0793f83f DK |
230 | */ |
231 | u16 bnx2x_get_mf_speed(struct bnx2x *bp); | |
232 | ||
9f6c9258 | 233 | /** |
e8920674 | 234 | * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler |
9f6c9258 | 235 | * |
e8920674 DK |
236 | * @irq: irq number |
237 | * @dev_instance: private instance | |
9f6c9258 DK |
238 | */ |
239 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); | |
240 | ||
241 | /** | |
e8920674 | 242 | * bnx2x_interrupt - non MSI-X interrupt handler |
9f6c9258 | 243 | * |
e8920674 DK |
244 | * @irq: irq number |
245 | * @dev_instance: private instance | |
9f6c9258 DK |
246 | */ |
247 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); | |
9f6c9258 DK |
248 | |
249 | /** | |
e8920674 | 250 | * bnx2x_cnic_notify - send command to cnic driver |
9f6c9258 | 251 | * |
e8920674 DK |
252 | * @bp: driver handle |
253 | * @cmd: command | |
9f6c9258 DK |
254 | */ |
255 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); | |
256 | ||
257 | /** | |
e8920674 | 258 | * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information |
9f6c9258 | 259 | * |
e8920674 | 260 | * @bp: driver handle |
9f6c9258 DK |
261 | */ |
262 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); | |
37ae41a9 MS |
263 | |
264 | /** | |
265 | * bnx2x_setup_cnic_info - provides cnic with updated info | |
266 | * | |
267 | * @bp: driver handle | |
268 | */ | |
269 | void bnx2x_setup_cnic_info(struct bnx2x *bp); | |
270 | ||
9f6c9258 | 271 | /** |
e8920674 | 272 | * bnx2x_int_enable - enable HW interrupts. |
9f6c9258 | 273 | * |
e8920674 | 274 | * @bp: driver handle |
9f6c9258 DK |
275 | */ |
276 | void bnx2x_int_enable(struct bnx2x *bp); | |
277 | ||
278 | /** | |
e8920674 DK |
279 | * bnx2x_int_disable_sync - disable interrupts. |
280 | * | |
281 | * @bp: driver handle | |
282 | * @disable_hw: true, disable HW interrupts. | |
9f6c9258 | 283 | * |
e8920674 DK |
284 | * This function ensures that there are no |
285 | * ISRs or SP DPCs (sp_task) are running after it returns. | |
9f6c9258 DK |
286 | */ |
287 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); | |
288 | ||
9f6c9258 | 289 | /** |
55c11941 | 290 | * bnx2x_nic_init_cnic - init driver internals for cnic. |
e8920674 DK |
291 | * |
292 | * @bp: driver handle | |
293 | * @load_code: COMMON, PORT or FUNCTION | |
294 | * | |
295 | * Initializes: | |
9f6c9258 DK |
296 | * - rings |
297 | * - status blocks | |
298 | * - etc. | |
9f6c9258 | 299 | */ |
55c11941 | 300 | void bnx2x_nic_init_cnic(struct bnx2x *bp); |
9f6c9258 | 301 | |
55c11941 | 302 | /** |
ecf01c22 | 303 | * bnx2x_preirq_nic_init - init driver internals. |
55c11941 MS |
304 | * |
305 | * @bp: driver handle | |
306 | * | |
307 | * Initializes: | |
ecf01c22 YM |
308 | * - fastpath object |
309 | * - fastpath rings | |
310 | * etc. | |
311 | */ | |
312 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp); | |
313 | ||
314 | /** | |
315 | * bnx2x_postirq_nic_init - init driver internals. | |
316 | * | |
317 | * @bp: driver handle | |
318 | * @load_code: COMMON, PORT or FUNCTION | |
319 | * | |
320 | * Initializes: | |
55c11941 | 321 | * - status blocks |
ecf01c22 | 322 | * - slowpath rings |
55c11941 MS |
323 | * - etc. |
324 | */ | |
ecf01c22 | 325 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code); |
55c11941 MS |
326 | /** |
327 | * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. | |
328 | * | |
329 | * @bp: driver handle | |
330 | */ | |
331 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp); | |
9f6c9258 | 332 | /** |
e8920674 | 333 | * bnx2x_alloc_mem - allocate driver's memory. |
9f6c9258 | 334 | * |
e8920674 | 335 | * @bp: driver handle |
9f6c9258 DK |
336 | */ |
337 | int bnx2x_alloc_mem(struct bnx2x *bp); | |
338 | ||
55c11941 MS |
339 | /** |
340 | * bnx2x_free_mem_cnic - release driver's memory for cnic. | |
341 | * | |
342 | * @bp: driver handle | |
343 | */ | |
344 | void bnx2x_free_mem_cnic(struct bnx2x *bp); | |
9f6c9258 | 345 | /** |
e8920674 | 346 | * bnx2x_free_mem - release driver's memory. |
9f6c9258 | 347 | * |
e8920674 | 348 | * @bp: driver handle |
9f6c9258 DK |
349 | */ |
350 | void bnx2x_free_mem(struct bnx2x *bp); | |
351 | ||
9f6c9258 | 352 | /** |
e8920674 | 353 | * bnx2x_set_num_queues - set number of queues according to mode. |
9f6c9258 | 354 | * |
e8920674 | 355 | * @bp: driver handle |
9f6c9258 | 356 | */ |
d6214d7a | 357 | void bnx2x_set_num_queues(struct bnx2x *bp); |
9f6c9258 DK |
358 | |
359 | /** | |
e8920674 DK |
360 | * bnx2x_chip_cleanup - cleanup chip internals. |
361 | * | |
362 | * @bp: driver handle | |
363 | * @unload_mode: COMMON, PORT, FUNCTION | |
5d07d868 | 364 | * @keep_link: true iff link should be kept up. |
e8920674 | 365 | * |
9f6c9258 | 366 | * - Cleanup MAC configuration. |
e8920674 | 367 | * - Closes clients. |
9f6c9258 | 368 | * - etc. |
9f6c9258 | 369 | */ |
5d07d868 | 370 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link); |
9f6c9258 DK |
371 | |
372 | /** | |
e8920674 | 373 | * bnx2x_acquire_hw_lock - acquire HW lock. |
9f6c9258 | 374 | * |
e8920674 DK |
375 | * @bp: driver handle |
376 | * @resource: resource bit which was locked | |
9f6c9258 DK |
377 | */ |
378 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); | |
379 | ||
380 | /** | |
e8920674 | 381 | * bnx2x_release_hw_lock - release HW lock. |
9f6c9258 | 382 | * |
e8920674 DK |
383 | * @bp: driver handle |
384 | * @resource: resource bit which was locked | |
9f6c9258 DK |
385 | */ |
386 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); | |
387 | ||
c9ee9206 VZ |
388 | /** |
389 | * bnx2x_release_leader_lock - release recovery leader lock | |
390 | * | |
391 | * @bp: driver handle | |
392 | */ | |
393 | int bnx2x_release_leader_lock(struct bnx2x *bp); | |
394 | ||
9f6c9258 | 395 | /** |
e8920674 DK |
396 | * bnx2x_set_eth_mac - configure eth MAC address in the HW |
397 | * | |
398 | * @bp: driver handle | |
399 | * @set: set or clear | |
9f6c9258 | 400 | * |
e8920674 | 401 | * Configures according to the value in netdev->dev_addr. |
9f6c9258 | 402 | */ |
619c5cb6 | 403 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); |
9f6c9258 | 404 | |
ec6ba945 | 405 | /** |
619c5cb6 | 406 | * bnx2x_set_rx_mode - set MAC filtering configurations. |
ec6ba945 | 407 | * |
619c5cb6 | 408 | * @dev: netdevice |
ec6ba945 | 409 | * |
619c5cb6 VZ |
410 | * called with netif_tx_lock from dev_mcast.c |
411 | * If bp->state is OPEN, should be called with | |
412 | * netif_addr_lock_bh() | |
ec6ba945 | 413 | */ |
8b09be5f | 414 | void bnx2x_set_rx_mode_inner(struct bnx2x *bp); |
ec6ba945 | 415 | |
9f6c9258 | 416 | /* Parity errors related */ |
889b9af3 AE |
417 | void bnx2x_set_pf_load(struct bnx2x *bp); |
418 | bool bnx2x_clear_pf_load(struct bnx2x *bp); | |
c9ee9206 VZ |
419 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); |
420 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); | |
421 | void bnx2x_set_reset_in_progress(struct bnx2x *bp); | |
422 | void bnx2x_set_reset_global(struct bnx2x *bp); | |
9f6c9258 | 423 | void bnx2x_disable_close_the_gate(struct bnx2x *bp); |
55c11941 | 424 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp); |
9f6c9258 | 425 | |
9f6c9258 | 426 | /** |
e8920674 | 427 | * bnx2x_sp_event - handle ramrods completion. |
9f6c9258 | 428 | * |
e8920674 DK |
429 | * @fp: fastpath handle for the event |
430 | * @rr_cqe: eth_rx_cqe | |
9f6c9258 | 431 | */ |
f85582f8 | 432 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); |
9f6c9258 | 433 | |
523224a3 | 434 | /** |
e8920674 | 435 | * bnx2x_ilt_set_info - prepare ILT configurations. |
523224a3 | 436 | * |
e8920674 | 437 | * @bp: driver handle |
523224a3 DK |
438 | */ |
439 | void bnx2x_ilt_set_info(struct bnx2x *bp); | |
9f6c9258 | 440 | |
55c11941 MS |
441 | /** |
442 | * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC | |
443 | * and TM. | |
444 | * | |
445 | * @bp: driver handle | |
446 | */ | |
447 | void bnx2x_ilt_set_info_cnic(struct bnx2x *bp); | |
448 | ||
e4901dde | 449 | /** |
e8920674 | 450 | * bnx2x_dcbx_init - initialize dcbx protocol. |
e4901dde | 451 | * |
e8920674 | 452 | * @bp: driver handle |
e4901dde | 453 | */ |
9876879f | 454 | void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); |
e4901dde | 455 | |
f85582f8 | 456 | /** |
e8920674 | 457 | * bnx2x_set_power_state - set power state to the requested value. |
f85582f8 | 458 | * |
e8920674 DK |
459 | * @bp: driver handle |
460 | * @state: required state D0 or D3hot | |
f85582f8 | 461 | * |
e8920674 | 462 | * Currently only D0 and D3hot are supported. |
f85582f8 DK |
463 | */ |
464 | int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); | |
465 | ||
e3835b99 | 466 | /** |
e8920674 | 467 | * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. |
e3835b99 | 468 | * |
e8920674 DK |
469 | * @bp: driver handle |
470 | * @value: new value | |
e3835b99 DK |
471 | */ |
472 | void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); | |
619c5cb6 | 473 | /* Error handling */ |
7a25cc73 DK |
474 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); |
475 | ||
f85582f8 | 476 | /* dev_close main block */ |
5d07d868 | 477 | int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link); |
f85582f8 DK |
478 | |
479 | /* dev_open main block */ | |
480 | int bnx2x_nic_load(struct bnx2x *bp, int load_mode); | |
481 | ||
482 | /* hard_xmit callback */ | |
483 | netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
484 | ||
6383c0b3 AE |
485 | /* setup_tc callback */ |
486 | int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); | |
487 | ||
3ec9f9ca AE |
488 | int bnx2x_get_vf_config(struct net_device *dev, int vf, |
489 | struct ifla_vf_info *ivi); | |
abc5a021 | 490 | int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac); |
3ec9f9ca | 491 | int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos); |
abc5a021 | 492 | |
8307fa3e | 493 | /* select_queue callback */ |
f663dd9a | 494 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 495 | void *accel_priv, select_queue_fallback_t fallback); |
8307fa3e | 496 | |
dc1ba591 AE |
497 | static inline void bnx2x_update_rx_prod(struct bnx2x *bp, |
498 | struct bnx2x_fastpath *fp, | |
499 | u16 bd_prod, u16 rx_comp_prod, | |
500 | u16 rx_sge_prod) | |
501 | { | |
502 | struct ustorm_eth_rx_producers rx_prods = {0}; | |
503 | u32 i; | |
504 | ||
505 | /* Update producers */ | |
506 | rx_prods.bd_prod = bd_prod; | |
507 | rx_prods.cqe_prod = rx_comp_prod; | |
508 | rx_prods.sge_prod = rx_sge_prod; | |
509 | ||
510 | /* Make sure that the BD and SGE data is updated before updating the | |
511 | * producers since FW might read the BD/SGE right after the producer | |
512 | * is updated. | |
513 | * This is only applicable for weak-ordered memory model archs such | |
514 | * as IA-64. The following barrier is also mandatory since FW will | |
515 | * assumes BDs must have buffers. | |
516 | */ | |
517 | wmb(); | |
518 | ||
519 | for (i = 0; i < sizeof(rx_prods)/4; i++) | |
520 | REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, | |
521 | ((u32 *)&rx_prods)[i]); | |
522 | ||
523 | mmiowb(); /* keep prod updates ordered */ | |
524 | ||
525 | DP(NETIF_MSG_RX_STATUS, | |
526 | "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", | |
527 | fp->index, bd_prod, rx_comp_prod, rx_sge_prod); | |
528 | } | |
529 | ||
a9fccec7 DK |
530 | /* reload helper */ |
531 | int bnx2x_reload_if_running(struct net_device *dev); | |
532 | ||
f85582f8 DK |
533 | int bnx2x_change_mac_addr(struct net_device *dev, void *p); |
534 | ||
f85582f8 | 535 | /* NAPI poll Tx part */ |
6383c0b3 | 536 | int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); |
f85582f8 DK |
537 | |
538 | /* suspend/resume callbacks */ | |
539 | int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); | |
540 | int bnx2x_resume(struct pci_dev *pdev); | |
541 | ||
542 | /* Release IRQ vectors */ | |
543 | void bnx2x_free_irq(struct bnx2x *bp); | |
544 | ||
b3b83c3f | 545 | void bnx2x_free_fp_mem(struct bnx2x *bp); |
f85582f8 | 546 | void bnx2x_init_rx_rings(struct bnx2x *bp); |
55c11941 | 547 | void bnx2x_init_rx_rings_cnic(struct bnx2x *bp); |
f85582f8 DK |
548 | void bnx2x_free_skbs(struct bnx2x *bp); |
549 | void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); | |
550 | void bnx2x_netif_start(struct bnx2x *bp); | |
55c11941 | 551 | int bnx2x_load_cnic(struct bnx2x *bp); |
f85582f8 | 552 | |
d6214d7a | 553 | /** |
e8920674 | 554 | * bnx2x_enable_msix - set msix configuration. |
d6214d7a | 555 | * |
e8920674 | 556 | * @bp: driver handle |
d6214d7a | 557 | * |
e8920674 DK |
558 | * fills msix_table, requests vectors, updates num_queues |
559 | * according to number of available vectors. | |
d6214d7a | 560 | */ |
0e8d2ec5 | 561 | int bnx2x_enable_msix(struct bnx2x *bp); |
d6214d7a DK |
562 | |
563 | /** | |
e8920674 | 564 | * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly |
d6214d7a | 565 | * |
e8920674 | 566 | * @bp: driver handle |
d6214d7a DK |
567 | */ |
568 | int bnx2x_enable_msi(struct bnx2x *bp); | |
569 | ||
8f20aa57 DK |
570 | /** |
571 | * bnx2x_low_latency_recv - LL callback | |
572 | * | |
573 | * @napi: napi structure | |
574 | */ | |
575 | int bnx2x_low_latency_recv(struct napi_struct *napi); | |
576 | ||
f85582f8 | 577 | /** |
e8920674 | 578 | * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure |
f85582f8 | 579 | * |
e8920674 | 580 | * @bp: driver handle |
f85582f8 | 581 | */ |
0329aba1 | 582 | int bnx2x_alloc_mem_bp(struct bnx2x *bp); |
e8920674 DK |
583 | |
584 | /** | |
585 | * bnx2x_free_mem_bp - release memories outsize main driver structure | |
586 | * | |
587 | * @bp: driver handle | |
588 | */ | |
f85582f8 DK |
589 | void bnx2x_free_mem_bp(struct bnx2x *bp); |
590 | ||
591 | /** | |
e8920674 | 592 | * bnx2x_change_mtu - change mtu netdev callback |
f85582f8 | 593 | * |
e8920674 DK |
594 | * @dev: net device |
595 | * @new_mtu: requested mtu | |
f85582f8 | 596 | * |
f85582f8 DK |
597 | */ |
598 | int bnx2x_change_mtu(struct net_device *dev, int new_mtu); | |
599 | ||
55c11941 | 600 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
601 | /** |
602 | * bnx2x_fcoe_get_wwn - return the requested WWN value for this port | |
603 | * | |
604 | * @dev: net_device | |
605 | * @wwn: output buffer | |
606 | * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) | |
607 | * | |
608 | */ | |
609 | int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); | |
610 | #endif | |
621b4d66 | 611 | |
c8f44aff | 612 | netdev_features_t bnx2x_fix_features(struct net_device *dev, |
621b4d66 | 613 | netdev_features_t features); |
c8f44aff | 614 | int bnx2x_set_features(struct net_device *dev, netdev_features_t features); |
66371c44 | 615 | |
f85582f8 | 616 | /** |
e8920674 | 617 | * bnx2x_tx_timeout - tx timeout netdev callback |
f85582f8 | 618 | * |
e8920674 | 619 | * @dev: net device |
f85582f8 DK |
620 | */ |
621 | void bnx2x_tx_timeout(struct net_device *dev); | |
622 | ||
619c5cb6 VZ |
623 | /*********************** Inlines **********************************/ |
624 | /*********************** Fast path ********************************/ | |
9f6c9258 DK |
625 | static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) |
626 | { | |
9f6c9258 | 627 | barrier(); /* status block is written to by the chip */ |
523224a3 | 628 | fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; |
9f6c9258 DK |
629 | } |
630 | ||
f2e0899f DK |
631 | static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, |
632 | u8 segment, u16 index, u8 op, | |
633 | u8 update, u32 igu_addr) | |
634 | { | |
635 | struct igu_regular cmd_data = {0}; | |
636 | ||
637 | cmd_data.sb_id_and_flags = | |
638 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
639 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
640 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
641 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
642 | ||
51c1a580 | 643 | DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", |
f2e0899f DK |
644 | cmd_data.sb_id_and_flags, igu_addr); |
645 | REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); | |
646 | ||
647 | /* Make sure that ACK is written */ | |
648 | mmiowb(); | |
649 | barrier(); | |
650 | } | |
651 | ||
f2e0899f DK |
652 | static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, |
653 | u8 storm, u16 index, u8 op, u8 update) | |
9f6c9258 DK |
654 | { |
655 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
656 | COMMAND_REG_INT_ACK); | |
657 | struct igu_ack_register igu_ack; | |
658 | ||
659 | igu_ack.status_block_index = index; | |
660 | igu_ack.sb_id_and_flags = | |
661 | ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | | |
662 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
663 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
664 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
665 | ||
9f6c9258 DK |
666 | REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); |
667 | ||
668 | /* Make sure that ACK is written */ | |
669 | mmiowb(); | |
670 | barrier(); | |
671 | } | |
f2e0899f | 672 | |
f2e0899f DK |
673 | static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, |
674 | u16 index, u8 op, u8 update) | |
675 | { | |
676 | if (bp->common.int_block == INT_BLOCK_HC) | |
677 | bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); | |
678 | else { | |
679 | u8 segment; | |
680 | ||
681 | if (CHIP_INT_MODE_IS_BC(bp)) | |
682 | segment = storm; | |
683 | else if (igu_sb_id != bp->igu_dsb_id) | |
684 | segment = IGU_SEG_ACCESS_DEF; | |
685 | else if (storm == ATTENTION_ID) | |
686 | segment = IGU_SEG_ACCESS_ATTN; | |
687 | else | |
688 | segment = IGU_SEG_ACCESS_DEF; | |
689 | bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); | |
690 | } | |
691 | } | |
692 | ||
693 | static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) | |
9f6c9258 DK |
694 | { |
695 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
696 | COMMAND_REG_SIMD_MASK); | |
697 | u32 result = REG_RD(bp, hc_addr); | |
698 | ||
f2e0899f | 699 | barrier(); |
9f6c9258 DK |
700 | return result; |
701 | } | |
702 | ||
f2e0899f DK |
703 | static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) |
704 | { | |
705 | u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); | |
706 | u32 result = REG_RD(bp, igu_addr); | |
707 | ||
51c1a580 | 708 | DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", |
f2e0899f DK |
709 | result, igu_addr); |
710 | ||
711 | barrier(); | |
712 | return result; | |
713 | } | |
714 | ||
715 | static inline u16 bnx2x_ack_int(struct bnx2x *bp) | |
716 | { | |
717 | barrier(); | |
718 | if (bp->common.int_block == INT_BLOCK_HC) | |
719 | return bnx2x_hc_ack_int(bp); | |
720 | else | |
721 | return bnx2x_igu_ack_int(bp); | |
722 | } | |
723 | ||
6383c0b3 | 724 | static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
725 | { |
726 | /* Tell compiler that consumer and producer can change */ | |
727 | barrier(); | |
6383c0b3 | 728 | return txdata->tx_pkt_prod != txdata->tx_pkt_cons; |
9f6c9258 DK |
729 | } |
730 | ||
6383c0b3 AE |
731 | static inline u16 bnx2x_tx_avail(struct bnx2x *bp, |
732 | struct bnx2x_fp_txdata *txdata) | |
9f6c9258 DK |
733 | { |
734 | s16 used; | |
735 | u16 prod; | |
736 | u16 cons; | |
737 | ||
6383c0b3 AE |
738 | prod = txdata->tx_bd_prod; |
739 | cons = txdata->tx_bd_cons; | |
9f6c9258 | 740 | |
7b5342d9 | 741 | used = SUB_S16(prod, cons); |
9f6c9258 DK |
742 | |
743 | #ifdef BNX2X_STOP_ON_ERROR | |
744 | WARN_ON(used < 0); | |
7b5342d9 YM |
745 | WARN_ON(used > txdata->tx_ring_size); |
746 | WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); | |
9f6c9258 DK |
747 | #endif |
748 | ||
7b5342d9 | 749 | return (s16)(txdata->tx_ring_size) - used; |
9f6c9258 DK |
750 | } |
751 | ||
6383c0b3 | 752 | static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
753 | { |
754 | u16 hw_cons; | |
755 | ||
756 | /* Tell compiler that status block fields can change */ | |
757 | barrier(); | |
6383c0b3 AE |
758 | hw_cons = le16_to_cpu(*txdata->tx_cons_sb); |
759 | return hw_cons != txdata->tx_pkt_cons; | |
760 | } | |
761 | ||
762 | static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) | |
763 | { | |
764 | u8 cos; | |
765 | for_each_cos_in_tx_queue(fp, cos) | |
65565884 | 766 | if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) |
6383c0b3 AE |
767 | return true; |
768 | return false; | |
9f6c9258 DK |
769 | } |
770 | ||
75b29459 DK |
771 | #define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0) |
772 | #define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF) | |
523224a3 DK |
773 | static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) |
774 | { | |
75b29459 DK |
775 | u16 cons; |
776 | union eth_rx_cqe *cqe; | |
777 | struct eth_fast_path_rx_cqe *cqe_fp; | |
523224a3 | 778 | |
75b29459 DK |
779 | cons = RCQ_BD(fp->rx_comp_cons); |
780 | cqe = &fp->rx_comp_ring[cons]; | |
781 | cqe_fp = &cqe->fast_path_cqe; | |
782 | return BNX2X_IS_CQE_COMPLETED(cqe_fp); | |
523224a3 | 783 | } |
f85582f8 | 784 | |
f2e0899f | 785 | /** |
619c5cb6 | 786 | * bnx2x_tx_disable - disables tx from stack point of view |
f2e0899f | 787 | * |
e8920674 | 788 | * @bp: driver handle |
f2e0899f DK |
789 | */ |
790 | static inline void bnx2x_tx_disable(struct bnx2x *bp) | |
791 | { | |
792 | netif_tx_disable(bp->dev); | |
793 | netif_carrier_off(bp->dev); | |
794 | } | |
795 | ||
9f6c9258 DK |
796 | static inline void bnx2x_free_rx_sge(struct bnx2x *bp, |
797 | struct bnx2x_fastpath *fp, u16 index) | |
798 | { | |
799 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
800 | struct page *page = sw_buf->page; | |
801 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
802 | ||
803 | /* Skip "next page" elements */ | |
804 | if (!page) | |
805 | return; | |
806 | ||
807 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), | |
924d75ab | 808 | SGE_PAGES, DMA_FROM_DEVICE); |
9f6c9258 DK |
809 | __free_pages(page, PAGES_PER_SGE_SHIFT); |
810 | ||
811 | sw_buf->page = NULL; | |
812 | sge->addr_hi = 0; | |
813 | sge->addr_lo = 0; | |
814 | } | |
815 | ||
55c11941 MS |
816 | static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) |
817 | { | |
818 | int i; | |
819 | ||
8f20aa57 DK |
820 | for_each_rx_queue_cnic(bp, i) { |
821 | napi_hash_del(&bnx2x_fp(bp, i, napi)); | |
55c11941 | 822 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
8f20aa57 | 823 | } |
55c11941 MS |
824 | } |
825 | ||
d6214d7a DK |
826 | static inline void bnx2x_del_all_napi(struct bnx2x *bp) |
827 | { | |
828 | int i; | |
829 | ||
8f20aa57 DK |
830 | for_each_eth_queue(bp, i) { |
831 | napi_hash_del(&bnx2x_fp(bp, i, napi)); | |
d6214d7a | 832 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
8f20aa57 | 833 | } |
d6214d7a | 834 | } |
523224a3 | 835 | |
1ab4434c | 836 | int bnx2x_set_int_mode(struct bnx2x *bp); |
0e8d2ec5 | 837 | |
d6214d7a DK |
838 | static inline void bnx2x_disable_msi(struct bnx2x *bp) |
839 | { | |
840 | if (bp->flags & USING_MSIX_FLAG) { | |
841 | pci_disable_msix(bp->pdev); | |
30a5de77 | 842 | bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); |
d6214d7a DK |
843 | } else if (bp->flags & USING_MSI_FLAG) { |
844 | pci_disable_msi(bp->pdev); | |
845 | bp->flags &= ~USING_MSI_FLAG; | |
846 | } | |
847 | } | |
848 | ||
523224a3 | 849 | static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) |
9f6c9258 | 850 | { |
523224a3 | 851 | int i, j; |
9f6c9258 | 852 | |
523224a3 DK |
853 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { |
854 | int idx = RX_SGE_CNT * i - 1; | |
855 | ||
856 | for (j = 0; j < 2; j++) { | |
619c5cb6 | 857 | BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); |
523224a3 DK |
858 | idx--; |
859 | } | |
860 | } | |
861 | } | |
862 | ||
863 | static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) | |
864 | { | |
865 | /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ | |
b3637827 | 866 | memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); |
523224a3 DK |
867 | |
868 | /* Clear the two last indices in the page to 1: | |
869 | these are the indices that correspond to the "next" element, | |
870 | hence will never be indicated and should be removed from | |
871 | the calculations. */ | |
872 | bnx2x_clear_sge_mask_next_elems(fp); | |
9f6c9258 DK |
873 | } |
874 | ||
e52fcb24 | 875 | /* note that we are not allocating a new buffer, |
9f6c9258 DK |
876 | * we are just moving one from cons to prod |
877 | * we are not creating a new mapping, | |
878 | * so there is no need to check for dma_mapping_error(). | |
879 | */ | |
e52fcb24 | 880 | static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, |
749a8503 | 881 | u16 cons, u16 prod) |
9f6c9258 | 882 | { |
9f6c9258 DK |
883 | struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; |
884 | struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; | |
885 | struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; | |
886 | struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; | |
887 | ||
9f6c9258 DK |
888 | dma_unmap_addr_set(prod_rx_buf, mapping, |
889 | dma_unmap_addr(cons_rx_buf, mapping)); | |
e52fcb24 | 890 | prod_rx_buf->data = cons_rx_buf->data; |
9f6c9258 DK |
891 | *prod_bd = *cons_bd; |
892 | } | |
f85582f8 | 893 | |
619c5cb6 VZ |
894 | /************************* Init ******************************************/ |
895 | ||
b475d78f YM |
896 | /* returns func by VN for current port */ |
897 | static inline int func_by_vn(struct bnx2x *bp, int vn) | |
898 | { | |
899 | return 2 * vn + BP_PORT(bp); | |
900 | } | |
901 | ||
5d317c6a | 902 | static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) |
96305234 | 903 | { |
60cad4e6 | 904 | return bnx2x_rss(bp, &bp->rss_conf_obj, config_hash, true); |
96305234 DK |
905 | } |
906 | ||
619c5cb6 VZ |
907 | /** |
908 | * bnx2x_func_start - init function | |
909 | * | |
910 | * @bp: driver handle | |
911 | * | |
912 | * Must be called before sending CLIENT_SETUP for the first client. | |
913 | */ | |
914 | static inline int bnx2x_func_start(struct bnx2x *bp) | |
915 | { | |
3b603066 | 916 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 VZ |
917 | struct bnx2x_func_start_params *start_params = |
918 | &func_params.params.start; | |
919 | ||
920 | /* Prepare parameters for function state transitions */ | |
921 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
922 | ||
923 | func_params.f_obj = &bp->func_obj; | |
924 | func_params.cmd = BNX2X_F_CMD_START; | |
925 | ||
926 | /* Function parameters */ | |
927 | start_params->mf_mode = bp->mf_mode; | |
928 | start_params->sd_vlan_tag = bp->mf_ov; | |
8d7b0278 AE |
929 | |
930 | if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) | |
6383c0b3 | 931 | start_params->network_cos_mode = STATIC_COS; |
8d7b0278 AE |
932 | else /* CHIP_IS_E1X */ |
933 | start_params->network_cos_mode = FW_WRR; | |
619c5cb6 | 934 | |
e42780b6 DK |
935 | start_params->tunnel_mode = TUNN_MODE_GRE; |
936 | start_params->gre_tunnel_type = IPGRE_TUNNEL; | |
937 | start_params->inner_gre_rss_en = 1; | |
1bc277f7 | 938 | |
7609647e YM |
939 | if (IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { |
940 | start_params->class_fail_ethtype = ETH_P_FIP; | |
941 | start_params->class_fail = 1; | |
942 | start_params->no_added_tags = 1; | |
943 | } | |
944 | ||
619c5cb6 VZ |
945 | return bnx2x_func_state_change(bp, &func_params); |
946 | } | |
947 | ||
619c5cb6 VZ |
948 | /** |
949 | * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format | |
950 | * | |
951 | * @fw_hi: pointer to upper part | |
952 | * @fw_mid: pointer to middle part | |
953 | * @fw_lo: pointer to lower part | |
954 | * @mac: pointer to MAC address | |
955 | */ | |
86564c3f YM |
956 | static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, |
957 | __le16 *fw_lo, u8 *mac) | |
619c5cb6 VZ |
958 | { |
959 | ((u8 *)fw_hi)[0] = mac[1]; | |
960 | ((u8 *)fw_hi)[1] = mac[0]; | |
961 | ((u8 *)fw_mid)[0] = mac[3]; | |
962 | ((u8 *)fw_mid)[1] = mac[2]; | |
963 | ((u8 *)fw_lo)[0] = mac[5]; | |
964 | ((u8 *)fw_lo)[1] = mac[4]; | |
965 | } | |
966 | ||
523224a3 DK |
967 | static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, |
968 | struct bnx2x_fastpath *fp, int last) | |
9f6c9258 | 969 | { |
523224a3 | 970 | int i; |
9f6c9258 | 971 | |
7e6b4d44 | 972 | if (fp->mode == TPA_MODE_DISABLED) |
b3b83c3f DK |
973 | return; |
974 | ||
523224a3 DK |
975 | for (i = 0; i < last; i++) |
976 | bnx2x_free_rx_sge(bp, fp, i); | |
9f6c9258 DK |
977 | } |
978 | ||
523224a3 | 979 | static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) |
9f6c9258 | 980 | { |
523224a3 | 981 | int i; |
9f6c9258 | 982 | |
523224a3 DK |
983 | for (i = 1; i <= NUM_RX_RINGS; i++) { |
984 | struct eth_rx_bd *rx_bd; | |
985 | ||
986 | rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; | |
987 | rx_bd->addr_hi = | |
988 | cpu_to_le32(U64_HI(fp->rx_desc_mapping + | |
989 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
990 | rx_bd->addr_lo = | |
991 | cpu_to_le32(U64_LO(fp->rx_desc_mapping + | |
992 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
993 | } | |
9f6c9258 DK |
994 | } |
995 | ||
619c5cb6 VZ |
996 | /* Statistics ID are global per chip/path, while Client IDs for E1x are per |
997 | * port. | |
998 | */ | |
999 | static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) | |
1000 | { | |
de5c3741 YM |
1001 | struct bnx2x *bp = fp->bp; |
1002 | if (!CHIP_IS_E1x(bp)) { | |
de5c3741 YM |
1003 | /* there are special statistics counters for FCoE 136..140 */ |
1004 | if (IS_FCOE_FP(fp)) | |
1005 | return bp->cnic_base_cl_id + (bp->pf_num >> 1); | |
619c5cb6 | 1006 | return fp->cl_id; |
de5c3741 YM |
1007 | } |
1008 | return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; | |
619c5cb6 VZ |
1009 | } |
1010 | ||
1011 | static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, | |
1012 | bnx2x_obj_type obj_type) | |
1013 | { | |
1014 | struct bnx2x *bp = fp->bp; | |
1015 | ||
1016 | /* Configure classification DBs */ | |
15192a8c BW |
1017 | bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, |
1018 | fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), | |
619c5cb6 VZ |
1019 | bnx2x_sp_mapping(bp, mac_rdata), |
1020 | BNX2X_FILTER_MAC_PENDING, | |
1021 | &bp->sp_state, obj_type, | |
1022 | &bp->macs_pool); | |
1023 | } | |
1024 | ||
1025 | /** | |
1026 | * bnx2x_get_path_func_num - get number of active functions | |
1027 | * | |
1028 | * @bp: driver handle | |
1029 | * | |
1030 | * Calculates the number of active (not hidden) functions on the | |
1031 | * current path. | |
1032 | */ | |
1033 | static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) | |
1034 | { | |
1035 | u8 func_num = 0, i; | |
1036 | ||
1037 | /* 57710 has only one function per-port */ | |
1038 | if (CHIP_IS_E1(bp)) | |
1039 | return 1; | |
1040 | ||
1041 | /* Calculate a number of functions enabled on the current | |
1042 | * PATH/PORT. | |
1043 | */ | |
1044 | if (CHIP_REV_IS_SLOW(bp)) { | |
1045 | if (IS_MF(bp)) | |
1046 | func_num = 4; | |
1047 | else | |
1048 | func_num = 2; | |
1049 | } else { | |
1050 | for (i = 0; i < E1H_FUNC_MAX / 2; i++) { | |
1051 | u32 func_config = | |
1052 | MF_CFG_RD(bp, | |
1053 | func_mf_config[BP_PORT(bp) + 2 * i]. | |
1054 | config); | |
1055 | func_num += | |
1056 | ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); | |
1057 | } | |
1058 | } | |
1059 | ||
1060 | WARN_ON(!func_num); | |
1061 | ||
1062 | return func_num; | |
1063 | } | |
1064 | ||
1065 | static inline void bnx2x_init_bp_objs(struct bnx2x *bp) | |
1066 | { | |
1067 | /* RX_MODE controlling object */ | |
1068 | bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); | |
1069 | ||
1070 | /* multicast configuration controlling object */ | |
1071 | bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, | |
1072 | BP_FUNC(bp), BP_FUNC(bp), | |
1073 | bnx2x_sp(bp, mcast_rdata), | |
1074 | bnx2x_sp_mapping(bp, mcast_rdata), | |
1075 | BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, | |
1076 | BNX2X_OBJ_TYPE_RX); | |
1077 | ||
1078 | /* Setup CAM credit pools */ | |
1079 | bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), | |
1080 | bnx2x_get_path_func_num(bp)); | |
1081 | ||
b56e9670 AE |
1082 | bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1, |
1083 | bnx2x_get_path_func_num(bp)); | |
1084 | ||
619c5cb6 VZ |
1085 | /* RSS configuration object */ |
1086 | bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, | |
1087 | bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), | |
1088 | bnx2x_sp(bp, rss_rdata), | |
1089 | bnx2x_sp_mapping(bp, rss_rdata), | |
1090 | BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, | |
1091 | BNX2X_OBJ_TYPE_RX); | |
1092 | } | |
1093 | ||
1094 | static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) | |
1095 | { | |
1096 | if (CHIP_IS_E1x(fp->bp)) | |
1097 | return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; | |
1098 | else | |
1099 | return fp->cl_id; | |
1100 | } | |
1101 | ||
6383c0b3 | 1102 | static inline void bnx2x_init_txdata(struct bnx2x *bp, |
65565884 MS |
1103 | struct bnx2x_fp_txdata *txdata, u32 cid, |
1104 | int txq_index, __le16 *tx_cons_sb, | |
1105 | struct bnx2x_fastpath *fp) | |
6383c0b3 AE |
1106 | { |
1107 | txdata->cid = cid; | |
1108 | txdata->txq_index = txq_index; | |
1109 | txdata->tx_cons_sb = tx_cons_sb; | |
65565884 | 1110 | txdata->parent_fp = fp; |
7b5342d9 | 1111 | txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; |
6383c0b3 | 1112 | |
51c1a580 | 1113 | DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", |
6383c0b3 AE |
1114 | txdata->cid, txdata->txq_index); |
1115 | } | |
619c5cb6 | 1116 | |
619c5cb6 VZ |
1117 | static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) |
1118 | { | |
1119 | return bp->cnic_base_cl_id + cl_idx + | |
134d0f97 | 1120 | (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; |
619c5cb6 VZ |
1121 | } |
1122 | ||
1123 | static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) | |
1124 | { | |
619c5cb6 VZ |
1125 | /* the 'first' id is allocated for the cnic */ |
1126 | return bp->base_fw_ndsb; | |
1127 | } | |
1128 | ||
1129 | static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) | |
1130 | { | |
1131 | return bp->igu_base_sb; | |
1132 | } | |
1133 | ||
619c5cb6 | 1134 | static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, |
6383c0b3 | 1135 | struct bnx2x_fp_txdata *txdata) |
619c5cb6 VZ |
1136 | { |
1137 | int cnt = 1000; | |
1138 | ||
6383c0b3 | 1139 | while (bnx2x_has_tx_work_unload(txdata)) { |
619c5cb6 | 1140 | if (!cnt) { |
51c1a580 | 1141 | BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", |
6383c0b3 AE |
1142 | txdata->txq_index, txdata->tx_pkt_prod, |
1143 | txdata->tx_pkt_cons); | |
619c5cb6 VZ |
1144 | #ifdef BNX2X_STOP_ON_ERROR |
1145 | bnx2x_panic(); | |
1146 | return -EBUSY; | |
1147 | #else | |
1148 | break; | |
1149 | #endif | |
1150 | } | |
1151 | cnt--; | |
0926d499 | 1152 | usleep_range(1000, 2000); |
619c5cb6 VZ |
1153 | } |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1ac9e428 YR |
1158 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
1159 | ||
523224a3 DK |
1160 | static inline void __storm_memset_struct(struct bnx2x *bp, |
1161 | u32 addr, size_t size, u32 *data) | |
1162 | { | |
1163 | int i; | |
1164 | for (i = 0; i < size/4; i++) | |
1165 | REG_WR(bp, addr + (i * 4), data[i]); | |
1166 | } | |
1167 | ||
619c5cb6 VZ |
1168 | /** |
1169 | * bnx2x_wait_sp_comp - wait for the outstanding SP commands. | |
1170 | * | |
1171 | * @bp: driver handle | |
1172 | * @mask: bits that need to be cleared | |
1173 | */ | |
1174 | static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) | |
1175 | { | |
1176 | int tout = 5000; /* Wait for 5 secs tops */ | |
1177 | ||
1178 | while (tout--) { | |
1179 | smp_mb(); | |
1180 | netif_addr_lock_bh(bp->dev); | |
1181 | if (!(bp->sp_state & mask)) { | |
1182 | netif_addr_unlock_bh(bp->dev); | |
1183 | return true; | |
1184 | } | |
1185 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1186 | |
0926d499 | 1187 | usleep_range(1000, 2000); |
619c5cb6 VZ |
1188 | } |
1189 | ||
1190 | smp_mb(); | |
1191 | ||
1192 | netif_addr_lock_bh(bp->dev); | |
1193 | if (bp->sp_state & mask) { | |
51c1a580 MS |
1194 | BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", |
1195 | bp->sp_state, mask); | |
619c5cb6 VZ |
1196 | netif_addr_unlock_bh(bp->dev); |
1197 | return false; | |
1198 | } | |
1199 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1200 | |
619c5cb6 | 1201 | return true; |
523224a3 | 1202 | } |
f85582f8 | 1203 | |
619c5cb6 VZ |
1204 | /** |
1205 | * bnx2x_set_ctx_validation - set CDU context validation values | |
1206 | * | |
1207 | * @bp: driver handle | |
1208 | * @cxt: context of the connection on the host memory | |
1209 | * @cid: SW CID of the connection to be configured | |
1210 | */ | |
1211 | void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, | |
1212 | u32 cid); | |
1213 | ||
1214 | void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, | |
1215 | u8 sb_index, u8 disable, u16 usec); | |
9f6c9258 DK |
1216 | void bnx2x_acquire_phy_lock(struct bnx2x *bp); |
1217 | void bnx2x_release_phy_lock(struct bnx2x *bp); | |
1218 | ||
faa6fcbb | 1219 | /** |
e8920674 | 1220 | * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. |
faa6fcbb | 1221 | * |
e8920674 DK |
1222 | * @bp: driver handle |
1223 | * @mf_cfg: MF configuration | |
faa6fcbb | 1224 | * |
faa6fcbb DK |
1225 | */ |
1226 | static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) | |
1227 | { | |
1228 | u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> | |
1229 | FUNC_MF_CFG_MAX_BW_SHIFT; | |
1230 | if (!max_cfg) { | |
51c1a580 | 1231 | DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, |
96b0accb | 1232 | "Max BW configured to 0 - using 100 instead\n"); |
faa6fcbb DK |
1233 | max_cfg = 100; |
1234 | } | |
1235 | return max_cfg; | |
1236 | } | |
1237 | ||
621b4d66 DK |
1238 | /* checks if HW supports GRO for given MTU */ |
1239 | static inline bool bnx2x_mtu_allows_gro(int mtu) | |
1240 | { | |
1241 | /* gro frags per page */ | |
1242 | int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); | |
1243 | ||
1244 | /* | |
16a5fd92 YM |
1245 | * 1. Number of frags should not grow above MAX_SKB_FRAGS |
1246 | * 2. Frag must fit the page | |
621b4d66 DK |
1247 | */ |
1248 | return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; | |
1249 | } | |
55c11941 | 1250 | |
b306f5ed DK |
1251 | /** |
1252 | * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. | |
1253 | * | |
1254 | * @bp: driver handle | |
1255 | * | |
1256 | */ | |
1257 | void bnx2x_get_iscsi_info(struct bnx2x *bp); | |
00253a8c DK |
1258 | |
1259 | /** | |
1260 | * bnx2x_link_sync_notify - send notification to other functions. | |
1261 | * | |
1262 | * @bp: driver handle | |
1263 | * | |
1264 | */ | |
1265 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) | |
1266 | { | |
1267 | int func; | |
1268 | int vn; | |
1269 | ||
1270 | /* Set the attention towards other drivers on the same port */ | |
1271 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
1272 | if (vn == BP_VN(bp)) | |
1273 | continue; | |
1274 | ||
1275 | func = func_by_vn(bp, vn); | |
1276 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + | |
1277 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); | |
1278 | } | |
1279 | } | |
1280 | ||
1281 | /** | |
1282 | * bnx2x_update_drv_flags - update flags in shmem | |
1283 | * | |
1284 | * @bp: driver handle | |
1285 | * @flags: flags to update | |
1286 | * @set: set or clear | |
1287 | * | |
1288 | */ | |
1289 | static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) | |
1290 | { | |
1291 | if (SHMEM2_HAS(bp, drv_flags)) { | |
1292 | u32 drv_flags; | |
f16da43b | 1293 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1294 | drv_flags = SHMEM2_RD(bp, drv_flags); |
1295 | ||
1296 | if (set) | |
1297 | SET_FLAGS(drv_flags, flags); | |
1298 | else | |
1299 | RESET_FLAGS(drv_flags, flags); | |
1300 | ||
1301 | SHMEM2_WR(bp, drv_flags, drv_flags); | |
51c1a580 | 1302 | DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); |
f16da43b | 1303 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1304 | } |
1305 | } | |
1306 | ||
55c11941 | 1307 | |
614c76df | 1308 | |
8ca5e17e | 1309 | /** |
2de67439 | 1310 | * bnx2x_fill_fw_str - Fill buffer with FW version string |
8ca5e17e AE |
1311 | * |
1312 | * @bp: driver handle | |
1313 | * @buf: character buffer to fill with the fw name | |
1314 | * @buf_len: length of the above buffer | |
1315 | * | |
1316 | */ | |
1317 | void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len); | |
7fa6f340 YM |
1318 | |
1319 | int bnx2x_drain_tx_queues(struct bnx2x *bp); | |
1320 | void bnx2x_squeeze_objects(struct bnx2x *bp); | |
1321 | ||
230bb0f3 YM |
1322 | void bnx2x_schedule_sp_rtnl(struct bnx2x*, enum sp_rtnl_flag, |
1323 | u32 verbose); | |
1324 | ||
9f6c9258 | 1325 | #endif /* BNX2X_CMN_H */ |