[linux-2.6-block.git] / drivers / net / ethernet / apm / xgene / xgene_enet_main.h

/* Applied Micro X-Gene SoC Ethernet Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Authors: Iyappan Subramanian <isubramanian@apm.com>
 *	    Ravi Patel <rapatel@apm.com>
 *	    Keyur Chudgar <kchudgar@apm.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __XGENE_ENET_MAIN_H__
#define __XGENE_ENET_MAIN_H__

#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/efi.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of_platform.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include <linux/module.h>
#include <net/ip.h>
#include <linux/prefetch.h>
#include <linux/if_vlan.h>
#include <linux/phy.h>
#include "xgene_enet_hw.h"
#include "xgene_enet_cle.h"
#include "xgene_enet_ring2.h"

#define XGENE_DRV_VERSION	"v1.0"
#define XGENE_ENET_MAX_MTU	1536
#define SKB_BUFFER_SIZE		(XGENE_ENET_MAX_MTU - NET_IP_ALIGN)
#define BUFLEN_16K	(16 * 1024)
#define NUM_PKT_BUF	64
#define NUM_BUFPOOL	32
#define MAX_EXP_BUFFS	256
#define XGENE_ENET_MSS	1448
#define XGENE_MIN_ENET_FRAME_SIZE	60

#define XGENE_MAX_ENET_IRQ	16
#define XGENE_NUM_RX_RING	8
#define XGENE_NUM_TX_RING	8
#define XGENE_NUM_TXC_RING	8

#define START_CPU_BUFNUM_0	0
#define START_ETH_BUFNUM_0	2
#define START_BP_BUFNUM_0	0x22
#define START_RING_NUM_0	8
#define START_CPU_BUFNUM_1	12
#define START_ETH_BUFNUM_1	10
#define START_BP_BUFNUM_1	0x2A
#define START_RING_NUM_1	264

#define XG_START_CPU_BUFNUM_1	12
#define XG_START_ETH_BUFNUM_1	2
#define XG_START_BP_BUFNUM_1	0x22
#define XG_START_RING_NUM_1	264

#define X2_START_CPU_BUFNUM_0	0
#define X2_START_ETH_BUFNUM_0	0
#define X2_START_BP_BUFNUM_0	0x20
#define X2_START_RING_NUM_0	0
#define X2_START_CPU_BUFNUM_1	0xc
#define X2_START_ETH_BUFNUM_1	0
#define X2_START_BP_BUFNUM_1	0x20
#define X2_START_RING_NUM_1	256

#define IRQ_ID_SIZE		16

#define PHY_POLL_LINK_ON	(10 * HZ)
#define PHY_POLL_LINK_OFF	(PHY_POLL_LINK_ON / 5)

enum xgene_enet_id {
	XGENE_ENET1 = 1,
	XGENE_ENET2
};

/* software context of a descriptor ring */
struct xgene_enet_desc_ring {
	struct net_device *ndev;
	u16 id;
	u16 num;
	u16 head;
	u16 tail;
	u16 exp_buf_tail;
	u16 slots;
	u16 irq;
	char irq_name[IRQ_ID_SIZE];
	u32 size;
	u32 state[X2_NUM_RING_CONFIG];
	void __iomem *cmd_base;
	void __iomem *cmd;
	dma_addr_t dma;
	dma_addr_t irq_mbox_dma;
	void *irq_mbox_addr;
	u16 dst_ring_num;
	u8 nbufpool;
	u8 index;
	struct sk_buff *(*rx_skb);
	struct sk_buff *(*cp_skb);
	dma_addr_t *frag_dma_addr;
	enum xgene_enet_ring_cfgsize cfgsize;
	struct xgene_enet_desc_ring *cp_ring;
	struct xgene_enet_desc_ring *buf_pool;
	struct napi_struct napi;
	union {
		void *desc_addr;
		struct xgene_enet_raw_desc *raw_desc;
		struct xgene_enet_raw_desc16 *raw_desc16;
	};
	__le64 *exp_bufs;
	u64 tx_packets;
	u64 tx_bytes;
	u64 rx_packets;
	u64 rx_bytes;
	u64 rx_dropped;
	u64 rx_errors;
	u64 rx_length_errors;
	u64 rx_crc_errors;
	u64 rx_frame_errors;
	u64 rx_fifo_errors;
};

struct xgene_mac_ops {
	void (*init)(struct xgene_enet_pdata *pdata);
	void (*reset)(struct xgene_enet_pdata *pdata);
	void (*tx_enable)(struct xgene_enet_pdata *pdata);
	void (*rx_enable)(struct xgene_enet_pdata *pdata);
	void (*tx_disable)(struct xgene_enet_pdata *pdata);
	void (*rx_disable)(struct xgene_enet_pdata *pdata);
	void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
	void (*set_mss)(struct xgene_enet_pdata *pdata);
	void (*link_state)(struct work_struct *work);
};

struct xgene_port_ops {
	int (*reset)(struct xgene_enet_pdata *pdata);
	void (*cle_bypass)(struct xgene_enet_pdata *pdata,
			   u32 dst_ring_num, u16 bufpool_id);
	void (*shutdown)(struct xgene_enet_pdata *pdata);
};

struct xgene_ring_ops {
	u8 num_ring_config;
	u8 num_ring_id_shift;
	struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
	void (*clear)(struct xgene_enet_desc_ring *);
	void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
	u32 (*len)(struct xgene_enet_desc_ring *);
	void (*coalesce)(struct xgene_enet_desc_ring *);
};

struct xgene_cle_ops {
	int (*cle_init)(struct xgene_enet_pdata *pdata);
};

/* ethernet private data */
struct xgene_enet_pdata {
	struct net_device *ndev;
	struct mii_bus *mdio_bus;
	struct phy_device *phy_dev;
	int phy_speed;
	struct clk *clk;
	struct platform_device *pdev;
	enum xgene_enet_id enet_id;
	struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING];
	struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING];
	u16 tx_level[XGENE_NUM_TX_RING];
	u16 txc_level[XGENE_NUM_TX_RING];
	char *dev_name;
	u32 rx_buff_cnt;
	u32 tx_qcnt_hi;
	u32 irqs[XGENE_MAX_ENET_IRQ];
	u8 rxq_cnt;
	u8 txq_cnt;
	u8 cq_cnt;
	void __iomem *eth_csr_addr;
	void __iomem *eth_ring_if_addr;
	void __iomem *eth_diag_csr_addr;
	void __iomem *mcx_mac_addr;
	void __iomem *mcx_mac_csr_addr;
	void __iomem *base_addr;
	void __iomem *ring_csr_addr;
	void __iomem *ring_cmd_addr;
	int phy_mode;
	enum xgene_enet_rm rm;
	struct xgene_enet_cle cle;
	struct rtnl_link_stats64 stats;
	const struct xgene_mac_ops *mac_ops;
	const struct xgene_port_ops *port_ops;
	struct xgene_ring_ops *ring_ops;
	struct xgene_cle_ops *cle_ops;
	struct delayed_work link_work;
	u32 port_id;
	u8 cpu_bufnum;
	u8 eth_bufnum;
	u8 bp_bufnum;
	u16 ring_num;
	u32 mss;
	u8 tx_delay;
	u8 rx_delay;
};

struct xgene_indirect_ctl {
	void __iomem *addr;
	void __iomem *ctl;
	void __iomem *cmd;
	void __iomem *cmd_done;
};

/* Set the specified value into a bit-field defined by its starting position
 * and length within a single u64.
 */
static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val)
{
	return (val & ((1ULL << len) - 1)) << pos;
}

#define SET_VAL(field, val) \
		xgene_enet_set_field_value(field ## _POS, field ## _LEN, val)

#define SET_BIT(field) \
		xgene_enet_set_field_value(field ## _POS, 1, 1)

/* Get the value from a bit-field defined by its starting position
 * and length within the specified u64.
 */
static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
{
	return (src >> pos) & ((1ULL << len) - 1);
}

#define GET_VAL(field, src) \
		xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)

#define GET_BIT(field, src) \
		xgene_enet_get_field_value(field ## _POS, 1, src)

static inline struct device *ndev_to_dev(struct net_device *ndev)
{
	return ndev->dev.parent;
}

static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
{
	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);

	return ((u16)pdata->rm << 10) | ring->num;
}

void xgene_enet_set_ethtool_ops(struct net_device *netdev);

#endif /* __XGENE_ENET_MAIN_H__ */
Commit	Line	Data
e6ad7673 IS	1	/* Applied Micro X-Gene SoC Ethernet Driver
	2	*
	3	* Copyright (c) 2014, Applied Micro Circuits Corporation
	4	* Authors: Iyappan Subramanian <isubramanian@apm.com>
	5	* Ravi Patel <rapatel@apm.com>
	6	* Keyur Chudgar <kchudgar@apm.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef __XGENE_ENET_MAIN_H__
	23	#define __XGENE_ENET_MAIN_H__
	24
de7b5b3d	25	#include <linux/acpi.h>
e6ad7673	26	#include <linux/clk.h>
de7b5b3d	27	#include <linux/efi.h>
b5d7a069	28	#include <linux/irq.h>
de7b5b3d	29	#include <linux/io.h>
e6ad7673 IS	30	#include <linux/of_platform.h>
	31	#include <linux/of_net.h>
	32	#include <linux/of_mdio.h>
	33	#include <linux/module.h>
	34	#include <net/ip.h>
	35	#include <linux/prefetch.h>
	36	#include <linux/if_vlan.h>
	37	#include <linux/phy.h>
	38	#include "xgene_enet_hw.h"
76f94a9c	39	#include "xgene_enet_cle.h"
bc1b7c13	40	#include "xgene_enet_ring2.h"
e6ad7673 IS	41
	42	#define XGENE_DRV_VERSION "v1.0"
	43	#define XGENE_ENET_MAX_MTU 1536
	44	#define SKB_BUFFER_SIZE (XGENE_ENET_MAX_MTU - NET_IP_ALIGN)
949c40bb	45	#define BUFLEN_16K (16 * 1024)
e6ad7673 IS	46	#define NUM_PKT_BUF 64
e6ad7673 IS	47	#define NUM_BUFPOOL 32
9b00eb49 IS	48	#define MAX_EXP_BUFFS 256
	49	#define XGENE_ENET_MSS 1448
	50	#define XGENE_MIN_ENET_FRAME_SIZE 60
ca626454	51
1b090a48 IS	52	#define XGENE_MAX_ENET_IRQ 16
	53	#define XGENE_NUM_RX_RING 8
	54	#define XGENE_NUM_TX_RING 8
	55	#define XGENE_NUM_TXC_RING 8
107dec27	56
ca626454 KC	57	#define START_CPU_BUFNUM_0 0
	58	#define START_ETH_BUFNUM_0 2
	59	#define START_BP_BUFNUM_0 0x22
	60	#define START_RING_NUM_0 8
	61	#define START_CPU_BUFNUM_1 12
	62	#define START_ETH_BUFNUM_1 10
	63	#define START_BP_BUFNUM_1 0x2A
	64	#define START_RING_NUM_1 264
e6ad7673	65
149e9ab4 IS	66	#define XG_START_CPU_BUFNUM_1 12
	67	#define XG_START_ETH_BUFNUM_1 2
	68	#define XG_START_BP_BUFNUM_1 0x22
	69	#define XG_START_RING_NUM_1 264
	70
bc1b7c13 IS	71	#define X2_START_CPU_BUFNUM_0 0
	72	#define X2_START_ETH_BUFNUM_0 0
	73	#define X2_START_BP_BUFNUM_0 0x20
	74	#define X2_START_RING_NUM_0 0
bc1b7c13 IS	75	#define X2_START_CPU_BUFNUM_1 0xc
	76	#define X2_START_ETH_BUFNUM_1 0
	77	#define X2_START_BP_BUFNUM_1 0x20
	78	#define X2_START_RING_NUM_1 256
	79
6772b653	80	#define IRQ_ID_SIZE 16
6772b653	81
32f784b5 IS	82	#define PHY_POLL_LINK_ON (10 * HZ)
	83	#define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
	84
bc1b7c13 IS	85	enum xgene_enet_id {
	86	XGENE_ENET1 = 1,
	87	XGENE_ENET2
	88	};
	89
e6ad7673 IS	90	/* software context of a descriptor ring */
	91	struct xgene_enet_desc_ring {
	92	struct net_device *ndev;
	93	u16 id;
	94	u16 num;
	95	u16 head;
	96	u16 tail;
9b00eb49	97	u16 exp_buf_tail;
e6ad7673 IS	98	u16 slots;
e6ad7673 IS	99	u16 irq;
6772b653	100	char irq_name[IRQ_ID_SIZE];
e6ad7673	101	u32 size;
9dd3c797	102	u32 state[X2_NUM_RING_CONFIG];
e6ad7673 IS	103	void __iomem *cmd_base;
	104	void __iomem *cmd;
	105	dma_addr_t dma;
ed9b7da0 IS	106	dma_addr_t irq_mbox_dma;
ed9b7da0 IS	107	void *irq_mbox_addr;
e6ad7673 IS	108	u16 dst_ring_num;
e6ad7673 IS	109	u8 nbufpool;
107dec27	110	u8 index;
e6ad7673 IS	111	struct sk_buff (rx_skb);
e6ad7673 IS	112	struct sk_buff (cp_skb);
9b00eb49	113	dma_addr_t *frag_dma_addr;
e6ad7673 IS	114	enum xgene_enet_ring_cfgsize cfgsize;
	115	struct xgene_enet_desc_ring *cp_ring;
	116	struct xgene_enet_desc_ring *buf_pool;
	117	struct napi_struct napi;
	118	union {
	119	void *desc_addr;
	120	struct xgene_enet_raw_desc *raw_desc;
	121	struct xgene_enet_raw_desc16 *raw_desc16;
	122	};
9b00eb49	123	__le64 *exp_bufs;
3bb502f8 IS	124	u64 tx_packets;
	125	u64 tx_bytes;
	126	u64 rx_packets;
	127	u64 rx_bytes;
	128	u64 rx_dropped;
	129	u64 rx_errors;
	130	u64 rx_length_errors;
	131	u64 rx_crc_errors;
	132	u64 rx_frame_errors;
	133	u64 rx_fifo_errors;
e6ad7673 IS	134	};
e6ad7673 IS	135
d0eb7458 IS	136	struct xgene_mac_ops {
	137	void (init)(struct xgene_enet_pdata pdata);
	138	void (reset)(struct xgene_enet_pdata pdata);
	139	void (tx_enable)(struct xgene_enet_pdata pdata);
	140	void (rx_enable)(struct xgene_enet_pdata pdata);
	141	void (tx_disable)(struct xgene_enet_pdata pdata);
	142	void (rx_disable)(struct xgene_enet_pdata pdata);
	143	void (set_mac_addr)(struct xgene_enet_pdata pdata);
9b00eb49	144	void (set_mss)(struct xgene_enet_pdata pdata);
dc8385f0	145	void (link_state)(struct work_struct work);
d0eb7458 IS	146	};
	147
	148	struct xgene_port_ops {
c3f4465d	149	int (reset)(struct xgene_enet_pdata pdata);
d0eb7458 IS	150	void (cle_bypass)(struct xgene_enet_pdata pdata,
	151	u32 dst_ring_num, u16 bufpool_id);
	152	void (shutdown)(struct xgene_enet_pdata pdata);
	153	};
	154
81cefb81 IS	155	struct xgene_ring_ops {
	156	u8 num_ring_config;
	157	u8 num_ring_id_shift;
	158	struct xgene_enet_desc_ring * (setup)(struct xgene_enet_desc_ring );
	159	void (clear)(struct xgene_enet_desc_ring );
	160	void (wr_cmd)(struct xgene_enet_desc_ring , int);
	161	u32 (len)(struct xgene_enet_desc_ring );
107dec27	162	void (coalesce)(struct xgene_enet_desc_ring );
81cefb81 IS	163	};
81cefb81 IS	164
76f94a9c IS	165	struct xgene_cle_ops {
	166	int (cle_init)(struct xgene_enet_pdata pdata);
	167	};
	168
e6ad7673 IS	169	/* ethernet private data */
	170	struct xgene_enet_pdata {
	171	struct net_device *ndev;
	172	struct mii_bus *mdio_bus;
	173	struct phy_device *phy_dev;
	174	int phy_speed;
	175	struct clk *clk;
	176	struct platform_device *pdev;
bc1b7c13	177	enum xgene_enet_id enet_id;
107dec27 IS	178	struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING];
	179	struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING];
	180	u16 tx_level[XGENE_NUM_TX_RING];
	181	u16 txc_level[XGENE_NUM_TX_RING];
e6ad7673 IS	182	char *dev_name;
	183	u32 rx_buff_cnt;
	184	u32 tx_qcnt_hi;
107dec27 IS	185	u32 irqs[XGENE_MAX_ENET_IRQ];
	186	u8 rxq_cnt;
	187	u8 txq_cnt;
6772b653	188	u8 cq_cnt;
e6ad7673 IS	189	void __iomem *eth_csr_addr;
	190	void __iomem *eth_ring_if_addr;
	191	void __iomem *eth_diag_csr_addr;
	192	void __iomem *mcx_mac_addr;
e6ad7673 IS	193	void __iomem *mcx_mac_csr_addr;
	194	void __iomem *base_addr;
	195	void __iomem *ring_csr_addr;
	196	void __iomem *ring_cmd_addr;
e6ad7673	197	int phy_mode;
0148d38d	198	enum xgene_enet_rm rm;
76f94a9c	199	struct xgene_enet_cle cle;
e6ad7673	200	struct rtnl_link_stats64 stats;
3cdb7309 JL	201	const struct xgene_mac_ops *mac_ops;
3cdb7309 JL	202	const struct xgene_port_ops *port_ops;
81cefb81	203	struct xgene_ring_ops *ring_ops;
76f94a9c	204	struct xgene_cle_ops *cle_ops;
0148d38d	205	struct delayed_work link_work;
ca626454 KC	206	u32 port_id;
	207	u8 cpu_bufnum;
	208	u8 eth_bufnum;
	209	u8 bp_bufnum;
	210	u16 ring_num;
9b00eb49	211	u32 mss;
16615a4c IS	212	u8 tx_delay;
16615a4c IS	213	u8 rx_delay;
e6ad7673 IS	214	};
e6ad7673 IS	215
32f784b5 IS	216	struct xgene_indirect_ctl {
	217	void __iomem *addr;
	218	void __iomem *ctl;
	219	void __iomem *cmd;
	220	void __iomem *cmd_done;
	221	};
	222
e6ad7673 IS	223	/* Set the specified value into a bit-field defined by its starting position
	224	* and length within a single u64.
	225	*/
	226	static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val)
	227	{
	228	return (val & ((1ULL << len) - 1)) << pos;
	229	}
	230
	231	#define SET_VAL(field, val) \
	232	xgene_enet_set_field_value(field ## _POS, field ## _LEN, val)
	233
	234	#define SET_BIT(field) \
	235	xgene_enet_set_field_value(field ## _POS, 1, 1)
	236
	237	/* Get the value from a bit-field defined by its starting position
	238	* and length within the specified u64.
	239	*/
	240	static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
	241	{
	242	return (src >> pos) & ((1ULL << len) - 1);
	243	}
	244
	245	#define GET_VAL(field, src) \
	246	xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)
	247
9b00eb49 IS	248	#define GET_BIT(field, src) \
	249	xgene_enet_get_field_value(field ## _POS, 1, src)
	250
e6ad7673 IS	251	static inline struct device ndev_to_dev(struct net_device ndev)
	252	{
	253	return ndev->dev.parent;
	254	}
	255
76f94a9c IS	256	static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
	257	{
	258	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
	259
	260	return ((u16)pdata->rm << 10) \| ring->num;
	261	}
	262
e6ad7673 IS	263	void xgene_enet_set_ethtool_ops(struct net_device *netdev);
	264
	265	#endif /* __XGENE_ENET_MAIN_H__ */