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1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // | |
3 | // flexcan.c - FLEXCAN CAN controller driver | |
4 | // | |
5 | // Copyright (c) 2005-2006 Varma Electronics Oy | |
6 | // Copyright (c) 2009 Sascha Hauer, Pengutronix | |
7 | // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de> | |
8 | // Copyright (c) 2014 David Jander, Protonic Holland | |
9 | // | |
10 | // Based on code originally by Andrey Volkov <avolkov@varma-el.com> | |
e955cead MKB |
11 | |
12 | #include <linux/netdevice.h> | |
13 | #include <linux/can.h> | |
14 | #include <linux/can/dev.h> | |
15 | #include <linux/can/error.h> | |
adccadb9 | 16 | #include <linux/can/led.h> |
30164759 | 17 | #include <linux/can/rx-offload.h> |
e955cead MKB |
18 | #include <linux/clk.h> |
19 | #include <linux/delay.h> | |
e955cead MKB |
20 | #include <linux/interrupt.h> |
21 | #include <linux/io.h> | |
de3578c1 | 22 | #include <linux/mfd/syscon.h> |
e955cead | 23 | #include <linux/module.h> |
97efe9ae | 24 | #include <linux/of.h> |
30c1e672 | 25 | #include <linux/of_device.h> |
e955cead | 26 | #include <linux/platform_device.h> |
b7c4114b | 27 | #include <linux/regulator/consumer.h> |
de3578c1 | 28 | #include <linux/regmap.h> |
e955cead | 29 | |
e955cead MKB |
30 | #define DRV_NAME "flexcan" |
31 | ||
32 | /* 8 for RX fifo and 2 error handling */ | |
33 | #define FLEXCAN_NAPI_WEIGHT (8 + 2) | |
34 | ||
35 | /* FLEXCAN module configuration register (CANMCR) bits */ | |
36 | #define FLEXCAN_MCR_MDIS BIT(31) | |
37 | #define FLEXCAN_MCR_FRZ BIT(30) | |
38 | #define FLEXCAN_MCR_FEN BIT(29) | |
39 | #define FLEXCAN_MCR_HALT BIT(28) | |
40 | #define FLEXCAN_MCR_NOT_RDY BIT(27) | |
41 | #define FLEXCAN_MCR_WAK_MSK BIT(26) | |
42 | #define FLEXCAN_MCR_SOFTRST BIT(25) | |
43 | #define FLEXCAN_MCR_FRZ_ACK BIT(24) | |
44 | #define FLEXCAN_MCR_SUPV BIT(23) | |
45 | #define FLEXCAN_MCR_SLF_WAK BIT(22) | |
46 | #define FLEXCAN_MCR_WRN_EN BIT(21) | |
47 | #define FLEXCAN_MCR_LPM_ACK BIT(20) | |
48 | #define FLEXCAN_MCR_WAK_SRC BIT(19) | |
49 | #define FLEXCAN_MCR_DOZE BIT(18) | |
50 | #define FLEXCAN_MCR_SRX_DIS BIT(17) | |
62d1086e | 51 | #define FLEXCAN_MCR_IRMQ BIT(16) |
e955cead MKB |
52 | #define FLEXCAN_MCR_LPRIO_EN BIT(13) |
53 | #define FLEXCAN_MCR_AEN BIT(12) | |
b3cf53e9 | 54 | /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */ |
4c728d80 | 55 | #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f) |
0012e5c9 MKB |
56 | #define FLEXCAN_MCR_IDAM_A (0x0 << 8) |
57 | #define FLEXCAN_MCR_IDAM_B (0x1 << 8) | |
58 | #define FLEXCAN_MCR_IDAM_C (0x2 << 8) | |
59 | #define FLEXCAN_MCR_IDAM_D (0x3 << 8) | |
e955cead MKB |
60 | |
61 | /* FLEXCAN control register (CANCTRL) bits */ | |
62 | #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) | |
63 | #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) | |
64 | #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) | |
65 | #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) | |
66 | #define FLEXCAN_CTRL_BOFF_MSK BIT(15) | |
67 | #define FLEXCAN_CTRL_ERR_MSK BIT(14) | |
68 | #define FLEXCAN_CTRL_CLK_SRC BIT(13) | |
69 | #define FLEXCAN_CTRL_LPB BIT(12) | |
70 | #define FLEXCAN_CTRL_TWRN_MSK BIT(11) | |
71 | #define FLEXCAN_CTRL_RWRN_MSK BIT(10) | |
72 | #define FLEXCAN_CTRL_SMP BIT(7) | |
73 | #define FLEXCAN_CTRL_BOFF_REC BIT(6) | |
74 | #define FLEXCAN_CTRL_TSYN BIT(5) | |
75 | #define FLEXCAN_CTRL_LBUF BIT(4) | |
76 | #define FLEXCAN_CTRL_LOM BIT(3) | |
77 | #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) | |
78 | #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) | |
79 | #define FLEXCAN_CTRL_ERR_STATE \ | |
80 | (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ | |
81 | FLEXCAN_CTRL_BOFF_MSK) | |
82 | #define FLEXCAN_CTRL_ERR_ALL \ | |
83 | (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) | |
84 | ||
cdce8448 | 85 | /* FLEXCAN control register 2 (CTRL2) bits */ |
6f75fce1 MKB |
86 | #define FLEXCAN_CTRL2_ECRWRE BIT(29) |
87 | #define FLEXCAN_CTRL2_WRMFRZ BIT(28) | |
88 | #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24) | |
89 | #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19) | |
90 | #define FLEXCAN_CTRL2_MRP BIT(18) | |
91 | #define FLEXCAN_CTRL2_RRS BIT(17) | |
92 | #define FLEXCAN_CTRL2_EACEN BIT(16) | |
cdce8448 SA |
93 | |
94 | /* FLEXCAN memory error control register (MECR) bits */ | |
95 | #define FLEXCAN_MECR_ECRWRDIS BIT(31) | |
96 | #define FLEXCAN_MECR_HANCEI_MSK BIT(19) | |
97 | #define FLEXCAN_MECR_FANCEI_MSK BIT(18) | |
98 | #define FLEXCAN_MECR_CEI_MSK BIT(16) | |
99 | #define FLEXCAN_MECR_HAERRIE BIT(15) | |
100 | #define FLEXCAN_MECR_FAERRIE BIT(14) | |
101 | #define FLEXCAN_MECR_EXTERRIE BIT(13) | |
102 | #define FLEXCAN_MECR_RERRDIS BIT(9) | |
103 | #define FLEXCAN_MECR_ECCDIS BIT(8) | |
104 | #define FLEXCAN_MECR_NCEFAFRZ BIT(7) | |
105 | ||
e955cead MKB |
106 | /* FLEXCAN error and status register (ESR) bits */ |
107 | #define FLEXCAN_ESR_TWRN_INT BIT(17) | |
108 | #define FLEXCAN_ESR_RWRN_INT BIT(16) | |
109 | #define FLEXCAN_ESR_BIT1_ERR BIT(15) | |
110 | #define FLEXCAN_ESR_BIT0_ERR BIT(14) | |
111 | #define FLEXCAN_ESR_ACK_ERR BIT(13) | |
112 | #define FLEXCAN_ESR_CRC_ERR BIT(12) | |
113 | #define FLEXCAN_ESR_FRM_ERR BIT(11) | |
114 | #define FLEXCAN_ESR_STF_ERR BIT(10) | |
115 | #define FLEXCAN_ESR_TX_WRN BIT(9) | |
116 | #define FLEXCAN_ESR_RX_WRN BIT(8) | |
117 | #define FLEXCAN_ESR_IDLE BIT(7) | |
118 | #define FLEXCAN_ESR_TXRX BIT(6) | |
119 | #define FLEXCAN_EST_FLT_CONF_SHIFT (4) | |
120 | #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) | |
121 | #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) | |
122 | #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) | |
123 | #define FLEXCAN_ESR_BOFF_INT BIT(2) | |
124 | #define FLEXCAN_ESR_ERR_INT BIT(1) | |
125 | #define FLEXCAN_ESR_WAK_INT BIT(0) | |
126 | #define FLEXCAN_ESR_ERR_BUS \ | |
127 | (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ | |
128 | FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ | |
129 | FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) | |
130 | #define FLEXCAN_ESR_ERR_STATE \ | |
131 | (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) | |
132 | #define FLEXCAN_ESR_ERR_ALL \ | |
133 | (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) | |
6e9d554f WG |
134 | #define FLEXCAN_ESR_ALL_INT \ |
135 | (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ | |
de3578c1 AD |
136 | FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \ |
137 | FLEXCAN_ESR_WAK_INT) | |
e955cead MKB |
138 | |
139 | /* FLEXCAN interrupt flag register (IFLAG) bits */ | |
25e92445 | 140 | /* Errata ERR005829 step7: Reserve first valid MB */ |
cbffaf7a | 141 | #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8 |
b3cf53e9 | 142 | #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0 |
cbffaf7a | 143 | #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1) |
22233f7b | 144 | #define FLEXCAN_IFLAG_MB(x) BIT((x) & 0x1f) |
e955cead MKB |
145 | #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) |
146 | #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) | |
147 | #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) | |
e955cead MKB |
148 | |
149 | /* FLEXCAN message buffers */ | |
b3cf53e9 MKB |
150 | #define FLEXCAN_MB_CODE_MASK (0xf << 24) |
151 | #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24) | |
c32fe4ad MKB |
152 | #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24) |
153 | #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24) | |
154 | #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24) | |
0012e5c9 | 155 | #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24) |
c32fe4ad MKB |
156 | #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24) |
157 | ||
158 | #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24) | |
159 | #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24) | |
160 | #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24) | |
161 | #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24) | |
162 | ||
e955cead MKB |
163 | #define FLEXCAN_MB_CNT_SRR BIT(22) |
164 | #define FLEXCAN_MB_CNT_IDE BIT(21) | |
165 | #define FLEXCAN_MB_CNT_RTR BIT(20) | |
166 | #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) | |
167 | #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) | |
168 | ||
247e5356 | 169 | #define FLEXCAN_TIMEOUT_US (250) |
e955cead | 170 | |
0012e5c9 | 171 | /* FLEXCAN hardware feature flags |
bb698ca4 WG |
172 | * |
173 | * Below is some version info we got: | |
da49a807 ZYSFEZ |
174 | * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re- |
175 | * Filter? connected? Passive detection ception in MB | |
658f534c | 176 | * MX25 FlexCAN2 03.00.00.00 no no no no no |
da49a807 | 177 | * MX28 FlexCAN2 03.00.04.00 yes yes no no no |
658f534c | 178 | * MX35 FlexCAN2 03.00.00.00 no no no no no |
da49a807 ZYSFEZ |
179 | * MX53 FlexCAN2 03.00.00.00 yes no no no no |
180 | * MX6s FlexCAN3 10.00.12.00 yes yes no no yes | |
29c64b17 | 181 | * VF610 FlexCAN3 ? no yes no yes yes? |
99b7668c | 182 | * LS1021A FlexCAN2 03.00.04.00 no yes no no yes |
bb698ca4 WG |
183 | * |
184 | * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. | |
185 | */ | |
2f8639b2 | 186 | #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */ |
f377bff0 | 187 | #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */ |
9eb7aa89 | 188 | #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */ |
66ddb821 | 189 | #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */ |
b3cf53e9 | 190 | #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */ |
da49a807 | 191 | #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */ |
0e030a37 | 192 | #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7) /* default to BE register access */ |
de3578c1 | 193 | #define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8) /* Setup stop mode to support wakeup */ |
4f72e5f0 | 194 | |
e955cead MKB |
195 | /* Structure of the message buffer */ |
196 | struct flexcan_mb { | |
197 | u32 can_ctrl; | |
198 | u32 can_id; | |
0517961c | 199 | u32 data[]; |
e955cead MKB |
200 | }; |
201 | ||
202 | /* Structure of the hardware registers */ | |
203 | struct flexcan_regs { | |
204 | u32 mcr; /* 0x00 */ | |
205 | u32 ctrl; /* 0x04 */ | |
206 | u32 timer; /* 0x08 */ | |
207 | u32 _reserved1; /* 0x0c */ | |
208 | u32 rxgmask; /* 0x10 */ | |
209 | u32 rx14mask; /* 0x14 */ | |
210 | u32 rx15mask; /* 0x18 */ | |
211 | u32 ecr; /* 0x1c */ | |
212 | u32 esr; /* 0x20 */ | |
213 | u32 imask2; /* 0x24 */ | |
214 | u32 imask1; /* 0x28 */ | |
215 | u32 iflag2; /* 0x2c */ | |
216 | u32 iflag1; /* 0x30 */ | |
62d1086e MKB |
217 | union { /* 0x34 */ |
218 | u32 gfwr_mx28; /* MX28, MX53 */ | |
219 | u32 ctrl2; /* MX6, VF610 */ | |
220 | }; | |
30c1e672 HW |
221 | u32 esr2; /* 0x38 */ |
222 | u32 imeur; /* 0x3c */ | |
223 | u32 lrfr; /* 0x40 */ | |
224 | u32 crcr; /* 0x44 */ | |
225 | u32 rxfgmask; /* 0x48 */ | |
226 | u32 rxfir; /* 0x4c */ | |
cdce8448 | 227 | u32 _reserved3[12]; /* 0x50 */ |
6cbf7602 | 228 | u8 mb[2][512]; /* 0x80 */ |
66a6ef02 MKB |
229 | /* FIFO-mode: |
230 | * MB | |
231 | * 0x080...0x08f 0 RX message buffer | |
232 | * 0x090...0x0df 1-5 reserverd | |
233 | * 0x0e0...0x0ff 6-7 8 entry ID table | |
234 | * (mx25, mx28, mx35, mx53) | |
235 | * 0x0e0...0x2df 6-7..37 8..128 entry ID table | |
0012e5c9 | 236 | * size conf'ed via ctrl2::RFFN |
66a6ef02 MKB |
237 | * (mx6, vf610) |
238 | */ | |
62d1086e MKB |
239 | u32 _reserved4[256]; /* 0x480 */ |
240 | u32 rximr[64]; /* 0x880 */ | |
241 | u32 _reserved5[24]; /* 0x980 */ | |
242 | u32 gfwr_mx6; /* 0x9e0 - MX6 */ | |
243 | u32 _reserved6[63]; /* 0x9e4 */ | |
cdce8448 SA |
244 | u32 mecr; /* 0xae0 */ |
245 | u32 erriar; /* 0xae4 */ | |
246 | u32 erridpr; /* 0xae8 */ | |
247 | u32 errippr; /* 0xaec */ | |
248 | u32 rerrar; /* 0xaf0 */ | |
249 | u32 rerrdr; /* 0xaf4 */ | |
250 | u32 rerrsynr; /* 0xaf8 */ | |
251 | u32 errsr; /* 0xafc */ | |
e955cead MKB |
252 | }; |
253 | ||
30c1e672 | 254 | struct flexcan_devtype_data { |
f377bff0 | 255 | u32 quirks; /* quirks needed for different IP cores */ |
30c1e672 HW |
256 | }; |
257 | ||
de3578c1 AD |
258 | struct flexcan_stop_mode { |
259 | struct regmap *gpr; | |
260 | u8 req_gpr; | |
261 | u8 req_bit; | |
262 | u8 ack_gpr; | |
263 | u8 ack_bit; | |
264 | }; | |
265 | ||
e955cead MKB |
266 | struct flexcan_priv { |
267 | struct can_priv can; | |
30164759 | 268 | struct can_rx_offload offload; |
e955cead | 269 | |
89af8746 | 270 | struct flexcan_regs __iomem *regs; |
0517961c | 271 | struct flexcan_mb __iomem *tx_mb; |
b93917c3 | 272 | struct flexcan_mb __iomem *tx_mb_reserved; |
0517961c PB |
273 | u8 tx_mb_idx; |
274 | u8 mb_count; | |
275 | u8 mb_size; | |
e955cead | 276 | u32 reg_ctrl_default; |
28ac7dcd | 277 | u32 reg_imask1_default; |
b3cf53e9 | 278 | u32 reg_imask2_default; |
e955cead | 279 | |
3d42a379 ST |
280 | struct clk *clk_ipg; |
281 | struct clk *clk_per; | |
dda0b3bd | 282 | const struct flexcan_devtype_data *devtype_data; |
b7c4114b | 283 | struct regulator *reg_xceiver; |
de3578c1 | 284 | struct flexcan_stop_mode stm; |
88462d2a PB |
285 | |
286 | /* Read and Write APIs */ | |
287 | u32 (*read)(void __iomem *addr); | |
288 | void (*write)(u32 val, void __iomem *addr); | |
30c1e672 HW |
289 | }; |
290 | ||
a3c11a7a | 291 | static const struct flexcan_devtype_data fsl_p1010_devtype_data = { |
0e030a37 UKK |
292 | .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE | |
293 | FLEXCAN_QUIRK_BROKEN_PERR_STATE | | |
294 | FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN, | |
295 | }; | |
296 | ||
297 | static const struct flexcan_devtype_data fsl_imx25_devtype_data = { | |
fb5b91d6 ZYSFEZ |
298 | .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE | |
299 | FLEXCAN_QUIRK_BROKEN_PERR_STATE, | |
30c1e672 | 300 | }; |
0012e5c9 | 301 | |
083c5571 ZYSFEZ |
302 | static const struct flexcan_devtype_data fsl_imx28_devtype_data = { |
303 | .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE, | |
304 | }; | |
0012e5c9 | 305 | |
a3c11a7a | 306 | static const struct flexcan_devtype_data fsl_imx6q_devtype_data = { |
096de07f | 307 | .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | |
de3578c1 AD |
308 | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE | |
309 | FLEXCAN_QUIRK_SETUP_STOP_MODE, | |
e955cead | 310 | }; |
0012e5c9 | 311 | |
a3c11a7a | 312 | static const struct flexcan_devtype_data fsl_vf610_devtype_data = { |
9eb7aa89 | 313 | .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | |
29c64b17 MKB |
314 | FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | |
315 | FLEXCAN_QUIRK_BROKEN_PERR_STATE, | |
cdce8448 | 316 | }; |
e955cead | 317 | |
99b7668c PB |
318 | static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = { |
319 | .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | | |
320 | FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE | | |
321 | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP, | |
322 | }; | |
323 | ||
194b9a4c | 324 | static const struct can_bittiming_const flexcan_bittiming_const = { |
e955cead MKB |
325 | .name = DRV_NAME, |
326 | .tseg1_min = 4, | |
327 | .tseg1_max = 16, | |
328 | .tseg2_min = 2, | |
329 | .tseg2_max = 8, | |
330 | .sjw_max = 4, | |
331 | .brp_min = 1, | |
332 | .brp_max = 256, | |
333 | .brp_inc = 1, | |
334 | }; | |
335 | ||
88462d2a PB |
336 | /* FlexCAN module is essentially modelled as a little-endian IP in most |
337 | * SoCs, i.e the registers as well as the message buffer areas are | |
338 | * implemented in a little-endian fashion. | |
339 | * | |
340 | * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN | |
341 | * module in a big-endian fashion (i.e the registers as well as the | |
342 | * message buffer areas are implemented in a big-endian way). | |
343 | * | |
344 | * In addition, the FlexCAN module can be found on SoCs having ARM or | |
345 | * PPC cores. So, we need to abstract off the register read/write | |
346 | * functions, ensuring that these cater to all the combinations of module | |
347 | * endianness and underlying CPU endianness. | |
61e271ee | 348 | */ |
88462d2a | 349 | static inline u32 flexcan_read_be(void __iomem *addr) |
61e271ee | 350 | { |
88462d2a | 351 | return ioread32be(addr); |
61e271ee | 352 | } |
353 | ||
88462d2a | 354 | static inline void flexcan_write_be(u32 val, void __iomem *addr) |
61e271ee | 355 | { |
88462d2a | 356 | iowrite32be(val, addr); |
61e271ee | 357 | } |
88462d2a PB |
358 | |
359 | static inline u32 flexcan_read_le(void __iomem *addr) | |
61e271ee | 360 | { |
88462d2a | 361 | return ioread32(addr); |
61e271ee | 362 | } |
363 | ||
88462d2a | 364 | static inline void flexcan_write_le(u32 val, void __iomem *addr) |
61e271ee | 365 | { |
88462d2a | 366 | iowrite32(val, addr); |
61e271ee | 367 | } |
61e271ee | 368 | |
0517961c PB |
369 | static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv, |
370 | u8 mb_index) | |
371 | { | |
6cbf7602 PB |
372 | u8 bank_size; |
373 | bool bank; | |
374 | ||
0517961c PB |
375 | if (WARN_ON(mb_index >= priv->mb_count)) |
376 | return NULL; | |
377 | ||
6cbf7602 PB |
378 | bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size; |
379 | ||
380 | bank = mb_index >= bank_size; | |
381 | if (bank) | |
382 | mb_index -= bank_size; | |
383 | ||
0517961c | 384 | return (struct flexcan_mb __iomem *) |
6cbf7602 | 385 | (&priv->regs->mb[bank][priv->mb_size * mb_index]); |
0517961c PB |
386 | } |
387 | ||
de3578c1 AD |
388 | static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable) |
389 | { | |
390 | struct flexcan_regs __iomem *regs = priv->regs; | |
391 | u32 reg_mcr; | |
392 | ||
393 | reg_mcr = priv->read(®s->mcr); | |
394 | ||
395 | if (enable) | |
396 | reg_mcr |= FLEXCAN_MCR_WAK_MSK; | |
397 | else | |
398 | reg_mcr &= ~FLEXCAN_MCR_WAK_MSK; | |
399 | ||
400 | priv->write(reg_mcr, ®s->mcr); | |
401 | } | |
402 | ||
403 | static inline void flexcan_enter_stop_mode(struct flexcan_priv *priv) | |
404 | { | |
405 | struct flexcan_regs __iomem *regs = priv->regs; | |
406 | u32 reg_mcr; | |
407 | ||
408 | reg_mcr = priv->read(®s->mcr); | |
409 | reg_mcr |= FLEXCAN_MCR_SLF_WAK; | |
410 | priv->write(reg_mcr, ®s->mcr); | |
411 | ||
412 | /* enable stop request */ | |
413 | regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr, | |
414 | 1 << priv->stm.req_bit, 1 << priv->stm.req_bit); | |
415 | } | |
416 | ||
417 | static inline void flexcan_exit_stop_mode(struct flexcan_priv *priv) | |
418 | { | |
419 | struct flexcan_regs __iomem *regs = priv->regs; | |
420 | u32 reg_mcr; | |
421 | ||
422 | /* remove stop request */ | |
423 | regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr, | |
424 | 1 << priv->stm.req_bit, 0); | |
425 | ||
426 | reg_mcr = priv->read(®s->mcr); | |
427 | reg_mcr &= ~FLEXCAN_MCR_SLF_WAK; | |
428 | priv->write(reg_mcr, ®s->mcr); | |
429 | } | |
430 | ||
da49a807 ZYSFEZ |
431 | static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv) |
432 | { | |
433 | struct flexcan_regs __iomem *regs = priv->regs; | |
434 | u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK); | |
435 | ||
88462d2a | 436 | priv->write(reg_ctrl, ®s->ctrl); |
da49a807 ZYSFEZ |
437 | } |
438 | ||
439 | static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv) | |
440 | { | |
441 | struct flexcan_regs __iomem *regs = priv->regs; | |
442 | u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK); | |
443 | ||
88462d2a | 444 | priv->write(reg_ctrl, ®s->ctrl); |
da49a807 ZYSFEZ |
445 | } |
446 | ||
f003698e MKB |
447 | static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv) |
448 | { | |
449 | if (!priv->reg_xceiver) | |
450 | return 0; | |
451 | ||
452 | return regulator_enable(priv->reg_xceiver); | |
453 | } | |
454 | ||
455 | static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv) | |
456 | { | |
457 | if (!priv->reg_xceiver) | |
458 | return 0; | |
459 | ||
460 | return regulator_disable(priv->reg_xceiver); | |
461 | } | |
462 | ||
9b00b300 | 463 | static int flexcan_chip_enable(struct flexcan_priv *priv) |
e955cead | 464 | { |
89af8746 | 465 | struct flexcan_regs __iomem *regs = priv->regs; |
9b00b300 | 466 | unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; |
e955cead MKB |
467 | u32 reg; |
468 | ||
88462d2a | 469 | reg = priv->read(®s->mcr); |
e955cead | 470 | reg &= ~FLEXCAN_MCR_MDIS; |
88462d2a | 471 | priv->write(reg, ®s->mcr); |
e955cead | 472 | |
88462d2a | 473 | while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) |
8badd65e | 474 | udelay(10); |
9b00b300 | 475 | |
88462d2a | 476 | if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) |
9b00b300 MKB |
477 | return -ETIMEDOUT; |
478 | ||
479 | return 0; | |
e955cead MKB |
480 | } |
481 | ||
9b00b300 | 482 | static int flexcan_chip_disable(struct flexcan_priv *priv) |
e955cead | 483 | { |
89af8746 | 484 | struct flexcan_regs __iomem *regs = priv->regs; |
9b00b300 | 485 | unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; |
e955cead MKB |
486 | u32 reg; |
487 | ||
88462d2a | 488 | reg = priv->read(®s->mcr); |
e955cead | 489 | reg |= FLEXCAN_MCR_MDIS; |
88462d2a | 490 | priv->write(reg, ®s->mcr); |
9b00b300 | 491 | |
88462d2a | 492 | while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) |
8badd65e | 493 | udelay(10); |
9b00b300 | 494 | |
88462d2a | 495 | if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) |
9b00b300 MKB |
496 | return -ETIMEDOUT; |
497 | ||
498 | return 0; | |
e955cead MKB |
499 | } |
500 | ||
b1aa1c7a MKB |
501 | static int flexcan_chip_freeze(struct flexcan_priv *priv) |
502 | { | |
89af8746 | 503 | struct flexcan_regs __iomem *regs = priv->regs; |
b1aa1c7a MKB |
504 | unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate; |
505 | u32 reg; | |
506 | ||
88462d2a | 507 | reg = priv->read(®s->mcr); |
b1aa1c7a | 508 | reg |= FLEXCAN_MCR_HALT; |
88462d2a | 509 | priv->write(reg, ®s->mcr); |
b1aa1c7a | 510 | |
88462d2a | 511 | while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) |
8badd65e | 512 | udelay(100); |
b1aa1c7a | 513 | |
88462d2a | 514 | if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) |
b1aa1c7a MKB |
515 | return -ETIMEDOUT; |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
520 | static int flexcan_chip_unfreeze(struct flexcan_priv *priv) | |
521 | { | |
89af8746 | 522 | struct flexcan_regs __iomem *regs = priv->regs; |
b1aa1c7a MKB |
523 | unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; |
524 | u32 reg; | |
525 | ||
88462d2a | 526 | reg = priv->read(®s->mcr); |
b1aa1c7a | 527 | reg &= ~FLEXCAN_MCR_HALT; |
88462d2a | 528 | priv->write(reg, ®s->mcr); |
b1aa1c7a | 529 | |
88462d2a | 530 | while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) |
8badd65e | 531 | udelay(10); |
b1aa1c7a | 532 | |
88462d2a | 533 | if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK) |
b1aa1c7a MKB |
534 | return -ETIMEDOUT; |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
4b5b8227 MKB |
539 | static int flexcan_chip_softreset(struct flexcan_priv *priv) |
540 | { | |
89af8746 | 541 | struct flexcan_regs __iomem *regs = priv->regs; |
4b5b8227 MKB |
542 | unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; |
543 | ||
88462d2a PB |
544 | priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr); |
545 | while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)) | |
8badd65e | 546 | udelay(10); |
4b5b8227 | 547 | |
88462d2a | 548 | if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST) |
4b5b8227 MKB |
549 | return -ETIMEDOUT; |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
ec56acfe SA |
554 | static int __flexcan_get_berr_counter(const struct net_device *dev, |
555 | struct can_berr_counter *bec) | |
e955cead MKB |
556 | { |
557 | const struct flexcan_priv *priv = netdev_priv(dev); | |
89af8746 | 558 | struct flexcan_regs __iomem *regs = priv->regs; |
88462d2a | 559 | u32 reg = priv->read(®s->ecr); |
e955cead MKB |
560 | |
561 | bec->txerr = (reg >> 0) & 0xff; | |
562 | bec->rxerr = (reg >> 8) & 0xff; | |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
ec56acfe SA |
567 | static int flexcan_get_berr_counter(const struct net_device *dev, |
568 | struct can_berr_counter *bec) | |
569 | { | |
570 | const struct flexcan_priv *priv = netdev_priv(dev); | |
571 | int err; | |
572 | ||
573 | err = clk_prepare_enable(priv->clk_ipg); | |
574 | if (err) | |
575 | return err; | |
576 | ||
577 | err = clk_prepare_enable(priv->clk_per); | |
578 | if (err) | |
579 | goto out_disable_ipg; | |
580 | ||
581 | err = __flexcan_get_berr_counter(dev, bec); | |
582 | ||
583 | clk_disable_unprepare(priv->clk_per); | |
584 | out_disable_ipg: | |
585 | clk_disable_unprepare(priv->clk_ipg); | |
586 | ||
587 | return err; | |
588 | } | |
589 | ||
fb1e13e6 | 590 | static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) |
e955cead MKB |
591 | { |
592 | const struct flexcan_priv *priv = netdev_priv(dev); | |
e955cead MKB |
593 | struct can_frame *cf = (struct can_frame *)skb->data; |
594 | u32 can_id; | |
0012e5c9 | 595 | u32 data; |
10d089bd | 596 | u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16); |
0517961c | 597 | int i; |
e955cead MKB |
598 | |
599 | if (can_dropped_invalid_skb(dev, skb)) | |
600 | return NETDEV_TX_OK; | |
601 | ||
602 | netif_stop_queue(dev); | |
603 | ||
604 | if (cf->can_id & CAN_EFF_FLAG) { | |
605 | can_id = cf->can_id & CAN_EFF_MASK; | |
606 | ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; | |
607 | } else { | |
608 | can_id = (cf->can_id & CAN_SFF_MASK) << 18; | |
609 | } | |
610 | ||
611 | if (cf->can_id & CAN_RTR_FLAG) | |
612 | ctrl |= FLEXCAN_MB_CNT_RTR; | |
613 | ||
0517961c PB |
614 | for (i = 0; i < cf->can_dlc; i += sizeof(u32)) { |
615 | data = be32_to_cpup((__be32 *)&cf->data[i]); | |
616 | priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]); | |
e955cead MKB |
617 | } |
618 | ||
9a123496 RD |
619 | can_put_echo_skb(skb, dev, 0); |
620 | ||
0517961c PB |
621 | priv->write(can_id, &priv->tx_mb->can_id); |
622 | priv->write(ctrl, &priv->tx_mb->can_ctrl); | |
e955cead | 623 | |
25e92445 DJ |
624 | /* Errata ERR005829 step8: |
625 | * Write twice INACTIVE(0x8) code to first MB. | |
626 | */ | |
88462d2a | 627 | priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, |
9dc1ee11 | 628 | &priv->tx_mb_reserved->can_ctrl); |
88462d2a | 629 | priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, |
9dc1ee11 | 630 | &priv->tx_mb_reserved->can_ctrl); |
25e92445 | 631 | |
e955cead MKB |
632 | return NETDEV_TX_OK; |
633 | } | |
634 | ||
30164759 | 635 | static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr) |
e955cead MKB |
636 | { |
637 | struct flexcan_priv *priv = netdev_priv(dev); | |
d788905f | 638 | struct flexcan_regs __iomem *regs = priv->regs; |
a5c02f66 MKB |
639 | struct sk_buff *skb; |
640 | struct can_frame *cf; | |
d166f56b | 641 | bool rx_errors = false, tx_errors = false; |
d788905f OR |
642 | u32 timestamp; |
643 | ||
644 | timestamp = priv->read(®s->timer) << 16; | |
e955cead | 645 | |
a5c02f66 MKB |
646 | skb = alloc_can_err_skb(dev, &cf); |
647 | if (unlikely(!skb)) | |
30164759 | 648 | return; |
a5c02f66 | 649 | |
e955cead MKB |
650 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; |
651 | ||
652 | if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { | |
aabdfd6a | 653 | netdev_dbg(dev, "BIT1_ERR irq\n"); |
e955cead | 654 | cf->data[2] |= CAN_ERR_PROT_BIT1; |
d166f56b | 655 | tx_errors = true; |
e955cead MKB |
656 | } |
657 | if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { | |
aabdfd6a | 658 | netdev_dbg(dev, "BIT0_ERR irq\n"); |
e955cead | 659 | cf->data[2] |= CAN_ERR_PROT_BIT0; |
d166f56b | 660 | tx_errors = true; |
e955cead MKB |
661 | } |
662 | if (reg_esr & FLEXCAN_ESR_ACK_ERR) { | |
aabdfd6a | 663 | netdev_dbg(dev, "ACK_ERR irq\n"); |
e955cead | 664 | cf->can_id |= CAN_ERR_ACK; |
ffd461f8 | 665 | cf->data[3] = CAN_ERR_PROT_LOC_ACK; |
d166f56b | 666 | tx_errors = true; |
e955cead MKB |
667 | } |
668 | if (reg_esr & FLEXCAN_ESR_CRC_ERR) { | |
aabdfd6a | 669 | netdev_dbg(dev, "CRC_ERR irq\n"); |
e955cead | 670 | cf->data[2] |= CAN_ERR_PROT_BIT; |
ffd461f8 | 671 | cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; |
d166f56b | 672 | rx_errors = true; |
e955cead MKB |
673 | } |
674 | if (reg_esr & FLEXCAN_ESR_FRM_ERR) { | |
aabdfd6a | 675 | netdev_dbg(dev, "FRM_ERR irq\n"); |
e955cead | 676 | cf->data[2] |= CAN_ERR_PROT_FORM; |
d166f56b | 677 | rx_errors = true; |
e955cead MKB |
678 | } |
679 | if (reg_esr & FLEXCAN_ESR_STF_ERR) { | |
aabdfd6a | 680 | netdev_dbg(dev, "STF_ERR irq\n"); |
e955cead | 681 | cf->data[2] |= CAN_ERR_PROT_STUFF; |
d166f56b | 682 | rx_errors = true; |
e955cead MKB |
683 | } |
684 | ||
685 | priv->can.can_stats.bus_error++; | |
686 | if (rx_errors) | |
687 | dev->stats.rx_errors++; | |
688 | if (tx_errors) | |
689 | dev->stats.tx_errors++; | |
e955cead | 690 | |
d788905f | 691 | can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); |
e955cead MKB |
692 | } |
693 | ||
30164759 | 694 | static void flexcan_irq_state(struct net_device *dev, u32 reg_esr) |
e955cead MKB |
695 | { |
696 | struct flexcan_priv *priv = netdev_priv(dev); | |
d788905f | 697 | struct flexcan_regs __iomem *regs = priv->regs; |
e955cead MKB |
698 | struct sk_buff *skb; |
699 | struct can_frame *cf; | |
238443df | 700 | enum can_state new_state, rx_state, tx_state; |
e955cead | 701 | int flt; |
71a3aedc | 702 | struct can_berr_counter bec; |
d788905f OR |
703 | u32 timestamp; |
704 | ||
705 | timestamp = priv->read(®s->timer) << 16; | |
e955cead MKB |
706 | |
707 | flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; | |
708 | if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { | |
71a3aedc | 709 | tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ? |
0012e5c9 | 710 | CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE; |
71a3aedc | 711 | rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ? |
0012e5c9 | 712 | CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE; |
71a3aedc | 713 | new_state = max(tx_state, rx_state); |
258ce80e | 714 | } else { |
71a3aedc | 715 | __flexcan_get_berr_counter(dev, &bec); |
258ce80e | 716 | new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ? |
0012e5c9 | 717 | CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF; |
71a3aedc AY |
718 | rx_state = bec.rxerr >= bec.txerr ? new_state : 0; |
719 | tx_state = bec.rxerr <= bec.txerr ? new_state : 0; | |
71a3aedc | 720 | } |
e955cead MKB |
721 | |
722 | /* state hasn't changed */ | |
723 | if (likely(new_state == priv->can.state)) | |
30164759 | 724 | return; |
e955cead MKB |
725 | |
726 | skb = alloc_can_err_skb(dev, &cf); | |
727 | if (unlikely(!skb)) | |
30164759 | 728 | return; |
e955cead | 729 | |
71a3aedc AY |
730 | can_change_state(dev, cf, tx_state, rx_state); |
731 | ||
732 | if (unlikely(new_state == CAN_STATE_BUS_OFF)) | |
733 | can_bus_off(dev); | |
734 | ||
d788905f | 735 | can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); |
30164759 | 736 | } |
e955cead | 737 | |
30164759 MKB |
738 | static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload) |
739 | { | |
740 | return container_of(offload, struct flexcan_priv, offload); | |
e955cead MKB |
741 | } |
742 | ||
30164759 MKB |
743 | static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload, |
744 | struct can_frame *cf, | |
745 | u32 *timestamp, unsigned int n) | |
e955cead | 746 | { |
30164759 | 747 | struct flexcan_priv *priv = rx_offload_to_priv(offload); |
89af8746 | 748 | struct flexcan_regs __iomem *regs = priv->regs; |
0517961c | 749 | struct flexcan_mb __iomem *mb; |
30164759 | 750 | u32 reg_ctrl, reg_id, reg_iflag1; |
0517961c PB |
751 | int i; |
752 | ||
753 | mb = flexcan_get_mb(priv, n); | |
30164759 | 754 | |
b3cf53e9 MKB |
755 | if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { |
756 | u32 code; | |
757 | ||
758 | do { | |
88462d2a | 759 | reg_ctrl = priv->read(&mb->can_ctrl); |
b3cf53e9 MKB |
760 | } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT); |
761 | ||
762 | /* is this MB empty? */ | |
763 | code = reg_ctrl & FLEXCAN_MB_CODE_MASK; | |
764 | if ((code != FLEXCAN_MB_CODE_RX_FULL) && | |
765 | (code != FLEXCAN_MB_CODE_RX_OVERRUN)) | |
766 | return 0; | |
767 | ||
768 | if (code == FLEXCAN_MB_CODE_RX_OVERRUN) { | |
769 | /* This MB was overrun, we lost data */ | |
770 | offload->dev->stats.rx_over_errors++; | |
771 | offload->dev->stats.rx_errors++; | |
772 | } | |
773 | } else { | |
88462d2a | 774 | reg_iflag1 = priv->read(®s->iflag1); |
b3cf53e9 MKB |
775 | if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE)) |
776 | return 0; | |
777 | ||
88462d2a | 778 | reg_ctrl = priv->read(&mb->can_ctrl); |
b3cf53e9 | 779 | } |
e955cead | 780 | |
30164759 MKB |
781 | /* increase timstamp to full 32 bit */ |
782 | *timestamp = reg_ctrl << 16; | |
783 | ||
88462d2a | 784 | reg_id = priv->read(&mb->can_id); |
e955cead MKB |
785 | if (reg_ctrl & FLEXCAN_MB_CNT_IDE) |
786 | cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
787 | else | |
788 | cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; | |
789 | ||
790 | if (reg_ctrl & FLEXCAN_MB_CNT_RTR) | |
791 | cf->can_id |= CAN_RTR_FLAG; | |
792 | cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); | |
793 | ||
0517961c PB |
794 | for (i = 0; i < cf->can_dlc; i += sizeof(u32)) { |
795 | __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)])); | |
796 | *(__be32 *)(cf->data + i) = data; | |
797 | } | |
e955cead MKB |
798 | |
799 | /* mark as read */ | |
b3cf53e9 MKB |
800 | if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { |
801 | /* Clear IRQ */ | |
802 | if (n < 32) | |
88462d2a | 803 | priv->write(BIT(n), ®s->iflag1); |
b3cf53e9 | 804 | else |
88462d2a | 805 | priv->write(BIT(n - 32), ®s->iflag2); |
b3cf53e9 | 806 | } else { |
88462d2a | 807 | priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); |
b3cf53e9 | 808 | } |
adccadb9 | 809 | |
5178b7cd PB |
810 | /* Read the Free Running Timer. It is optional but recommended |
811 | * to unlock Mailbox as soon as possible and make it available | |
812 | * for reception. | |
813 | */ | |
814 | priv->read(®s->timer); | |
815 | ||
e955cead MKB |
816 | return 1; |
817 | } | |
818 | ||
b3cf53e9 MKB |
819 | |
820 | static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv) | |
821 | { | |
822 | struct flexcan_regs __iomem *regs = priv->regs; | |
823 | u32 iflag1, iflag2; | |
824 | ||
cbffaf7a | 825 | iflag2 = priv->read(®s->iflag2) & priv->reg_imask2_default & |
0517961c | 826 | ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx); |
cbffaf7a | 827 | iflag1 = priv->read(®s->iflag1) & priv->reg_imask1_default; |
b3cf53e9 MKB |
828 | |
829 | return (u64)iflag2 << 32 | iflag1; | |
830 | } | |
831 | ||
e955cead MKB |
832 | static irqreturn_t flexcan_irq(int irq, void *dev_id) |
833 | { | |
834 | struct net_device *dev = dev_id; | |
835 | struct net_device_stats *stats = &dev->stats; | |
836 | struct flexcan_priv *priv = netdev_priv(dev); | |
89af8746 | 837 | struct flexcan_regs __iomem *regs = priv->regs; |
dd2f122a | 838 | irqreturn_t handled = IRQ_NONE; |
cbffaf7a | 839 | u32 reg_iflag2, reg_esr; |
da49a807 | 840 | enum can_state last_state = priv->can.state; |
e955cead | 841 | |
30164759 | 842 | /* reception interrupt */ |
b3cf53e9 MKB |
843 | if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { |
844 | u64 reg_iflag; | |
845 | int ret; | |
846 | ||
847 | while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) { | |
848 | handled = IRQ_HANDLED; | |
849 | ret = can_rx_offload_irq_offload_timestamp(&priv->offload, | |
850 | reg_iflag); | |
851 | if (!ret) | |
852 | break; | |
853 | } | |
854 | } else { | |
cbffaf7a AS |
855 | u32 reg_iflag1; |
856 | ||
857 | reg_iflag1 = priv->read(®s->iflag1); | |
b3cf53e9 MKB |
858 | if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) { |
859 | handled = IRQ_HANDLED; | |
860 | can_rx_offload_irq_offload_fifo(&priv->offload); | |
861 | } | |
e955cead | 862 | |
b3cf53e9 MKB |
863 | /* FIFO overflow interrupt */ |
864 | if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { | |
865 | handled = IRQ_HANDLED; | |
88462d2a PB |
866 | priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, |
867 | ®s->iflag1); | |
b3cf53e9 MKB |
868 | dev->stats.rx_over_errors++; |
869 | dev->stats.rx_errors++; | |
870 | } | |
e955cead MKB |
871 | } |
872 | ||
cbffaf7a AS |
873 | reg_iflag2 = priv->read(®s->iflag2); |
874 | ||
e955cead | 875 | /* transmission complete interrupt */ |
0517961c PB |
876 | if (reg_iflag2 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) { |
877 | u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl); | |
ed72bc8b | 878 | |
dd2f122a | 879 | handled = IRQ_HANDLED; |
ed72bc8b OR |
880 | stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload, |
881 | 0, reg_ctrl << 16); | |
e955cead | 882 | stats->tx_packets++; |
adccadb9 | 883 | can_led_event(dev, CAN_LED_EVENT_TX); |
0012e5c9 MKB |
884 | |
885 | /* after sending a RTR frame MB is in RX mode */ | |
88462d2a | 886 | priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, |
0517961c PB |
887 | &priv->tx_mb->can_ctrl); |
888 | priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag2); | |
e955cead MKB |
889 | netif_wake_queue(dev); |
890 | } | |
891 | ||
88462d2a | 892 | reg_esr = priv->read(®s->esr); |
30164759 | 893 | |
dd2f122a MKB |
894 | /* ACK all bus error and state change IRQ sources */ |
895 | if (reg_esr & FLEXCAN_ESR_ALL_INT) { | |
896 | handled = IRQ_HANDLED; | |
88462d2a | 897 | priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); |
dd2f122a MKB |
898 | } |
899 | ||
ad230234 ZYSFEZ |
900 | /* state change interrupt or broken error state quirk fix is enabled */ |
901 | if ((reg_esr & FLEXCAN_ESR_ERR_STATE) || | |
da49a807 | 902 | (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE | |
bc8ad651 | 903 | FLEXCAN_QUIRK_BROKEN_PERR_STATE))) |
30164759 MKB |
904 | flexcan_irq_state(dev, reg_esr); |
905 | ||
906 | /* bus error IRQ - handle if bus error reporting is activated */ | |
907 | if ((reg_esr & FLEXCAN_ESR_ERR_BUS) && | |
908 | (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) | |
909 | flexcan_irq_bus_err(dev, reg_esr); | |
910 | ||
da49a807 ZYSFEZ |
911 | /* availability of error interrupt among state transitions in case |
912 | * bus error reporting is de-activated and | |
913 | * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled: | |
914 | * +--------------------------------------------------------------+ | |
915 | * | +----------------------------------------------+ [stopped / | | |
916 | * | | | sleeping] -+ | |
917 | * +-+-> active <-> warning <-> passive -> bus off -+ | |
918 | * ___________^^^^^^^^^^^^_______________________________ | |
919 | * disabled(1) enabled disabled | |
920 | * | |
921 | * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled | |
922 | */ | |
923 | if ((last_state != priv->can.state) && | |
924 | (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) && | |
925 | !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { | |
926 | switch (priv->can.state) { | |
927 | case CAN_STATE_ERROR_ACTIVE: | |
928 | if (priv->devtype_data->quirks & | |
929 | FLEXCAN_QUIRK_BROKEN_WERR_STATE) | |
930 | flexcan_error_irq_enable(priv); | |
931 | else | |
932 | flexcan_error_irq_disable(priv); | |
933 | break; | |
934 | ||
935 | case CAN_STATE_ERROR_WARNING: | |
936 | flexcan_error_irq_enable(priv); | |
937 | break; | |
938 | ||
939 | case CAN_STATE_ERROR_PASSIVE: | |
940 | case CAN_STATE_BUS_OFF: | |
941 | flexcan_error_irq_disable(priv); | |
942 | break; | |
943 | ||
944 | default: | |
945 | break; | |
946 | } | |
947 | } | |
948 | ||
dd2f122a | 949 | return handled; |
e955cead MKB |
950 | } |
951 | ||
952 | static void flexcan_set_bittiming(struct net_device *dev) | |
953 | { | |
954 | const struct flexcan_priv *priv = netdev_priv(dev); | |
955 | const struct can_bittiming *bt = &priv->can.bittiming; | |
89af8746 | 956 | struct flexcan_regs __iomem *regs = priv->regs; |
e955cead MKB |
957 | u32 reg; |
958 | ||
88462d2a | 959 | reg = priv->read(®s->ctrl); |
e955cead MKB |
960 | reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | |
961 | FLEXCAN_CTRL_RJW(0x3) | | |
962 | FLEXCAN_CTRL_PSEG1(0x7) | | |
963 | FLEXCAN_CTRL_PSEG2(0x7) | | |
964 | FLEXCAN_CTRL_PROPSEG(0x7) | | |
965 | FLEXCAN_CTRL_LPB | | |
966 | FLEXCAN_CTRL_SMP | | |
967 | FLEXCAN_CTRL_LOM); | |
968 | ||
969 | reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | | |
970 | FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | | |
971 | FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | | |
972 | FLEXCAN_CTRL_RJW(bt->sjw - 1) | | |
973 | FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); | |
974 | ||
975 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) | |
976 | reg |= FLEXCAN_CTRL_LPB; | |
977 | if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) | |
978 | reg |= FLEXCAN_CTRL_LOM; | |
979 | if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) | |
980 | reg |= FLEXCAN_CTRL_SMP; | |
981 | ||
7a4b6c86 | 982 | netdev_dbg(dev, "writing ctrl=0x%08x\n", reg); |
88462d2a | 983 | priv->write(reg, ®s->ctrl); |
e955cead MKB |
984 | |
985 | /* print chip status */ | |
aabdfd6a | 986 | netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, |
88462d2a | 987 | priv->read(®s->mcr), priv->read(®s->ctrl)); |
e955cead MKB |
988 | } |
989 | ||
0012e5c9 | 990 | /* flexcan_chip_start |
e955cead MKB |
991 | * |
992 | * this functions is entered with clocks enabled | |
993 | * | |
994 | */ | |
995 | static int flexcan_chip_start(struct net_device *dev) | |
996 | { | |
997 | struct flexcan_priv *priv = netdev_priv(dev); | |
89af8746 | 998 | struct flexcan_regs __iomem *regs = priv->regs; |
6f75fce1 | 999 | u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr; |
1f6d8035 | 1000 | int err, i; |
0517961c | 1001 | struct flexcan_mb __iomem *mb; |
e955cead MKB |
1002 | |
1003 | /* enable module */ | |
9b00b300 MKB |
1004 | err = flexcan_chip_enable(priv); |
1005 | if (err) | |
1006 | return err; | |
e955cead MKB |
1007 | |
1008 | /* soft reset */ | |
4b5b8227 MKB |
1009 | err = flexcan_chip_softreset(priv); |
1010 | if (err) | |
b1aa1c7a | 1011 | goto out_chip_disable; |
e955cead MKB |
1012 | |
1013 | flexcan_set_bittiming(dev); | |
1014 | ||
0012e5c9 | 1015 | /* MCR |
e955cead MKB |
1016 | * |
1017 | * enable freeze | |
e955cead MKB |
1018 | * halt now |
1019 | * only supervisor access | |
1020 | * enable warning int | |
4bd888a8 | 1021 | * enable individual RX masking |
749de6fc MKB |
1022 | * choose format C |
1023 | * set max mailbox number | |
e955cead | 1024 | */ |
88462d2a | 1025 | reg_mcr = priv->read(®s->mcr); |
d5a7b406 | 1026 | reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); |
b3cf53e9 | 1027 | reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV | |
7ad0f53a | 1028 | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C | |
0517961c | 1029 | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx); |
b3cf53e9 | 1030 | |
c982a3ca MKB |
1031 | /* MCR |
1032 | * | |
1033 | * FIFO: | |
1034 | * - disable for timestamp mode | |
1035 | * - enable for FIFO mode | |
1036 | */ | |
cbffaf7a | 1037 | if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) |
b3cf53e9 | 1038 | reg_mcr &= ~FLEXCAN_MCR_FEN; |
cbffaf7a AS |
1039 | else |
1040 | reg_mcr |= FLEXCAN_MCR_FEN; | |
1041 | ||
7ad0f53a PB |
1042 | /* MCR |
1043 | * | |
1044 | * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be | |
1045 | * asserted because this will impede the self reception | |
1046 | * of a transmitted message. This is not documented in | |
1047 | * earlier versions of flexcan block guide. | |
1048 | * | |
1049 | * Self Reception: | |
1050 | * - enable Self Reception for loopback mode | |
1051 | * (by clearing "Self Reception Disable" bit) | |
1052 | * - disable for normal operation | |
1053 | */ | |
1054 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) | |
1055 | reg_mcr &= ~FLEXCAN_MCR_SRX_DIS; | |
1056 | else | |
1057 | reg_mcr |= FLEXCAN_MCR_SRX_DIS; | |
1058 | ||
aabdfd6a | 1059 | netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); |
88462d2a | 1060 | priv->write(reg_mcr, ®s->mcr); |
e955cead | 1061 | |
0012e5c9 | 1062 | /* CTRL |
e955cead MKB |
1063 | * |
1064 | * disable timer sync feature | |
1065 | * | |
1066 | * disable auto busoff recovery | |
1067 | * transmit lowest buffer first | |
1068 | * | |
1069 | * enable tx and rx warning interrupt | |
1070 | * enable bus off interrupt | |
1071 | * (== FLEXCAN_CTRL_ERR_STATE) | |
e955cead | 1072 | */ |
88462d2a | 1073 | reg_ctrl = priv->read(®s->ctrl); |
e955cead MKB |
1074 | reg_ctrl &= ~FLEXCAN_CTRL_TSYN; |
1075 | reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | | |
4f72e5f0 | 1076 | FLEXCAN_CTRL_ERR_STATE; |
0012e5c9 MKB |
1077 | |
1078 | /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), | |
4f72e5f0 WG |
1079 | * on most Flexcan cores, too. Otherwise we don't get |
1080 | * any error warning or passive interrupts. | |
1081 | */ | |
2f8639b2 | 1082 | if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE || |
4f72e5f0 WG |
1083 | priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) |
1084 | reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; | |
bc03a541 AS |
1085 | else |
1086 | reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK; | |
e955cead MKB |
1087 | |
1088 | /* save for later use */ | |
1089 | priv->reg_ctrl_default = reg_ctrl; | |
6fa7da24 MKB |
1090 | /* leave interrupts disabled for now */ |
1091 | reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL; | |
aabdfd6a | 1092 | netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); |
88462d2a | 1093 | priv->write(reg_ctrl, ®s->ctrl); |
e955cead | 1094 | |
9eb7aa89 | 1095 | if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) { |
88462d2a | 1096 | reg_ctrl2 = priv->read(®s->ctrl2); |
9eb7aa89 | 1097 | reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS; |
88462d2a | 1098 | priv->write(reg_ctrl2, ®s->ctrl2); |
9eb7aa89 MKB |
1099 | } |
1100 | ||
b3cf53e9 | 1101 | if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { |
cbffaf7a | 1102 | for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) { |
0517961c | 1103 | mb = flexcan_get_mb(priv, i); |
88462d2a | 1104 | priv->write(FLEXCAN_MB_CODE_RX_EMPTY, |
0517961c | 1105 | &mb->can_ctrl); |
cbffaf7a AS |
1106 | } |
1107 | } else { | |
1108 | /* clear and invalidate unused mailboxes first */ | |
a55234da | 1109 | for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) { |
0517961c | 1110 | mb = flexcan_get_mb(priv, i); |
cbffaf7a | 1111 | priv->write(FLEXCAN_MB_CODE_RX_INACTIVE, |
0517961c | 1112 | &mb->can_ctrl); |
cbffaf7a | 1113 | } |
b3cf53e9 MKB |
1114 | } |
1115 | ||
25e92445 | 1116 | /* Errata ERR005829: mark first TX mailbox as INACTIVE */ |
88462d2a PB |
1117 | priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, |
1118 | &priv->tx_mb_reserved->can_ctrl); | |
25e92445 | 1119 | |
c32fe4ad | 1120 | /* mark TX mailbox as INACTIVE */ |
88462d2a | 1121 | priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, |
0517961c | 1122 | &priv->tx_mb->can_ctrl); |
d5a7b406 | 1123 | |
e955cead | 1124 | /* acceptance mask/acceptance code (accept everything) */ |
88462d2a PB |
1125 | priv->write(0x0, ®s->rxgmask); |
1126 | priv->write(0x0, ®s->rx14mask); | |
1127 | priv->write(0x0, ®s->rx15mask); | |
e955cead | 1128 | |
f377bff0 | 1129 | if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG) |
88462d2a | 1130 | priv->write(0x0, ®s->rxfgmask); |
30c1e672 | 1131 | |
4bd888a8 | 1132 | /* clear acceptance filters */ |
0517961c | 1133 | for (i = 0; i < priv->mb_count; i++) |
88462d2a | 1134 | priv->write(0, ®s->rximr[i]); |
4bd888a8 | 1135 | |
0012e5c9 | 1136 | /* On Vybrid, disable memory error detection interrupts |
cdce8448 SA |
1137 | * and freeze mode. |
1138 | * This also works around errata e5295 which generates | |
1139 | * false positive memory errors and put the device in | |
1140 | * freeze mode. | |
1141 | */ | |
f377bff0 | 1142 | if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) { |
0012e5c9 | 1143 | /* Follow the protocol as described in "Detection |
cdce8448 SA |
1144 | * and Correction of Memory Errors" to write to |
1145 | * MECR register | |
1146 | */ | |
88462d2a | 1147 | reg_ctrl2 = priv->read(®s->ctrl2); |
6f75fce1 | 1148 | reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE; |
88462d2a | 1149 | priv->write(reg_ctrl2, ®s->ctrl2); |
cdce8448 | 1150 | |
88462d2a | 1151 | reg_mecr = priv->read(®s->mecr); |
cdce8448 | 1152 | reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS; |
88462d2a | 1153 | priv->write(reg_mecr, ®s->mecr); |
cdce8448 | 1154 | reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK | |
0012e5c9 | 1155 | FLEXCAN_MECR_FANCEI_MSK); |
88462d2a | 1156 | priv->write(reg_mecr, ®s->mecr); |
cdce8448 SA |
1157 | } |
1158 | ||
f003698e MKB |
1159 | err = flexcan_transceiver_enable(priv); |
1160 | if (err) | |
b1aa1c7a | 1161 | goto out_chip_disable; |
e955cead MKB |
1162 | |
1163 | /* synchronize with the can bus */ | |
b1aa1c7a MKB |
1164 | err = flexcan_chip_unfreeze(priv); |
1165 | if (err) | |
1166 | goto out_transceiver_disable; | |
e955cead MKB |
1167 | |
1168 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1169 | ||
6fa7da24 MKB |
1170 | /* enable interrupts atomically */ |
1171 | disable_irq(dev->irq); | |
88462d2a PB |
1172 | priv->write(priv->reg_ctrl_default, ®s->ctrl); |
1173 | priv->write(priv->reg_imask1_default, ®s->imask1); | |
1174 | priv->write(priv->reg_imask2_default, ®s->imask2); | |
6fa7da24 | 1175 | enable_irq(dev->irq); |
e955cead MKB |
1176 | |
1177 | /* print chip status */ | |
aabdfd6a | 1178 | netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, |
88462d2a | 1179 | priv->read(®s->mcr), priv->read(®s->ctrl)); |
e955cead MKB |
1180 | |
1181 | return 0; | |
1182 | ||
b1aa1c7a MKB |
1183 | out_transceiver_disable: |
1184 | flexcan_transceiver_disable(priv); | |
1185 | out_chip_disable: | |
e955cead MKB |
1186 | flexcan_chip_disable(priv); |
1187 | return err; | |
1188 | } | |
1189 | ||
0012e5c9 | 1190 | /* flexcan_chip_stop |
e955cead MKB |
1191 | * |
1192 | * this functions is entered with clocks enabled | |
e955cead MKB |
1193 | */ |
1194 | static void flexcan_chip_stop(struct net_device *dev) | |
1195 | { | |
1196 | struct flexcan_priv *priv = netdev_priv(dev); | |
89af8746 | 1197 | struct flexcan_regs __iomem *regs = priv->regs; |
e955cead | 1198 | |
b1aa1c7a MKB |
1199 | /* freeze + disable module */ |
1200 | flexcan_chip_freeze(priv); | |
1201 | flexcan_chip_disable(priv); | |
e955cead | 1202 | |
5be93bdd | 1203 | /* Disable all interrupts */ |
88462d2a PB |
1204 | priv->write(0, ®s->imask2); |
1205 | priv->write(0, ®s->imask1); | |
1206 | priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, | |
1207 | ®s->ctrl); | |
5be93bdd | 1208 | |
f003698e | 1209 | flexcan_transceiver_disable(priv); |
e955cead | 1210 | priv->can.state = CAN_STATE_STOPPED; |
e955cead MKB |
1211 | } |
1212 | ||
1213 | static int flexcan_open(struct net_device *dev) | |
1214 | { | |
1215 | struct flexcan_priv *priv = netdev_priv(dev); | |
1216 | int err; | |
1217 | ||
aa10181b FE |
1218 | err = clk_prepare_enable(priv->clk_ipg); |
1219 | if (err) | |
1220 | return err; | |
1221 | ||
1222 | err = clk_prepare_enable(priv->clk_per); | |
1223 | if (err) | |
1224 | goto out_disable_ipg; | |
e955cead MKB |
1225 | |
1226 | err = open_candev(dev); | |
1227 | if (err) | |
aa10181b | 1228 | goto out_disable_per; |
e955cead MKB |
1229 | |
1230 | err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); | |
1231 | if (err) | |
1232 | goto out_close; | |
1233 | ||
0517961c | 1234 | priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN; |
6cbf7602 PB |
1235 | priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) + |
1236 | (sizeof(priv->regs->mb[1]) / priv->mb_size); | |
0517961c | 1237 | |
5156c7b1 | 1238 | if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) |
0517961c PB |
1239 | priv->tx_mb_reserved = |
1240 | flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP); | |
5156c7b1 | 1241 | else |
0517961c PB |
1242 | priv->tx_mb_reserved = |
1243 | flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO); | |
1244 | priv->tx_mb_idx = priv->mb_count - 1; | |
1245 | priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx); | |
5156c7b1 PB |
1246 | |
1247 | priv->reg_imask1_default = 0; | |
0517961c | 1248 | priv->reg_imask2_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx); |
5156c7b1 PB |
1249 | |
1250 | priv->offload.mailbox_read = flexcan_mailbox_read; | |
1251 | ||
1252 | if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { | |
1253 | u64 imask; | |
1254 | ||
1255 | priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST; | |
0517961c | 1256 | priv->offload.mb_last = priv->mb_count - 2; |
5156c7b1 PB |
1257 | |
1258 | imask = GENMASK_ULL(priv->offload.mb_last, | |
1259 | priv->offload.mb_first); | |
1260 | priv->reg_imask1_default |= imask; | |
1261 | priv->reg_imask2_default |= imask >> 32; | |
1262 | ||
1263 | err = can_rx_offload_add_timestamp(dev, &priv->offload); | |
1264 | } else { | |
1265 | priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | | |
1266 | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE; | |
1267 | err = can_rx_offload_add_fifo(dev, &priv->offload, | |
1268 | FLEXCAN_NAPI_WEIGHT); | |
1269 | } | |
1270 | if (err) | |
1271 | goto out_free_irq; | |
1272 | ||
e955cead MKB |
1273 | /* start chip and queuing */ |
1274 | err = flexcan_chip_start(dev); | |
1275 | if (err) | |
5156c7b1 | 1276 | goto out_offload_del; |
adccadb9 FB |
1277 | |
1278 | can_led_event(dev, CAN_LED_EVENT_OPEN); | |
1279 | ||
30164759 | 1280 | can_rx_offload_enable(&priv->offload); |
e955cead MKB |
1281 | netif_start_queue(dev); |
1282 | ||
1283 | return 0; | |
1284 | ||
5156c7b1 PB |
1285 | out_offload_del: |
1286 | can_rx_offload_del(&priv->offload); | |
7e9e148a MKB |
1287 | out_free_irq: |
1288 | free_irq(dev->irq, dev); | |
e955cead MKB |
1289 | out_close: |
1290 | close_candev(dev); | |
aa10181b | 1291 | out_disable_per: |
3d42a379 | 1292 | clk_disable_unprepare(priv->clk_per); |
aa10181b | 1293 | out_disable_ipg: |
3d42a379 | 1294 | clk_disable_unprepare(priv->clk_ipg); |
e955cead MKB |
1295 | |
1296 | return err; | |
1297 | } | |
1298 | ||
1299 | static int flexcan_close(struct net_device *dev) | |
1300 | { | |
1301 | struct flexcan_priv *priv = netdev_priv(dev); | |
1302 | ||
1303 | netif_stop_queue(dev); | |
30164759 | 1304 | can_rx_offload_disable(&priv->offload); |
e955cead MKB |
1305 | flexcan_chip_stop(dev); |
1306 | ||
5156c7b1 | 1307 | can_rx_offload_del(&priv->offload); |
e955cead | 1308 | free_irq(dev->irq, dev); |
3d42a379 ST |
1309 | clk_disable_unprepare(priv->clk_per); |
1310 | clk_disable_unprepare(priv->clk_ipg); | |
e955cead MKB |
1311 | |
1312 | close_candev(dev); | |
1313 | ||
adccadb9 FB |
1314 | can_led_event(dev, CAN_LED_EVENT_STOP); |
1315 | ||
e955cead MKB |
1316 | return 0; |
1317 | } | |
1318 | ||
1319 | static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) | |
1320 | { | |
1321 | int err; | |
1322 | ||
1323 | switch (mode) { | |
1324 | case CAN_MODE_START: | |
1325 | err = flexcan_chip_start(dev); | |
1326 | if (err) | |
1327 | return err; | |
1328 | ||
1329 | netif_wake_queue(dev); | |
1330 | break; | |
1331 | ||
1332 | default: | |
1333 | return -EOPNOTSUPP; | |
1334 | } | |
1335 | ||
1336 | return 0; | |
1337 | } | |
1338 | ||
1339 | static const struct net_device_ops flexcan_netdev_ops = { | |
1340 | .ndo_open = flexcan_open, | |
1341 | .ndo_stop = flexcan_close, | |
1342 | .ndo_start_xmit = flexcan_start_xmit, | |
c971fa2a | 1343 | .ndo_change_mtu = can_change_mtu, |
e955cead MKB |
1344 | }; |
1345 | ||
3c8ac0f2 | 1346 | static int register_flexcandev(struct net_device *dev) |
e955cead MKB |
1347 | { |
1348 | struct flexcan_priv *priv = netdev_priv(dev); | |
89af8746 | 1349 | struct flexcan_regs __iomem *regs = priv->regs; |
e955cead MKB |
1350 | u32 reg, err; |
1351 | ||
aa10181b FE |
1352 | err = clk_prepare_enable(priv->clk_ipg); |
1353 | if (err) | |
1354 | return err; | |
1355 | ||
1356 | err = clk_prepare_enable(priv->clk_per); | |
1357 | if (err) | |
1358 | goto out_disable_ipg; | |
e955cead MKB |
1359 | |
1360 | /* select "bus clock", chip must be disabled */ | |
9b00b300 MKB |
1361 | err = flexcan_chip_disable(priv); |
1362 | if (err) | |
1363 | goto out_disable_per; | |
88462d2a | 1364 | reg = priv->read(®s->ctrl); |
e955cead | 1365 | reg |= FLEXCAN_CTRL_CLK_SRC; |
88462d2a | 1366 | priv->write(reg, ®s->ctrl); |
e955cead | 1367 | |
9b00b300 MKB |
1368 | err = flexcan_chip_enable(priv); |
1369 | if (err) | |
1370 | goto out_chip_disable; | |
e955cead MKB |
1371 | |
1372 | /* set freeze, halt and activate FIFO, restrict register access */ | |
88462d2a | 1373 | reg = priv->read(®s->mcr); |
e955cead MKB |
1374 | reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | |
1375 | FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; | |
88462d2a | 1376 | priv->write(reg, ®s->mcr); |
e955cead | 1377 | |
0012e5c9 | 1378 | /* Currently we only support newer versions of this core |
b3cf53e9 MKB |
1379 | * featuring a RX hardware FIFO (although this driver doesn't |
1380 | * make use of it on some cores). Older cores, found on some | |
1381 | * Coldfire derivates are not tested. | |
e955cead | 1382 | */ |
88462d2a | 1383 | reg = priv->read(®s->mcr); |
e955cead | 1384 | if (!(reg & FLEXCAN_MCR_FEN)) { |
aabdfd6a | 1385 | netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); |
e955cead | 1386 | err = -ENODEV; |
9b00b300 | 1387 | goto out_chip_disable; |
e955cead MKB |
1388 | } |
1389 | ||
1390 | err = register_candev(dev); | |
1391 | ||
e955cead | 1392 | /* disable core and turn off clocks */ |
9b00b300 | 1393 | out_chip_disable: |
e955cead | 1394 | flexcan_chip_disable(priv); |
9b00b300 | 1395 | out_disable_per: |
3d42a379 | 1396 | clk_disable_unprepare(priv->clk_per); |
aa10181b | 1397 | out_disable_ipg: |
3d42a379 | 1398 | clk_disable_unprepare(priv->clk_ipg); |
e955cead MKB |
1399 | |
1400 | return err; | |
1401 | } | |
1402 | ||
3c8ac0f2 | 1403 | static void unregister_flexcandev(struct net_device *dev) |
e955cead MKB |
1404 | { |
1405 | unregister_candev(dev); | |
1406 | } | |
1407 | ||
de3578c1 AD |
1408 | static int flexcan_setup_stop_mode(struct platform_device *pdev) |
1409 | { | |
1410 | struct net_device *dev = platform_get_drvdata(pdev); | |
1411 | struct device_node *np = pdev->dev.of_node; | |
1412 | struct device_node *gpr_np; | |
1413 | struct flexcan_priv *priv; | |
1414 | phandle phandle; | |
1415 | u32 out_val[5]; | |
1416 | int ret; | |
1417 | ||
1418 | if (!np) | |
1419 | return -EINVAL; | |
1420 | ||
1421 | /* stop mode property format is: | |
1422 | * <&gpr req_gpr req_bit ack_gpr ack_bit>. | |
1423 | */ | |
1424 | ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, | |
1425 | ARRAY_SIZE(out_val)); | |
1426 | if (ret) { | |
1427 | dev_dbg(&pdev->dev, "no stop-mode property\n"); | |
1428 | return ret; | |
1429 | } | |
1430 | phandle = *out_val; | |
1431 | ||
1432 | gpr_np = of_find_node_by_phandle(phandle); | |
1433 | if (!gpr_np) { | |
1434 | dev_dbg(&pdev->dev, "could not find gpr node by phandle\n"); | |
7873e98c | 1435 | return -ENODEV; |
de3578c1 AD |
1436 | } |
1437 | ||
1438 | priv = netdev_priv(dev); | |
1439 | priv->stm.gpr = syscon_node_to_regmap(gpr_np); | |
1440 | of_node_put(gpr_np); | |
1441 | if (IS_ERR(priv->stm.gpr)) { | |
1442 | dev_dbg(&pdev->dev, "could not find gpr regmap\n"); | |
1443 | return PTR_ERR(priv->stm.gpr); | |
1444 | } | |
1445 | ||
1446 | priv->stm.req_gpr = out_val[1]; | |
1447 | priv->stm.req_bit = out_val[2]; | |
1448 | priv->stm.ack_gpr = out_val[3]; | |
1449 | priv->stm.ack_bit = out_val[4]; | |
1450 | ||
1451 | dev_dbg(&pdev->dev, | |
1452 | "gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n", | |
1453 | gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit, | |
1454 | priv->stm.ack_gpr, priv->stm.ack_bit); | |
1455 | ||
1456 | device_set_wakeup_capable(&pdev->dev, true); | |
1457 | ||
1458 | return 0; | |
1459 | } | |
1460 | ||
30c1e672 | 1461 | static const struct of_device_id flexcan_of_match[] = { |
30c1e672 | 1462 | { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, |
e3587842 | 1463 | { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, |
0e030a37 UKK |
1464 | { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, }, |
1465 | { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, }, | |
1466 | { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, }, | |
e3587842 | 1467 | { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, |
cdce8448 | 1468 | { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, }, |
99b7668c | 1469 | { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, }, |
30c1e672 HW |
1470 | { /* sentinel */ }, |
1471 | }; | |
4358a9dc | 1472 | MODULE_DEVICE_TABLE(of, flexcan_of_match); |
30c1e672 HW |
1473 | |
1474 | static const struct platform_device_id flexcan_id_table[] = { | |
1475 | { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, | |
1476 | { /* sentinel */ }, | |
1477 | }; | |
4358a9dc | 1478 | MODULE_DEVICE_TABLE(platform, flexcan_id_table); |
30c1e672 | 1479 | |
3c8ac0f2 | 1480 | static int flexcan_probe(struct platform_device *pdev) |
e955cead | 1481 | { |
30c1e672 | 1482 | const struct of_device_id *of_id; |
dda0b3bd | 1483 | const struct flexcan_devtype_data *devtype_data; |
e955cead MKB |
1484 | struct net_device *dev; |
1485 | struct flexcan_priv *priv; | |
555828ef | 1486 | struct regulator *reg_xceiver; |
e955cead | 1487 | struct resource *mem; |
3d42a379 | 1488 | struct clk *clk_ipg = NULL, *clk_per = NULL; |
89af8746 | 1489 | struct flexcan_regs __iomem *regs; |
e955cead | 1490 | int err, irq; |
97efe9ae | 1491 | u32 clock_freq = 0; |
1492 | ||
555828ef AW |
1493 | reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); |
1494 | if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) | |
1495 | return -EPROBE_DEFER; | |
1496 | else if (IS_ERR(reg_xceiver)) | |
1497 | reg_xceiver = NULL; | |
1498 | ||
afc016d8 HW |
1499 | if (pdev->dev.of_node) |
1500 | of_property_read_u32(pdev->dev.of_node, | |
0012e5c9 | 1501 | "clock-frequency", &clock_freq); |
97efe9ae | 1502 | |
1503 | if (!clock_freq) { | |
3d42a379 ST |
1504 | clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1505 | if (IS_ERR(clk_ipg)) { | |
1506 | dev_err(&pdev->dev, "no ipg clock defined\n"); | |
933e4af4 | 1507 | return PTR_ERR(clk_ipg); |
3d42a379 | 1508 | } |
3d42a379 ST |
1509 | |
1510 | clk_per = devm_clk_get(&pdev->dev, "per"); | |
1511 | if (IS_ERR(clk_per)) { | |
1512 | dev_err(&pdev->dev, "no per clock defined\n"); | |
933e4af4 | 1513 | return PTR_ERR(clk_per); |
97efe9ae | 1514 | } |
1a3e5173 | 1515 | clock_freq = clk_get_rate(clk_per); |
e955cead MKB |
1516 | } |
1517 | ||
1518 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1519 | irq = platform_get_irq(pdev, 0); | |
933e4af4 FE |
1520 | if (irq <= 0) |
1521 | return -ENODEV; | |
e955cead | 1522 | |
89af8746 MKB |
1523 | regs = devm_ioremap_resource(&pdev->dev, mem); |
1524 | if (IS_ERR(regs)) | |
1525 | return PTR_ERR(regs); | |
e955cead | 1526 | |
30c1e672 HW |
1527 | of_id = of_match_device(flexcan_of_match, &pdev->dev); |
1528 | if (of_id) { | |
1529 | devtype_data = of_id->data; | |
d0873e6f | 1530 | } else if (platform_get_device_id(pdev)->driver_data) { |
30c1e672 | 1531 | devtype_data = (struct flexcan_devtype_data *) |
d0873e6f | 1532 | platform_get_device_id(pdev)->driver_data; |
30c1e672 | 1533 | } else { |
933e4af4 | 1534 | return -ENODEV; |
30c1e672 HW |
1535 | } |
1536 | ||
933e4af4 FE |
1537 | dev = alloc_candev(sizeof(struct flexcan_priv), 1); |
1538 | if (!dev) | |
1539 | return -ENOMEM; | |
1540 | ||
30164759 MKB |
1541 | platform_set_drvdata(pdev, dev); |
1542 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1543 | ||
e955cead MKB |
1544 | dev->netdev_ops = &flexcan_netdev_ops; |
1545 | dev->irq = irq; | |
9a123496 | 1546 | dev->flags |= IFF_ECHO; |
e955cead MKB |
1547 | |
1548 | priv = netdev_priv(dev); | |
88462d2a | 1549 | |
0e030a37 UKK |
1550 | if (of_property_read_bool(pdev->dev.of_node, "big-endian") || |
1551 | devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) { | |
88462d2a PB |
1552 | priv->read = flexcan_read_be; |
1553 | priv->write = flexcan_write_be; | |
1554 | } else { | |
0e030a37 UKK |
1555 | priv->read = flexcan_read_le; |
1556 | priv->write = flexcan_write_le; | |
88462d2a PB |
1557 | } |
1558 | ||
97efe9ae | 1559 | priv->can.clock.freq = clock_freq; |
e955cead MKB |
1560 | priv->can.bittiming_const = &flexcan_bittiming_const; |
1561 | priv->can.do_set_mode = flexcan_set_mode; | |
1562 | priv->can.do_get_berr_counter = flexcan_get_berr_counter; | |
1563 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | | |
1564 | CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | | |
1565 | CAN_CTRLMODE_BERR_REPORTING; | |
89af8746 | 1566 | priv->regs = regs; |
3d42a379 ST |
1567 | priv->clk_ipg = clk_ipg; |
1568 | priv->clk_per = clk_per; | |
30c1e672 | 1569 | priv->devtype_data = devtype_data; |
555828ef | 1570 | priv->reg_xceiver = reg_xceiver; |
b7c4114b | 1571 | |
e955cead MKB |
1572 | err = register_flexcandev(dev); |
1573 | if (err) { | |
1574 | dev_err(&pdev->dev, "registering netdev failed\n"); | |
1575 | goto failed_register; | |
1576 | } | |
1577 | ||
adccadb9 FB |
1578 | devm_can_led_init(dev); |
1579 | ||
de3578c1 AD |
1580 | if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) { |
1581 | err = flexcan_setup_stop_mode(pdev); | |
1582 | if (err) | |
1583 | dev_dbg(&pdev->dev, "failed to setup stop-mode\n"); | |
1584 | } | |
1585 | ||
e955cead MKB |
1586 | return 0; |
1587 | ||
1588 | failed_register: | |
1589 | free_candev(dev); | |
e955cead MKB |
1590 | return err; |
1591 | } | |
1592 | ||
3c8ac0f2 | 1593 | static int flexcan_remove(struct platform_device *pdev) |
e955cead MKB |
1594 | { |
1595 | struct net_device *dev = platform_get_drvdata(pdev); | |
e955cead MKB |
1596 | |
1597 | unregister_flexcandev(dev); | |
9a27586d MKB |
1598 | free_candev(dev); |
1599 | ||
e955cead MKB |
1600 | return 0; |
1601 | } | |
1602 | ||
08c6d351 | 1603 | static int __maybe_unused flexcan_suspend(struct device *device) |
8b5e218d | 1604 | { |
588e7a8e | 1605 | struct net_device *dev = dev_get_drvdata(device); |
8b5e218d | 1606 | struct flexcan_priv *priv = netdev_priv(dev); |
9b00b300 | 1607 | int err; |
8b5e218d | 1608 | |
8b5e218d | 1609 | if (netif_running(dev)) { |
de3578c1 AD |
1610 | /* if wakeup is enabled, enter stop mode |
1611 | * else enter disabled mode. | |
1612 | */ | |
1613 | if (device_may_wakeup(device)) { | |
1614 | enable_irq_wake(dev->irq); | |
1615 | flexcan_enter_stop_mode(priv); | |
1616 | } else { | |
1617 | err = flexcan_chip_disable(priv); | |
1618 | if (err) | |
1619 | return err; | |
1620 | } | |
8b5e218d EB |
1621 | netif_stop_queue(dev); |
1622 | netif_device_detach(dev); | |
1623 | } | |
1624 | priv->can.state = CAN_STATE_SLEEPING; | |
1625 | ||
1626 | return 0; | |
1627 | } | |
1628 | ||
08c6d351 | 1629 | static int __maybe_unused flexcan_resume(struct device *device) |
8b5e218d | 1630 | { |
588e7a8e | 1631 | struct net_device *dev = dev_get_drvdata(device); |
8b5e218d | 1632 | struct flexcan_priv *priv = netdev_priv(dev); |
4de349e7 | 1633 | int err; |
8b5e218d EB |
1634 | |
1635 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1636 | if (netif_running(dev)) { | |
1637 | netif_device_attach(dev); | |
1638 | netif_start_queue(dev); | |
de3578c1 AD |
1639 | if (device_may_wakeup(device)) { |
1640 | disable_irq_wake(dev->irq); | |
1641 | } else { | |
1642 | err = flexcan_chip_enable(priv); | |
1643 | if (err) | |
1644 | return err; | |
1645 | } | |
8b5e218d | 1646 | } |
4de349e7 | 1647 | return 0; |
8b5e218d | 1648 | } |
588e7a8e | 1649 | |
de3578c1 AD |
1650 | static int __maybe_unused flexcan_noirq_suspend(struct device *device) |
1651 | { | |
1652 | struct net_device *dev = dev_get_drvdata(device); | |
1653 | struct flexcan_priv *priv = netdev_priv(dev); | |
1654 | ||
1655 | if (netif_running(dev) && device_may_wakeup(device)) | |
1656 | flexcan_enable_wakeup_irq(priv, true); | |
1657 | ||
1658 | return 0; | |
1659 | } | |
1660 | ||
1661 | static int __maybe_unused flexcan_noirq_resume(struct device *device) | |
1662 | { | |
1663 | struct net_device *dev = dev_get_drvdata(device); | |
1664 | struct flexcan_priv *priv = netdev_priv(dev); | |
1665 | ||
1666 | if (netif_running(dev) && device_may_wakeup(device)) { | |
1667 | flexcan_enable_wakeup_irq(priv, false); | |
1668 | flexcan_exit_stop_mode(priv); | |
1669 | } | |
1670 | ||
1671 | return 0; | |
1672 | } | |
1673 | ||
1674 | static const struct dev_pm_ops flexcan_pm_ops = { | |
1675 | SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume) | |
1676 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume) | |
1677 | }; | |
8b5e218d | 1678 | |
e955cead | 1679 | static struct platform_driver flexcan_driver = { |
c8aef4cb | 1680 | .driver = { |
1681 | .name = DRV_NAME, | |
588e7a8e | 1682 | .pm = &flexcan_pm_ops, |
c8aef4cb | 1683 | .of_match_table = flexcan_of_match, |
1684 | }, | |
e955cead | 1685 | .probe = flexcan_probe, |
3c8ac0f2 | 1686 | .remove = flexcan_remove, |
30c1e672 | 1687 | .id_table = flexcan_id_table, |
e955cead MKB |
1688 | }; |
1689 | ||
871d3372 | 1690 | module_platform_driver(flexcan_driver); |
e955cead MKB |
1691 | |
1692 | MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " | |
1693 | "Marc Kleine-Budde <kernel@pengutronix.de>"); | |
1694 | MODULE_LICENSE("GPL v2"); | |
1695 | MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); |