[linux-2.6-block.git] / drivers / mmc / host / sdhci.h

/*
 *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
 *
 *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */

/*
 * PCI registers
 */

#define PCI_SDHCI_IFPIO			0x00
#define PCI_SDHCI_IFDMA			0x01
#define PCI_SDHCI_IFVENDOR		0x02

#define PCI_SLOT_INFO			0x40	/* 8 bits */
#define  PCI_SLOT_INFO_SLOTS(x)		((x >> 4) & 7)
#define  PCI_SLOT_INFO_FIRST_BAR_MASK	0x07

/*
 * Controller registers
 */

#define SDHCI_DMA_ADDRESS	0x00

#define SDHCI_BLOCK_SIZE	0x04
#define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))

#define SDHCI_BLOCK_COUNT	0x06

#define SDHCI_ARGUMENT		0x08

#define SDHCI_TRANSFER_MODE	0x0C
#define  SDHCI_TRNS_DMA		0x01
#define  SDHCI_TRNS_BLK_CNT_EN	0x02
#define  SDHCI_TRNS_ACMD12	0x04
#define  SDHCI_TRNS_READ	0x10
#define  SDHCI_TRNS_MULTI	0x20

#define SDHCI_COMMAND		0x0E
#define  SDHCI_CMD_RESP_MASK	0x03
#define  SDHCI_CMD_CRC		0x08
#define  SDHCI_CMD_INDEX	0x10
#define  SDHCI_CMD_DATA		0x20

#define  SDHCI_CMD_RESP_NONE	0x00
#define  SDHCI_CMD_RESP_LONG	0x01
#define  SDHCI_CMD_RESP_SHORT	0x02
#define  SDHCI_CMD_RESP_SHORT_BUSY 0x03

#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))

#define SDHCI_RESPONSE		0x10

#define SDHCI_BUFFER		0x20

#define SDHCI_PRESENT_STATE	0x24
#define  SDHCI_CMD_INHIBIT	0x00000001
#define  SDHCI_DATA_INHIBIT	0x00000002
#define  SDHCI_DOING_WRITE	0x00000100
#define  SDHCI_DOING_READ	0x00000200
#define  SDHCI_SPACE_AVAILABLE	0x00000400
#define  SDHCI_DATA_AVAILABLE	0x00000800
#define  SDHCI_CARD_PRESENT	0x00010000
#define  SDHCI_WRITE_PROTECT	0x00080000

#define SDHCI_HOST_CONTROL 	0x28
#define  SDHCI_CTRL_LED		0x01
#define  SDHCI_CTRL_4BITBUS	0x02
#define  SDHCI_CTRL_HISPD	0x04

#define SDHCI_POWER_CONTROL	0x29
#define  SDHCI_POWER_ON		0x01
#define  SDHCI_POWER_180	0x0A
#define  SDHCI_POWER_300	0x0C
#define  SDHCI_POWER_330	0x0E

#define SDHCI_BLOCK_GAP_CONTROL	0x2A

#define SDHCI_WAKE_UP_CONTROL	0x2B

#define SDHCI_CLOCK_CONTROL	0x2C
#define  SDHCI_DIVIDER_SHIFT	8
#define  SDHCI_CLOCK_CARD_EN	0x0004
#define  SDHCI_CLOCK_INT_STABLE	0x0002
#define  SDHCI_CLOCK_INT_EN	0x0001

#define SDHCI_TIMEOUT_CONTROL	0x2E

#define SDHCI_SOFTWARE_RESET	0x2F
#define  SDHCI_RESET_ALL	0x01
#define  SDHCI_RESET_CMD	0x02
#define  SDHCI_RESET_DATA	0x04

#define SDHCI_INT_STATUS	0x30
#define SDHCI_INT_ENABLE	0x34
#define SDHCI_SIGNAL_ENABLE	0x38
#define  SDHCI_INT_RESPONSE	0x00000001
#define  SDHCI_INT_DATA_END	0x00000002
#define  SDHCI_INT_DMA_END	0x00000008
#define  SDHCI_INT_SPACE_AVAIL	0x00000010
#define  SDHCI_INT_DATA_AVAIL	0x00000020
#define  SDHCI_INT_CARD_INSERT	0x00000040
#define  SDHCI_INT_CARD_REMOVE	0x00000080
#define  SDHCI_INT_CARD_INT	0x00000100
#define  SDHCI_INT_ERROR	0x00008000
#define  SDHCI_INT_TIMEOUT	0x00010000
#define  SDHCI_INT_CRC		0x00020000
#define  SDHCI_INT_END_BIT	0x00040000
#define  SDHCI_INT_INDEX	0x00080000
#define  SDHCI_INT_DATA_TIMEOUT	0x00100000
#define  SDHCI_INT_DATA_CRC	0x00200000
#define  SDHCI_INT_DATA_END_BIT	0x00400000
#define  SDHCI_INT_BUS_POWER	0x00800000
#define  SDHCI_INT_ACMD12ERR	0x01000000

#define  SDHCI_INT_NORMAL_MASK	0x00007FFF
#define  SDHCI_INT_ERROR_MASK	0xFFFF8000

#define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
#define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
		SDHCI_INT_DATA_END_BIT)

#define SDHCI_ACMD12_ERR	0x3C

/* 3E-3F reserved */

#define SDHCI_CAPABILITIES	0x40
#define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
#define  SDHCI_TIMEOUT_CLK_SHIFT 0
#define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
#define  SDHCI_CLOCK_BASE_MASK	0x00003F00
#define  SDHCI_CLOCK_BASE_SHIFT	8
#define  SDHCI_MAX_BLOCK_MASK	0x00030000
#define  SDHCI_MAX_BLOCK_SHIFT  16
#define  SDHCI_CAN_DO_HISPD	0x00200000
#define  SDHCI_CAN_DO_DMA	0x00400000
#define  SDHCI_CAN_VDD_330	0x01000000
#define  SDHCI_CAN_VDD_300	0x02000000
#define  SDHCI_CAN_VDD_180	0x04000000

/* 44-47 reserved for more caps */

#define SDHCI_MAX_CURRENT	0x48

/* 4C-4F reserved for more max current */

/* 50-FB reserved */

#define SDHCI_SLOT_INT_STATUS	0xFC

#define SDHCI_HOST_VERSION	0xFE
#define  SDHCI_VENDOR_VER_MASK	0xFF00
#define  SDHCI_VENDOR_VER_SHIFT	8
#define  SDHCI_SPEC_VER_MASK	0x00FF
#define  SDHCI_SPEC_VER_SHIFT	0

struct sdhci_chip;

struct sdhci_host {
	struct sdhci_chip	*chip;
	struct mmc_host		*mmc;		/* MMC structure */

#ifdef CONFIG_LEDS_CLASS
	struct led_classdev	led;		/* LED control */
#endif

	spinlock_t		lock;		/* Mutex */

	int			flags;		/* Host attributes */
#define SDHCI_USE_DMA		(1<<0)		/* Host is DMA capable */
#define SDHCI_REQ_USE_DMA	(1<<1)		/* Use DMA for this req. */

	unsigned int		max_clk;	/* Max possible freq (MHz) */
	unsigned int		timeout_clk;	/* Timeout freq (KHz) */

	unsigned int		clock;		/* Current clock (MHz) */
	unsigned short		power;		/* Current voltage */

	struct mmc_request	*mrq;		/* Current request */
	struct mmc_command	*cmd;		/* Current command */
	struct mmc_data		*data;		/* Current data request */
	int			data_early:1;	/* Data finished before cmd */

	struct scatterlist	*cur_sg;	/* We're working on this */
	int			num_sg;		/* Entries left */
	int			offset;		/* Offset into current sg */
	int			remain;		/* Bytes left in current */

	int			irq;		/* Device IRQ */
	int			bar;		/* PCI BAR index */
	unsigned long		addr;		/* Bus address */
	void __iomem *		ioaddr;		/* Mapped address */

	struct tasklet_struct	card_tasklet;	/* Tasklet structures */
	struct tasklet_struct	finish_tasklet;

	struct timer_list	timer;		/* Timer for timeouts */
};

struct sdhci_chip {
	struct pci_dev		*pdev;

	unsigned long		quirks;

	int			num_slots;	/* Slots on controller */
	struct sdhci_host	*hosts[0];	/* Pointers to hosts */
};
Commit	Line	Data
d129bceb	1	/*
70f10482	2	* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
d129bceb	3	*
b69c9058	4	* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb PO	5	*
d129bceb PO	6	* This program is free software; you can redistribute it and/or modify
643f720c PO	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or (at
	9	* your option) any later version.
d129bceb PO	10	*/
	11
	12	/*
	13	* PCI registers
	14	*/
	15
67435274 PO	16	#define PCI_SDHCI_IFPIO 0x00
	17	#define PCI_SDHCI_IFDMA 0x01
	18	#define PCI_SDHCI_IFVENDOR 0x02
	19
d129bceb PO	20	#define PCI_SLOT_INFO 0x40 /* 8 bits */
	21	#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
	22	#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
	23
	24	/*
	25	* Controller registers
	26	*/
	27
	28	#define SDHCI_DMA_ADDRESS 0x00
	29
	30	#define SDHCI_BLOCK_SIZE 0x04
bab76961	31	#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) \| (blksz & 0xFFF))
d129bceb PO	32
	33	#define SDHCI_BLOCK_COUNT 0x06
	34
	35	#define SDHCI_ARGUMENT 0x08
	36
	37	#define SDHCI_TRANSFER_MODE 0x0C
	38	#define SDHCI_TRNS_DMA 0x01
	39	#define SDHCI_TRNS_BLK_CNT_EN 0x02
	40	#define SDHCI_TRNS_ACMD12 0x04
	41	#define SDHCI_TRNS_READ 0x10
	42	#define SDHCI_TRNS_MULTI 0x20
	43
	44	#define SDHCI_COMMAND 0x0E
	45	#define SDHCI_CMD_RESP_MASK 0x03
	46	#define SDHCI_CMD_CRC 0x08
	47	#define SDHCI_CMD_INDEX 0x10
	48	#define SDHCI_CMD_DATA 0x20
	49
	50	#define SDHCI_CMD_RESP_NONE 0x00
	51	#define SDHCI_CMD_RESP_LONG 0x01
	52	#define SDHCI_CMD_RESP_SHORT 0x02
	53	#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
	54
	55	#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) \| (f & 0xff))
	56
	57	#define SDHCI_RESPONSE 0x10
	58
	59	#define SDHCI_BUFFER 0x20
	60
	61	#define SDHCI_PRESENT_STATE 0x24
	62	#define SDHCI_CMD_INHIBIT 0x00000001
	63	#define SDHCI_DATA_INHIBIT 0x00000002
	64	#define SDHCI_DOING_WRITE 0x00000100
	65	#define SDHCI_DOING_READ 0x00000200
	66	#define SDHCI_SPACE_AVAILABLE 0x00000400
	67	#define SDHCI_DATA_AVAILABLE 0x00000800
	68	#define SDHCI_CARD_PRESENT 0x00010000
	69	#define SDHCI_WRITE_PROTECT 0x00080000
	70
	71	#define SDHCI_HOST_CONTROL 0x28
	72	#define SDHCI_CTRL_LED 0x01
	73	#define SDHCI_CTRL_4BITBUS 0x02
077df884	74	#define SDHCI_CTRL_HISPD 0x04
d129bceb PO	75
d129bceb PO	76	#define SDHCI_POWER_CONTROL 0x29
146ad66e PO	77	#define SDHCI_POWER_ON 0x01
	78	#define SDHCI_POWER_180 0x0A
	79	#define SDHCI_POWER_300 0x0C
	80	#define SDHCI_POWER_330 0x0E
d129bceb PO	81
	82	#define SDHCI_BLOCK_GAP_CONTROL 0x2A
	83
2df3b71b	84	#define SDHCI_WAKE_UP_CONTROL 0x2B
d129bceb PO	85
	86	#define SDHCI_CLOCK_CONTROL 0x2C
	87	#define SDHCI_DIVIDER_SHIFT 8
	88	#define SDHCI_CLOCK_CARD_EN 0x0004
	89	#define SDHCI_CLOCK_INT_STABLE 0x0002
	90	#define SDHCI_CLOCK_INT_EN 0x0001
	91
	92	#define SDHCI_TIMEOUT_CONTROL 0x2E
	93
	94	#define SDHCI_SOFTWARE_RESET 0x2F
	95	#define SDHCI_RESET_ALL 0x01
	96	#define SDHCI_RESET_CMD 0x02
	97	#define SDHCI_RESET_DATA 0x04
	98
	99	#define SDHCI_INT_STATUS 0x30
	100	#define SDHCI_INT_ENABLE 0x34
	101	#define SDHCI_SIGNAL_ENABLE 0x38
	102	#define SDHCI_INT_RESPONSE 0x00000001
	103	#define SDHCI_INT_DATA_END 0x00000002
	104	#define SDHCI_INT_DMA_END 0x00000008
a406f5a3 PO	105	#define SDHCI_INT_SPACE_AVAIL 0x00000010
a406f5a3 PO	106	#define SDHCI_INT_DATA_AVAIL 0x00000020
d129bceb PO	107	#define SDHCI_INT_CARD_INSERT 0x00000040
	108	#define SDHCI_INT_CARD_REMOVE 0x00000080
	109	#define SDHCI_INT_CARD_INT 0x00000100
964f9ce2	110	#define SDHCI_INT_ERROR 0x00008000
d129bceb PO	111	#define SDHCI_INT_TIMEOUT 0x00010000
	112	#define SDHCI_INT_CRC 0x00020000
	113	#define SDHCI_INT_END_BIT 0x00040000
	114	#define SDHCI_INT_INDEX 0x00080000
	115	#define SDHCI_INT_DATA_TIMEOUT 0x00100000
	116	#define SDHCI_INT_DATA_CRC 0x00200000
	117	#define SDHCI_INT_DATA_END_BIT 0x00400000
	118	#define SDHCI_INT_BUS_POWER 0x00800000
	119	#define SDHCI_INT_ACMD12ERR 0x01000000
	120
	121	#define SDHCI_INT_NORMAL_MASK 0x00007FFF
	122	#define SDHCI_INT_ERROR_MASK 0xFFFF8000
	123
	124	#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE \| SDHCI_INT_TIMEOUT \| \
	125	SDHCI_INT_CRC \| SDHCI_INT_END_BIT \| SDHCI_INT_INDEX)
	126	#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END \| SDHCI_INT_DMA_END \| \
a406f5a3	127	SDHCI_INT_DATA_AVAIL \| SDHCI_INT_SPACE_AVAIL \| \
d129bceb PO	128	SDHCI_INT_DATA_TIMEOUT \| SDHCI_INT_DATA_CRC \| \
	129	SDHCI_INT_DATA_END_BIT)
	130
	131	#define SDHCI_ACMD12_ERR 0x3C
	132
	133	/* 3E-3F reserved */
	134
	135	#define SDHCI_CAPABILITIES 0x40
1c8cde92 PO	136	#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
	137	#define SDHCI_TIMEOUT_CLK_SHIFT 0
	138	#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
d129bceb PO	139	#define SDHCI_CLOCK_BASE_MASK 0x00003F00
d129bceb PO	140	#define SDHCI_CLOCK_BASE_SHIFT 8
1d676e02 PO	141	#define SDHCI_MAX_BLOCK_MASK 0x00030000
1d676e02 PO	142	#define SDHCI_MAX_BLOCK_SHIFT 16
077df884	143	#define SDHCI_CAN_DO_HISPD 0x00200000
146ad66e PO	144	#define SDHCI_CAN_DO_DMA 0x00400000
	145	#define SDHCI_CAN_VDD_330 0x01000000
	146	#define SDHCI_CAN_VDD_300 0x02000000
	147	#define SDHCI_CAN_VDD_180 0x04000000
d129bceb PO	148
	149	/* 44-47 reserved for more caps */
	150
	151	#define SDHCI_MAX_CURRENT 0x48
	152
	153	/* 4C-4F reserved for more max current */
	154
	155	/* 50-FB reserved */
	156
	157	#define SDHCI_SLOT_INT_STATUS 0xFC
	158
	159	#define SDHCI_HOST_VERSION 0xFE
4a965505 PO	160	#define SDHCI_VENDOR_VER_MASK 0xFF00
	161	#define SDHCI_VENDOR_VER_SHIFT 8
	162	#define SDHCI_SPEC_VER_MASK 0x00FF
	163	#define SDHCI_SPEC_VER_SHIFT 0
d129bceb PO	164
	165	struct sdhci_chip;
	166
	167	struct sdhci_host {
	168	struct sdhci_chip *chip;
	169	struct mmc_host mmc; / MMC structure */
	170
2f730fec PO	171	#ifdef CONFIG_LEDS_CLASS
	172	struct led_classdev led; /* LED control */
	173	#endif
	174
d129bceb PO	175	spinlock_t lock; /* Mutex */
	176
	177	int flags; /* Host attributes */
c9fddbc4 PO	178	#define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */
c9fddbc4 PO	179	#define SDHCI_REQ_USE_DMA (1<<1) /* Use DMA for this req. */
d129bceb PO	180
d129bceb PO	181	unsigned int max_clk; /* Max possible freq (MHz) */
1c8cde92	182	unsigned int timeout_clk; /* Timeout freq (KHz) */
d129bceb PO	183
d129bceb PO	184	unsigned int clock; /* Current clock (MHz) */
146ad66e	185	unsigned short power; /* Current voltage */
d129bceb PO	186
	187	struct mmc_request mrq; / Current request */
	188	struct mmc_command cmd; / Current command */
	189	struct mmc_data data; / Current data request */
e538fbe8	190	int data_early:1; /* Data finished before cmd */
d129bceb PO	191
d129bceb PO	192	struct scatterlist cur_sg; / We're working on this */
d129bceb PO	193	int num_sg; /* Entries left */
	194	int offset; /* Offset into current sg */
	195	int remain; /* Bytes left in current */
	196
d129bceb PO	197	int irq; /* Device IRQ */
	198	int bar; /* PCI BAR index */
	199	unsigned long addr; /* Bus address */
	200	void __iomem * ioaddr; /* Mapped address */
	201
	202	struct tasklet_struct card_tasklet; /* Tasklet structures */
	203	struct tasklet_struct finish_tasklet;
	204
	205	struct timer_list timer; /* Timer for timeouts */
	206	};
	207
	208	struct sdhci_chip {
	209	struct pci_dev *pdev;
	210
df673b22 PO	211	unsigned long quirks;
df673b22 PO	212
d129bceb PO	213	int num_slots; /* Slots on controller */
	214	struct sdhci_host hosts[0]; / Pointers to hosts */
	215	};