[linux-2.6-block.git] / drivers / mmc / host / sdhci-pxav3.c

/*
 * Copyright (C) 2010 Marvell International Ltd.
 *		Zhangfei Gao <zhangfei.gao@marvell.com>
 *		Kevin Wang <dwang4@marvell.com>
 *		Mingwei Wang <mwwang@marvell.com>
 *		Philip Rakity <prakity@marvell.com>
 *		Mark Brown <markb@marvell.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/platform_data/pxa_sdhci.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/mbus.h>

#include "sdhci.h"
#include "sdhci-pltfm.h"

#define PXAV3_RPM_DELAY_MS     50

#define SD_CLOCK_BURST_SIZE_SETUP		0x10A
#define SDCLK_SEL	0x100
#define SDCLK_DELAY_SHIFT	9
#define SDCLK_DELAY_MASK	0x1f

#define SD_CFG_FIFO_PARAM       0x100
#define SDCFG_GEN_PAD_CLK_ON	(1<<6)
#define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
#define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24

#define SD_SPI_MODE          0x108
#define SD_CE_ATA_1          0x10C

#define SD_CE_ATA_2          0x10E
#define SDCE_MISC_INT		(1<<2)
#define SDCE_MISC_INT_EN	(1<<1)

struct sdhci_pxa {
	struct clk *clk_core;
	struct clk *clk_io;
	u8	power_mode;
	void __iomem *sdio3_conf_reg;
};

/*
 * These registers are relative to the second register region, for the
 * MBus bridge.
 */
#define SDHCI_WINDOW_CTRL(i)	(0x80 + ((i) << 3))
#define SDHCI_WINDOW_BASE(i)	(0x84 + ((i) << 3))
#define SDHCI_MAX_WIN_NUM	8

/*
 * Fields below belong to SDIO3 Configuration Register (third register
 * region for the Armada 38x flavor)
 */

#define SDIO3_CONF_CLK_INV	BIT(0)
#define SDIO3_CONF_SD_FB_CLK	BIT(2)

static int mv_conf_mbus_windows(struct platform_device *pdev,
				const struct mbus_dram_target_info *dram)
{
	int i;
	void __iomem *regs;
	struct resource *res;

	if (!dram) {
		dev_err(&pdev->dev, "no mbus dram info\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		dev_err(&pdev->dev, "cannot get mbus registers\n");
		return -EINVAL;
	}

	regs = ioremap(res->start, resource_size(res));
	if (!regs) {
		dev_err(&pdev->dev, "cannot map mbus registers\n");
		return -ENOMEM;
	}

	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
		writel(0, regs + SDHCI_WINDOW_CTRL(i));
		writel(0, regs + SDHCI_WINDOW_BASE(i));
	}

	for (i = 0; i < dram->num_cs; i++) {
		const struct mbus_dram_window *cs = dram->cs + i;

		/* Write size, attributes and target id to control register */
		writel(((cs->size - 1) & 0xffff0000) |
			(cs->mbus_attr << 8) |
			(dram->mbus_dram_target_id << 4) | 1,
			regs + SDHCI_WINDOW_CTRL(i));
		/* Write base address to base register */
		writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
	}

	iounmap(regs);

	return 0;
}

static int armada_38x_quirks(struct platform_device *pdev,
			     struct sdhci_host *host)
{
	struct device_node *np = pdev->dev.of_node;
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
	struct resource *res;

	host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;

	host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
					   "conf-sdio3");
	if (res) {
		pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(pxa->sdio3_conf_reg))
			return PTR_ERR(pxa->sdio3_conf_reg);
	} else {
		/*
		 * According to erratum 'FE-2946959' both SDR50 and DDR50
		 * modes require specific clock adjustments in SDIO3
		 * Configuration register, if the adjustment is not done,
		 * remove them from the capabilities.
		 */
		host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);

		dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
	}

	/*
	 * According to erratum 'ERR-7878951' Armada 38x SDHCI
	 * controller has different capabilities than the ones shown
	 * in its registers
	 */
	if (of_property_read_bool(np, "no-1-8-v")) {
		host->caps &= ~SDHCI_CAN_VDD_180;
		host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
	} else {
		host->caps &= ~SDHCI_CAN_VDD_330;
	}
	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);

	return 0;
}

static void pxav3_reset(struct sdhci_host *host, u8 mask)
{
	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;

	sdhci_reset(host, mask);

	if (mask == SDHCI_RESET_ALL) {
		/*
		 * tune timing of read data/command when crc error happen
		 * no performance impact
		 */
		if (pdata && 0 != pdata->clk_delay_cycles) {
			u16 tmp;

			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
				<< SDCLK_DELAY_SHIFT;
			tmp |= SDCLK_SEL;
			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
		}
	}
}

#define MAX_WAIT_COUNT 5
static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
	u16 tmp;
	int count;

	if (pxa->power_mode == MMC_POWER_UP
			&& power_mode == MMC_POWER_ON) {

		dev_dbg(mmc_dev(host->mmc),
				"%s: slot->power_mode = %d,"
				"ios->power_mode = %d\n",
				__func__,
				pxa->power_mode,
				power_mode);

		/* set we want notice of when 74 clocks are sent */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT_EN;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);

		/* start sending the 74 clocks */
		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
		tmp |= SDCFG_GEN_PAD_CLK_ON;
		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);

		/* slowest speed is about 100KHz or 10usec per clock */
		udelay(740);
		count = 0;

		while (count++ < MAX_WAIT_COUNT) {
			if ((readw(host->ioaddr + SD_CE_ATA_2)
						& SDCE_MISC_INT) == 0)
				break;
			udelay(10);
		}

		if (count == MAX_WAIT_COUNT)
			dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");

		/* clear the interrupt bit if posted */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);
	}
	pxa->power_mode = power_mode;
}

static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
	u16 ctrl_2;

	/*
	 * Set V18_EN -- UHS modes do not work without this.
	 * does not change signaling voltage
	 */
	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/* Select Bus Speed Mode for host */
	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	switch (uhs) {
	case MMC_TIMING_UHS_SDR12:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
		break;
	case MMC_TIMING_UHS_SDR25:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
		break;
	case MMC_TIMING_UHS_SDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_SDR104:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_MMC_DDR52:
	case MMC_TIMING_UHS_DDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
		break;
	}

	/*
	 * Update SDIO3 Configuration register according to erratum
	 * FE-2946959
	 */
	if (pxa->sdio3_conf_reg) {
		u8 reg_val  = readb(pxa->sdio3_conf_reg);

		if (uhs == MMC_TIMING_UHS_SDR50 ||
		    uhs == MMC_TIMING_UHS_DDR50) {
			reg_val &= ~SDIO3_CONF_CLK_INV;
			reg_val |= SDIO3_CONF_SD_FB_CLK;
		} else if (uhs == MMC_TIMING_MMC_HS) {
			reg_val &= ~SDIO3_CONF_CLK_INV;
			reg_val &= ~SDIO3_CONF_SD_FB_CLK;
		} else {
			reg_val |= SDIO3_CONF_CLK_INV;
			reg_val &= ~SDIO3_CONF_SD_FB_CLK;
		}
		writeb(reg_val, pxa->sdio3_conf_reg);
	}

	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	dev_dbg(mmc_dev(host->mmc),
		"%s uhs = %d, ctrl_2 = %04X\n",
		__func__, uhs, ctrl_2);
}

static void pxav3_set_power(struct sdhci_host *host, unsigned char mode,
			    unsigned short vdd)
{
	struct mmc_host *mmc = host->mmc;
	u8 pwr = host->pwr;

	sdhci_set_power(host, mode, vdd);

	if (host->pwr == pwr)
		return;

	if (host->pwr == 0)
		vdd = 0;

	if (!IS_ERR(mmc->supply.vmmc)) {
		spin_unlock_irq(&host->lock);
		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
		spin_lock_irq(&host->lock);
	}
}

static const struct sdhci_ops pxav3_sdhci_ops = {
	.set_clock = sdhci_set_clock,
	.set_power = pxav3_set_power,
	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
	.set_bus_width = sdhci_set_bus_width,
	.reset = pxav3_reset,
	.set_uhs_signaling = pxav3_set_uhs_signaling,
};

static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
		| SDHCI_QUIRK_32BIT_ADMA_SIZE
		| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops = &pxav3_sdhci_ops,
};

#ifdef CONFIG_OF
static const struct of_device_id sdhci_pxav3_of_match[] = {
	{
		.compatible = "mrvl,pxav3-mmc",
	},
	{
		.compatible = "marvell,armada-380-sdhci",
	},
	{},
};
MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);

static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	struct sdhci_pxa_platdata *pdata;
	struct device_node *np = dev->of_node;
	u32 clk_delay_cycles;

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
				  &clk_delay_cycles))
		pdata->clk_delay_cycles = clk_delay_cycles;

	return pdata;
}
#else
static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	return NULL;
}
#endif

static int sdhci_pxav3_probe(struct platform_device *pdev)
{
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	struct device *dev = &pdev->dev;
	struct device_node *np = pdev->dev.of_node;
	struct sdhci_host *host = NULL;
	struct sdhci_pxa *pxa = NULL;
	const struct of_device_id *match;
	int ret;

	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, sizeof(*pxa));
	if (IS_ERR(host))
		return PTR_ERR(host);

	pltfm_host = sdhci_priv(host);
	pxa = sdhci_pltfm_priv(pltfm_host);

	pxa->clk_io = devm_clk_get(dev, "io");
	if (IS_ERR(pxa->clk_io))
		pxa->clk_io = devm_clk_get(dev, NULL);
	if (IS_ERR(pxa->clk_io)) {
		dev_err(dev, "failed to get io clock\n");
		ret = PTR_ERR(pxa->clk_io);
		goto err_clk_get;
	}
	pltfm_host->clk = pxa->clk_io;
	clk_prepare_enable(pxa->clk_io);

	pxa->clk_core = devm_clk_get(dev, "core");
	if (!IS_ERR(pxa->clk_core))
		clk_prepare_enable(pxa->clk_core);

	/* enable 1/8V DDR capable */
	host->mmc->caps |= MMC_CAP_1_8V_DDR;

	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
		ret = armada_38x_quirks(pdev, host);
		if (ret < 0)
			goto err_mbus_win;
		ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
		if (ret < 0)
			goto err_mbus_win;
	}

	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
	if (match) {
		ret = mmc_of_parse(host->mmc);
		if (ret)
			goto err_of_parse;
		sdhci_get_of_property(pdev);
		pdata = pxav3_get_mmc_pdata(dev);
		pdev->dev.platform_data = pdata;
	} else if (pdata) {
		/* on-chip device */
		if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
			host->mmc->caps |= MMC_CAP_NONREMOVABLE;

		/* If slot design supports 8 bit data, indicate this to MMC. */
		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
			host->mmc->caps |= MMC_CAP_8_BIT_DATA;

		if (pdata->quirks)
			host->quirks |= pdata->quirks;
		if (pdata->quirks2)
			host->quirks2 |= pdata->quirks2;
		if (pdata->host_caps)
			host->mmc->caps |= pdata->host_caps;
		if (pdata->host_caps2)
			host->mmc->caps2 |= pdata->host_caps2;
		if (pdata->pm_caps)
			host->mmc->pm_caps |= pdata->pm_caps;

		if (gpio_is_valid(pdata->ext_cd_gpio)) {
			ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
						  0);
			if (ret) {
				dev_err(mmc_dev(host->mmc),
					"failed to allocate card detect gpio\n");
				goto err_cd_req;
			}
		}
	}

	pm_runtime_get_noresume(&pdev->dev);
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	pm_suspend_ignore_children(&pdev->dev, 1);

	ret = sdhci_add_host(host);
	if (ret) {
		dev_err(&pdev->dev, "failed to add host\n");
		goto err_add_host;
	}

	platform_set_drvdata(pdev, host);

	if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)
		device_init_wakeup(&pdev->dev, 1);

	pm_runtime_put_autosuspend(&pdev->dev);

	return 0;

err_add_host:
	pm_runtime_disable(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);
err_of_parse:
err_cd_req:
err_mbus_win:
	clk_disable_unprepare(pxa->clk_io);
	clk_disable_unprepare(pxa->clk_core);
err_clk_get:
	sdhci_pltfm_free(pdev);
	return ret;
}

static int sdhci_pxav3_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);

	pm_runtime_get_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);

	sdhci_remove_host(host, 1);

	clk_disable_unprepare(pxa->clk_io);
	clk_disable_unprepare(pxa->clk_core);

	sdhci_pltfm_free(pdev);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int sdhci_pxav3_suspend(struct device *dev)
{
	int ret;
	struct sdhci_host *host = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	ret = sdhci_suspend_host(host);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_put_autosuspend(dev);

	return ret;
}

static int sdhci_pxav3_resume(struct device *dev)
{
	int ret;
	struct sdhci_host *host = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	ret = sdhci_resume_host(host);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_put_autosuspend(dev);

	return ret;
}
#endif

#ifdef CONFIG_PM
static int sdhci_pxav3_runtime_suspend(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
	int ret;

	ret = sdhci_runtime_suspend_host(host);
	if (ret)
		return ret;

	clk_disable_unprepare(pxa->clk_io);
	if (!IS_ERR(pxa->clk_core))
		clk_disable_unprepare(pxa->clk_core);

	return 0;
}

static int sdhci_pxav3_runtime_resume(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);

	clk_prepare_enable(pxa->clk_io);
	if (!IS_ERR(pxa->clk_core))
		clk_prepare_enable(pxa->clk_core);

	return sdhci_runtime_resume_host(host);
}
#endif

#ifdef CONFIG_PM
static const struct dev_pm_ops sdhci_pxav3_pmops = {
	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
		sdhci_pxav3_runtime_resume, NULL)
};

#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)

#else
#define SDHCI_PXAV3_PMOPS NULL
#endif

static struct platform_driver sdhci_pxav3_driver = {
	.driver		= {
		.name	= "sdhci-pxav3",
		.of_match_table = of_match_ptr(sdhci_pxav3_of_match),
		.pm	= SDHCI_PXAV3_PMOPS,
	},
	.probe		= sdhci_pxav3_probe,
	.remove		= sdhci_pxav3_remove,
};

module_platform_driver(sdhci_pxav3_driver);

MODULE_DESCRIPTION("SDHCI driver for pxav3");
MODULE_AUTHOR("Marvell International Ltd.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a702c8ab ZG	1	/*
	2	* Copyright (C) 2010 Marvell International Ltd.
	3	* Zhangfei Gao <zhangfei.gao@marvell.com>
	4	* Kevin Wang <dwang4@marvell.com>
	5	* Mingwei Wang <mwwang@marvell.com>
	6	* Philip Rakity <prakity@marvell.com>
	7	* Mark Brown <markb@marvell.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19	#include <linux/err.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/clk.h>
	23	#include <linux/io.h>
	24	#include <linux/gpio.h>
	25	#include <linux/mmc/card.h>
	26	#include <linux/mmc/host.h>
8f63795c	27	#include <linux/mmc/slot-gpio.h>
bfed345e	28	#include <linux/platform_data/pxa_sdhci.h>
a702c8ab ZG	29	#include <linux/slab.h>
a702c8ab ZG	30	#include <linux/delay.h>
88b47679	31	#include <linux/module.h>
b650352d CB	32	#include <linux/of.h>
b650352d CB	33	#include <linux/of_device.h>
8f63795c	34	#include <linux/of_gpio.h>
bb691ae4 KL	35	#include <linux/pm.h>
bb691ae4 KL	36	#include <linux/pm_runtime.h>
5491ce3f	37	#include <linux/mbus.h>
b650352d	38
a702c8ab ZG	39	#include "sdhci.h"
	40	#include "sdhci-pltfm.h"
	41
bb691ae4 KL	42	#define PXAV3_RPM_DELAY_MS 50
bb691ae4 KL	43
a702c8ab ZG	44	#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
	45	#define SDCLK_SEL 0x100
	46	#define SDCLK_DELAY_SHIFT 9
	47	#define SDCLK_DELAY_MASK 0x1f
	48
	49	#define SD_CFG_FIFO_PARAM 0x100
	50	#define SDCFG_GEN_PAD_CLK_ON (1<<6)
	51	#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
	52	#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
	53
	54	#define SD_SPI_MODE 0x108
	55	#define SD_CE_ATA_1 0x10C
	56
	57	#define SD_CE_ATA_2 0x10E
	58	#define SDCE_MISC_INT (1<<2)
	59	#define SDCE_MISC_INT_EN (1<<1)
	60
cc9571e8	61	struct sdhci_pxa {
8afdc9cc	62	struct clk *clk_core;
8c96a7a3	63	struct clk *clk_io;
cc9571e8	64	u8 power_mode;
1140011e	65	void __iomem *sdio3_conf_reg;
cc9571e8 SH	66	};
cc9571e8 SH	67
5491ce3f MW	68	/*
	69	* These registers are relative to the second register region, for the
	70	* MBus bridge.
	71	*/
	72	#define SDHCI_WINDOW_CTRL(i) (0x80 + ((i) << 3))
	73	#define SDHCI_WINDOW_BASE(i) (0x84 + ((i) << 3))
	74	#define SDHCI_MAX_WIN_NUM 8
	75
1140011e MW	76	/*
	77	* Fields below belong to SDIO3 Configuration Register (third register
	78	* region for the Armada 38x flavor)
	79	*/
	80
	81	#define SDIO3_CONF_CLK_INV BIT(0)
	82	#define SDIO3_CONF_SD_FB_CLK BIT(2)
	83
5491ce3f MW	84	static int mv_conf_mbus_windows(struct platform_device *pdev,
	85	const struct mbus_dram_target_info *dram)
	86	{
	87	int i;
	88	void __iomem *regs;
	89	struct resource *res;
	90
	91	if (!dram) {
	92	dev_err(&pdev->dev, "no mbus dram info\n");
	93	return -EINVAL;
	94	}
	95
	96	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	97	if (!res) {
	98	dev_err(&pdev->dev, "cannot get mbus registers\n");
	99	return -EINVAL;
	100	}
	101
	102	regs = ioremap(res->start, resource_size(res));
	103	if (!regs) {
	104	dev_err(&pdev->dev, "cannot map mbus registers\n");
	105	return -ENOMEM;
	106	}
	107
	108	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
	109	writel(0, regs + SDHCI_WINDOW_CTRL(i));
	110	writel(0, regs + SDHCI_WINDOW_BASE(i));
	111	}
	112
	113	for (i = 0; i < dram->num_cs; i++) {
	114	const struct mbus_dram_window *cs = dram->cs + i;
	115
	116	/* Write size, attributes and target id to control register */
	117	writel(((cs->size - 1) & 0xffff0000) \|
	118	(cs->mbus_attr << 8) \|
	119	(dram->mbus_dram_target_id << 4) \| 1,
	120	regs + SDHCI_WINDOW_CTRL(i));
	121	/* Write base address to base register */
	122	writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
	123	}
	124
	125	iounmap(regs);
	126
	127	return 0;
	128	}
	129
a39128bc MW	130	static int armada_38x_quirks(struct platform_device *pdev,
a39128bc MW	131	struct sdhci_host *host)
d4b803c5	132	{
a39128bc	133	struct device_node *np = pdev->dev.of_node;
1140011e	134	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
f599da40	135	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
1140011e	136	struct resource *res;
a39128bc	137
5de76bfc	138	host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
d4b803c5	139	host->quirks \|= SDHCI_QUIRK_MISSING_CAPS;
0ca33b4a RK	140
	141	host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	142	host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
	143
1140011e MW	144	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	145	"conf-sdio3");
	146	if (res) {
	147	pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
	148	if (IS_ERR(pxa->sdio3_conf_reg))
	149	return PTR_ERR(pxa->sdio3_conf_reg);
	150	} else {
	151	/*
	152	* According to erratum 'FE-2946959' both SDR50 and DDR50
	153	* modes require specific clock adjustments in SDIO3
	154	* Configuration register, if the adjustment is not done,
	155	* remove them from the capabilities.
	156	*/
1140011e MW	157	host->caps1 &= ~(SDHCI_SUPPORT_SDR50 \| SDHCI_SUPPORT_DDR50);
	158
	159	dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
	160	}
a39128bc MW	161
	162	/*
	163	* According to erratum 'ERR-7878951' Armada 38x SDHCI
	164	* controller has different capabilities than the ones shown
	165	* in its registers
	166	*/
a39128bc MW	167	if (of_property_read_bool(np, "no-1-8-v")) {
	168	host->caps &= ~SDHCI_CAN_VDD_180;
	169	host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
	170	} else {
	171	host->caps &= ~SDHCI_CAN_VDD_330;
	172	}
	173	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 \| SDHCI_USE_SDR50_TUNING);
	174
d4b803c5 GC	175	return 0;
	176	}
	177
03231f9b	178	static void pxav3_reset(struct sdhci_host *host, u8 mask)
a702c8ab ZG	179	{
	180	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	181	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	182
03231f9b RK	183	sdhci_reset(host, mask);
03231f9b RK	184
a702c8ab ZG	185	if (mask == SDHCI_RESET_ALL) {
	186	/*
	187	* tune timing of read data/command when crc error happen
	188	* no performance impact
	189	*/
	190	if (pdata && 0 != pdata->clk_delay_cycles) {
	191	u16 tmp;
	192
	193	tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	194	tmp \|= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
	195	<< SDCLK_DELAY_SHIFT;
	196	tmp \|= SDCLK_SEL;
	197	writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	198	}
	199	}
	200	}
	201
	202	#define MAX_WAIT_COUNT 5
	203	static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
	204	{
	205	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
f599da40	206	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
a702c8ab ZG	207	u16 tmp;
	208	int count;
	209
	210	if (pxa->power_mode == MMC_POWER_UP
	211	&& power_mode == MMC_POWER_ON) {
	212
	213	dev_dbg(mmc_dev(host->mmc),
	214	"%s: slot->power_mode = %d,"
	215	"ios->power_mode = %d\n",
	216	__func__,
	217	pxa->power_mode,
	218	power_mode);
	219
	220	/* set we want notice of when 74 clocks are sent */
	221	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	222	tmp \|= SDCE_MISC_INT_EN;
	223	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	224
	225	/* start sending the 74 clocks */
	226	tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
	227	tmp \|= SDCFG_GEN_PAD_CLK_ON;
	228	writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
	229
	230	/* slowest speed is about 100KHz or 10usec per clock */
	231	udelay(740);
	232	count = 0;
	233
	234	while (count++ < MAX_WAIT_COUNT) {
	235	if ((readw(host->ioaddr + SD_CE_ATA_2)
	236	& SDCE_MISC_INT) == 0)
	237	break;
	238	udelay(10);
	239	}
	240
	241	if (count == MAX_WAIT_COUNT)
	242	dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
	243
	244	/* clear the interrupt bit if posted */
	245	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	246	tmp \|= SDCE_MISC_INT;
	247	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	248	}
	249	pxa->power_mode = power_mode;
	250	}
	251
13e64501	252	static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
a702c8ab	253	{
1140011e	254	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
f599da40	255	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
a702c8ab ZG	256	u16 ctrl_2;
	257
	258	/*
	259	* Set V18_EN -- UHS modes do not work without this.
	260	* does not change signaling voltage
	261	*/
	262	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	263
	264	/* Select Bus Speed Mode for host */
	265	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	266	switch (uhs) {
	267	case MMC_TIMING_UHS_SDR12:
	268	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;
	269	break;
	270	case MMC_TIMING_UHS_SDR25:
	271	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;
	272	break;
	273	case MMC_TIMING_UHS_SDR50:
	274	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50 \| SDHCI_CTRL_VDD_180;
	275	break;
	276	case MMC_TIMING_UHS_SDR104:
	277	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;
	278	break;
668e84b2	279	case MMC_TIMING_MMC_DDR52:
a702c8ab ZG	280	case MMC_TIMING_UHS_DDR50:
	281	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;
	282	break;
	283	}
	284
1140011e MW	285	/*
	286	* Update SDIO3 Configuration register according to erratum
	287	* FE-2946959
	288	*/
	289	if (pxa->sdio3_conf_reg) {
	290	u8 reg_val = readb(pxa->sdio3_conf_reg);
	291
	292	if (uhs == MMC_TIMING_UHS_SDR50 \|\|
	293	uhs == MMC_TIMING_UHS_DDR50) {
	294	reg_val &= ~SDIO3_CONF_CLK_INV;
	295	reg_val \|= SDIO3_CONF_SD_FB_CLK;
fa796414 NH	296	} else if (uhs == MMC_TIMING_MMC_HS) {
	297	reg_val &= ~SDIO3_CONF_CLK_INV;
	298	reg_val &= ~SDIO3_CONF_SD_FB_CLK;
1140011e MW	299	} else {
	300	reg_val \|= SDIO3_CONF_CLK_INV;
	301	reg_val &= ~SDIO3_CONF_SD_FB_CLK;
	302	}
	303	writeb(reg_val, pxa->sdio3_conf_reg);
	304	}
	305
a702c8ab ZG	306	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	307	dev_dbg(mmc_dev(host->mmc),
	308	"%s uhs = %d, ctrl_2 = %04X\n",
	309	__func__, uhs, ctrl_2);
a702c8ab ZG	310	}
a702c8ab ZG	311
1dceb041 AH	312	static void pxav3_set_power(struct sdhci_host *host, unsigned char mode,
	313	unsigned short vdd)
	314	{
	315	struct mmc_host *mmc = host->mmc;
	316	u8 pwr = host->pwr;
	317
	318	sdhci_set_power(host, mode, vdd);
	319
	320	if (host->pwr == pwr)
	321	return;
	322
	323	if (host->pwr == 0)
	324	vdd = 0;
	325
	326	if (!IS_ERR(mmc->supply.vmmc)) {
	327	spin_unlock_irq(&host->lock);
	328	mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
	329	spin_lock_irq(&host->lock);
	330	}
	331	}
	332
c915568d	333	static const struct sdhci_ops pxav3_sdhci_ops = {
1771059c	334	.set_clock = sdhci_set_clock,
1dceb041	335	.set_power = pxav3_set_power,
a702c8ab	336	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
d005d943	337	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
2317f56c	338	.set_bus_width = sdhci_set_bus_width,
03231f9b	339	.reset = pxav3_reset,
b3153765	340	.set_uhs_signaling = pxav3_set_uhs_signaling,
a702c8ab ZG	341	};
a702c8ab ZG	342
73b7afb9	343	static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
e065162a	344	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
73b7afb9 KL	345	\| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
	346	\| SDHCI_QUIRK_32BIT_ADMA_SIZE
	347	\| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	348	.ops = &pxav3_sdhci_ops,
	349	};
	350
b650352d CB	351	#ifdef CONFIG_OF
	352	static const struct of_device_id sdhci_pxav3_of_match[] = {
	353	{
	354	.compatible = "mrvl,pxav3-mmc",
	355	},
5491ce3f MW	356	{
	357	.compatible = "marvell,armada-380-sdhci",
	358	},
b650352d CB	359	{},
	360	};
	361	MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
	362
	363	static struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	364	{
	365	struct sdhci_pxa_platdata *pdata;
	366	struct device_node *np = dev->of_node;
b650352d CB	367	u32 clk_delay_cycles;
	368
	369	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	370	if (!pdata)
	371	return NULL;
	372
14460dba JZ	373	if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
14460dba JZ	374	&clk_delay_cycles))
b650352d CB	375	pdata->clk_delay_cycles = clk_delay_cycles;
	376
	377	return pdata;
	378	}
	379	#else
	380	static inline struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	381	{
	382	return NULL;
	383	}
	384	#endif
	385
c3be1efd	386	static int sdhci_pxav3_probe(struct platform_device *pdev)
a702c8ab ZG	387	{
	388	struct sdhci_pltfm_host *pltfm_host;
	389	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	390	struct device *dev = &pdev->dev;
5491ce3f	391	struct device_node *np = pdev->dev.of_node;
a702c8ab ZG	392	struct sdhci_host *host = NULL;
a702c8ab ZG	393	struct sdhci_pxa *pxa = NULL;
b650352d	394	const struct of_device_id *match;
a702c8ab	395	int ret;
a702c8ab	396
f599da40	397	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, sizeof(*pxa));
3df5b281	398	if (IS_ERR(host))
a702c8ab	399	return PTR_ERR(host);
5491ce3f	400
a702c8ab	401	pltfm_host = sdhci_priv(host);
f599da40	402	pxa = sdhci_pltfm_priv(pltfm_host);
a702c8ab	403
01ae1070 SH	404	pxa->clk_io = devm_clk_get(dev, "io");
	405	if (IS_ERR(pxa->clk_io))
	406	pxa->clk_io = devm_clk_get(dev, NULL);
8c96a7a3	407	if (IS_ERR(pxa->clk_io)) {
a702c8ab	408	dev_err(dev, "failed to get io clock\n");
8c96a7a3	409	ret = PTR_ERR(pxa->clk_io);
a702c8ab ZG	410	goto err_clk_get;
a702c8ab ZG	411	}
8c96a7a3 SH	412	pltfm_host->clk = pxa->clk_io;
8c96a7a3 SH	413	clk_prepare_enable(pxa->clk_io);
a702c8ab	414
8afdc9cc SH	415	pxa->clk_core = devm_clk_get(dev, "core");
	416	if (!IS_ERR(pxa->clk_core))
	417	clk_prepare_enable(pxa->clk_core);
	418
a39128bc MW	419	/* enable 1/8V DDR capable */
	420	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
	421
aa8165f9	422	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
a39128bc	423	ret = armada_38x_quirks(pdev, host);
d4b803c5	424	if (ret < 0)
2162d9f4	425	goto err_mbus_win;
aa8165f9 TP	426	ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
	427	if (ret < 0)
	428	goto err_mbus_win;
	429	}
	430
b650352d	431	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
943647f6	432	if (match) {
d2cf6071 SB	433	ret = mmc_of_parse(host->mmc);
	434	if (ret)
	435	goto err_of_parse;
943647f6	436	sdhci_get_of_property(pdev);
b650352d	437	pdata = pxav3_get_mmc_pdata(dev);
9cd76049	438	pdev->dev.platform_data = pdata;
943647f6	439	} else if (pdata) {
c844a46f KL	440	/* on-chip device */
c844a46f KL	441	if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
a702c8ab	442	host->mmc->caps \|= MMC_CAP_NONREMOVABLE;
a702c8ab ZG	443
	444	/* If slot design supports 8 bit data, indicate this to MMC. */
	445	if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
	446	host->mmc->caps \|= MMC_CAP_8_BIT_DATA;
	447
	448	if (pdata->quirks)
	449	host->quirks \|= pdata->quirks;
7c52d7bb KL	450	if (pdata->quirks2)
7c52d7bb KL	451	host->quirks2 \|= pdata->quirks2;
a702c8ab ZG	452	if (pdata->host_caps)
a702c8ab ZG	453	host->mmc->caps \|= pdata->host_caps;
8f63795c CB	454	if (pdata->host_caps2)
8f63795c CB	455	host->mmc->caps2 \|= pdata->host_caps2;
a702c8ab ZG	456	if (pdata->pm_caps)
a702c8ab ZG	457	host->mmc->pm_caps \|= pdata->pm_caps;
8f63795c CB	458
8f63795c CB	459	if (gpio_is_valid(pdata->ext_cd_gpio)) {
214fc309 LP	460	ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
214fc309 LP	461	0);
8f63795c CB	462	if (ret) {
	463	dev_err(mmc_dev(host->mmc),
	464	"failed to allocate card detect gpio\n");
	465	goto err_cd_req;
	466	}
	467	}
a702c8ab ZG	468	}
a702c8ab ZG	469
62cf983a JZ	470	pm_runtime_get_noresume(&pdev->dev);
62cf983a JZ	471	pm_runtime_set_active(&pdev->dev);
bb691ae4 KL	472	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
bb691ae4 KL	473	pm_runtime_use_autosuspend(&pdev->dev);
62cf983a	474	pm_runtime_enable(&pdev->dev);
bb691ae4	475	pm_suspend_ignore_children(&pdev->dev, 1);
bb691ae4	476
a702c8ab ZG	477	ret = sdhci_add_host(host);
	478	if (ret) {
	479	dev_err(&pdev->dev, "failed to add host\n");
	480	goto err_add_host;
	481	}
	482
	483	platform_set_drvdata(pdev, host);
	484
83dc9fec	485	if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)
740b7a44	486	device_init_wakeup(&pdev->dev, 1);
740b7a44	487
bb691ae4 KL	488	pm_runtime_put_autosuspend(&pdev->dev);
bb691ae4 KL	489
a702c8ab ZG	490	return 0;
	491
	492	err_add_host:
0dcaa249	493	pm_runtime_disable(&pdev->dev);
62cf983a	494	pm_runtime_put_noidle(&pdev->dev);
87d2163d XW	495	err_of_parse:
87d2163d XW	496	err_cd_req:
aa8165f9	497	err_mbus_win:
8c96a7a3	498	clk_disable_unprepare(pxa->clk_io);
c25d9e1b	499	clk_disable_unprepare(pxa->clk_core);
a702c8ab ZG	500	err_clk_get:
a702c8ab ZG	501	sdhci_pltfm_free(pdev);
a702c8ab ZG	502	return ret;
	503	}
	504
6e0ee714	505	static int sdhci_pxav3_remove(struct platform_device *pdev)
a702c8ab ZG	506	{
	507	struct sdhci_host *host = platform_get_drvdata(pdev);
	508	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
f599da40	509	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
a702c8ab	510
bb691ae4	511	pm_runtime_get_sync(&pdev->dev);
bb691ae4	512	pm_runtime_disable(&pdev->dev);
20f1f2d7 JZ	513	pm_runtime_put_noidle(&pdev->dev);
	514
	515	sdhci_remove_host(host, 1);
a702c8ab	516
8c96a7a3	517	clk_disable_unprepare(pxa->clk_io);
c25d9e1b	518	clk_disable_unprepare(pxa->clk_core);
8f63795c	519
a702c8ab	520	sdhci_pltfm_free(pdev);
a702c8ab	521
a702c8ab ZG	522	return 0;
	523	}
	524
bb691ae4 KL	525	#ifdef CONFIG_PM_SLEEP
	526	static int sdhci_pxav3_suspend(struct device *dev)
	527	{
	528	int ret;
	529	struct sdhci_host *host = dev_get_drvdata(dev);
	530
	531	pm_runtime_get_sync(dev);
	532	ret = sdhci_suspend_host(host);
	533	pm_runtime_mark_last_busy(dev);
	534	pm_runtime_put_autosuspend(dev);
	535
	536	return ret;
	537	}
	538
	539	static int sdhci_pxav3_resume(struct device *dev)
	540	{
	541	int ret;
	542	struct sdhci_host *host = dev_get_drvdata(dev);
	543
	544	pm_runtime_get_sync(dev);
	545	ret = sdhci_resume_host(host);
	546	pm_runtime_mark_last_busy(dev);
	547	pm_runtime_put_autosuspend(dev);
	548
	549	return ret;
	550	}
	551	#endif
	552
162d6f98	553	#ifdef CONFIG_PM
bb691ae4 KL	554	static int sdhci_pxav3_runtime_suspend(struct device *dev)
	555	{
	556	struct sdhci_host *host = dev_get_drvdata(dev);
	557	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
f599da40	558	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
3bb10f60	559	int ret;
bb691ae4	560
3bb10f60 JZ	561	ret = sdhci_runtime_suspend_host(host);
	562	if (ret)
	563	return ret;
bb691ae4	564
8c96a7a3	565	clk_disable_unprepare(pxa->clk_io);
8afdc9cc SH	566	if (!IS_ERR(pxa->clk_core))
8afdc9cc SH	567	clk_disable_unprepare(pxa->clk_core);
bb691ae4 KL	568
	569	return 0;
	570	}
	571
	572	static int sdhci_pxav3_runtime_resume(struct device *dev)
	573	{
	574	struct sdhci_host *host = dev_get_drvdata(dev);
	575	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
f599da40	576	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
bb691ae4	577
8c96a7a3	578	clk_prepare_enable(pxa->clk_io);
8afdc9cc SH	579	if (!IS_ERR(pxa->clk_core))
8afdc9cc SH	580	clk_prepare_enable(pxa->clk_core);
bb691ae4	581
3bb10f60	582	return sdhci_runtime_resume_host(host);
bb691ae4 KL	583	}
	584	#endif
	585
	586	#ifdef CONFIG_PM
	587	static const struct dev_pm_ops sdhci_pxav3_pmops = {
	588	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
	589	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
	590	sdhci_pxav3_runtime_resume, NULL)
	591	};
	592
	593	#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
	594
	595	#else
	596	#define SDHCI_PXAV3_PMOPS NULL
	597	#endif
	598
a702c8ab ZG	599	static struct platform_driver sdhci_pxav3_driver = {
	600	.driver = {
	601	.name = "sdhci-pxav3",
59d22309	602	.of_match_table = of_match_ptr(sdhci_pxav3_of_match),
bb691ae4	603	.pm = SDHCI_PXAV3_PMOPS,
a702c8ab ZG	604	},
a702c8ab ZG	605	.probe = sdhci_pxav3_probe,
0433c143	606	.remove = sdhci_pxav3_remove,
a702c8ab	607	};
a702c8ab	608
d1f81a64	609	module_platform_driver(sdhci_pxav3_driver);
a702c8ab ZG	610
	611	MODULE_DESCRIPTION("SDHCI driver for pxav3");
	612	MODULE_AUTHOR("Marvell International Ltd.");
	613	MODULE_LICENSE("GPL v2");
	614