Commit | Line | Data |
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95f25efe WS |
1 | /* |
2 | * Freescale eSDHC i.MX controller driver for the platform bus. | |
3 | * | |
4 | * derived from the OF-version. | |
5 | * | |
6 | * Copyright (c) 2010 Pengutronix e.K. | |
035ff831 | 7 | * Author: Wolfram Sang <kernel@pengutronix.de> |
95f25efe WS |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/clk.h> | |
0c6d49ce | 18 | #include <linux/gpio.h> |
66506f76 | 19 | #include <linux/module.h> |
e149860d | 20 | #include <linux/slab.h> |
95f25efe | 21 | #include <linux/mmc/host.h> |
58ac8177 RZ |
22 | #include <linux/mmc/mmc.h> |
23 | #include <linux/mmc/sdio.h> | |
fbe5fdd1 | 24 | #include <linux/mmc/slot-gpio.h> |
abfafc2d SG |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/of_gpio.h> | |
e62d8b8f | 28 | #include <linux/pinctrl/consumer.h> |
82906b13 | 29 | #include <linux/platform_data/mmc-esdhc-imx.h> |
89d7e5c1 | 30 | #include <linux/pm_runtime.h> |
95f25efe WS |
31 | #include "sdhci-pltfm.h" |
32 | #include "sdhci-esdhc.h" | |
33 | ||
60bf6396 | 34 | #define ESDHC_CTRL_D3CD 0x08 |
58ac8177 | 35 | /* VENDOR SPEC register */ |
60bf6396 SG |
36 | #define ESDHC_VENDOR_SPEC 0xc0 |
37 | #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) | |
0322191e | 38 | #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) |
fed2f6e2 | 39 | #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) |
60bf6396 SG |
40 | #define ESDHC_WTMK_LVL 0x44 |
41 | #define ESDHC_MIX_CTRL 0x48 | |
de5bdbff | 42 | #define ESDHC_MIX_CTRL_DDREN (1 << 3) |
2a15f981 | 43 | #define ESDHC_MIX_CTRL_AC23EN (1 << 7) |
0322191e DA |
44 | #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) |
45 | #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) | |
46 | #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) | |
2a15f981 SG |
47 | /* Bits 3 and 6 are not SDHCI standard definitions */ |
48 | #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 | |
d131a71c DA |
49 | /* Tuning bits */ |
50 | #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 | |
58ac8177 | 51 | |
602519b2 DA |
52 | /* dll control register */ |
53 | #define ESDHC_DLL_CTRL 0x60 | |
54 | #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 | |
55 | #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 | |
56 | ||
0322191e DA |
57 | /* tune control register */ |
58 | #define ESDHC_TUNE_CTRL_STATUS 0x68 | |
59 | #define ESDHC_TUNE_CTRL_STEP 1 | |
60 | #define ESDHC_TUNE_CTRL_MIN 0 | |
61 | #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) | |
62 | ||
6e9fd28e DA |
63 | #define ESDHC_TUNING_CTRL 0xcc |
64 | #define ESDHC_STD_TUNING_EN (1 << 24) | |
65 | /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ | |
66 | #define ESDHC_TUNING_START_TAP 0x1 | |
67 | ||
ad93220d DA |
68 | /* pinctrl state */ |
69 | #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" | |
70 | #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" | |
71 | ||
af51079e SH |
72 | /* |
73 | * Our interpretation of the SDHCI_HOST_CONTROL register | |
74 | */ | |
75 | #define ESDHC_CTRL_4BITBUS (0x1 << 1) | |
76 | #define ESDHC_CTRL_8BITBUS (0x2 << 1) | |
77 | #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) | |
78 | ||
97e4ba6a RZ |
79 | /* |
80 | * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: | |
81 | * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, | |
82 | * but bit28 is used as the INT DMA ERR in fsl eSDHC design. | |
83 | * Define this macro DMA error INT for fsl eSDHC | |
84 | */ | |
60bf6396 | 85 | #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) |
97e4ba6a | 86 | |
58ac8177 RZ |
87 | /* |
88 | * The CMDTYPE of the CMD register (offset 0xE) should be set to | |
89 | * "11" when the STOP CMD12 is issued on imx53 to abort one | |
90 | * open ended multi-blk IO. Otherwise the TC INT wouldn't | |
91 | * be generated. | |
92 | * In exact block transfer, the controller doesn't complete the | |
93 | * operations automatically as required at the end of the | |
94 | * transfer and remains on hold if the abort command is not sent. | |
95 | * As a result, the TC flag is not asserted and SW received timeout | |
96 | * exeception. Bit1 of Vendor Spec registor is used to fix it. | |
97 | */ | |
31fbb301 SG |
98 | #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) |
99 | /* | |
100 | * The flag enables the workaround for ESDHC errata ENGcm07207 which | |
101 | * affects i.MX25 and i.MX35. | |
102 | */ | |
103 | #define ESDHC_FLAG_ENGCM07207 BIT(2) | |
9d61c009 SG |
104 | /* |
105 | * The flag tells that the ESDHC controller is an USDHC block that is | |
106 | * integrated on the i.MX6 series. | |
107 | */ | |
108 | #define ESDHC_FLAG_USDHC BIT(3) | |
6e9fd28e DA |
109 | /* The IP supports manual tuning process */ |
110 | #define ESDHC_FLAG_MAN_TUNING BIT(4) | |
111 | /* The IP supports standard tuning process */ | |
112 | #define ESDHC_FLAG_STD_TUNING BIT(5) | |
113 | /* The IP has SDHCI_CAPABILITIES_1 register */ | |
114 | #define ESDHC_FLAG_HAVE_CAP1 BIT(6) | |
18094430 DA |
115 | /* |
116 | * The IP has errata ERR004536 | |
117 | * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, | |
118 | * when reading data from the card | |
119 | */ | |
120 | #define ESDHC_FLAG_ERR004536 BIT(7) | |
4245afff DA |
121 | /* The IP supports HS200 mode */ |
122 | #define ESDHC_FLAG_HS200 BIT(8) | |
e149860d | 123 | |
f47c4bbf SG |
124 | struct esdhc_soc_data { |
125 | u32 flags; | |
126 | }; | |
127 | ||
128 | static struct esdhc_soc_data esdhc_imx25_data = { | |
129 | .flags = ESDHC_FLAG_ENGCM07207, | |
130 | }; | |
131 | ||
132 | static struct esdhc_soc_data esdhc_imx35_data = { | |
133 | .flags = ESDHC_FLAG_ENGCM07207, | |
134 | }; | |
135 | ||
136 | static struct esdhc_soc_data esdhc_imx51_data = { | |
137 | .flags = 0, | |
138 | }; | |
139 | ||
140 | static struct esdhc_soc_data esdhc_imx53_data = { | |
141 | .flags = ESDHC_FLAG_MULTIBLK_NO_INT, | |
142 | }; | |
143 | ||
144 | static struct esdhc_soc_data usdhc_imx6q_data = { | |
6e9fd28e DA |
145 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, |
146 | }; | |
147 | ||
148 | static struct esdhc_soc_data usdhc_imx6sl_data = { | |
149 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | |
4245afff DA |
150 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 |
151 | | ESDHC_FLAG_HS200, | |
57ed3314 SG |
152 | }; |
153 | ||
913d4951 DA |
154 | static struct esdhc_soc_data usdhc_imx6sx_data = { |
155 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | |
4245afff | 156 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, |
913d4951 DA |
157 | }; |
158 | ||
e149860d | 159 | struct pltfm_imx_data { |
e149860d | 160 | u32 scratchpad; |
e62d8b8f | 161 | struct pinctrl *pinctrl; |
ad93220d DA |
162 | struct pinctrl_state *pins_default; |
163 | struct pinctrl_state *pins_100mhz; | |
164 | struct pinctrl_state *pins_200mhz; | |
f47c4bbf | 165 | const struct esdhc_soc_data *socdata; |
842afc02 | 166 | struct esdhc_platform_data boarddata; |
52dac615 SH |
167 | struct clk *clk_ipg; |
168 | struct clk *clk_ahb; | |
169 | struct clk *clk_per; | |
361b8482 LS |
170 | enum { |
171 | NO_CMD_PENDING, /* no multiblock command pending*/ | |
172 | MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ | |
173 | WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ | |
174 | } multiblock_status; | |
de5bdbff | 175 | u32 is_ddr; |
e149860d RZ |
176 | }; |
177 | ||
f8cbf461 | 178 | static const struct platform_device_id imx_esdhc_devtype[] = { |
57ed3314 SG |
179 | { |
180 | .name = "sdhci-esdhc-imx25", | |
f47c4bbf | 181 | .driver_data = (kernel_ulong_t) &esdhc_imx25_data, |
57ed3314 SG |
182 | }, { |
183 | .name = "sdhci-esdhc-imx35", | |
f47c4bbf | 184 | .driver_data = (kernel_ulong_t) &esdhc_imx35_data, |
57ed3314 SG |
185 | }, { |
186 | .name = "sdhci-esdhc-imx51", | |
f47c4bbf | 187 | .driver_data = (kernel_ulong_t) &esdhc_imx51_data, |
57ed3314 SG |
188 | }, { |
189 | /* sentinel */ | |
190 | } | |
191 | }; | |
192 | MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); | |
193 | ||
abfafc2d | 194 | static const struct of_device_id imx_esdhc_dt_ids[] = { |
f47c4bbf SG |
195 | { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, |
196 | { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, | |
197 | { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, | |
198 | { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, | |
913d4951 | 199 | { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, |
6e9fd28e | 200 | { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, |
f47c4bbf | 201 | { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, |
abfafc2d SG |
202 | { /* sentinel */ } |
203 | }; | |
204 | MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); | |
205 | ||
57ed3314 SG |
206 | static inline int is_imx25_esdhc(struct pltfm_imx_data *data) |
207 | { | |
f47c4bbf | 208 | return data->socdata == &esdhc_imx25_data; |
57ed3314 SG |
209 | } |
210 | ||
211 | static inline int is_imx53_esdhc(struct pltfm_imx_data *data) | |
212 | { | |
f47c4bbf | 213 | return data->socdata == &esdhc_imx53_data; |
57ed3314 SG |
214 | } |
215 | ||
95a2482a SG |
216 | static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) |
217 | { | |
f47c4bbf | 218 | return data->socdata == &usdhc_imx6q_data; |
95a2482a SG |
219 | } |
220 | ||
9d61c009 SG |
221 | static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) |
222 | { | |
f47c4bbf | 223 | return !!(data->socdata->flags & ESDHC_FLAG_USDHC); |
9d61c009 SG |
224 | } |
225 | ||
95f25efe WS |
226 | static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) |
227 | { | |
228 | void __iomem *base = host->ioaddr + (reg & ~0x3); | |
229 | u32 shift = (reg & 0x3) * 8; | |
230 | ||
231 | writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); | |
232 | } | |
233 | ||
7e29c306 WS |
234 | static u32 esdhc_readl_le(struct sdhci_host *host, int reg) |
235 | { | |
361b8482 LS |
236 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
237 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
7e29c306 WS |
238 | u32 val = readl(host->ioaddr + reg); |
239 | ||
0322191e DA |
240 | if (unlikely(reg == SDHCI_PRESENT_STATE)) { |
241 | u32 fsl_prss = val; | |
242 | /* save the least 20 bits */ | |
243 | val = fsl_prss & 0x000FFFFF; | |
244 | /* move dat[0-3] bits */ | |
245 | val |= (fsl_prss & 0x0F000000) >> 4; | |
246 | /* move cmd line bit */ | |
247 | val |= (fsl_prss & 0x00800000) << 1; | |
248 | } | |
249 | ||
97e4ba6a | 250 | if (unlikely(reg == SDHCI_CAPABILITIES)) { |
6b4fb671 DA |
251 | /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ |
252 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) | |
253 | val &= 0xffff0000; | |
254 | ||
97e4ba6a RZ |
255 | /* In FSL esdhc IC module, only bit20 is used to indicate the |
256 | * ADMA2 capability of esdhc, but this bit is messed up on | |
257 | * some SOCs (e.g. on MX25, MX35 this bit is set, but they | |
258 | * don't actually support ADMA2). So set the BROKEN_ADMA | |
259 | * uirk on MX25/35 platforms. | |
260 | */ | |
261 | ||
262 | if (val & SDHCI_CAN_DO_ADMA1) { | |
263 | val &= ~SDHCI_CAN_DO_ADMA1; | |
264 | val |= SDHCI_CAN_DO_ADMA2; | |
265 | } | |
266 | } | |
267 | ||
6e9fd28e DA |
268 | if (unlikely(reg == SDHCI_CAPABILITIES_1)) { |
269 | if (esdhc_is_usdhc(imx_data)) { | |
270 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) | |
271 | val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; | |
272 | else | |
273 | /* imx6q/dl does not have cap_1 register, fake one */ | |
274 | val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 | |
888824bb DA |
275 | | SDHCI_SUPPORT_SDR50 |
276 | | SDHCI_USE_SDR50_TUNING; | |
6e9fd28e DA |
277 | } |
278 | } | |
0322191e | 279 | |
9d61c009 | 280 | if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { |
0322191e DA |
281 | val = 0; |
282 | val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; | |
283 | val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; | |
284 | val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; | |
285 | } | |
286 | ||
97e4ba6a | 287 | if (unlikely(reg == SDHCI_INT_STATUS)) { |
60bf6396 SG |
288 | if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { |
289 | val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; | |
97e4ba6a RZ |
290 | val |= SDHCI_INT_ADMA_ERROR; |
291 | } | |
361b8482 LS |
292 | |
293 | /* | |
294 | * mask off the interrupt we get in response to the manually | |
295 | * sent CMD12 | |
296 | */ | |
297 | if ((imx_data->multiblock_status == WAIT_FOR_INT) && | |
298 | ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { | |
299 | val &= ~SDHCI_INT_RESPONSE; | |
300 | writel(SDHCI_INT_RESPONSE, host->ioaddr + | |
301 | SDHCI_INT_STATUS); | |
302 | imx_data->multiblock_status = NO_CMD_PENDING; | |
303 | } | |
97e4ba6a RZ |
304 | } |
305 | ||
7e29c306 WS |
306 | return val; |
307 | } | |
308 | ||
309 | static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) | |
310 | { | |
e149860d RZ |
311 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
312 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
0d58864b TL |
313 | u32 data; |
314 | ||
315 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { | |
b7321042 | 316 | if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { |
0d58864b TL |
317 | /* |
318 | * Clear and then set D3CD bit to avoid missing the | |
319 | * card interrupt. This is a eSDHC controller problem | |
320 | * so we need to apply the following workaround: clear | |
321 | * and set D3CD bit will make eSDHC re-sample the card | |
322 | * interrupt. In case a card interrupt was lost, | |
323 | * re-sample it by the following steps. | |
324 | */ | |
325 | data = readl(host->ioaddr + SDHCI_HOST_CONTROL); | |
60bf6396 | 326 | data &= ~ESDHC_CTRL_D3CD; |
0d58864b | 327 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
60bf6396 | 328 | data |= ESDHC_CTRL_D3CD; |
0d58864b TL |
329 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
330 | } | |
915be485 DA |
331 | |
332 | if (val & SDHCI_INT_ADMA_ERROR) { | |
333 | val &= ~SDHCI_INT_ADMA_ERROR; | |
334 | val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; | |
335 | } | |
0d58864b | 336 | } |
7e29c306 | 337 | |
f47c4bbf | 338 | if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
58ac8177 RZ |
339 | && (reg == SDHCI_INT_STATUS) |
340 | && (val & SDHCI_INT_DATA_END))) { | |
341 | u32 v; | |
60bf6396 SG |
342 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
343 | v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
344 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
361b8482 LS |
345 | |
346 | if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) | |
347 | { | |
348 | /* send a manual CMD12 with RESPTYP=none */ | |
349 | data = MMC_STOP_TRANSMISSION << 24 | | |
350 | SDHCI_CMD_ABORTCMD << 16; | |
351 | writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); | |
352 | imx_data->multiblock_status = WAIT_FOR_INT; | |
353 | } | |
58ac8177 RZ |
354 | } |
355 | ||
7e29c306 WS |
356 | writel(val, host->ioaddr + reg); |
357 | } | |
358 | ||
95f25efe WS |
359 | static u16 esdhc_readw_le(struct sdhci_host *host, int reg) |
360 | { | |
ef4d0888 SG |
361 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
362 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
0322191e DA |
363 | u16 ret = 0; |
364 | u32 val; | |
ef4d0888 | 365 | |
95a2482a | 366 | if (unlikely(reg == SDHCI_HOST_VERSION)) { |
ef4d0888 | 367 | reg ^= 2; |
9d61c009 | 368 | if (esdhc_is_usdhc(imx_data)) { |
ef4d0888 SG |
369 | /* |
370 | * The usdhc register returns a wrong host version. | |
371 | * Correct it here. | |
372 | */ | |
373 | return SDHCI_SPEC_300; | |
374 | } | |
95a2482a | 375 | } |
95f25efe | 376 | |
0322191e DA |
377 | if (unlikely(reg == SDHCI_HOST_CONTROL2)) { |
378 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
379 | if (val & ESDHC_VENDOR_SPEC_VSELECT) | |
380 | ret |= SDHCI_CTRL_VDD_180; | |
381 | ||
9d61c009 | 382 | if (esdhc_is_usdhc(imx_data)) { |
6e9fd28e DA |
383 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
384 | val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
385 | else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) | |
386 | /* the std tuning bits is in ACMD12_ERR for imx6sl */ | |
387 | val = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
0322191e DA |
388 | } |
389 | ||
6e9fd28e DA |
390 | if (val & ESDHC_MIX_CTRL_EXE_TUNE) |
391 | ret |= SDHCI_CTRL_EXEC_TUNING; | |
392 | if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) | |
393 | ret |= SDHCI_CTRL_TUNED_CLK; | |
394 | ||
0322191e DA |
395 | ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
396 | ||
397 | return ret; | |
398 | } | |
399 | ||
7dd109ef DA |
400 | if (unlikely(reg == SDHCI_TRANSFER_MODE)) { |
401 | if (esdhc_is_usdhc(imx_data)) { | |
402 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
403 | ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; | |
404 | /* Swap AC23 bit */ | |
405 | if (m & ESDHC_MIX_CTRL_AC23EN) { | |
406 | ret &= ~ESDHC_MIX_CTRL_AC23EN; | |
407 | ret |= SDHCI_TRNS_AUTO_CMD23; | |
408 | } | |
409 | } else { | |
410 | ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); | |
411 | } | |
412 | ||
413 | return ret; | |
414 | } | |
415 | ||
95f25efe WS |
416 | return readw(host->ioaddr + reg); |
417 | } | |
418 | ||
419 | static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) | |
420 | { | |
421 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
e149860d | 422 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
0322191e | 423 | u32 new_val = 0; |
95f25efe WS |
424 | |
425 | switch (reg) { | |
0322191e DA |
426 | case SDHCI_CLOCK_CONTROL: |
427 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
428 | if (val & SDHCI_CLOCK_CARD_EN) | |
429 | new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; | |
430 | else | |
431 | new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; | |
eeed7026 | 432 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); |
0322191e DA |
433 | return; |
434 | case SDHCI_HOST_CONTROL2: | |
435 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
436 | if (val & SDHCI_CTRL_VDD_180) | |
437 | new_val |= ESDHC_VENDOR_SPEC_VSELECT; | |
438 | else | |
439 | new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; | |
440 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); | |
6e9fd28e DA |
441 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { |
442 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
443 | if (val & SDHCI_CTRL_TUNED_CLK) | |
444 | new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; | |
445 | else | |
446 | new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; | |
447 | writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); | |
448 | } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { | |
449 | u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
450 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
8b2bb0ad DA |
451 | if (val & SDHCI_CTRL_TUNED_CLK) { |
452 | v |= ESDHC_MIX_CTRL_SMPCLK_SEL; | |
453 | } else { | |
454 | v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; | |
455 | m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; | |
456 | } | |
457 | ||
6e9fd28e | 458 | if (val & SDHCI_CTRL_EXEC_TUNING) { |
6e9fd28e DA |
459 | v |= ESDHC_MIX_CTRL_EXE_TUNE; |
460 | m |= ESDHC_MIX_CTRL_FBCLK_SEL; | |
461 | } else { | |
6e9fd28e | 462 | v &= ~ESDHC_MIX_CTRL_EXE_TUNE; |
6e9fd28e DA |
463 | } |
464 | ||
6e9fd28e DA |
465 | writel(v, host->ioaddr + SDHCI_ACMD12_ERR); |
466 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); | |
467 | } | |
0322191e | 468 | return; |
95f25efe | 469 | case SDHCI_TRANSFER_MODE: |
f47c4bbf | 470 | if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
58ac8177 RZ |
471 | && (host->cmd->opcode == SD_IO_RW_EXTENDED) |
472 | && (host->cmd->data->blocks > 1) | |
473 | && (host->cmd->data->flags & MMC_DATA_READ)) { | |
474 | u32 v; | |
60bf6396 SG |
475 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
476 | v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
477 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
58ac8177 | 478 | } |
69f54698 | 479 | |
9d61c009 | 480 | if (esdhc_is_usdhc(imx_data)) { |
69f54698 | 481 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
2a15f981 SG |
482 | /* Swap AC23 bit */ |
483 | if (val & SDHCI_TRNS_AUTO_CMD23) { | |
484 | val &= ~SDHCI_TRNS_AUTO_CMD23; | |
485 | val |= ESDHC_MIX_CTRL_AC23EN; | |
486 | } | |
487 | m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); | |
69f54698 SG |
488 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
489 | } else { | |
490 | /* | |
491 | * Postpone this write, we must do it together with a | |
492 | * command write that is down below. | |
493 | */ | |
494 | imx_data->scratchpad = val; | |
495 | } | |
95f25efe WS |
496 | return; |
497 | case SDHCI_COMMAND: | |
361b8482 | 498 | if (host->cmd->opcode == MMC_STOP_TRANSMISSION) |
58ac8177 | 499 | val |= SDHCI_CMD_ABORTCMD; |
95a2482a | 500 | |
361b8482 | 501 | if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && |
f47c4bbf | 502 | (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) |
361b8482 LS |
503 | imx_data->multiblock_status = MULTIBLK_IN_PROCESS; |
504 | ||
9d61c009 | 505 | if (esdhc_is_usdhc(imx_data)) |
95a2482a SG |
506 | writel(val << 16, |
507 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
69f54698 | 508 | else |
95a2482a SG |
509 | writel(val << 16 | imx_data->scratchpad, |
510 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
95f25efe WS |
511 | return; |
512 | case SDHCI_BLOCK_SIZE: | |
513 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); | |
514 | break; | |
515 | } | |
516 | esdhc_clrset_le(host, 0xffff, val, reg); | |
517 | } | |
518 | ||
519 | static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) | |
520 | { | |
9a0985b7 WC |
521 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
522 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
95f25efe | 523 | u32 new_val; |
af51079e | 524 | u32 mask; |
95f25efe WS |
525 | |
526 | switch (reg) { | |
527 | case SDHCI_POWER_CONTROL: | |
528 | /* | |
529 | * FSL put some DMA bits here | |
530 | * If your board has a regulator, code should be here | |
531 | */ | |
532 | return; | |
533 | case SDHCI_HOST_CONTROL: | |
6b40d182 | 534 | /* FSL messed up here, so we need to manually compose it. */ |
af51079e | 535 | new_val = val & SDHCI_CTRL_LED; |
7122bbb0 | 536 | /* ensure the endianness */ |
95f25efe | 537 | new_val |= ESDHC_HOST_CONTROL_LE; |
9a0985b7 WC |
538 | /* bits 8&9 are reserved on mx25 */ |
539 | if (!is_imx25_esdhc(imx_data)) { | |
540 | /* DMA mode bits are shifted */ | |
541 | new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; | |
542 | } | |
95f25efe | 543 | |
af51079e SH |
544 | /* |
545 | * Do not touch buswidth bits here. This is done in | |
546 | * esdhc_pltfm_bus_width. | |
f6825748 MF |
547 | * Do not touch the D3CD bit either which is used for the |
548 | * SDIO interrupt errata workaround. | |
af51079e | 549 | */ |
f6825748 | 550 | mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); |
af51079e SH |
551 | |
552 | esdhc_clrset_le(host, mask, new_val, reg); | |
95f25efe WS |
553 | return; |
554 | } | |
555 | esdhc_clrset_le(host, 0xff, val, reg); | |
913413c3 SG |
556 | |
557 | /* | |
558 | * The esdhc has a design violation to SDHC spec which tells | |
559 | * that software reset should not affect card detection circuit. | |
560 | * But esdhc clears its SYSCTL register bits [0..2] during the | |
561 | * software reset. This will stop those clocks that card detection | |
562 | * circuit relies on. To work around it, we turn the clocks on back | |
563 | * to keep card detection circuit functional. | |
564 | */ | |
58c8c4fb | 565 | if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { |
913413c3 | 566 | esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); |
58c8c4fb SG |
567 | /* |
568 | * The reset on usdhc fails to clear MIX_CTRL register. | |
569 | * Do it manually here. | |
570 | */ | |
de5bdbff | 571 | if (esdhc_is_usdhc(imx_data)) { |
d131a71c DA |
572 | /* the tuning bits should be kept during reset */ |
573 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
574 | writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, | |
575 | host->ioaddr + ESDHC_MIX_CTRL); | |
de5bdbff DA |
576 | imx_data->is_ddr = 0; |
577 | } | |
58c8c4fb | 578 | } |
95f25efe WS |
579 | } |
580 | ||
0ddf03c9 LS |
581 | static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) |
582 | { | |
583 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
0ddf03c9 | 584 | |
a3bd4f98 | 585 | return pltfm_host->clock; |
0ddf03c9 LS |
586 | } |
587 | ||
95f25efe WS |
588 | static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) |
589 | { | |
590 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
591 | ||
a974862f | 592 | return pltfm_host->clock / 256 / 16; |
95f25efe WS |
593 | } |
594 | ||
8ba9580a LS |
595 | static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, |
596 | unsigned int clock) | |
597 | { | |
598 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
fed2f6e2 | 599 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
a974862f | 600 | unsigned int host_clock = pltfm_host->clock; |
d31fc00a DA |
601 | int pre_div = 2; |
602 | int div = 1; | |
fed2f6e2 | 603 | u32 temp, val; |
d31fc00a | 604 | |
fed2f6e2 | 605 | if (clock == 0) { |
1650d0c7 RK |
606 | host->mmc->actual_clock = 0; |
607 | ||
9d61c009 | 608 | if (esdhc_is_usdhc(imx_data)) { |
fed2f6e2 DA |
609 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
610 | writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
611 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
612 | } | |
373073ef | 613 | return; |
fed2f6e2 | 614 | } |
d31fc00a | 615 | |
de5bdbff | 616 | if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) |
5f7886c5 DA |
617 | pre_div = 1; |
618 | ||
d31fc00a DA |
619 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |
620 | temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | |
621 | | ESDHC_CLOCK_MASK); | |
622 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | |
623 | ||
624 | while (host_clock / pre_div / 16 > clock && pre_div < 256) | |
625 | pre_div *= 2; | |
626 | ||
627 | while (host_clock / pre_div / div > clock && div < 16) | |
628 | div++; | |
629 | ||
e76b8559 | 630 | host->mmc->actual_clock = host_clock / pre_div / div; |
d31fc00a | 631 | dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", |
e76b8559 | 632 | clock, host->mmc->actual_clock); |
d31fc00a | 633 | |
de5bdbff DA |
634 | if (imx_data->is_ddr) |
635 | pre_div >>= 2; | |
636 | else | |
637 | pre_div >>= 1; | |
d31fc00a DA |
638 | div--; |
639 | ||
640 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); | |
641 | temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | |
642 | | (div << ESDHC_DIVIDER_SHIFT) | |
643 | | (pre_div << ESDHC_PREDIV_SHIFT)); | |
644 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | |
fed2f6e2 | 645 | |
9d61c009 | 646 | if (esdhc_is_usdhc(imx_data)) { |
fed2f6e2 DA |
647 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
648 | writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
649 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
650 | } | |
651 | ||
d31fc00a | 652 | mdelay(1); |
8ba9580a LS |
653 | } |
654 | ||
913413c3 SG |
655 | static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) |
656 | { | |
842afc02 SG |
657 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
658 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
659 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; | |
913413c3 SG |
660 | |
661 | switch (boarddata->wp_type) { | |
662 | case ESDHC_WP_GPIO: | |
fbe5fdd1 | 663 | return mmc_gpio_get_ro(host->mmc); |
913413c3 SG |
664 | case ESDHC_WP_CONTROLLER: |
665 | return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & | |
666 | SDHCI_WRITE_PROTECT); | |
667 | case ESDHC_WP_NONE: | |
668 | break; | |
669 | } | |
670 | ||
671 | return -ENOSYS; | |
672 | } | |
673 | ||
2317f56c | 674 | static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) |
af51079e SH |
675 | { |
676 | u32 ctrl; | |
677 | ||
678 | switch (width) { | |
679 | case MMC_BUS_WIDTH_8: | |
680 | ctrl = ESDHC_CTRL_8BITBUS; | |
681 | break; | |
682 | case MMC_BUS_WIDTH_4: | |
683 | ctrl = ESDHC_CTRL_4BITBUS; | |
684 | break; | |
685 | default: | |
686 | ctrl = 0; | |
687 | break; | |
688 | } | |
689 | ||
690 | esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, | |
691 | SDHCI_HOST_CONTROL); | |
af51079e SH |
692 | } |
693 | ||
0322191e DA |
694 | static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) |
695 | { | |
696 | u32 reg; | |
697 | ||
698 | /* FIXME: delay a bit for card to be ready for next tuning due to errors */ | |
699 | mdelay(1); | |
700 | ||
701 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
702 | reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | | |
703 | ESDHC_MIX_CTRL_FBCLK_SEL; | |
704 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); | |
705 | writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); | |
706 | dev_dbg(mmc_dev(host->mmc), | |
707 | "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", | |
708 | val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); | |
709 | } | |
710 | ||
0322191e DA |
711 | static void esdhc_post_tuning(struct sdhci_host *host) |
712 | { | |
713 | u32 reg; | |
714 | ||
715 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
716 | reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; | |
717 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); | |
718 | } | |
719 | ||
720 | static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) | |
721 | { | |
722 | int min, max, avg, ret; | |
723 | ||
724 | /* find the mininum delay first which can pass tuning */ | |
725 | min = ESDHC_TUNE_CTRL_MIN; | |
726 | while (min < ESDHC_TUNE_CTRL_MAX) { | |
727 | esdhc_prepare_tuning(host, min); | |
d1785326 | 728 | if (!mmc_send_tuning(host->mmc)) |
0322191e DA |
729 | break; |
730 | min += ESDHC_TUNE_CTRL_STEP; | |
731 | } | |
732 | ||
733 | /* find the maxinum delay which can not pass tuning */ | |
734 | max = min + ESDHC_TUNE_CTRL_STEP; | |
735 | while (max < ESDHC_TUNE_CTRL_MAX) { | |
736 | esdhc_prepare_tuning(host, max); | |
d1785326 | 737 | if (mmc_send_tuning(host->mmc)) { |
0322191e DA |
738 | max -= ESDHC_TUNE_CTRL_STEP; |
739 | break; | |
740 | } | |
741 | max += ESDHC_TUNE_CTRL_STEP; | |
742 | } | |
743 | ||
744 | /* use average delay to get the best timing */ | |
745 | avg = (min + max) / 2; | |
746 | esdhc_prepare_tuning(host, avg); | |
d1785326 | 747 | ret = mmc_send_tuning(host->mmc); |
0322191e DA |
748 | esdhc_post_tuning(host); |
749 | ||
750 | dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", | |
751 | ret ? "failed" : "passed", avg, ret); | |
752 | ||
753 | return ret; | |
754 | } | |
755 | ||
ad93220d DA |
756 | static int esdhc_change_pinstate(struct sdhci_host *host, |
757 | unsigned int uhs) | |
758 | { | |
759 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
760 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
761 | struct pinctrl_state *pinctrl; | |
762 | ||
763 | dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); | |
764 | ||
765 | if (IS_ERR(imx_data->pinctrl) || | |
766 | IS_ERR(imx_data->pins_default) || | |
767 | IS_ERR(imx_data->pins_100mhz) || | |
768 | IS_ERR(imx_data->pins_200mhz)) | |
769 | return -EINVAL; | |
770 | ||
771 | switch (uhs) { | |
772 | case MMC_TIMING_UHS_SDR50: | |
773 | pinctrl = imx_data->pins_100mhz; | |
774 | break; | |
775 | case MMC_TIMING_UHS_SDR104: | |
429a5b45 | 776 | case MMC_TIMING_MMC_HS200: |
ad93220d DA |
777 | pinctrl = imx_data->pins_200mhz; |
778 | break; | |
779 | default: | |
780 | /* back to default state for other legacy timing */ | |
781 | pinctrl = imx_data->pins_default; | |
782 | } | |
783 | ||
784 | return pinctrl_select_state(imx_data->pinctrl, pinctrl); | |
785 | } | |
786 | ||
850a29b8 | 787 | static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
ad93220d DA |
788 | { |
789 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
790 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
602519b2 | 791 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
ad93220d | 792 | |
850a29b8 | 793 | switch (timing) { |
ad93220d | 794 | case MMC_TIMING_UHS_SDR12: |
ad93220d | 795 | case MMC_TIMING_UHS_SDR25: |
ad93220d | 796 | case MMC_TIMING_UHS_SDR50: |
ad93220d | 797 | case MMC_TIMING_UHS_SDR104: |
429a5b45 | 798 | case MMC_TIMING_MMC_HS200: |
ad93220d DA |
799 | break; |
800 | case MMC_TIMING_UHS_DDR50: | |
69f5bf38 | 801 | case MMC_TIMING_MMC_DDR52: |
de5bdbff DA |
802 | writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | |
803 | ESDHC_MIX_CTRL_DDREN, | |
804 | host->ioaddr + ESDHC_MIX_CTRL); | |
805 | imx_data->is_ddr = 1; | |
602519b2 DA |
806 | if (boarddata->delay_line) { |
807 | u32 v; | |
808 | v = boarddata->delay_line << | |
809 | ESDHC_DLL_OVERRIDE_VAL_SHIFT | | |
810 | (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); | |
811 | if (is_imx53_esdhc(imx_data)) | |
812 | v <<= 1; | |
813 | writel(v, host->ioaddr + ESDHC_DLL_CTRL); | |
814 | } | |
ad93220d DA |
815 | break; |
816 | } | |
817 | ||
850a29b8 | 818 | esdhc_change_pinstate(host, timing); |
ad93220d DA |
819 | } |
820 | ||
0718e59a RK |
821 | static void esdhc_reset(struct sdhci_host *host, u8 mask) |
822 | { | |
823 | sdhci_reset(host, mask); | |
824 | ||
825 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
826 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
827 | } | |
828 | ||
10fd0ad9 AD |
829 | static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) |
830 | { | |
831 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
832 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
833 | ||
834 | return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27; | |
835 | } | |
836 | ||
e33eb8e2 AD |
837 | static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
838 | { | |
839 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
840 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
841 | ||
842 | /* use maximum timeout counter */ | |
843 | sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE, | |
844 | SDHCI_TIMEOUT_CONTROL); | |
845 | } | |
846 | ||
6e9fd28e | 847 | static struct sdhci_ops sdhci_esdhc_ops = { |
e149860d | 848 | .read_l = esdhc_readl_le, |
0c6d49ce | 849 | .read_w = esdhc_readw_le, |
e149860d | 850 | .write_l = esdhc_writel_le, |
0c6d49ce WS |
851 | .write_w = esdhc_writew_le, |
852 | .write_b = esdhc_writeb_le, | |
8ba9580a | 853 | .set_clock = esdhc_pltfm_set_clock, |
0ddf03c9 | 854 | .get_max_clock = esdhc_pltfm_get_max_clock, |
0c6d49ce | 855 | .get_min_clock = esdhc_pltfm_get_min_clock, |
10fd0ad9 | 856 | .get_max_timeout_count = esdhc_get_max_timeout_count, |
913413c3 | 857 | .get_ro = esdhc_pltfm_get_ro, |
e33eb8e2 | 858 | .set_timeout = esdhc_set_timeout, |
2317f56c | 859 | .set_bus_width = esdhc_pltfm_set_bus_width, |
ad93220d | 860 | .set_uhs_signaling = esdhc_set_uhs_signaling, |
0718e59a | 861 | .reset = esdhc_reset, |
0c6d49ce WS |
862 | }; |
863 | ||
1db5eebf | 864 | static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { |
97e4ba6a RZ |
865 | .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT |
866 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | |
867 | | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
85d6509d | 868 | | SDHCI_QUIRK_BROKEN_CARD_DETECTION, |
85d6509d SG |
869 | .ops = &sdhci_esdhc_ops, |
870 | }; | |
871 | ||
abfafc2d | 872 | #ifdef CONFIG_OF |
c3be1efd | 873 | static int |
abfafc2d | 874 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, |
07bf2b54 | 875 | struct sdhci_host *host, |
91fa4252 | 876 | struct pltfm_imx_data *imx_data) |
abfafc2d SG |
877 | { |
878 | struct device_node *np = pdev->dev.of_node; | |
91fa4252 | 879 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
4800e87a | 880 | int ret; |
abfafc2d | 881 | |
abfafc2d SG |
882 | if (of_get_property(np, "fsl,wp-controller", NULL)) |
883 | boarddata->wp_type = ESDHC_WP_CONTROLLER; | |
884 | ||
abfafc2d SG |
885 | boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); |
886 | if (gpio_is_valid(boarddata->wp_gpio)) | |
887 | boarddata->wp_type = ESDHC_WP_GPIO; | |
888 | ||
ad93220d DA |
889 | if (of_find_property(np, "no-1-8-v", NULL)) |
890 | boarddata->support_vsel = false; | |
891 | else | |
892 | boarddata->support_vsel = true; | |
893 | ||
602519b2 DA |
894 | if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) |
895 | boarddata->delay_line = 0; | |
896 | ||
07bf2b54 SH |
897 | mmc_of_parse_voltage(np, &host->ocr_mask); |
898 | ||
91fa4252 DA |
899 | /* sdr50 and sdr104 needs work on 1.8v signal voltage */ |
900 | if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && | |
901 | !IS_ERR(imx_data->pins_default)) { | |
902 | imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, | |
903 | ESDHC_PINCTRL_STATE_100MHZ); | |
904 | imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, | |
905 | ESDHC_PINCTRL_STATE_200MHZ); | |
906 | if (IS_ERR(imx_data->pins_100mhz) || | |
907 | IS_ERR(imx_data->pins_200mhz)) { | |
908 | dev_warn(mmc_dev(host->mmc), | |
909 | "could not get ultra high speed state, work on normal mode\n"); | |
910 | /* | |
911 | * fall back to not support uhs by specify no 1.8v quirk | |
912 | */ | |
913 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
914 | } | |
915 | } else { | |
916 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
917 | } | |
918 | ||
15064119 | 919 | /* call to generic mmc_of_parse to support additional capabilities */ |
4800e87a DA |
920 | ret = mmc_of_parse(host->mmc); |
921 | if (ret) | |
922 | return ret; | |
923 | ||
924 | if (!IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc))) | |
925 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
926 | ||
927 | return 0; | |
abfafc2d SG |
928 | } |
929 | #else | |
930 | static inline int | |
931 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, | |
07bf2b54 | 932 | struct sdhci_host *host, |
91fa4252 | 933 | struct pltfm_imx_data *imx_data) |
abfafc2d SG |
934 | { |
935 | return -ENODEV; | |
936 | } | |
937 | #endif | |
938 | ||
91fa4252 DA |
939 | static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, |
940 | struct sdhci_host *host, | |
941 | struct pltfm_imx_data *imx_data) | |
942 | { | |
943 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; | |
944 | int err; | |
945 | ||
946 | if (!host->mmc->parent->platform_data) { | |
947 | dev_err(mmc_dev(host->mmc), "no board data!\n"); | |
948 | return -EINVAL; | |
949 | } | |
950 | ||
951 | imx_data->boarddata = *((struct esdhc_platform_data *) | |
952 | host->mmc->parent->platform_data); | |
953 | /* write_protect */ | |
954 | if (boarddata->wp_type == ESDHC_WP_GPIO) { | |
955 | err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); | |
956 | if (err) { | |
957 | dev_err(mmc_dev(host->mmc), | |
958 | "failed to request write-protect gpio!\n"); | |
959 | return err; | |
960 | } | |
961 | host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; | |
962 | } | |
963 | ||
964 | /* card_detect */ | |
965 | switch (boarddata->cd_type) { | |
966 | case ESDHC_CD_GPIO: | |
967 | err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); | |
968 | if (err) { | |
969 | dev_err(mmc_dev(host->mmc), | |
970 | "failed to request card-detect gpio!\n"); | |
971 | return err; | |
972 | } | |
973 | /* fall through */ | |
974 | ||
975 | case ESDHC_CD_CONTROLLER: | |
976 | /* we have a working card_detect back */ | |
977 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
978 | break; | |
979 | ||
980 | case ESDHC_CD_PERMANENT: | |
981 | host->mmc->caps |= MMC_CAP_NONREMOVABLE; | |
982 | break; | |
983 | ||
984 | case ESDHC_CD_NONE: | |
985 | break; | |
986 | } | |
987 | ||
988 | switch (boarddata->max_bus_width) { | |
989 | case 8: | |
990 | host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; | |
991 | break; | |
992 | case 4: | |
993 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
994 | break; | |
995 | case 1: | |
996 | default: | |
997 | host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; | |
998 | break; | |
999 | } | |
1000 | ||
1001 | return 0; | |
1002 | } | |
1003 | ||
c3be1efd | 1004 | static int sdhci_esdhc_imx_probe(struct platform_device *pdev) |
95f25efe | 1005 | { |
abfafc2d SG |
1006 | const struct of_device_id *of_id = |
1007 | of_match_device(imx_esdhc_dt_ids, &pdev->dev); | |
85d6509d SG |
1008 | struct sdhci_pltfm_host *pltfm_host; |
1009 | struct sdhci_host *host; | |
0c6d49ce | 1010 | int err; |
e149860d | 1011 | struct pltfm_imx_data *imx_data; |
95f25efe | 1012 | |
0e748234 | 1013 | host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); |
85d6509d SG |
1014 | if (IS_ERR(host)) |
1015 | return PTR_ERR(host); | |
1016 | ||
1017 | pltfm_host = sdhci_priv(host); | |
1018 | ||
e3af31c6 | 1019 | imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); |
abfafc2d SG |
1020 | if (!imx_data) { |
1021 | err = -ENOMEM; | |
e3af31c6 | 1022 | goto free_sdhci; |
abfafc2d | 1023 | } |
57ed3314 | 1024 | |
f47c4bbf SG |
1025 | imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) |
1026 | pdev->id_entry->driver_data; | |
85d6509d SG |
1027 | pltfm_host->priv = imx_data; |
1028 | ||
52dac615 SH |
1029 | imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1030 | if (IS_ERR(imx_data->clk_ipg)) { | |
1031 | err = PTR_ERR(imx_data->clk_ipg); | |
e3af31c6 | 1032 | goto free_sdhci; |
95f25efe | 1033 | } |
52dac615 SH |
1034 | |
1035 | imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
1036 | if (IS_ERR(imx_data->clk_ahb)) { | |
1037 | err = PTR_ERR(imx_data->clk_ahb); | |
e3af31c6 | 1038 | goto free_sdhci; |
52dac615 SH |
1039 | } |
1040 | ||
1041 | imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); | |
1042 | if (IS_ERR(imx_data->clk_per)) { | |
1043 | err = PTR_ERR(imx_data->clk_per); | |
e3af31c6 | 1044 | goto free_sdhci; |
52dac615 SH |
1045 | } |
1046 | ||
1047 | pltfm_host->clk = imx_data->clk_per; | |
a974862f | 1048 | pltfm_host->clock = clk_get_rate(pltfm_host->clk); |
52dac615 SH |
1049 | clk_prepare_enable(imx_data->clk_per); |
1050 | clk_prepare_enable(imx_data->clk_ipg); | |
1051 | clk_prepare_enable(imx_data->clk_ahb); | |
95f25efe | 1052 | |
ad93220d | 1053 | imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); |
e62d8b8f DA |
1054 | if (IS_ERR(imx_data->pinctrl)) { |
1055 | err = PTR_ERR(imx_data->pinctrl); | |
e3af31c6 | 1056 | goto disable_clk; |
e62d8b8f DA |
1057 | } |
1058 | ||
ad93220d DA |
1059 | imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, |
1060 | PINCTRL_STATE_DEFAULT); | |
cd529af7 DB |
1061 | if (IS_ERR(imx_data->pins_default)) |
1062 | dev_warn(mmc_dev(host->mmc), "could not get default state\n"); | |
ad93220d | 1063 | |
b8915282 | 1064 | host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; |
37865fe9 | 1065 | |
f47c4bbf | 1066 | if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) |
0c6d49ce | 1067 | /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ |
97e4ba6a RZ |
1068 | host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK |
1069 | | SDHCI_QUIRK_BROKEN_ADMA; | |
0c6d49ce | 1070 | |
f750ba9b SG |
1071 | /* |
1072 | * The imx6q ROM code will change the default watermark level setting | |
1073 | * to something insane. Change it back here. | |
1074 | */ | |
69ed60e0 | 1075 | if (esdhc_is_usdhc(imx_data)) { |
60bf6396 | 1076 | writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); |
69ed60e0 | 1077 | host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; |
e2997c94 | 1078 | host->mmc->caps |= MMC_CAP_1_8V_DDR; |
18094430 | 1079 | |
4245afff DA |
1080 | if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) |
1081 | host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; | |
1082 | ||
18094430 DA |
1083 | /* |
1084 | * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL | |
1085 | * TO1.1, it's harmless for MX6SL | |
1086 | */ | |
1087 | writel(readl(host->ioaddr + 0x6c) | BIT(7), | |
1088 | host->ioaddr + 0x6c); | |
69ed60e0 | 1089 | } |
f750ba9b | 1090 | |
6e9fd28e DA |
1091 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
1092 | sdhci_esdhc_ops.platform_execute_tuning = | |
1093 | esdhc_executing_tuning; | |
8b2bb0ad DA |
1094 | |
1095 | if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) | |
1096 | writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) | | |
1097 | ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP, | |
1098 | host->ioaddr + ESDHC_TUNING_CTRL); | |
1099 | ||
18094430 DA |
1100 | if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) |
1101 | host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; | |
1102 | ||
91fa4252 DA |
1103 | if (of_id) |
1104 | err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); | |
1105 | else | |
1106 | err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); | |
1107 | if (err) | |
1108 | goto disable_clk; | |
ad93220d | 1109 | |
85d6509d SG |
1110 | err = sdhci_add_host(host); |
1111 | if (err) | |
e3af31c6 | 1112 | goto disable_clk; |
85d6509d | 1113 | |
89d7e5c1 | 1114 | pm_runtime_set_active(&pdev->dev); |
89d7e5c1 DA |
1115 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1116 | pm_runtime_use_autosuspend(&pdev->dev); | |
1117 | pm_suspend_ignore_children(&pdev->dev, 1); | |
77903c01 | 1118 | pm_runtime_enable(&pdev->dev); |
89d7e5c1 | 1119 | |
95f25efe | 1120 | return 0; |
7e29c306 | 1121 | |
e3af31c6 | 1122 | disable_clk: |
52dac615 SH |
1123 | clk_disable_unprepare(imx_data->clk_per); |
1124 | clk_disable_unprepare(imx_data->clk_ipg); | |
1125 | clk_disable_unprepare(imx_data->clk_ahb); | |
e3af31c6 | 1126 | free_sdhci: |
85d6509d SG |
1127 | sdhci_pltfm_free(pdev); |
1128 | return err; | |
95f25efe WS |
1129 | } |
1130 | ||
6e0ee714 | 1131 | static int sdhci_esdhc_imx_remove(struct platform_device *pdev) |
95f25efe | 1132 | { |
85d6509d | 1133 | struct sdhci_host *host = platform_get_drvdata(pdev); |
95f25efe | 1134 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
e149860d | 1135 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
85d6509d SG |
1136 | int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
1137 | ||
0b414368 | 1138 | pm_runtime_get_sync(&pdev->dev); |
89d7e5c1 | 1139 | pm_runtime_disable(&pdev->dev); |
0b414368 | 1140 | pm_runtime_put_noidle(&pdev->dev); |
89d7e5c1 | 1141 | |
0b414368 UH |
1142 | sdhci_remove_host(host, dead); |
1143 | ||
1144 | clk_disable_unprepare(imx_data->clk_per); | |
1145 | clk_disable_unprepare(imx_data->clk_ipg); | |
1146 | clk_disable_unprepare(imx_data->clk_ahb); | |
52dac615 | 1147 | |
85d6509d SG |
1148 | sdhci_pltfm_free(pdev); |
1149 | ||
1150 | return 0; | |
95f25efe WS |
1151 | } |
1152 | ||
162d6f98 | 1153 | #ifdef CONFIG_PM |
89d7e5c1 DA |
1154 | static int sdhci_esdhc_runtime_suspend(struct device *dev) |
1155 | { | |
1156 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1157 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1158 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
1159 | int ret; | |
1160 | ||
1161 | ret = sdhci_runtime_suspend_host(host); | |
1162 | ||
be138554 RK |
1163 | if (!sdhci_sdio_irq_enabled(host)) { |
1164 | clk_disable_unprepare(imx_data->clk_per); | |
1165 | clk_disable_unprepare(imx_data->clk_ipg); | |
1166 | } | |
89d7e5c1 DA |
1167 | clk_disable_unprepare(imx_data->clk_ahb); |
1168 | ||
1169 | return ret; | |
1170 | } | |
1171 | ||
1172 | static int sdhci_esdhc_runtime_resume(struct device *dev) | |
1173 | { | |
1174 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1175 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1176 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
1177 | ||
be138554 RK |
1178 | if (!sdhci_sdio_irq_enabled(host)) { |
1179 | clk_prepare_enable(imx_data->clk_per); | |
1180 | clk_prepare_enable(imx_data->clk_ipg); | |
1181 | } | |
89d7e5c1 DA |
1182 | clk_prepare_enable(imx_data->clk_ahb); |
1183 | ||
1184 | return sdhci_runtime_resume_host(host); | |
1185 | } | |
1186 | #endif | |
1187 | ||
1188 | static const struct dev_pm_ops sdhci_esdhc_pmops = { | |
1189 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) | |
1190 | SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, | |
1191 | sdhci_esdhc_runtime_resume, NULL) | |
1192 | }; | |
1193 | ||
85d6509d SG |
1194 | static struct platform_driver sdhci_esdhc_imx_driver = { |
1195 | .driver = { | |
1196 | .name = "sdhci-esdhc-imx", | |
abfafc2d | 1197 | .of_match_table = imx_esdhc_dt_ids, |
89d7e5c1 | 1198 | .pm = &sdhci_esdhc_pmops, |
85d6509d | 1199 | }, |
57ed3314 | 1200 | .id_table = imx_esdhc_devtype, |
85d6509d | 1201 | .probe = sdhci_esdhc_imx_probe, |
0433c143 | 1202 | .remove = sdhci_esdhc_imx_remove, |
95f25efe | 1203 | }; |
85d6509d | 1204 | |
d1f81a64 | 1205 | module_platform_driver(sdhci_esdhc_imx_driver); |
85d6509d SG |
1206 | |
1207 | MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); | |
035ff831 | 1208 | MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); |
85d6509d | 1209 | MODULE_LICENSE("GPL v2"); |