[linux-2.6-block.git] / drivers / misc / cxl / irq.c

/*
 * Copyright 2014 IBM Corp.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/interrupt.h>
#include <linux/workqueue.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/slab.h>
#include <linux/pid.h>
#include <asm/cputable.h>
#include <misc/cxl-base.h>

#include "cxl.h"
#include "trace.h"

static int afu_irq_range_start(void)
{
	if (cpu_has_feature(CPU_FTR_HVMODE))
		return 1;
	return 0;
}

static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar)
{
	ctx->dsisr = dsisr;
	ctx->dar = dar;
	schedule_work(&ctx->fault_work);
	return IRQ_HANDLED;
}

irqreturn_t cxl_irq(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info)
{
	u64 dsisr, dar;

	dsisr = irq_info->dsisr;
	dar = irq_info->dar;

	trace_cxl_psl_irq(ctx, irq, dsisr, dar);

	pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);

	if (dsisr & CXL_PSL_DSISR_An_DS) {
		/*
		 * We don't inherently need to sleep to handle this, but we do
		 * need to get a ref to the task's mm, which we can't do from
		 * irq context without the potential for a deadlock since it
		 * takes the task_lock. An alternate option would be to keep a
		 * reference to the task's mm the entire time it has cxl open,
		 * but to do that we need to solve the issue where we hold a
		 * ref to the mm, but the mm can hold a ref to the fd after an
		 * mmap preventing anything from being cleaned up.
		 */
		pr_devel("Scheduling segment miss handling for later pe: %i\n", ctx->pe);
		return schedule_cxl_fault(ctx, dsisr, dar);
	}

	if (dsisr & CXL_PSL_DSISR_An_M)
		pr_devel("CXL interrupt: PTE not found\n");
	if (dsisr & CXL_PSL_DSISR_An_P)
		pr_devel("CXL interrupt: Storage protection violation\n");
	if (dsisr & CXL_PSL_DSISR_An_A)
		pr_devel("CXL interrupt: AFU lock access to write through or cache inhibited storage\n");
	if (dsisr & CXL_PSL_DSISR_An_S)
		pr_devel("CXL interrupt: Access was afu_wr or afu_zero\n");
	if (dsisr & CXL_PSL_DSISR_An_K)
		pr_devel("CXL interrupt: Access not permitted by virtual page class key protection\n");

	if (dsisr & CXL_PSL_DSISR_An_DM) {
		/*
		 * In some cases we might be able to handle the fault
		 * immediately if hash_page would succeed, but we still need
		 * the task's mm, which as above we can't get without a lock
		 */
		pr_devel("Scheduling page fault handling for later pe: %i\n", ctx->pe);
		return schedule_cxl_fault(ctx, dsisr, dar);
	}
	if (dsisr & CXL_PSL_DSISR_An_ST)
		WARN(1, "CXL interrupt: Segment Table PTE not found\n");
	if (dsisr & CXL_PSL_DSISR_An_UR)
		pr_devel("CXL interrupt: AURP PTE not found\n");
	if (dsisr & CXL_PSL_DSISR_An_PE)
		return cxl_ops->handle_psl_slice_error(ctx, dsisr,
						irq_info->errstat);
	if (dsisr & CXL_PSL_DSISR_An_AE) {
		pr_devel("CXL interrupt: AFU Error 0x%016llx\n", irq_info->afu_err);

		if (ctx->pending_afu_err) {
			/*
			 * This shouldn't happen - the PSL treats these errors
			 * as fatal and will have reset the AFU, so there's not
			 * much point buffering multiple AFU errors.
			 * OTOH if we DO ever see a storm of these come in it's
			 * probably best that we log them somewhere:
			 */
			dev_err_ratelimited(&ctx->afu->dev, "CXL AFU Error "
					    "undelivered to pe %i: 0x%016llx\n",
					    ctx->pe, irq_info->afu_err);
		} else {
			spin_lock(&ctx->lock);
			ctx->afu_err = irq_info->afu_err;
			ctx->pending_afu_err = 1;
			spin_unlock(&ctx->lock);

			wake_up_all(&ctx->wq);
		}

		cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_A, 0);
		return IRQ_HANDLED;
	}
	if (dsisr & CXL_PSL_DSISR_An_OC)
		pr_devel("CXL interrupt: OS Context Warning\n");

	WARN(1, "Unhandled CXL PSL IRQ\n");
	return IRQ_HANDLED;
}

static irqreturn_t cxl_irq_afu(int irq, void *data)
{
	struct cxl_context *ctx = data;
	irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq));
	int irq_off, afu_irq = 0;
	__u16 range;
	int r;

	/*
	 * Look for the interrupt number.
	 * On bare-metal, we know range 0 only contains the PSL
	 * interrupt so we could start counting at range 1 and initialize
	 * afu_irq at 1.
	 * In a guest, range 0 also contains AFU interrupts, so it must
	 * be counted for. Therefore we initialize afu_irq at 0 to take into
	 * account the PSL interrupt.
	 *
	 * For code-readability, it just seems easier to go over all
	 * the ranges on bare-metal and guest. The end result is the same.
	 */
	for (r = 0; r < CXL_IRQ_RANGES; r++) {
		irq_off = hwirq - ctx->irqs.offset[r];
		range = ctx->irqs.range[r];
		if (irq_off >= 0 && irq_off < range) {
			afu_irq += irq_off;
			break;
		}
		afu_irq += range;
	}
	if (unlikely(r >= CXL_IRQ_RANGES)) {
		WARN(1, "Received AFU IRQ out of range for pe %i (virq %i hwirq %lx)\n",
		     ctx->pe, irq, hwirq);
		return IRQ_HANDLED;
	}

	trace_cxl_afu_irq(ctx, afu_irq, irq, hwirq);
	pr_devel("Received AFU interrupt %i for pe: %i (virq %i hwirq %lx)\n",
	       afu_irq, ctx->pe, irq, hwirq);

	if (unlikely(!ctx->irq_bitmap)) {
		WARN(1, "Received AFU IRQ for context with no IRQ bitmap\n");
		return IRQ_HANDLED;
	}
	spin_lock(&ctx->lock);
	set_bit(afu_irq - 1, ctx->irq_bitmap);
	ctx->pending_irq = true;
	spin_unlock(&ctx->lock);

	wake_up_all(&ctx->wq);

	return IRQ_HANDLED;
}

unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
			 irq_handler_t handler, void *cookie, const char *name)
{
	unsigned int virq;
	int result;

	/* IRQ Domain? */
	virq = irq_create_mapping(NULL, hwirq);
	if (!virq) {
		dev_warn(&adapter->dev, "cxl_map_irq: irq_create_mapping failed\n");
		return 0;
	}

	if (cxl_ops->setup_irq)
		cxl_ops->setup_irq(adapter, hwirq, virq);

	pr_devel("hwirq %#lx mapped to virq %u\n", hwirq, virq);

	result = request_irq(virq, handler, 0, name, cookie);
	if (result) {
		dev_warn(&adapter->dev, "cxl_map_irq: request_irq failed: %i\n", result);
		return 0;
	}

	return virq;
}

void cxl_unmap_irq(unsigned int virq, void *cookie)
{
	free_irq(virq, cookie);
}

int cxl_register_one_irq(struct cxl *adapter,
			irq_handler_t handler,
			void *cookie,
			irq_hw_number_t *dest_hwirq,
			unsigned int *dest_virq,
			const char *name)
{
	int hwirq, virq;

	if ((hwirq = cxl_ops->alloc_one_irq(adapter)) < 0)
		return hwirq;

	if (!(virq = cxl_map_irq(adapter, hwirq, handler, cookie, name)))
		goto err;

	*dest_hwirq = hwirq;
	*dest_virq = virq;

	return 0;

err:
	cxl_ops->release_one_irq(adapter, hwirq);
	return -ENOMEM;
}

void afu_irq_name_free(struct cxl_context *ctx)
{
	struct cxl_irq_name *irq_name, *tmp;

	list_for_each_entry_safe(irq_name, tmp, &ctx->irq_names, list) {
		kfree(irq_name->name);
		list_del(&irq_name->list);
		kfree(irq_name);
	}
}

int afu_allocate_irqs(struct cxl_context *ctx, u32 count)
{
	int rc, r, i, j = 1;
	struct cxl_irq_name *irq_name;
	int alloc_count;

	/*
	 * In native mode, range 0 is reserved for the multiplexed
	 * PSL interrupt. It has been allocated when the AFU was initialized.
	 *
	 * In a guest, the PSL interrupt is not mutliplexed, but per-context,
	 * and is the first interrupt from range 0. It still needs to be
	 * allocated, so bump the count by one.
	 */
	if (cpu_has_feature(CPU_FTR_HVMODE))
		alloc_count = count;
	else
		alloc_count = count + 1;

	/* Initialize the list head to hold irq names */
	INIT_LIST_HEAD(&ctx->irq_names);

	if ((rc = cxl_ops->alloc_irq_ranges(&ctx->irqs, ctx->afu->adapter,
							alloc_count)))
		return rc;

	if (cpu_has_feature(CPU_FTR_HVMODE)) {
		/* Multiplexed PSL Interrupt */
		ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
		ctx->irqs.range[0] = 1;
	}

	ctx->irq_count = count;
	ctx->irq_bitmap = kcalloc(BITS_TO_LONGS(count),
				  sizeof(*ctx->irq_bitmap), GFP_KERNEL);
	if (!ctx->irq_bitmap)
		goto out;

	/*
	 * Allocate names first.  If any fail, bail out before allocating
	 * actual hardware IRQs.
	 */
	for (r = afu_irq_range_start(); r < CXL_IRQ_RANGES; r++) {
		for (i = 0; i < ctx->irqs.range[r]; i++) {
			irq_name = kmalloc(sizeof(struct cxl_irq_name),
					   GFP_KERNEL);
			if (!irq_name)
				goto out;
			irq_name->name = kasprintf(GFP_KERNEL, "cxl-%s-pe%i-%i",
						   dev_name(&ctx->afu->dev),
						   ctx->pe, j);
			if (!irq_name->name) {
				kfree(irq_name);
				goto out;
			}
			/* Add to tail so next look get the correct order */
			list_add_tail(&irq_name->list, &ctx->irq_names);
			j++;
		}
	}
	return 0;

out:
	cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter);
	afu_irq_name_free(ctx);
	return -ENOMEM;
}

static void afu_register_hwirqs(struct cxl_context *ctx)
{
	irq_hw_number_t hwirq;
	struct cxl_irq_name *irq_name;
	int r, i;
	irqreturn_t (*handler)(int irq, void *data);

	/* We've allocated all memory now, so let's do the irq allocations */
	irq_name = list_first_entry(&ctx->irq_names, struct cxl_irq_name, list);
	for (r = afu_irq_range_start(); r < CXL_IRQ_RANGES; r++) {
		hwirq = ctx->irqs.offset[r];
		for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
			if (r == 0 && i == 0)
				/*
				 * The very first interrupt of range 0 is
				 * always the PSL interrupt, but we only
				 * need to connect a handler for guests,
				 * because there's one PSL interrupt per
				 * context.
				 * On bare-metal, the PSL interrupt is
				 * multiplexed and was setup when the AFU
				 * was configured.
				 */
				handler = cxl_ops->psl_interrupt;
			else
				handler = cxl_irq_afu;
			cxl_map_irq(ctx->afu->adapter, hwirq, handler, ctx,
				irq_name->name);
			irq_name = list_next_entry(irq_name, list);
		}
	}
}

int afu_register_irqs(struct cxl_context *ctx, u32 count)
{
	int rc;

	rc = afu_allocate_irqs(ctx, count);
	if (rc)
		return rc;

	afu_register_hwirqs(ctx);
	return 0;
}

void afu_release_irqs(struct cxl_context *ctx, void *cookie)
{
	irq_hw_number_t hwirq;
	unsigned int virq;
	int r, i;

	for (r = afu_irq_range_start(); r < CXL_IRQ_RANGES; r++) {
		hwirq = ctx->irqs.offset[r];
		for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
			virq = irq_find_mapping(NULL, hwirq);
			if (virq)
				cxl_unmap_irq(virq, cookie);
		}
	}

	afu_irq_name_free(ctx);
	cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter);

	ctx->irq_count = 0;
}
Commit	Line	Data
f204e0b8 IM	1	/*
	2	* Copyright 2014 IBM Corp.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9
	10	#include <linux/interrupt.h>
	11	#include <linux/workqueue.h>
	12	#include <linux/sched.h>
	13	#include <linux/wait.h>
	14	#include <linux/slab.h>
	15	#include <linux/pid.h>
	16	#include <asm/cputable.h>
ec249dd8	17	#include <misc/cxl-base.h>
f204e0b8 IM	18
f204e0b8 IM	19	#include "cxl.h"
9bcf28cd	20	#include "trace.h"
f204e0b8	21
73d55c3b FB	22	static int afu_irq_range_start(void)
	23	{
	24	if (cpu_has_feature(CPU_FTR_HVMODE))
	25	return 1;
	26	return 0;
	27	}
	28
f204e0b8 IM	29	static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar)
	30	{
	31	ctx->dsisr = dsisr;
	32	ctx->dar = dar;
	33	schedule_work(&ctx->fault_work);
	34	return IRQ_HANDLED;
	35	}
	36
6d625ed9	37	irqreturn_t cxl_irq(int irq, struct cxl_context ctx, struct cxl_irq_info irq_info)
f204e0b8	38	{
f204e0b8	39	u64 dsisr, dar;
f204e0b8	40
bc78b05b IM	41	dsisr = irq_info->dsisr;
bc78b05b IM	42	dar = irq_info->dar;
f204e0b8	43
9bcf28cd IM	44	trace_cxl_psl_irq(ctx, irq, dsisr, dar);
9bcf28cd IM	45
f204e0b8 IM	46	pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);
	47
	48	if (dsisr & CXL_PSL_DSISR_An_DS) {
	49	/*
	50	* We don't inherently need to sleep to handle this, but we do
	51	* need to get a ref to the task's mm, which we can't do from
	52	* irq context without the potential for a deadlock since it
	53	* takes the task_lock. An alternate option would be to keep a
	54	* reference to the task's mm the entire time it has cxl open,
	55	* but to do that we need to solve the issue where we hold a
	56	* ref to the mm, but the mm can hold a ref to the fd after an
	57	* mmap preventing anything from being cleaned up.
	58	*/
	59	pr_devel("Scheduling segment miss handling for later pe: %i\n", ctx->pe);
	60	return schedule_cxl_fault(ctx, dsisr, dar);
	61	}
	62
	63	if (dsisr & CXL_PSL_DSISR_An_M)
	64	pr_devel("CXL interrupt: PTE not found\n");
	65	if (dsisr & CXL_PSL_DSISR_An_P)
	66	pr_devel("CXL interrupt: Storage protection violation\n");
	67	if (dsisr & CXL_PSL_DSISR_An_A)
	68	pr_devel("CXL interrupt: AFU lock access to write through or cache inhibited storage\n");
	69	if (dsisr & CXL_PSL_DSISR_An_S)
	70	pr_devel("CXL interrupt: Access was afu_wr or afu_zero\n");
	71	if (dsisr & CXL_PSL_DSISR_An_K)
	72	pr_devel("CXL interrupt: Access not permitted by virtual page class key protection\n");
	73
	74	if (dsisr & CXL_PSL_DSISR_An_DM) {
	75	/*
	76	* In some cases we might be able to handle the fault
	77	* immediately if hash_page would succeed, but we still need
	78	* the task's mm, which as above we can't get without a lock
	79	*/
	80	pr_devel("Scheduling page fault handling for later pe: %i\n", ctx->pe);
	81	return schedule_cxl_fault(ctx, dsisr, dar);
	82	}
	83	if (dsisr & CXL_PSL_DSISR_An_ST)
	84	WARN(1, "CXL interrupt: Segment Table PTE not found\n");
	85	if (dsisr & CXL_PSL_DSISR_An_UR)
	86	pr_devel("CXL interrupt: AURP PTE not found\n");
	87	if (dsisr & CXL_PSL_DSISR_An_PE)
5be587b1 FB	88	return cxl_ops->handle_psl_slice_error(ctx, dsisr,
5be587b1 FB	89	irq_info->errstat);
f204e0b8	90	if (dsisr & CXL_PSL_DSISR_An_AE) {
de369538	91	pr_devel("CXL interrupt: AFU Error 0x%016llx\n", irq_info->afu_err);
f204e0b8 IM	92
	93	if (ctx->pending_afu_err) {
	94	/*
	95	* This shouldn't happen - the PSL treats these errors
	96	* as fatal and will have reset the AFU, so there's not
	97	* much point buffering multiple AFU errors.
	98	* OTOH if we DO ever see a storm of these come in it's
	99	* probably best that we log them somewhere:
	100	*/
	101	dev_err_ratelimited(&ctx->afu->dev, "CXL AFU Error "
de369538	102	"undelivered to pe %i: 0x%016llx\n",
bc78b05b	103	ctx->pe, irq_info->afu_err);
f204e0b8 IM	104	} else {
f204e0b8 IM	105	spin_lock(&ctx->lock);
bc78b05b	106	ctx->afu_err = irq_info->afu_err;
f204e0b8 IM	107	ctx->pending_afu_err = 1;
	108	spin_unlock(&ctx->lock);
	109
	110	wake_up_all(&ctx->wq);
	111	}
	112
5be587b1	113	cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_A, 0);
a6130ed2	114	return IRQ_HANDLED;
f204e0b8 IM	115	}
	116	if (dsisr & CXL_PSL_DSISR_An_OC)
	117	pr_devel("CXL interrupt: OS Context Warning\n");
	118
	119	WARN(1, "Unhandled CXL PSL IRQ\n");
	120	return IRQ_HANDLED;
	121	}
	122
f204e0b8 IM	123	static irqreturn_t cxl_irq_afu(int irq, void *data)
	124	{
	125	struct cxl_context *ctx = data;
	126	irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq));
73d55c3b	127	int irq_off, afu_irq = 0;
f204e0b8 IM	128	__u16 range;
	129	int r;
	130
73d55c3b FB	131	/*
	132	* Look for the interrupt number.
	133	* On bare-metal, we know range 0 only contains the PSL
	134	* interrupt so we could start counting at range 1 and initialize
	135	* afu_irq at 1.
	136	* In a guest, range 0 also contains AFU interrupts, so it must
	137	* be counted for. Therefore we initialize afu_irq at 0 to take into
	138	* account the PSL interrupt.
	139	*
	140	* For code-readability, it just seems easier to go over all
	141	* the ranges on bare-metal and guest. The end result is the same.
	142	*/
	143	for (r = 0; r < CXL_IRQ_RANGES; r++) {
f204e0b8 IM	144	irq_off = hwirq - ctx->irqs.offset[r];
	145	range = ctx->irqs.range[r];
	146	if (irq_off >= 0 && irq_off < range) {
	147	afu_irq += irq_off;
	148	break;
	149	}
	150	afu_irq += range;
	151	}
	152	if (unlikely(r >= CXL_IRQ_RANGES)) {
73d55c3b	153	WARN(1, "Received AFU IRQ out of range for pe %i (virq %i hwirq %lx)\n",
f204e0b8 IM	154	ctx->pe, irq, hwirq);
	155	return IRQ_HANDLED;
	156	}
	157
9bcf28cd	158	trace_cxl_afu_irq(ctx, afu_irq, irq, hwirq);
f204e0b8 IM	159	pr_devel("Received AFU interrupt %i for pe: %i (virq %i hwirq %lx)\n",
	160	afu_irq, ctx->pe, irq, hwirq);
	161
	162	if (unlikely(!ctx->irq_bitmap)) {
73d55c3b	163	WARN(1, "Received AFU IRQ for context with no IRQ bitmap\n");
f204e0b8 IM	164	return IRQ_HANDLED;
	165	}
	166	spin_lock(&ctx->lock);
	167	set_bit(afu_irq - 1, ctx->irq_bitmap);
	168	ctx->pending_irq = true;
	169	spin_unlock(&ctx->lock);
	170
	171	wake_up_all(&ctx->wq);
	172
	173	return IRQ_HANDLED;
	174	}
	175
	176	unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
80fa93fc	177	irq_handler_t handler, void cookie, const char name)
f204e0b8 IM	178	{
	179	unsigned int virq;
	180	int result;
	181
	182	/* IRQ Domain? */
	183	virq = irq_create_mapping(NULL, hwirq);
	184	if (!virq) {
	185	dev_warn(&adapter->dev, "cxl_map_irq: irq_create_mapping failed\n");
	186	return 0;
	187	}
	188
5be587b1 FB	189	if (cxl_ops->setup_irq)
5be587b1 FB	190	cxl_ops->setup_irq(adapter, hwirq, virq);
f204e0b8 IM	191
	192	pr_devel("hwirq %#lx mapped to virq %u\n", hwirq, virq);
	193
80fa93fc	194	result = request_irq(virq, handler, 0, name, cookie);
f204e0b8 IM	195	if (result) {
	196	dev_warn(&adapter->dev, "cxl_map_irq: request_irq failed: %i\n", result);
	197	return 0;
	198	}
	199
	200	return virq;
	201	}
	202
	203	void cxl_unmap_irq(unsigned int virq, void *cookie)
	204	{
	205	free_irq(virq, cookie);
f204e0b8 IM	206	}
f204e0b8 IM	207
86331862 CL	208	int cxl_register_one_irq(struct cxl *adapter,
	209	irq_handler_t handler,
	210	void *cookie,
	211	irq_hw_number_t *dest_hwirq,
	212	unsigned int *dest_virq,
	213	const char *name)
f204e0b8 IM	214	{
	215	int hwirq, virq;
	216
5be587b1	217	if ((hwirq = cxl_ops->alloc_one_irq(adapter)) < 0)
f204e0b8 IM	218	return hwirq;
f204e0b8 IM	219
80fa93fc	220	if (!(virq = cxl_map_irq(adapter, hwirq, handler, cookie, name)))
f204e0b8 IM	221	goto err;
	222
	223	*dest_hwirq = hwirq;
	224	*dest_virq = virq;
	225
	226	return 0;
	227
	228	err:
5be587b1	229	cxl_ops->release_one_irq(adapter, hwirq);
f204e0b8 IM	230	return -ENOMEM;
	231	}
	232
8dde152e	233	void afu_irq_name_free(struct cxl_context *ctx)
80fa93fc MN	234	{
	235	struct cxl_irq_name irq_name, tmp;
	236
	237	list_for_each_entry_safe(irq_name, tmp, &ctx->irq_names, list) {
	238	kfree(irq_name->name);
	239	list_del(&irq_name->list);
	240	kfree(irq_name);
	241	}
f204e0b8 IM	242	}
f204e0b8 IM	243
c358d84b	244	int afu_allocate_irqs(struct cxl_context *ctx, u32 count)
f204e0b8	245	{
80fa93fc MN	246	int rc, r, i, j = 1;
80fa93fc MN	247	struct cxl_irq_name *irq_name;
73d55c3b FB	248	int alloc_count;
	249
	250	/*
	251	* In native mode, range 0 is reserved for the multiplexed
	252	* PSL interrupt. It has been allocated when the AFU was initialized.
	253	*
	254	* In a guest, the PSL interrupt is not mutliplexed, but per-context,
	255	* and is the first interrupt from range 0. It still needs to be
	256	* allocated, so bump the count by one.
	257	*/
	258	if (cpu_has_feature(CPU_FTR_HVMODE))
	259	alloc_count = count;
	260	else
	261	alloc_count = count + 1;
f204e0b8	262
a6897f39 VJ	263	/* Initialize the list head to hold irq names */
	264	INIT_LIST_HEAD(&ctx->irq_names);
	265
5be587b1	266	if ((rc = cxl_ops->alloc_irq_ranges(&ctx->irqs, ctx->afu->adapter,
73d55c3b	267	alloc_count)))
f204e0b8 IM	268	return rc;
f204e0b8 IM	269
73d55c3b FB	270	if (cpu_has_feature(CPU_FTR_HVMODE)) {
73d55c3b FB	271	/* Multiplexed PSL Interrupt */
cbffa3a5	272	ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
73d55c3b FB	273	ctx->irqs.range[0] = 1;
73d55c3b FB	274	}
f204e0b8 IM	275
	276	ctx->irq_count = count;
	277	ctx->irq_bitmap = kcalloc(BITS_TO_LONGS(count),
	278	sizeof(*ctx->irq_bitmap), GFP_KERNEL);
	279	if (!ctx->irq_bitmap)
a6897f39	280	goto out;
80fa93fc MN	281
	282	/*
	283	* Allocate names first. If any fail, bail out before allocating
	284	* actual hardware IRQs.
	285	*/
73d55c3b	286	for (r = afu_irq_range_start(); r < CXL_IRQ_RANGES; r++) {
d3383aaa	287	for (i = 0; i < ctx->irqs.range[r]; i++) {
80fa93fc MN	288	irq_name = kmalloc(sizeof(struct cxl_irq_name),
	289	GFP_KERNEL);
	290	if (!irq_name)
	291	goto out;
	292	irq_name->name = kasprintf(GFP_KERNEL, "cxl-%s-pe%i-%i",
	293	dev_name(&ctx->afu->dev),
	294	ctx->pe, j);
	295	if (!irq_name->name) {
	296	kfree(irq_name);
	297	goto out;
	298	}
	299	/* Add to tail so next look get the correct order */
	300	list_add_tail(&irq_name->list, &ctx->irq_names);
	301	j++;
	302	}
	303	}
c358d84b MN	304	return 0;
	305
	306	out:
5be587b1	307	cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter);
c358d84b MN	308	afu_irq_name_free(ctx);
	309	return -ENOMEM;
	310	}
	311
3d6b040e	312	static void afu_register_hwirqs(struct cxl_context *ctx)
c358d84b MN	313	{
	314	irq_hw_number_t hwirq;
	315	struct cxl_irq_name *irq_name;
73d55c3b FB	316	int r, i;
73d55c3b FB	317	irqreturn_t (handler)(int irq, void data);
80fa93fc MN	318
	319	/* We've allocated all memory now, so let's do the irq allocations */
	320	irq_name = list_first_entry(&ctx->irq_names, struct cxl_irq_name, list);
73d55c3b	321	for (r = afu_irq_range_start(); r < CXL_IRQ_RANGES; r++) {
f204e0b8 IM	322	hwirq = ctx->irqs.offset[r];
f204e0b8 IM	323	for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
73d55c3b FB	324	if (r == 0 && i == 0)
	325	/*
	326	* The very first interrupt of range 0 is
	327	* always the PSL interrupt, but we only
	328	* need to connect a handler for guests,
	329	* because there's one PSL interrupt per
	330	* context.
	331	* On bare-metal, the PSL interrupt is
	332	* multiplexed and was setup when the AFU
	333	* was configured.
	334	*/
	335	handler = cxl_ops->psl_interrupt;
	336	else
	337	handler = cxl_irq_afu;
	338	cxl_map_irq(ctx->afu->adapter, hwirq, handler, ctx,
	339	irq_name->name);
80fa93fc	340	irq_name = list_next_entry(irq_name, list);
f204e0b8 IM	341	}
f204e0b8 IM	342	}
c358d84b	343	}
f204e0b8	344
c358d84b MN	345	int afu_register_irqs(struct cxl_context *ctx, u32 count)
	346	{
	347	int rc;
80fa93fc	348
c358d84b MN	349	rc = afu_allocate_irqs(ctx, count);
	350	if (rc)
	351	return rc;
	352
	353	afu_register_hwirqs(ctx);
	354	return 0;
d56d301b	355	}
f204e0b8	356
6428832a	357	void afu_release_irqs(struct cxl_context ctx, void cookie)
f204e0b8 IM	358	{
	359	irq_hw_number_t hwirq;
	360	unsigned int virq;
	361	int r, i;
	362
73d55c3b	363	for (r = afu_irq_range_start(); r < CXL_IRQ_RANGES; r++) {
f204e0b8 IM	364	hwirq = ctx->irqs.offset[r];
	365	for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
	366	virq = irq_find_mapping(NULL, hwirq);
	367	if (virq)
6428832a	368	cxl_unmap_irq(virq, cookie);
f204e0b8 IM	369	}
	370	}
	371
80fa93fc	372	afu_irq_name_free(ctx);
5be587b1	373	cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter);
8c7dd08a	374
8c7dd08a	375	ctx->irq_count = 0;
f204e0b8	376	}