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IB/mlx4: Suppress non-fatal memory allocations
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
5a0e3ad6 35#include <linux/slab.h>
fa417f7b 36#include <linux/netdevice.h>
0ef2f05c 37#include <linux/vmalloc.h>
ea54b10c 38
225c7b1f
RD		 39#include <rdma/ib_cache.h>
40#include <rdma/ib_pack.h>
4c3eb3ca 41#include <rdma/ib_addr.h>
1ffeb2eb 42#include <rdma/ib_mad.h>
225c7b1f 43
2f48485d 44#include <linux/mlx4/driver.h>
225c7b1f
RD		 45#include <linux/mlx4/qp.h>
46
47#include "mlx4_ib.h"
48#include "user.h"
49
35f05dab
YH		 50static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
51 struct mlx4_ib_cq *recv_cq);
52static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54
225c7b1f
RD		 55enum {
56 MLX4_IB_ACK_REQ_FREQ = 8,
57};
58
59enum {
60 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 61 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
62 MLX4_IB_LINK_TYPE_IB = 0,
63 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 64};
65
66enum {
67 /*
fa417f7b 68 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 69 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
70 * tag. (LRH would only use 8 bytes, so Ethernet is the
71 * biggest case)
225c7b1f 72 */
4c3eb3ca 73 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 74 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 75};
76
fa417f7b
EC		 77enum {
78 MLX4_IB_IBOE_ETHERTYPE = 0x8915
79};
80
225c7b1f
RD		 81struct mlx4_ib_sqp {
82 struct mlx4_ib_qp qp;
83 int pkey_index;
84 u32 qkey;
85 u32 send_psn;
86 struct ib_ud_header ud_header;
87 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
88};
89
83904132 90enum {
417608c2
EC		 91 MLX4_IB_MIN_SQ_STRIDE = 6,
92 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 93};
94
3987a2d3
OG		 95enum {
96 MLX4_RAW_QP_MTU = 7,
97 MLX4_RAW_QP_MSGMAX = 31,
98};
99
297e0dad
MS		 100#ifndef ETH_ALEN
101#define ETH_ALEN 6
102#endif
297e0dad 103
225c7b1f 104static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 105 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
106 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
107 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
108 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
109 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
110 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
111 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
112 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
113 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
114 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 115 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 116 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
117 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 118};
119
120static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
121{
122 return container_of(mqp, struct mlx4_ib_sqp, qp);
123}
124
1ffeb2eb
JM		 125static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
126{
127 if (!mlx4_is_master(dev->dev))
128 return 0;
129
47605df9
JM		 130 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
131 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
132 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 133}
134
225c7b1f
RD		 135static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
136{
47605df9
JM		 137 int proxy_sqp = 0;
138 int real_sqp = 0;
139 int i;
140 /* PPF or Native -- real SQP */
141 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
142 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
143 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
144 if (real_sqp)
145 return 1;
146 /* VF or PF -- proxy SQP */
147 if (mlx4_is_mfunc(dev->dev)) {
148 for (i = 0; i < dev->dev->caps.num_ports; i++) {
149 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
150 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
151 proxy_sqp = 1;
152 break;
153 }
154 }
155 }
156 return proxy_sqp;
225c7b1f
RD		 157}
158
1ffeb2eb 159/* used for INIT/CLOSE port logic */
225c7b1f
RD		 160static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
161{
47605df9
JM		 162 int proxy_qp0 = 0;
163 int real_qp0 = 0;
164 int i;
165 /* PPF or Native -- real QP0 */
166 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
167 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
168 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
169 if (real_qp0)
170 return 1;
171 /* VF or PF -- proxy QP0 */
172 if (mlx4_is_mfunc(dev->dev)) {
173 for (i = 0; i < dev->dev->caps.num_ports; i++) {
174 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
175 proxy_qp0 = 1;
176 break;
177 }
178 }
179 }
180 return proxy_qp0;
225c7b1f
RD		 181}
182
183static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
184{
1c69fc2a 185 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 186}
187
188static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
189{
190 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
191}
192
193static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
194{
195 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
196}
197
0e6e7416
RD		 198/*
199 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 200 * first four bytes of every 64 byte chunk with
201 * 0x7FFFFFF | (invalid_ownership_value << 31).
202 *
203 * When the max work request size is less than or equal to the WQE
204 * basic block size, as an optimization, we can stamp all WQEs with
205 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 206 */
ea54b10c 207static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 208{
d2ae16d5 209 __be32 *wqe;
0e6e7416 210 int i;
ea54b10c
JM		 211 int s;
212 int ind;
213 void *buf;
214 __be32 stamp;
9670e553 215 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 216
ea54b10c 217 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 218 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 219 for (i = 0; i < s; i += 64) {
220 ind = (i >> qp->sq.wqe_shift) + n;
221 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
222 cpu_to_be32(0xffffffff);
223 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
224 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
225 *wqe = stamp;
226 }
227 } else {
9670e553
EC		 228 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
229 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 230 for (i = 64; i < s; i += 64) {
231 wqe = buf + i;
d2ae16d5 232 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 233 }
234 }
235}
236
237static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
238{
239 struct mlx4_wqe_ctrl_seg *ctrl;
240 struct mlx4_wqe_inline_seg *inl;
241 void *wqe;
242 int s;
243
244 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
245 s = sizeof(struct mlx4_wqe_ctrl_seg);
246
247 if (qp->ibqp.qp_type == IB_QPT_UD) {
248 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
249 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
250 memset(dgram, 0, sizeof *dgram);
251 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
252 s += sizeof(struct mlx4_wqe_datagram_seg);
253 }
254
255 /* Pad the remainder of the WQE with an inline data segment. */
256 if (size > s) {
257 inl = wqe + s;
258 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
259 }
260 ctrl->srcrb_flags = 0;
261 ctrl->fence_size = size / 16;
262 /*
263 * Make sure descriptor is fully written before setting ownership bit
264 * (because HW can start executing as soon as we do).
265 */
266 wmb();
267
268 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
269 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 270
ea54b10c
JM		 271 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
272}
273
274/* Post NOP WQE to prevent wrap-around in the middle of WR */
275static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
276{
277 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
278 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
279 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
280 ind += s;
281 }
282 return ind;
0e6e7416
RD		 283}
284
225c7b1f
RD		 285static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
286{
287 struct ib_event event;
288 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
289
290 if (type == MLX4_EVENT_TYPE_PATH_MIG)
291 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
292
293 if (ibqp->event_handler) {
294 event.device = ibqp->device;
295 event.element.qp = ibqp;
296 switch (type) {
297 case MLX4_EVENT_TYPE_PATH_MIG:
298 event.event = IB_EVENT_PATH_MIG;
299 break;
300 case MLX4_EVENT_TYPE_COMM_EST:
301 event.event = IB_EVENT_COMM_EST;
302 break;
303 case MLX4_EVENT_TYPE_SQ_DRAINED:
304 event.event = IB_EVENT_SQ_DRAINED;
305 break;
306 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
307 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
308 break;
309 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
310 event.event = IB_EVENT_QP_FATAL;
311 break;
312 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
313 event.event = IB_EVENT_PATH_MIG_ERR;
314 break;
315 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
316 event.event = IB_EVENT_QP_REQ_ERR;
317 break;
318 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
319 event.event = IB_EVENT_QP_ACCESS_ERR;
320 break;
321 default:
987c8f8f 322 pr_warn("Unexpected event type %d "
225c7b1f
RD		 323 "on QP %06x\n", type, qp->qpn);
324 return;
325 }
326
327 ibqp->event_handler(&event, ibqp->qp_context);
328 }
329}
330
1ffeb2eb 331static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 332{
333 /*
334 * UD WQEs must have a datagram segment.
335 * RC and UC WQEs might have a remote address segment.
336 * MLX WQEs need two extra inline data segments (for the UD
337 * header and space for the ICRC).
338 */
339 switch (type) {
1ffeb2eb 340 case MLX4_IB_QPT_UD:
225c7b1f 341 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 342 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 343 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 344 case MLX4_IB_QPT_PROXY_SMI_OWNER:
345 case MLX4_IB_QPT_PROXY_SMI:
346 case MLX4_IB_QPT_PROXY_GSI:
347 return sizeof (struct mlx4_wqe_ctrl_seg) +
348 sizeof (struct mlx4_wqe_datagram_seg) + 64;
349 case MLX4_IB_QPT_TUN_SMI_OWNER:
350 case MLX4_IB_QPT_TUN_GSI:
351 return sizeof (struct mlx4_wqe_ctrl_seg) +
352 sizeof (struct mlx4_wqe_datagram_seg);
353
354 case MLX4_IB_QPT_UC:
225c7b1f
RD		 355 return sizeof (struct mlx4_wqe_ctrl_seg) +
356 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 357 case MLX4_IB_QPT_RC:
225c7b1f
RD		 358 return sizeof (struct mlx4_wqe_ctrl_seg) +
359 sizeof (struct mlx4_wqe_atomic_seg) +
360 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 361 case MLX4_IB_QPT_SMI:
362 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 363 return sizeof (struct mlx4_wqe_ctrl_seg) +
364 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 365 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
366 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 367 sizeof (struct mlx4_wqe_inline_seg),
368 sizeof (struct mlx4_wqe_data_seg)) +
369 ALIGN(4 +
370 sizeof (struct mlx4_wqe_inline_seg),
371 sizeof (struct mlx4_wqe_data_seg));
372 default:
373 return sizeof (struct mlx4_wqe_ctrl_seg);
374 }
375}
376
2446304d 377static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
0a1405da 378 int is_user, int has_rq, struct mlx4_ib_qp *qp)
225c7b1f 379{
2446304d 380 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 381 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
382 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 383 return -EINVAL;
384
0a1405da 385 if (!has_rq) {
a4cd7ed8
RD		 386 if (cap->max_recv_wr)
387 return -EINVAL;
2446304d 388
0e6e7416 389 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 390 } else {
391 /* HW requires >= 1 RQ entry with >= 1 gather entry */
392 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
393 return -EINVAL;
394
0e6e7416 395 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 396 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 397 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
398 }
2446304d 399
fc2d0044
SG		 400 /* leave userspace return values as they were, so as not to break ABI */
401 if (is_user) {
402 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
403 cap->max_recv_sge = qp->rq.max_gs;
404 } else {
405 cap->max_recv_wr = qp->rq.max_post =
406 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
407 cap->max_recv_sge = min(qp->rq.max_gs,
408 min(dev->dev->caps.max_sq_sg,
409 dev->dev->caps.max_rq_sg));
410 }
2446304d
EC		 411
412 return 0;
413}
414
415static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
1ffeb2eb 416 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 417{
ea54b10c
JM		 418 int s;
419
2446304d 420 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 421 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
422 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 423 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 424 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
425 return -EINVAL;
426
427 /*
428 * For MLX transport we need 2 extra S/G entries:
429 * one for the header and one for the checksum at the end
430 */
1ffeb2eb
JM		 431 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
432 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 433 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
434 return -EINVAL;
435
ea54b10c
JM		 436 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
437 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 438 send_wqe_overhead(type, qp->flags);
225c7b1f 439
cd155c1c
RD		 440 if (s > dev->dev->caps.max_sq_desc_sz)
441 return -EINVAL;
442
0e6e7416 443 /*
ea54b10c
JM		 444 * Hermon supports shrinking WQEs, such that a single work
445 * request can include multiple units of 1 << wqe_shift. This
446 * way, work requests can differ in size, and do not have to
447 * be a power of 2 in size, saving memory and speeding up send
448 * WR posting. Unfortunately, if we do this then the
449 * wqe_index field in CQEs can't be used to look up the WR ID
450 * anymore, so we do this only if selective signaling is off.
451 *
452 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 453 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 454 * constant-sized WRs to make sure a WR is always fully within
455 * a single page-sized chunk.
456 *
457 * Finally, we use NOP work requests to pad the end of the
458 * work queue, to avoid wrap-around in the middle of WR. We
459 * set NEC bit to avoid getting completions with error for
460 * these NOP WRs, but since NEC is only supported starting
461 * with firmware 2.2.232, we use constant-sized WRs for older
462 * firmware.
463 *
464 * And, since MLX QPs only support SEND, we use constant-sized
465 * WRs in this case.
466 *
467 * We look for the smallest value of wqe_shift such that the
468 * resulting number of wqes does not exceed device
469 * capabilities.
470 *
471 * We set WQE size to at least 64 bytes, this way stamping
472 * invalidates each WQE.
0e6e7416 473 */
ea54b10c
JM		 474 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
475 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 476 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
477 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
478 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 479 qp->sq.wqe_shift = ilog2(64);
480 else
481 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
482
483 for (;;) {
ea54b10c
JM		 484 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
485
486 /*
487 * We need to leave 2 KB + 1 WR of headroom in the SQ to
488 * allow HW to prefetch.
489 */
490 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
491 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
492 qp->sq_max_wqes_per_wr +
493 qp->sq_spare_wqes);
494
495 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
496 break;
497
498 if (qp->sq_max_wqes_per_wr <= 1)
499 return -EINVAL;
500
501 ++qp->sq.wqe_shift;
502 }
503
cd155c1c
RD		 504 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
505 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 506 send_wqe_overhead(type, qp->flags)) /
507 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 508
509 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
510 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 511 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
512 qp->rq.offset = 0;
0e6e7416 513 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 514 } else {
0e6e7416 515 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 516 qp->sq.offset = 0;
517 }
518
ea54b10c
JM		 519 cap->max_send_wr = qp->sq.max_post =
520 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 521 cap->max_send_sge = min(qp->sq.max_gs,
522 min(dev->dev->caps.max_sq_sg,
523 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 524 /* We don't support inline sends for kernel QPs (yet) */
525 cap->max_inline_data = 0;
225c7b1f
RD		 526
527 return 0;
528}
529
83904132
JM		 530static int set_user_sq_size(struct mlx4_ib_dev *dev,
531 struct mlx4_ib_qp *qp,
2446304d
EC		 532 struct mlx4_ib_create_qp *ucmd)
533{
83904132
JM		 534 /* Sanity check SQ size before proceeding */
535 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
536 ucmd->log_sq_stride >
537 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
538 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
539 return -EINVAL;
540
0e6e7416 541 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 542 qp->sq.wqe_shift = ucmd->log_sq_stride;
543
0e6e7416
RD		 544 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
545 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 546
547 return 0;
548}
549
1ffeb2eb
JM		 550static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
551{
552 int i;
553
554 qp->sqp_proxy_rcv =
555 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
556 GFP_KERNEL);
557 if (!qp->sqp_proxy_rcv)
558 return -ENOMEM;
559 for (i = 0; i < qp->rq.wqe_cnt; i++) {
560 qp->sqp_proxy_rcv[i].addr =
561 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
562 GFP_KERNEL);
563 if (!qp->sqp_proxy_rcv[i].addr)
564 goto err;
565 qp->sqp_proxy_rcv[i].map =
566 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
567 sizeof (struct mlx4_ib_proxy_sqp_hdr),
568 DMA_FROM_DEVICE);
cc47d369
SO		 569 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
570 kfree(qp->sqp_proxy_rcv[i].addr);
571 goto err;
572 }
1ffeb2eb
JM		 573 }
574 return 0;
575
576err:
577 while (i > 0) {
578 --i;
579 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
580 sizeof (struct mlx4_ib_proxy_sqp_hdr),
581 DMA_FROM_DEVICE);
582 kfree(qp->sqp_proxy_rcv[i].addr);
583 }
584 kfree(qp->sqp_proxy_rcv);
585 qp->sqp_proxy_rcv = NULL;
586 return -ENOMEM;
587}
588
589static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
590{
591 int i;
592
593 for (i = 0; i < qp->rq.wqe_cnt; i++) {
594 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
595 sizeof (struct mlx4_ib_proxy_sqp_hdr),
596 DMA_FROM_DEVICE);
597 kfree(qp->sqp_proxy_rcv[i].addr);
598 }
599 kfree(qp->sqp_proxy_rcv);
600}
601
0a1405da
SH		 602static int qp_has_rq(struct ib_qp_init_attr *attr)
603{
604 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
605 return 0;
606
607 return !attr->srq;
608}
609
99ec41d0
JM		 610static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
611{
612 int i;
613 for (i = 0; i < dev->caps.num_ports; i++) {
614 if (qpn == dev->caps.qp0_proxy[i])
615 return !!dev->caps.qp0_qkey[i];
616 }
617 return 0;
618}
619
7b59f0f9
EBE		 620static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
621 struct mlx4_ib_qp *qp)
622{
623 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
624 mlx4_counter_free(dev->dev, qp->counter_index->index);
625 list_del(&qp->counter_index->list);
626 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
627
628 kfree(qp->counter_index);
629 qp->counter_index = NULL;
630}
631
225c7b1f
RD		 632static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
633 struct ib_qp_init_attr *init_attr,
40f2287b
JK		 634 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
635 gfp_t gfp)
225c7b1f 636{
a3cdcbfa 637 int qpn;
225c7b1f 638 int err;
1ffeb2eb
JM		 639 struct mlx4_ib_sqp *sqp;
640 struct mlx4_ib_qp *qp;
641 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 642 struct mlx4_ib_cq *mcq;
643 unsigned long flags;
1ffeb2eb
JM		 644
645 /* When tunneling special qps, we use a plain UD qp */
646 if (sqpn) {
647 if (mlx4_is_mfunc(dev->dev) &&
648 (!mlx4_is_master(dev->dev) ||
649 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
650 if (init_attr->qp_type == IB_QPT_GSI)
651 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 652 else {
653 if (mlx4_is_master(dev->dev) ||
654 qp0_enabled_vf(dev->dev, sqpn))
655 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
656 else
657 qp_type = MLX4_IB_QPT_PROXY_SMI;
658 }
1ffeb2eb
JM		 659 }
660 qpn = sqpn;
661 /* add extra sg entry for tunneling */
662 init_attr->cap.max_recv_sge++;
663 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
664 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
665 container_of(init_attr,
666 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
667 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
668 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
669 !mlx4_is_master(dev->dev))
670 return -EINVAL;
671 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
672 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 673 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
674 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
675 tnl_init->port))
1ffeb2eb
JM		 676 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
677 else
678 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 679 /* we are definitely in the PPF here, since we are creating
680 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
681 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
682 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 683 sqpn = qpn;
684 }
685
686 if (!*caller_qp) {
687 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
688 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
689 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6fcd8d0d 690 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
1ffeb2eb
JM		 691 if (!sqp)
692 return -ENOMEM;
693 qp = &sqp->qp;
2f5bb473
JM		 694 qp->pri.vid = 0xFFFF;
695 qp->alt.vid = 0xFFFF;
1ffeb2eb 696 } else {
6fcd8d0d 697 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
1ffeb2eb
JM		 698 if (!qp)
699 return -ENOMEM;
2f5bb473
JM		 700 qp->pri.vid = 0xFFFF;
701 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 702 }
703 } else
704 qp = *caller_qp;
705
706 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 707
708 mutex_init(&qp->mutex);
709 spin_lock_init(&qp->sq.lock);
710 spin_lock_init(&qp->rq.lock);
fa417f7b 711 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 712 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 713
714 qp->state = IB_QPS_RESET;
ea54b10c
JM		 715 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
716 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 717
0a1405da 718 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
225c7b1f
RD		 719 if (err)
720 goto err;
721
722 if (pd->uobject) {
723 struct mlx4_ib_create_qp ucmd;
724
725 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
726 err = -EFAULT;
727 goto err;
728 }
729
0e6e7416
RD		 730 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
731
83904132 732 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 733 if (err)
734 goto err;
735
225c7b1f 736 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 737 qp->buf_size, 0, 0);
225c7b1f
RD		 738 if (IS_ERR(qp->umem)) {
739 err = PTR_ERR(qp->umem);
740 goto err;
741 }
742
743 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
744 ilog2(qp->umem->page_size), &qp->mtt);
745 if (err)
746 goto err_buf;
747
748 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
749 if (err)
750 goto err_mtt;
751
0a1405da 752 if (qp_has_rq(init_attr)) {
02d89b87
RD		 753 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
754 ucmd.db_addr, &qp->db);
755 if (err)
756 goto err_mtt;
757 }
225c7b1f 758 } else {
0e6e7416
RD		 759 qp->sq_no_prefetch = 0;
760
b832be1e
EC		 761 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
762 qp->flags |= MLX4_IB_QP_LSO;
763
c1c98501
MB		 764 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
765 if (dev->steering_support ==
766 MLX4_STEERING_MODE_DEVICE_MANAGED)
767 qp->flags |= MLX4_IB_QP_NETIF;
768 else
769 goto err;
770 }
771
1ffeb2eb 772 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 773 if (err)
774 goto err;
775
0a1405da 776 if (qp_has_rq(init_attr)) {
40f2287b 777 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
02d89b87
RD		 778 if (err)
779 goto err;
225c7b1f 780
02d89b87
RD		 781 *qp->db.db = 0;
782 }
225c7b1f 783
40f2287b 784 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
225c7b1f
RD		 785 err = -ENOMEM;
786 goto err_db;
787 }
788
789 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
790 &qp->mtt);
791 if (err)
792 goto err_buf;
793
40f2287b 794 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
225c7b1f
RD		 795 if (err)
796 goto err_mtt;
797
9afc60dc
LR		 798 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(u64),
799 gfp | __GFP_NOWARN);
0ef2f05c
WW		 800 if (!qp->sq.wrid)
801 qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
802 gfp, PAGE_KERNEL);
9afc60dc
LR		 803 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(u64),
804 gfp | __GFP_NOWARN);
0ef2f05c
WW		 805 if (!qp->rq.wrid)
806 qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
807 gfp, PAGE_KERNEL);
225c7b1f
RD		 808 if (!qp->sq.wrid || !qp->rq.wrid) {
809 err = -ENOMEM;
810 goto err_wrid;
811 }
225c7b1f
RD		 812 }
813
a3cdcbfa 814 if (sqpn) {
1ffeb2eb
JM		 815 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
816 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
817 if (alloc_proxy_bufs(pd->device, qp)) {
818 err = -ENOMEM;
819 goto err_wrid;
820 }
821 }
a3cdcbfa 822 } else {
ddae0349
EE		 823 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
824 * otherwise, the WQE BlueFlame setup flow wrongly causes
825 * VLAN insertion. */
3987a2d3 826 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 827 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 828 (init_attr->cap.max_send_wr ?
829 MLX4_RESERVE_ETH_BF_QP : 0) |
830 (init_attr->cap.max_recv_wr ?
831 MLX4_RESERVE_A0_QP : 0));
3987a2d3 832 else
c1c98501
MB		 833 if (qp->flags & MLX4_IB_QP_NETIF)
834 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
835 else
836 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
ddae0349 837 &qpn, 0);
a3cdcbfa 838 if (err)
1ffeb2eb 839 goto err_proxy;
a3cdcbfa
YP		 840 }
841
fbfb6625
EBE		 842 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
843 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
844
40f2287b 845 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
225c7b1f 846 if (err)
a3cdcbfa 847 goto err_qpn;
225c7b1f 848
0a1405da
SH		 849 if (init_attr->qp_type == IB_QPT_XRC_TGT)
850 qp->mqp.qpn |= (1 << 23);
851
225c7b1f
RD		 852 /*
853 * Hardware wants QPN written in big-endian order (after
854 * shifting) for send doorbell. Precompute this value to save
855 * a little bit when posting sends.
856 */
857 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
858
225c7b1f 859 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 860 if (!*caller_qp)
861 *caller_qp = qp;
35f05dab
YH		 862
863 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
864 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
865 to_mcq(init_attr->recv_cq));
866 /* Maintain device to QPs access, needed for further handling
867 * via reset flow
868 */
869 list_add_tail(&qp->qps_list, &dev->qp_list);
870 /* Maintain CQ to QPs access, needed for further handling
871 * via reset flow
872 */
873 mcq = to_mcq(init_attr->send_cq);
874 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
875 mcq = to_mcq(init_attr->recv_cq);
876 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
877 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
878 to_mcq(init_attr->recv_cq));
879 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 880 return 0;
881
a3cdcbfa 882err_qpn:
c1c98501
MB		 883 if (!sqpn) {
884 if (qp->flags & MLX4_IB_QP_NETIF)
885 mlx4_ib_steer_qp_free(dev, qpn, 1);
886 else
887 mlx4_qp_release_range(dev->dev, qpn, 1);
888 }
1ffeb2eb
JM		 889err_proxy:
890 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
891 free_proxy_bufs(pd->device, qp);
225c7b1f 892err_wrid:
23f1b384 893 if (pd->uobject) {
0a1405da
SH		 894 if (qp_has_rq(init_attr))
895 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 896 } else {
0ef2f05c
WW		 897 kvfree(qp->sq.wrid);
898 kvfree(qp->rq.wrid);
225c7b1f
RD		 899 }
900
901err_mtt:
902 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
903
904err_buf:
905 if (pd->uobject)
906 ib_umem_release(qp->umem);
907 else
908 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
909
910err_db:
0a1405da 911 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 912 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 913
914err:
1ffeb2eb
JM		 915 if (!*caller_qp)
916 kfree(qp);
225c7b1f
RD		 917 return err;
918}
919
920static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
921{
922 switch (state) {
923 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
924 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
925 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
926 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
927 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
928 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
929 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
930 default: return -1;
931 }
932}
933
934static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 935 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 936{
338a8fad 937 if (send_cq == recv_cq) {
35f05dab 938 spin_lock(&send_cq->lock);
338a8fad
RD		 939 __acquire(&recv_cq->lock);
940 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 941 spin_lock(&send_cq->lock);
225c7b1f
RD		 942 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
943 } else {
35f05dab 944 spin_lock(&recv_cq->lock);
225c7b1f
RD		 945 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
946 }
947}
948
949static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 950 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 951{
338a8fad
RD		 952 if (send_cq == recv_cq) {
953 __release(&recv_cq->lock);
35f05dab 954 spin_unlock(&send_cq->lock);
338a8fad 955 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 956 spin_unlock(&recv_cq->lock);
35f05dab 957 spin_unlock(&send_cq->lock);
225c7b1f
RD		 958 } else {
959 spin_unlock(&send_cq->lock);
35f05dab 960 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 961 }
962}
963
fa417f7b
EC		 964static void del_gid_entries(struct mlx4_ib_qp *qp)
965{
966 struct mlx4_ib_gid_entry *ge, *tmp;
967
968 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
969 list_del(&ge->list);
970 kfree(ge);
971 }
972}
973
0a1405da
SH		 974static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
975{
976 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
977 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
978 else
979 return to_mpd(qp->ibqp.pd);
980}
981
982static void get_cqs(struct mlx4_ib_qp *qp,
983 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
984{
985 switch (qp->ibqp.qp_type) {
986 case IB_QPT_XRC_TGT:
987 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
988 *recv_cq = *send_cq;
989 break;
990 case IB_QPT_XRC_INI:
991 *send_cq = to_mcq(qp->ibqp.send_cq);
992 *recv_cq = *send_cq;
993 break;
994 default:
995 *send_cq = to_mcq(qp->ibqp.send_cq);
996 *recv_cq = to_mcq(qp->ibqp.recv_cq);
997 break;
998 }
999}
1000
225c7b1f
RD		 1001static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1002 int is_user)
1003{
1004 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1005 unsigned long flags;
225c7b1f 1006
2f5bb473 1007 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1008 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1009 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1010 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1011 qp->mqp.qpn);
25476b02 1012 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1013 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1014 qp->pri.smac = 0;
25476b02 1015 qp->pri.smac_port = 0;
2f5bb473
JM		 1016 }
1017 if (qp->alt.smac) {
1018 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1019 qp->alt.smac = 0;
1020 }
1021 if (qp->pri.vid < 0x1000) {
1022 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1023 qp->pri.vid = 0xFFFF;
1024 qp->pri.candidate_vid = 0xFFFF;
1025 qp->pri.update_vid = 0;
1026 }
1027 if (qp->alt.vid < 0x1000) {
1028 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1029 qp->alt.vid = 0xFFFF;
1030 qp->alt.candidate_vid = 0xFFFF;
1031 qp->alt.update_vid = 0;
1032 }
1033 }
225c7b1f 1034
0a1405da 1035 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f 1036
35f05dab 1037 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1038 mlx4_ib_lock_cqs(send_cq, recv_cq);
1039
35f05dab
YH		 1040 /* del from lists under both locks above to protect reset flow paths */
1041 list_del(&qp->qps_list);
1042 list_del(&qp->cq_send_list);
1043 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1044 if (!is_user) {
1045 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1046 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1047 if (send_cq != recv_cq)
1048 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1049 }
1050
1051 mlx4_qp_remove(dev->dev, &qp->mqp);
1052
1053 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1054 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1055
1056 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1057
c1c98501
MB		 1058 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1059 if (qp->flags & MLX4_IB_QP_NETIF)
1060 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1061 else
1062 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1063 }
a3cdcbfa 1064
225c7b1f
RD		 1065 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1066
1067 if (is_user) {
0a1405da 1068 if (qp->rq.wqe_cnt)
02d89b87
RD		 1069 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1070 &qp->db);
225c7b1f
RD		 1071 ib_umem_release(qp->umem);
1072 } else {
0ef2f05c
WW		 1073 kvfree(qp->sq.wrid);
1074 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1075 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1076 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1077 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1078 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1079 if (qp->rq.wqe_cnt)
6296883c 1080 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1081 }
fa417f7b
EC		 1082
1083 del_gid_entries(qp);
225c7b1f
RD		 1084}
1085
47605df9
JM		 1086static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1087{
1088 /* Native or PPF */
1089 if (!mlx4_is_mfunc(dev->dev) ||
1090 (mlx4_is_master(dev->dev) &&
1091 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1092 return dev->dev->phys_caps.base_sqpn +
1093 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1094 attr->port_num - 1;
1095 }
1096 /* PF or VF -- creating proxies */
1097 if (attr->qp_type == IB_QPT_SMI)
1098 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1099 else
1100 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1101}
1102
225c7b1f
RD		 1103struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1104 struct ib_qp_init_attr *init_attr,
1105 struct ib_udata *udata)
1106{
1ffeb2eb 1107 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1108 int err;
fbfb6625 1109 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1110 u16 xrcdn = 0;
40f2287b 1111 gfp_t gfp;
225c7b1f 1112
40f2287b
JK		 1113 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1114 GFP_NOIO : GFP_KERNEL;
521e575b 1115 /*
1ffeb2eb
JM		 1116 * We only support LSO, vendor flag1, and multicast loopback blocking,
1117 * and only for kernel UD QPs.
521e575b 1118 */
1ffeb2eb
JM		 1119 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1120 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1121 MLX4_IB_SRIOV_TUNNEL_QP |
1122 MLX4_IB_SRIOV_SQP |
40f2287b
JK		 1123 MLX4_IB_QP_NETIF |
1124 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
b832be1e 1125 return ERR_PTR(-EINVAL);
521e575b 1126
c1c98501
MB		 1127 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1128 if (init_attr->qp_type != IB_QPT_UD)
1129 return ERR_PTR(-EINVAL);
1130 }
1131
521e575b 1132 if (init_attr->create_flags &&
fbfb6625
EBE		 1133 ((udata && init_attr->create_flags & ~(sup_u_create_flags)) ||
1134 ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1135 MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1136 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)) &&
1ffeb2eb
JM		 1137 init_attr->qp_type != IB_QPT_UD) ||
1138 ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1139 init_attr->qp_type > IB_QPT_GSI)))
b846f25a
EC		 1140 return ERR_PTR(-EINVAL);
1141
225c7b1f 1142 switch (init_attr->qp_type) {
0a1405da
SH		 1143 case IB_QPT_XRC_TGT:
1144 pd = to_mxrcd(init_attr->xrcd)->pd;
1145 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1146 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1147 /* fall through */
1148 case IB_QPT_XRC_INI:
1149 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1150 return ERR_PTR(-ENOSYS);
1151 init_attr->recv_cq = init_attr->send_cq;
1152 /* fall through */
225c7b1f
RD		 1153 case IB_QPT_RC:
1154 case IB_QPT_UC:
3987a2d3 1155 case IB_QPT_RAW_PACKET:
40f2287b 1156 qp = kzalloc(sizeof *qp, gfp);
225c7b1f
RD		 1157 if (!qp)
1158 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1159 qp->pri.vid = 0xFFFF;
1160 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1161 /* fall through */
1162 case IB_QPT_UD:
1163 {
1164 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
40f2287b 1165 udata, 0, &qp, gfp);
1ffeb2eb 1166 if (err)
225c7b1f 1167 return ERR_PTR(err);
225c7b1f
RD		 1168
1169 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1170 qp->xrcdn = xrcdn;
225c7b1f
RD		 1171
1172 break;
1173 }
1174 case IB_QPT_SMI:
1175 case IB_QPT_GSI:
1176 {
1177 /* Userspace is not allowed to create special QPs: */
0a1405da 1178 if (udata)
225c7b1f
RD		 1179 return ERR_PTR(-EINVAL);
1180
0a1405da 1181 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
47605df9 1182 get_sqp_num(to_mdev(pd->device), init_attr),
40f2287b 1183 &qp, gfp);
1ffeb2eb 1184 if (err)
225c7b1f 1185 return ERR_PTR(err);
225c7b1f
RD		 1186
1187 qp->port = init_attr->port_num;
1188 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1189
1190 break;
1191 }
1192 default:
1193 /* Don't support raw QPs */
1194 return ERR_PTR(-EINVAL);
1195 }
1196
1197 return &qp->ibqp;
1198}
1199
1200int mlx4_ib_destroy_qp(struct ib_qp *qp)
1201{
1202 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1203 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1204 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1205
1206 if (is_qp0(dev, mqp))
1207 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1208
9433c188
MB		 1209 if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1210 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1211 dev->qp1_proxy[mqp->port - 1] = NULL;
1212 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1213 }
1214
7b59f0f9
EBE		 1215 if (mqp->counter_index)
1216 mlx4_ib_free_qp_counter(dev, mqp);
1217
0a1405da
SH		 1218 pd = get_pd(mqp);
1219 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1220
1221 if (is_sqp(dev, mqp))
1222 kfree(to_msqp(mqp));
1223 else
1224 kfree(mqp);
1225
1226 return 0;
1227}
1228
1ffeb2eb 1229static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1230{
1231 switch (type) {
1ffeb2eb
JM		 1232 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1233 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1234 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1235 case MLX4_IB_QPT_XRC_INI:
1236 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1237 case MLX4_IB_QPT_SMI:
1238 case MLX4_IB_QPT_GSI:
1239 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1240
1241 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1242 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1243 MLX4_QP_ST_MLX : -1);
1244 case MLX4_IB_QPT_PROXY_SMI:
1245 case MLX4_IB_QPT_TUN_SMI:
1246 case MLX4_IB_QPT_PROXY_GSI:
1247 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1248 MLX4_QP_ST_UD : -1);
1249 default: return -1;
225c7b1f
RD		 1250 }
1251}
1252
65adfa91 1253static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1254 int attr_mask)
1255{
1256 u8 dest_rd_atomic;
1257 u32 access_flags;
1258 u32 hw_access_flags = 0;
1259
1260 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1261 dest_rd_atomic = attr->max_dest_rd_atomic;
1262 else
1263 dest_rd_atomic = qp->resp_depth;
1264
1265 if (attr_mask & IB_QP_ACCESS_FLAGS)
1266 access_flags = attr->qp_access_flags;
1267 else
1268 access_flags = qp->atomic_rd_en;
1269
1270 if (!dest_rd_atomic)
1271 access_flags &= IB_ACCESS_REMOTE_WRITE;
1272
1273 if (access_flags & IB_ACCESS_REMOTE_READ)
1274 hw_access_flags |= MLX4_QP_BIT_RRE;
1275 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1276 hw_access_flags |= MLX4_QP_BIT_RAE;
1277 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1278 hw_access_flags |= MLX4_QP_BIT_RWE;
1279
1280 return cpu_to_be32(hw_access_flags);
1281}
1282
65adfa91 1283static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1284 int attr_mask)
1285{
1286 if (attr_mask & IB_QP_PKEY_INDEX)
1287 sqp->pkey_index = attr->pkey_index;
1288 if (attr_mask & IB_QP_QKEY)
1289 sqp->qkey = attr->qkey;
1290 if (attr_mask & IB_QP_SQ_PSN)
1291 sqp->send_psn = attr->sq_psn;
1292}
1293
1294static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1295{
1296 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1297}
1298
297e0dad
MS		 1299static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1300 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1301 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1302{
fa417f7b
EC		 1303 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1304 IB_LINK_LAYER_ETHERNET;
4c3eb3ca 1305 int vidx;
297e0dad 1306 int smac_index;
2f5bb473 1307 int err;
297e0dad 1308
fa417f7b 1309
225c7b1f
RD		 1310 path->grh_mylmc = ah->src_path_bits & 0x7f;
1311 path->rlid = cpu_to_be16(ah->dlid);
1312 if (ah->static_rate) {
1313 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1314 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1315 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1316 --path->static_rate;
1317 } else
1318 path->static_rate = 0;
225c7b1f
RD		 1319
1320 if (ah->ah_flags & IB_AH_GRH) {
5070cd22
MS		 1321 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1322 port,
1323 ah->grh.sgid_index);
1324
1325 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1326 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1327 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1328 return -1;
1329 }
1330
1331 path->grh_mylmc |= 1 << 7;
5070cd22 1332 path->mgid_index = real_sgid_index;
225c7b1f
RD		 1333 path->hop_limit = ah->grh.hop_limit;
1334 path->tclass_flowlabel =
1335 cpu_to_be32((ah->grh.traffic_class << 20) |
1336 (ah->grh.flow_label));
1337 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1338 }
1339
fa417f7b
EC		 1340 if (is_eth) {
1341 if (!(ah->ah_flags & IB_AH_GRH))
1342 return -1;
1343
2f5bb473
JM		 1344 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1345 ((port - 1) << 6) | ((ah->sl & 7) << 3);
4c3eb3ca 1346
297e0dad 1347 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1348 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1349 if (smac_info->vid < 0x1000) {
1350 /* both valid vlan ids */
1351 if (smac_info->vid != vlan_tag) {
1352 /* different VIDs. unreg old and reg new */
1353 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1354 if (err)
1355 return err;
1356 smac_info->candidate_vid = vlan_tag;
1357 smac_info->candidate_vlan_index = vidx;
1358 smac_info->candidate_vlan_port = port;
1359 smac_info->update_vid = 1;
1360 path->vlan_index = vidx;
1361 } else {
1362 path->vlan_index = smac_info->vlan_index;
1363 }
1364 } else {
1365 /* no current vlan tag in qp */
1366 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1367 if (err)
1368 return err;
1369 smac_info->candidate_vid = vlan_tag;
1370 smac_info->candidate_vlan_index = vidx;
1371 smac_info->candidate_vlan_port = port;
1372 smac_info->update_vid = 1;
1373 path->vlan_index = vidx;
1374 }
297e0dad 1375 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1376 path->fl = 1 << 6;
1377 } else {
1378 /* have current vlan tag. unregister it at modify-qp success */
1379 if (smac_info->vid < 0x1000) {
1380 smac_info->candidate_vid = 0xFFFF;
1381 smac_info->update_vid = 1;
1382 }
4c3eb3ca 1383 }
2f5bb473
JM		 1384
1385 /* get smac_index for RoCE use.
1386 * If no smac was yet assigned, register one.
1387 * If one was already assigned, but the new mac differs,
1388 * unregister the old one and register the new one.
1389 */
25476b02
JM		 1390 if ((!smac_info->smac && !smac_info->smac_port) ||
1391 smac_info->smac != smac) {
2f5bb473
JM		 1392 /* register candidate now, unreg if needed, after success */
1393 smac_index = mlx4_register_mac(dev->dev, port, smac);
1394 if (smac_index >= 0) {
1395 smac_info->candidate_smac_index = smac_index;
1396 smac_info->candidate_smac = smac;
1397 smac_info->candidate_smac_port = port;
1398 } else {
1399 return -EINVAL;
1400 }
1401 } else {
1402 smac_index = smac_info->smac_index;
1403 }
1404
1405 memcpy(path->dmac, ah->dmac, 6);
1406 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1407 /* put MAC table smac index for IBoE */
1408 path->grh_mylmc = (u8) (smac_index) | 0x80;
1409 } else {
4c3eb3ca
EC		 1410 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1411 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
2f5bb473 1412 }
fa417f7b 1413
225c7b1f
RD		 1414 return 0;
1415}
1416
297e0dad
MS		 1417static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1418 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1419 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1420 struct mlx4_qp_path *path, u8 port,
1421 u16 vlan_id, u8 *smac)
297e0dad
MS		 1422{
1423 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1424 mlx4_mac_to_u64(smac),
1425 vlan_id,
2f5bb473 1426 path, &mqp->pri, port);
297e0dad
MS		 1427}
1428
1429static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1430 const struct ib_qp_attr *qp,
1431 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1432 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1433 struct mlx4_qp_path *path, u8 port)
1434{
1435 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1436 0,
1437 0xffff,
2f5bb473 1438 path, &mqp->alt, port);
297e0dad
MS		 1439}
1440
fa417f7b
EC		 1441static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1442{
1443 struct mlx4_ib_gid_entry *ge, *tmp;
1444
1445 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1446 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1447 ge->added = 1;
1448 ge->port = qp->port;
1449 }
1450 }
1451}
1452
dbf727de
MB		 1453static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1454 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1455 struct mlx4_qp_context *context)
1456{
2f5bb473
JM		 1457 u64 u64_mac;
1458 int smac_index;
1459
3e0629cb 1460 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1461
1462 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1463 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1464 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1465 if (smac_index >= 0) {
1466 qp->pri.candidate_smac_index = smac_index;
1467 qp->pri.candidate_smac = u64_mac;
1468 qp->pri.candidate_smac_port = qp->port;
1469 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1470 } else {
1471 return -ENOENT;
1472 }
1473 }
1474 return 0;
1475}
1476
7b59f0f9
EBE		 1477static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1478{
1479 struct counter_index *new_counter_index;
1480 int err;
1481 u32 tmp_idx;
1482
1483 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1484 IB_LINK_LAYER_ETHERNET ||
1485 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1486 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1487 return 0;
1488
1489 err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1490 if (err)
1491 return err;
1492
1493 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1494 if (!new_counter_index) {
1495 mlx4_counter_free(dev->dev, tmp_idx);
1496 return -ENOMEM;
1497 }
1498
1499 new_counter_index->index = tmp_idx;
1500 new_counter_index->allocated = 1;
1501 qp->counter_index = new_counter_index;
1502
1503 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1504 list_add_tail(&new_counter_index->list,
1505 &dev->counters_table[qp->port - 1].counters_list);
1506 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1507
1508 return 0;
1509}
1510
65adfa91
MT		 1511static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1512 const struct ib_qp_attr *attr, int attr_mask,
1513 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1514{
1515 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1516 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1517 struct mlx4_ib_pd *pd;
1518 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1519 struct mlx4_qp_context *context;
1520 enum mlx4_qp_optpar optpar = 0;
225c7b1f 1521 int sqd_event;
c1c98501 1522 int steer_qp = 0;
225c7b1f 1523 int err = -EINVAL;
3ba8e31d 1524 int counter_index;
225c7b1f 1525
3dec4878
JM		 1526 /* APM is not supported under RoCE */
1527 if (attr_mask & IB_QP_ALT_PATH &&
1528 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1529 IB_LINK_LAYER_ETHERNET)
1530 return -ENOTSUPP;
1531
225c7b1f
RD		 1532 context = kzalloc(sizeof *context, GFP_KERNEL);
1533 if (!context)
1534 return -ENOMEM;
1535
225c7b1f 1536 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1537 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1538
1539 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1540 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1541 else {
1542 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1543 switch (attr->path_mig_state) {
1544 case IB_MIG_MIGRATED:
1545 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1546 break;
1547 case IB_MIG_REARM:
1548 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1549 break;
1550 case IB_MIG_ARMED:
1551 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1552 break;
1553 }
1554 }
1555
b832be1e 1556 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1557 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1558 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1559 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1560 else if (ibqp->qp_type == IB_QPT_UD) {
1561 if (qp->flags & MLX4_IB_QP_LSO)
1562 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1563 ilog2(dev->dev->caps.max_gso_sz);
1564 else
6e0d733d 1565 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1566 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1567 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1568 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1569 attr->path_mtu);
f5b40431 1570 goto out;
225c7b1f 1571 }
d1f2cd89
EC		 1572 context->mtu_msgmax = (attr->path_mtu << 5) |
1573 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1574 }
1575
0e6e7416
RD		 1576 if (qp->rq.wqe_cnt)
1577 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1578 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1579
0e6e7416
RD		 1580 if (qp->sq.wqe_cnt)
1581 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1582 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1583
7b59f0f9
EBE		 1584 if (new_state == IB_QPS_RESET && qp->counter_index)
1585 mlx4_ib_free_qp_counter(dev, qp);
1586
0a1405da 1587 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1588 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 1589 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
02d7ef6f
DB		 1590 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1591 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 1592 }
0e6e7416 1593
225c7b1f
RD		 1594 if (qp->ibqp.uobject)
1595 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1596 else
1597 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1598
1599 if (attr_mask & IB_QP_DEST_QPN)
1600 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1601
1602 if (attr_mask & IB_QP_PORT) {
1603 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1604 !(attr_mask & IB_QP_AV)) {
1605 mlx4_set_sched(&context->pri_path, attr->port_num);
1606 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1607 }
1608 }
1609
cfcde11c 1610 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 1611 err = create_qp_lb_counter(dev, qp);
1612 if (err)
1613 goto out;
1614
3ba8e31d
EBE		 1615 counter_index =
1616 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 1617 if (qp->counter_index)
1618 counter_index = qp->counter_index->index;
1619
3ba8e31d
EBE		 1620 if (counter_index != -1) {
1621 context->pri_path.counter_index = counter_index;
cfcde11c 1622 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 1623 if (qp->counter_index) {
1624 context->pri_path.fl |=
1625 MLX4_FL_ETH_SRC_CHECK_MC_LB;
1626 context->pri_path.vlan_control |=
1627 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1628 }
cfcde11c 1629 } else
47d8417f
EBE		 1630 context->pri_path.counter_index =
1631 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 1632
1633 if (qp->flags & MLX4_IB_QP_NETIF) {
1634 mlx4_ib_steer_qp_reg(dev, qp, 1);
1635 steer_qp = 1;
1636 }
cfcde11c
OG		 1637 }
1638
225c7b1f 1639 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1640 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1641 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1642 context->pri_path.pkey_index = attr->pkey_index;
1643 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1644 }
1645
225c7b1f 1646 if (attr_mask & IB_QP_AV) {
dbf727de
MB		 1647 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1648 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1649 union ib_gid gid;
1650 struct ib_gid_attr gid_attr;
1651 u16 vlan = 0xffff;
1652 u8 smac[ETH_ALEN];
1653 int status = 0;
1654
1655 if (rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1656 attr->ah_attr.ah_flags & IB_AH_GRH) {
1657 int index = attr->ah_attr.grh.sgid_index;
1658
1659 status = ib_get_cached_gid(ibqp->device, port_num,
1660 index, &gid, &gid_attr);
1661 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1662 status = -ENOENT;
1663 if (!status && gid_attr.ndev) {
1664 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1665 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1666 dev_put(gid_attr.ndev);
1667 }
1668 }
1669 if (status)
1670 goto out;
1671
2f5bb473 1672 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 1673 port_num, vlan, smac))
225c7b1f 1674 goto out;
225c7b1f
RD		 1675
1676 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1677 MLX4_QP_OPTPAR_SCHED_QUEUE);
1678 }
1679
1680 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1681 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1682 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1683 }
1684
1685 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1686 if (attr->alt_port_num == 0 ||
1687 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1688 goto out;
225c7b1f 1689
5ae2a7a8
RD		 1690 if (attr->alt_pkey_index >=
1691 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1692 goto out;
5ae2a7a8 1693
2f5bb473
JM		 1694 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1695 &context->alt_path,
297e0dad 1696 attr->alt_port_num))
f5b40431 1697 goto out;
225c7b1f
RD		 1698
1699 context->alt_path.pkey_index = attr->alt_pkey_index;
1700 context->alt_path.ackto = attr->alt_timeout << 3;
1701 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1702 }
1703
0a1405da
SH		 1704 pd = get_pd(qp);
1705 get_cqs(qp, &send_cq, &recv_cq);
1706 context->pd = cpu_to_be32(pd->pdn);
1707 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1708 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1709 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1710
95d04f07
RD		 1711 /* Set "fast registration enabled" for all kernel QPs */
1712 if (!qp->ibqp.uobject)
1713 context->params1 |= cpu_to_be32(1 << 11);
1714
57f01b53
JM		 1715 if (attr_mask & IB_QP_RNR_RETRY) {
1716 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1717 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1718 }
1719
225c7b1f
RD		 1720 if (attr_mask & IB_QP_RETRY_CNT) {
1721 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1722 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1723 }
1724
1725 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1726 if (attr->max_rd_atomic)
1727 context->params1 |=
1728 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1729 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1730 }
1731
1732 if (attr_mask & IB_QP_SQ_PSN)
1733 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1734
225c7b1f
RD		 1735 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1736 if (attr->max_dest_rd_atomic)
1737 context->params2 |=
1738 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1739 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1740 }
1741
1742 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1743 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1744 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1745 }
1746
1747 if (ibqp->srq)
1748 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1749
1750 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1751 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1752 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1753 }
1754 if (attr_mask & IB_QP_RQ_PSN)
1755 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1756
1ffeb2eb 1757 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1758 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1759 if (qp->mlx4_ib_qp_type &
1760 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1761 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1762 else {
1763 if (mlx4_is_mfunc(dev->dev) &&
1764 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1765 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1766 MLX4_RESERVED_QKEY_BASE) {
1767 pr_err("Cannot use reserved QKEY"
1768 " 0x%x (range 0xffff0000..0xffffffff"
1769 " is reserved)\n", attr->qkey);
1770 err = -EINVAL;
1771 goto out;
1772 }
1773 context->qkey = cpu_to_be32(attr->qkey);
1774 }
225c7b1f
RD		 1775 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1776 }
1777
1778 if (ibqp->srq)
1779 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1780
0a1405da 1781 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1782 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1783
1784 if (cur_state == IB_QPS_INIT &&
1785 new_state == IB_QPS_RTR &&
1786 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1787 ibqp->qp_type == IB_QPT_UD ||
1788 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1789 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1790 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1791 qp->mlx4_ib_qp_type &
1792 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1793 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1794 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1795 context->pri_path.fl = 0x80;
1796 } else {
1797 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1798 context->pri_path.fl = 0x80;
225c7b1f 1799 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1800 }
2f5bb473
JM		 1801 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1802 IB_LINK_LAYER_ETHERNET) {
1803 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1804 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1805 context->pri_path.feup = 1 << 7; /* don't fsm */
1806 /* handle smac_index */
1807 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1808 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1809 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 1810 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 1811 if (err) {
1812 err = -EINVAL;
1813 goto out;
1814 }
9433c188
MB		 1815 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1816 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 1817 }
1818 }
225c7b1f
RD		 1819 }
1820
d2fce8a9 1821 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 1822 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1823 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 1824 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1825 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 1826 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 1827 context->srqn = cpu_to_be32(7 << 28);
1828 }
1829 }
3528f696 1830
297e0dad
MS		 1831 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1832 int is_eth = rdma_port_get_link_layer(
1833 &dev->ib_dev, qp->port) ==
1834 IB_LINK_LAYER_ETHERNET;
1835 if (is_eth) {
1836 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1837 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1838 }
1839 }
1840
1841
225c7b1f
RD		 1842 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1843 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1844 sqd_event = 1;
1845 else
1846 sqd_event = 0;
1847
d57f5f72
VS		 1848 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1849 context->rlkey |= (1 << 4);
1850
c0be5fb5
EC		 1851 /*
1852 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1853 * ownership bits of the send queue are set and the SQ
1854 * headroom is stamped so that the hardware doesn't start
1855 * processing stale work requests.
c0be5fb5
EC		 1856 */
1857 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1858 struct mlx4_wqe_ctrl_seg *ctrl;
1859 int i;
1860
0e6e7416 1861 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1862 ctrl = get_send_wqe(qp, i);
1863 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1864 if (qp->sq_max_wqes_per_wr == 1)
1865 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1866
ea54b10c 1867 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1868 }
1869 }
1870
225c7b1f
RD		 1871 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1872 to_mlx4_state(new_state), context, optpar,
1873 sqd_event, &qp->mqp);
1874 if (err)
1875 goto out;
1876
1877 qp->state = new_state;
1878
1879 if (attr_mask & IB_QP_ACCESS_FLAGS)
1880 qp->atomic_rd_en = attr->qp_access_flags;
1881 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1882 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 1883 if (attr_mask & IB_QP_PORT) {
225c7b1f 1884 qp->port = attr->port_num;
fa417f7b
EC		 1885 update_mcg_macs(dev, qp);
1886 }
225c7b1f
RD		 1887 if (attr_mask & IB_QP_ALT_PATH)
1888 qp->alt_port = attr->alt_port_num;
1889
1890 if (is_sqp(dev, qp))
1891 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1892
1893 /*
1894 * If we moved QP0 to RTR, bring the IB link up; if we moved
1895 * QP0 to RESET or ERROR, bring the link back down.
1896 */
1897 if (is_qp0(dev, qp)) {
1898 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 1899 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 1900 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 1901 qp->port);
225c7b1f
RD		 1902
1903 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1904 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1905 mlx4_CLOSE_PORT(dev->dev, qp->port);
1906 }
1907
1908 /*
1909 * If we moved a kernel QP to RESET, clean up all old CQ
1910 * entries and reinitialize the QP.
1911 */
2f5bb473
JM		 1912 if (new_state == IB_QPS_RESET) {
1913 if (!ibqp->uobject) {
1914 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1915 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1916 if (send_cq != recv_cq)
1917 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1918
1919 qp->rq.head = 0;
1920 qp->rq.tail = 0;
1921 qp->sq.head = 0;
1922 qp->sq.tail = 0;
1923 qp->sq_next_wqe = 0;
1924 if (qp->rq.wqe_cnt)
1925 *qp->db.db = 0;
225c7b1f 1926
2f5bb473
JM		 1927 if (qp->flags & MLX4_IB_QP_NETIF)
1928 mlx4_ib_steer_qp_reg(dev, qp, 0);
1929 }
25476b02 1930 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1931 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1932 qp->pri.smac = 0;
25476b02 1933 qp->pri.smac_port = 0;
2f5bb473
JM		 1934 }
1935 if (qp->alt.smac) {
1936 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1937 qp->alt.smac = 0;
1938 }
1939 if (qp->pri.vid < 0x1000) {
1940 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1941 qp->pri.vid = 0xFFFF;
1942 qp->pri.candidate_vid = 0xFFFF;
1943 qp->pri.update_vid = 0;
1944 }
c1c98501 1945
2f5bb473
JM		 1946 if (qp->alt.vid < 0x1000) {
1947 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1948 qp->alt.vid = 0xFFFF;
1949 qp->alt.candidate_vid = 0xFFFF;
1950 qp->alt.update_vid = 0;
1951 }
225c7b1f 1952 }
225c7b1f 1953out:
7b59f0f9
EBE		 1954 if (err && qp->counter_index)
1955 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 1956 if (err && steer_qp)
1957 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 1958 kfree(context);
25476b02
JM		 1959 if (qp->pri.candidate_smac ||
1960 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 1961 if (err) {
1962 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1963 } else {
25476b02 1964 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 1965 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1966 qp->pri.smac = qp->pri.candidate_smac;
1967 qp->pri.smac_index = qp->pri.candidate_smac_index;
1968 qp->pri.smac_port = qp->pri.candidate_smac_port;
1969 }
1970 qp->pri.candidate_smac = 0;
1971 qp->pri.candidate_smac_index = 0;
1972 qp->pri.candidate_smac_port = 0;
1973 }
1974 if (qp->alt.candidate_smac) {
1975 if (err) {
1976 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1977 } else {
1978 if (qp->alt.smac)
1979 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1980 qp->alt.smac = qp->alt.candidate_smac;
1981 qp->alt.smac_index = qp->alt.candidate_smac_index;
1982 qp->alt.smac_port = qp->alt.candidate_smac_port;
1983 }
1984 qp->alt.candidate_smac = 0;
1985 qp->alt.candidate_smac_index = 0;
1986 qp->alt.candidate_smac_port = 0;
1987 }
1988
1989 if (qp->pri.update_vid) {
1990 if (err) {
1991 if (qp->pri.candidate_vid < 0x1000)
1992 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1993 qp->pri.candidate_vid);
1994 } else {
1995 if (qp->pri.vid < 0x1000)
1996 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1997 qp->pri.vid);
1998 qp->pri.vid = qp->pri.candidate_vid;
1999 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2000 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2001 }
2002 qp->pri.candidate_vid = 0xFFFF;
2003 qp->pri.update_vid = 0;
2004 }
2005
2006 if (qp->alt.update_vid) {
2007 if (err) {
2008 if (qp->alt.candidate_vid < 0x1000)
2009 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2010 qp->alt.candidate_vid);
2011 } else {
2012 if (qp->alt.vid < 0x1000)
2013 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2014 qp->alt.vid);
2015 qp->alt.vid = qp->alt.candidate_vid;
2016 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2017 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2018 }
2019 qp->alt.candidate_vid = 0xFFFF;
2020 qp->alt.update_vid = 0;
2021 }
2022
225c7b1f
RD		 2023 return err;
2024}
2025
65adfa91
MT		 2026int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2027 int attr_mask, struct ib_udata *udata)
2028{
2029 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2030 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2031 enum ib_qp_state cur_state, new_state;
2032 int err = -EINVAL;
297e0dad 2033 int ll;
65adfa91
MT		 2034 mutex_lock(&qp->mutex);
2035
2036 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2037 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2038
297e0dad
MS		 2039 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2040 ll = IB_LINK_LAYER_UNSPECIFIED;
2041 } else {
2042 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2043 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2044 }
dd5f03be
MB		 2045
2046 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 2047 attr_mask, ll)) {
b1d8eb5a
JM		 2048 pr_debug("qpn 0x%x: invalid attribute mask specified "
2049 "for transition %d to %d. qp_type %d,"
2050 " attr_mask 0x%x\n",
2051 ibqp->qp_num, cur_state, new_state,
2052 ibqp->qp_type, attr_mask);
65adfa91 2053 goto out;
b1d8eb5a 2054 }
65adfa91 2055
c6215745
MS		 2056 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2057 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2058 if ((ibqp->qp_type == IB_QPT_RC) ||
2059 (ibqp->qp_type == IB_QPT_UD) ||
2060 (ibqp->qp_type == IB_QPT_UC) ||
2061 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2062 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2063 attr->port_num = mlx4_ib_bond_next_port(dev);
2064 }
2065 } else {
2066 /* no sense in changing port_num
2067 * when ports are bonded */
2068 attr_mask &= ~IB_QP_PORT;
2069 }
2070 }
2071
65adfa91 2072 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2073 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2074 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2075 "for transition %d to %d. qp_type %d\n",
2076 ibqp->qp_num, attr->port_num, cur_state,
2077 new_state, ibqp->qp_type);
65adfa91
MT		 2078 goto out;
2079 }
2080
3987a2d3
OG		 2081 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2082 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2083 IB_LINK_LAYER_ETHERNET))
2084 goto out;
2085
5ae2a7a8
RD		 2086 if (attr_mask & IB_QP_PKEY_INDEX) {
2087 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2088 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2089 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2090 "for transition %d to %d. qp_type %d\n",
2091 ibqp->qp_num, attr->pkey_index, cur_state,
2092 new_state, ibqp->qp_type);
5ae2a7a8 2093 goto out;
b1d8eb5a 2094 }
5ae2a7a8
RD		 2095 }
2096
65adfa91
MT		 2097 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2098 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2099 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2100 "Transition %d to %d. qp_type %d\n",
2101 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2102 new_state, ibqp->qp_type);
65adfa91
MT		 2103 goto out;
2104 }
2105
2106 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2107 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2108 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2109 "Transition %d to %d. qp_type %d\n",
2110 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2111 new_state, ibqp->qp_type);
65adfa91
MT		 2112 goto out;
2113 }
2114
2115 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2116 err = 0;
2117 goto out;
2118 }
2119
65adfa91
MT		 2120 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2121
c6215745
MS		 2122 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2123 attr->port_num = 1;
2124
65adfa91
MT		 2125out:
2126 mutex_unlock(&qp->mutex);
2127 return err;
2128}
2129
99ec41d0
JM		 2130static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2131{
2132 int i;
2133 for (i = 0; i < dev->caps.num_ports; i++) {
2134 if (qpn == dev->caps.qp0_proxy[i] ||
2135 qpn == dev->caps.qp0_tunnel[i]) {
2136 *qkey = dev->caps.qp0_qkey[i];
2137 return 0;
2138 }
2139 }
2140 return -EINVAL;
2141}
2142
1ffeb2eb 2143static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
e622f2f4 2144 struct ib_ud_wr *wr,
1ffeb2eb
JM		 2145 void *wqe, unsigned *mlx_seg_len)
2146{
2147 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2148 struct ib_device *ib_dev = &mdev->ib_dev;
2149 struct mlx4_wqe_mlx_seg *mlx = wqe;
2150 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2151 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2152 u16 pkey;
2153 u32 qkey;
2154 int send_size;
2155 int header_size;
2156 int spc;
2157 int i;
2158
e622f2f4 2159 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2160 return -EINVAL;
2161
2162 send_size = 0;
2163
e622f2f4
CH		 2164 for (i = 0; i < wr->wr.num_sge; ++i)
2165 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2166
2167 /* for proxy-qp0 sends, need to add in size of tunnel header */
2168 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2169 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2170 send_size += sizeof (struct mlx4_ib_tunnel_header);
2171
25f40220 2172 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2173
2174 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2175 sqp->ud_header.lrh.service_level =
2176 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2177 sqp->ud_header.lrh.destination_lid =
2178 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2179 sqp->ud_header.lrh.source_lid =
2180 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2181 }
2182
2183 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2184
2185 /* force loopback */
2186 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2187 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2188
2189 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2190 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2191 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2192 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2193 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2194 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2195 else
2196 sqp->ud_header.bth.destination_qpn =
47605df9 2197 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2198
2199 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2200 if (mlx4_is_master(mdev->dev)) {
2201 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2202 return -EINVAL;
2203 } else {
2204 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2205 return -EINVAL;
2206 }
1ffeb2eb
JM		 2207 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2208 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2209
2210 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2211 sqp->ud_header.immediate_present = 0;
2212
2213 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2214
2215 /*
2216 * Inline data segments may not cross a 64 byte boundary. If
2217 * our UD header is bigger than the space available up to the
2218 * next 64 byte boundary in the WQE, use two inline data
2219 * segments to hold the UD header.
2220 */
2221 spc = MLX4_INLINE_ALIGN -
2222 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2223 if (header_size <= spc) {
2224 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2225 memcpy(inl + 1, sqp->header_buf, header_size);
2226 i = 1;
2227 } else {
2228 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2229 memcpy(inl + 1, sqp->header_buf, spc);
2230
2231 inl = (void *) (inl + 1) + spc;
2232 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2233 /*
2234 * Need a barrier here to make sure all the data is
2235 * visible before the byte_count field is set.
2236 * Otherwise the HCA prefetcher could grab the 64-byte
2237 * chunk with this inline segment and get a valid (!=
2238 * 0xffffffff) byte count but stale data, and end up
2239 * generating a packet with bad headers.
2240 *
2241 * The first inline segment's byte_count field doesn't
2242 * need a barrier, because it comes after a
2243 * control/MLX segment and therefore is at an offset
2244 * of 16 mod 64.
2245 */
2246 wmb();
2247 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2248 i = 2;
2249 }
2250
2251 *mlx_seg_len =
2252 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2253 return 0;
2254}
2255
3e0629cb
JM		 2256static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2257{
2258 int i;
2259
2260 for (i = ETH_ALEN; i; i--) {
2261 dst_mac[i - 1] = src_mac & 0xff;
2262 src_mac >>= 8;
2263 }
2264}
2265
e622f2f4 2266static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
f438000f 2267 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2268{
a478868a 2269 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f 2270 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2271 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 2272 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2273 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 2274 union ib_gid sgid;
225c7b1f
RD		 2275 u16 pkey;
2276 int send_size;
2277 int header_size;
e61ef241 2278 int spc;
225c7b1f 2279 int i;
1ffeb2eb 2280 int err = 0;
57d88cff 2281 u16 vlan = 0xffff;
a29bec12
RD		 2282 bool is_eth;
2283 bool is_vlan = false;
2284 bool is_grh;
225c7b1f
RD		 2285
2286 send_size = 0;
e622f2f4
CH		 2287 for (i = 0; i < wr->wr.num_sge; ++i)
2288 send_size += wr->wr.sg_list[i].length;
225c7b1f 2289
fa417f7b
EC		 2290 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2291 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2292 if (is_eth) {
1ffeb2eb
JM		 2293 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2294 /* When multi-function is enabled, the ib_core gid
2295 * indexes don't necessarily match the hw ones, so
2296 * we must use our own cache */
6ee51a4e
JM		 2297 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2298 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2299 ah->av.ib.gid_index, &sgid.raw[0]);
2300 if (err)
2301 return err;
1ffeb2eb
JM		 2302 } else {
2303 err = ib_get_cached_gid(ib_dev,
2304 be32_to_cpu(ah->av.ib.port_pd) >> 24,
55ee3ab2
MB		 2305 ah->av.ib.gid_index, &sgid,
2306 NULL);
dbf727de
MB		 2307 if (!err && !memcmp(&sgid, &zgid, sizeof(sgid)))
2308 err = -ENOENT;
1ffeb2eb
JM		 2309 if (err)
2310 return err;
2311 }
2312
0e9855db 2313 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2314 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2315 is_vlan = 1;
2316 }
4c3eb3ca 2317 }
25f40220
MS		 2318 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
2319 0, 0, 0, &sqp->ud_header);
2320 if (err)
2321 return err;
fa417f7b
EC		 2322
2323 if (!is_eth) {
2324 sqp->ud_header.lrh.service_level =
2325 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2326 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2327 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2328 }
225c7b1f 2329
fa417f7b 2330 if (is_grh) {
225c7b1f 2331 sqp->ud_header.grh.traffic_class =
fa417f7b 2332 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 2333 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 2334 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2335 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
6ee51a4e
JM		 2336 if (is_eth)
2337 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2338 else {
1ffeb2eb
JM		 2339 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2340 /* When multi-function is enabled, the ib_core gid
2341 * indexes don't necessarily match the hw ones, so
2342 * we must use our own cache */
2343 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2344 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2345 subnet_prefix;
2346 sqp->ud_header.grh.source_gid.global.interface_id =
2347 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2348 guid_cache[ah->av.ib.gid_index];
2349 } else
2350 ib_get_cached_gid(ib_dev,
2351 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2352 ah->av.ib.gid_index,
55ee3ab2 2353 &sqp->ud_header.grh.source_gid, NULL);
6ee51a4e 2354 }
225c7b1f 2355 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 2356 ah->av.ib.dgid, 16);
225c7b1f
RD		 2357 }
2358
2359 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 2360
2361 if (!is_eth) {
2362 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2363 (sqp->ud_header.lrh.destination_lid ==
2364 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2365 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 2366 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2367 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 2368 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2369 }
225c7b1f 2370
e622f2f4 2371 switch (wr->wr.opcode) {
225c7b1f
RD		 2372 case IB_WR_SEND:
2373 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2374 sqp->ud_header.immediate_present = 0;
2375 break;
2376 case IB_WR_SEND_WITH_IMM:
2377 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2378 sqp->ud_header.immediate_present = 1;
e622f2f4 2379 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 2380 break;
2381 default:
2382 return -EINVAL;
2383 }
2384
fa417f7b 2385 if (is_eth) {
6ee51a4e
JM		 2386 struct in6_addr in6;
2387
c0c1d3d7
OD		 2388 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2389
2390 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b
EC		 2391
2392 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2393 /* FIXME: cache smac value? */
6ee51a4e
JM		 2394 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2395 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2396 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 2397
3e0629cb
JM		 2398 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2399 u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2400 u8 smac[ETH_ALEN];
2401
2402 mlx4_u64_to_smac(smac, mac);
2403 memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2404 } else {
2405 /* use the src mac of the tunnel */
2406 memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2407 }
2408
fa417f7b
EC		 2409 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2410 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca
EC		 2411 if (!is_vlan) {
2412 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2413 } else {
4c3eb3ca 2414 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
4c3eb3ca
EC		 2415 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2416 }
fa417f7b
EC		 2417 } else {
2418 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
2419 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2420 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2421 }
e622f2f4 2422 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 2423 if (!sqp->qp.ibqp.qp_num)
2424 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2425 else
e622f2f4 2426 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 2427 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 2428 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 2429 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 2430 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2431 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 2432 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2433
2434 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2435
2436 if (0) {
987c8f8f 2437 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 2438 for (i = 0; i < header_size / 4; ++i) {
2439 if (i % 8 == 0)
987c8f8f
SP		 2440 pr_err(" [%02x] ", i * 4);
2441 pr_cont(" %08x",
2442 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 2443 if ((i + 1) % 8 == 0)
987c8f8f 2444 pr_cont("\n");
225c7b1f 2445 }
987c8f8f 2446 pr_err("\n");
225c7b1f
RD		 2447 }
2448
e61ef241
RD		 2449 /*
2450 * Inline data segments may not cross a 64 byte boundary. If
2451 * our UD header is bigger than the space available up to the
2452 * next 64 byte boundary in the WQE, use two inline data
2453 * segments to hold the UD header.
2454 */
2455 spc = MLX4_INLINE_ALIGN -
2456 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2457 if (header_size <= spc) {
2458 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2459 memcpy(inl + 1, sqp->header_buf, header_size);
2460 i = 1;
2461 } else {
2462 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2463 memcpy(inl + 1, sqp->header_buf, spc);
2464
2465 inl = (void *) (inl + 1) + spc;
2466 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2467 /*
2468 * Need a barrier here to make sure all the data is
2469 * visible before the byte_count field is set.
2470 * Otherwise the HCA prefetcher could grab the 64-byte
2471 * chunk with this inline segment and get a valid (!=
2472 * 0xffffffff) byte count but stale data, and end up
2473 * generating a packet with bad headers.
2474 *
2475 * The first inline segment's byte_count field doesn't
2476 * need a barrier, because it comes after a
2477 * control/MLX segment and therefore is at an offset
2478 * of 16 mod 64.
2479 */
2480 wmb();
2481 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2482 i = 2;
2483 }
225c7b1f 2484
f438000f
RD		 2485 *mlx_seg_len =
2486 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2487 return 0;
225c7b1f
RD		 2488}
2489
2490static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2491{
2492 unsigned cur;
2493 struct mlx4_ib_cq *cq;
2494
2495 cur = wq->head - wq->tail;
0e6e7416 2496 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 2497 return 0;
2498
2499 cq = to_mcq(ib_cq);
2500 spin_lock(&cq->lock);
2501 cur = wq->head - wq->tail;
2502 spin_unlock(&cq->lock);
2503
0e6e7416 2504 return cur + nreq >= wq->max_post;
225c7b1f
RD		 2505}
2506
95d04f07
RD		 2507static __be32 convert_access(int acc)
2508{
6ff63e19
SM		 2509 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2510 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2511 (acc & IB_ACCESS_REMOTE_WRITE ?
2512 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2513 (acc & IB_ACCESS_REMOTE_READ ?
2514 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 2515 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2516 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2517}
2518
1b2cd0fc
SG		 2519static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2520 struct ib_reg_wr *wr)
2521{
2522 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2523
2524 fseg->flags = convert_access(wr->access);
2525 fseg->mem_key = cpu_to_be32(wr->key);
2526 fseg->buf_list = cpu_to_be64(mr->page_map);
2527 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
2528 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
2529 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2530 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
2531 fseg->reserved[0] = 0;
2532 fseg->reserved[1] = 0;
2533}
2534
95d04f07
RD		 2535static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2536{
aee38fad
SM		 2537 memset(iseg, 0, sizeof(*iseg));
2538 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 2539}
2540
0fbfa6a9
RD		 2541static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2542 u64 remote_addr, u32 rkey)
2543{
2544 rseg->raddr = cpu_to_be64(remote_addr);
2545 rseg->rkey = cpu_to_be32(rkey);
2546 rseg->reserved = 0;
2547}
2548
e622f2f4
CH		 2549static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2550 struct ib_atomic_wr *wr)
0fbfa6a9 2551{
e622f2f4
CH		 2552 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2553 aseg->swap_add = cpu_to_be64(wr->swap);
2554 aseg->compare = cpu_to_be64(wr->compare_add);
2555 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2556 aseg->swap_add = cpu_to_be64(wr->compare_add);
2557 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 2558 } else {
e622f2f4 2559 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 2560 aseg->compare = 0;
2561 }
2562
2563}
2564
6fa8f719 2565static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
e622f2f4 2566 struct ib_atomic_wr *wr)
6fa8f719 2567{
e622f2f4
CH		 2568 aseg->swap_add = cpu_to_be64(wr->swap);
2569 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
2570 aseg->compare = cpu_to_be64(wr->compare_add);
2571 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 2572}
2573
0fbfa6a9 2574static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2575 struct ib_ud_wr *wr)
0fbfa6a9 2576{
e622f2f4
CH		 2577 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2578 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2579 dseg->qkey = cpu_to_be32(wr->remote_qkey);
2580 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2581 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2582}
2583
1ffeb2eb
JM		 2584static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2585 struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2586 struct ib_ud_wr *wr,
97982f5a 2587 enum mlx4_ib_qp_type qpt)
1ffeb2eb 2588{
e622f2f4 2589 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 2590 struct mlx4_av sqp_av = {0};
2591 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2592
2593 /* force loopback */
2594 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2595 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2596 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2597 cpu_to_be32(0xf0000000);
2598
2599 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 2600 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2601 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2602 else
2603 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 2604 /* Use QKEY from the QP context, which is set by master */
2605 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2606}
2607
e622f2f4 2608static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
1ffeb2eb
JM		 2609{
2610 struct mlx4_wqe_inline_seg *inl = wqe;
2611 struct mlx4_ib_tunnel_header hdr;
e622f2f4 2612 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2613 int spc;
2614 int i;
2615
2616 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 2617 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2618 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2619 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 2620 memcpy(hdr.mac, ah->av.eth.mac, 6);
2621 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 2622
2623 spc = MLX4_INLINE_ALIGN -
2624 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2625 if (sizeof (hdr) <= spc) {
2626 memcpy(inl + 1, &hdr, sizeof (hdr));
2627 wmb();
2628 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2629 i = 1;
2630 } else {
2631 memcpy(inl + 1, &hdr, spc);
2632 wmb();
2633 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2634
2635 inl = (void *) (inl + 1) + spc;
2636 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2637 wmb();
2638 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2639 i = 2;
2640 }
2641
2642 *mlx_seg_len =
2643 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2644}
2645
6e694ea3
JM		 2646static void set_mlx_icrc_seg(void *dseg)
2647{
2648 u32 *t = dseg;
2649 struct mlx4_wqe_inline_seg *iseg = dseg;
2650
2651 t[1] = 0;
2652
2653 /*
2654 * Need a barrier here before writing the byte_count field to
2655 * make sure that all the data is visible before the
2656 * byte_count field is set. Otherwise, if the segment begins
2657 * a new cacheline, the HCA prefetcher could grab the 64-byte
2658 * chunk and get a valid (!= * 0xffffffff) byte count but
2659 * stale data, and end up sending the wrong data.
2660 */
2661 wmb();
2662
2663 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2664}
2665
2666static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2667{
d420d9e3
RD		 2668 dseg->lkey = cpu_to_be32(sg->lkey);
2669 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2670
2671 /*
2672 * Need a barrier here before writing the byte_count field to
2673 * make sure that all the data is visible before the
2674 * byte_count field is set. Otherwise, if the segment begins
2675 * a new cacheline, the HCA prefetcher could grab the 64-byte
2676 * chunk and get a valid (!= * 0xffffffff) byte count but
2677 * stale data, and end up sending the wrong data.
2678 */
2679 wmb();
2680
2681 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2682}
2683
2242fa4f
RD		 2684static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2685{
2686 dseg->byte_count = cpu_to_be32(sg->length);
2687 dseg->lkey = cpu_to_be32(sg->lkey);
2688 dseg->addr = cpu_to_be64(sg->addr);
2689}
2690
e622f2f4 2691static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
0fd7e1d8 2692 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2693 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 2694{
e622f2f4 2695 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 2696
417608c2
EC		 2697 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2698 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2699
2700 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 2701 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 2702 return -EINVAL;
2703
e622f2f4 2704 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 2705
e622f2f4 2706 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 2707 *lso_seg_len = halign;
2708 return 0;
2709}
2710
95d04f07
RD		 2711static __be32 send_ieth(struct ib_send_wr *wr)
2712{
2713 switch (wr->opcode) {
2714 case IB_WR_SEND_WITH_IMM:
2715 case IB_WR_RDMA_WRITE_WITH_IMM:
2716 return wr->ex.imm_data;
2717
2718 case IB_WR_SEND_WITH_INV:
2719 return cpu_to_be32(wr->ex.invalidate_rkey);
2720
2721 default:
2722 return 0;
2723 }
2724}
2725
1ffeb2eb
JM		 2726static void add_zero_len_inline(void *wqe)
2727{
2728 struct mlx4_wqe_inline_seg *inl = wqe;
2729 memset(wqe, 0, 16);
2730 inl->byte_count = cpu_to_be32(1 << 31);
2731}
2732
225c7b1f
RD		 2733int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2734 struct ib_send_wr **bad_wr)
2735{
2736 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2737 void *wqe;
2738 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2739 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2740 unsigned long flags;
2741 int nreq;
2742 int err = 0;
ea54b10c
JM		 2743 unsigned ind;
2744 int uninitialized_var(stamp);
2745 int uninitialized_var(size);
a3d8e159 2746 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2747 __be32 dummy;
2748 __be32 *lso_wqe;
2749 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2750 __be32 blh;
225c7b1f 2751 int i;
35f05dab 2752 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2753
96db0e03 2754 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 2755 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2756 err = -EIO;
2757 *bad_wr = wr;
2758 nreq = 0;
2759 goto out;
2760 }
225c7b1f 2761
ea54b10c 2762 ind = qp->sq_next_wqe;
225c7b1f
RD		 2763
2764 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 2765 lso_wqe = &dummy;
417608c2 2766 blh = 0;
0fd7e1d8 2767
225c7b1f
RD		 2768 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2769 err = -ENOMEM;
2770 *bad_wr = wr;
2771 goto out;
2772 }
2773
2774 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2775 err = -EINVAL;
2776 *bad_wr = wr;
2777 goto out;
2778 }
2779
0e6e7416 2780 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 2781 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 2782
2783 ctrl->srcrb_flags =
2784 (wr->send_flags & IB_SEND_SIGNALED ?
2785 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2786 (wr->send_flags & IB_SEND_SOLICITED ?
2787 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 2788 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2789 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2790 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 2791 qp->sq_signal_bits;
2792
95d04f07 2793 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 2794
2795 wqe += sizeof *ctrl;
2796 size = sizeof *ctrl / 16;
2797
1ffeb2eb
JM		 2798 switch (qp->mlx4_ib_qp_type) {
2799 case MLX4_IB_QPT_RC:
2800 case MLX4_IB_QPT_UC:
225c7b1f
RD		 2801 switch (wr->opcode) {
2802 case IB_WR_ATOMIC_CMP_AND_SWP:
2803 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 2804 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 2805 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2806 atomic_wr(wr)->rkey);
225c7b1f
RD		 2807 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2808
e622f2f4 2809 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 2810 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 2811
225c7b1f
RD		 2812 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2813 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 2814
2815 break;
2816
2817 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 2818 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2819 atomic_wr(wr)->rkey);
6fa8f719
VS		 2820 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2821
e622f2f4 2822 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 2823 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
2824
2825 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2826 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 2827
2828 break;
2829
2830 case IB_WR_RDMA_READ:
2831 case IB_WR_RDMA_WRITE:
2832 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 2833 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2834 rdma_wr(wr)->rkey);
225c7b1f
RD		 2835 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2836 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 2837 break;
95d04f07
RD		 2838
2839 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 2840 ctrl->srcrb_flags |=
2841 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2842 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2843 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
2844 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2845 break;
2846
1b2cd0fc
SG		 2847 case IB_WR_REG_MR:
2848 ctrl->srcrb_flags |=
2849 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2850 set_reg_seg(wqe, reg_wr(wr));
2851 wqe += sizeof(struct mlx4_wqe_fmr_seg);
2852 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
2853 break;
2854
225c7b1f
RD		 2855 default:
2856 /* No extra segments required for sends */
2857 break;
2858 }
2859 break;
2860
1ffeb2eb 2861 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 2862 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2863 ctrl, &seglen);
1ffeb2eb
JM		 2864 if (unlikely(err)) {
2865 *bad_wr = wr;
2866 goto out;
2867 }
2868 wqe += seglen;
2869 size += seglen / 16;
2870 break;
2871 case MLX4_IB_QPT_TUN_SMI:
2872 case MLX4_IB_QPT_TUN_GSI:
2873 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 2874 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 2875 /* set the forced-loopback bit in the data seg av */
2876 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2877 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2878 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2879 break;
2880 case MLX4_IB_QPT_UD:
e622f2f4 2881 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 2882 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2883 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 2884
2885 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 2886 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
2887 &lso_hdr_sz, &blh);
b832be1e
EC		 2888 if (unlikely(err)) {
2889 *bad_wr = wr;
2890 goto out;
2891 }
0fd7e1d8 2892 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 2893 wqe += seglen;
2894 size += seglen / 16;
2895 }
225c7b1f
RD		 2896 break;
2897
1ffeb2eb 2898 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 2899 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2900 ctrl, &seglen);
1ffeb2eb
JM		 2901 if (unlikely(err)) {
2902 *bad_wr = wr;
2903 goto out;
2904 }
2905 wqe += seglen;
2906 size += seglen / 16;
2907 /* to start tunnel header on a cache-line boundary */
2908 add_zero_len_inline(wqe);
2909 wqe += 16;
2910 size++;
e622f2f4 2911 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 2912 wqe += seglen;
2913 size += seglen / 16;
2914 break;
2915 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 2916 case MLX4_IB_QPT_PROXY_GSI:
2917 /* If we are tunneling special qps, this is a UD qp.
2918 * In this case we first add a UD segment targeting
2919 * the tunnel qp, and then add a header with address
2920 * information */
e622f2f4
CH		 2921 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
2922 ud_wr(wr),
97982f5a 2923 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 2924 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2925 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 2926 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 2927 wqe += seglen;
2928 size += seglen / 16;
2929 break;
2930
2931 case MLX4_IB_QPT_SMI:
2932 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 2933 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
2934 &seglen);
f438000f 2935 if (unlikely(err)) {
225c7b1f
RD		 2936 *bad_wr = wr;
2937 goto out;
2938 }
f438000f
RD		 2939 wqe += seglen;
2940 size += seglen / 16;
225c7b1f
RD		 2941 break;
2942
2943 default:
2944 break;
2945 }
2946
6e694ea3
JM		 2947 /*
2948 * Write data segments in reverse order, so as to
2949 * overwrite cacheline stamp last within each
2950 * cacheline. This avoids issues with WQE
2951 * prefetching.
2952 */
225c7b1f 2953
6e694ea3
JM		 2954 dseg = wqe;
2955 dseg += wr->num_sge - 1;
2956 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 2957
2958 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 2959 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2960 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2961 qp->mlx4_ib_qp_type &
2962 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 2963 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 2964 size += sizeof (struct mlx4_wqe_data_seg) / 16;
2965 }
2966
6e694ea3
JM		 2967 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2968 set_data_seg(dseg, wr->sg_list + i);
2969
0fd7e1d8
RD		 2970 /*
2971 * Possibly overwrite stamping in cacheline with LSO
2972 * segment only after making sure all data segments
2973 * are written.
2974 */
2975 wmb();
2976 *lso_wqe = lso_hdr_sz;
2977
225c7b1f
RD		 2978 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2979 MLX4_WQE_CTRL_FENCE : 0) | size;
2980
2981 /*
2982 * Make sure descriptor is fully written before
2983 * setting ownership bit (because HW can start
2984 * executing as soon as we do).
2985 */
2986 wmb();
2987
59b0ed12 2988 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 2989 *bad_wr = wr;
225c7b1f
RD		 2990 err = -EINVAL;
2991 goto out;
2992 }
2993
2994 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 2995 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 2996
ea54b10c
JM		 2997 stamp = ind + qp->sq_spare_wqes;
2998 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2999
0e6e7416
RD		 3000 /*
3001 * We can improve latency by not stamping the last
3002 * send queue WQE until after ringing the doorbell, so
3003 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 3004 *
3005 * Same optimization applies to padding with NOP wqe
3006 * in case of WQE shrinking (used to prevent wrap-around
3007 * in the middle of WR).
0e6e7416 3008 */
ea54b10c
JM		 3009 if (wr->next) {
3010 stamp_send_wqe(qp, stamp, size * 16);
3011 ind = pad_wraparound(qp, ind);
3012 }
225c7b1f
RD		 3013 }
3014
3015out:
3016 if (likely(nreq)) {
3017 qp->sq.head += nreq;
3018
3019 /*
3020 * Make sure that descriptors are written before
3021 * doorbell record.
3022 */
3023 wmb();
3024
3025 writel(qp->doorbell_qpn,
3026 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3027
3028 /*
3029 * Make sure doorbells don't leak out of SQ spinlock
3030 * and reach the HCA out of order.
3031 */
3032 mmiowb();
0e6e7416 3033
ea54b10c
JM		 3034 stamp_send_wqe(qp, stamp, size * 16);
3035
3036 ind = pad_wraparound(qp, ind);
3037 qp->sq_next_wqe = ind;
225c7b1f
RD		 3038 }
3039
96db0e03 3040 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3041
3042 return err;
3043}
3044
3045int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3046 struct ib_recv_wr **bad_wr)
3047{
3048 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3049 struct mlx4_wqe_data_seg *scat;
3050 unsigned long flags;
3051 int err = 0;
3052 int nreq;
3053 int ind;
1ffeb2eb 3054 int max_gs;
225c7b1f 3055 int i;
35f05dab 3056 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3057
1ffeb2eb 3058 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3059 spin_lock_irqsave(&qp->rq.lock, flags);
3060
35f05dab
YH		 3061 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3062 err = -EIO;
3063 *bad_wr = wr;
3064 nreq = 0;
3065 goto out;
3066 }
3067
0e6e7416 3068 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3069
3070 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3071 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3072 err = -ENOMEM;
3073 *bad_wr = wr;
3074 goto out;
3075 }
3076
3077 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3078 err = -EINVAL;
3079 *bad_wr = wr;
3080 goto out;
3081 }
3082
3083 scat = get_recv_wqe(qp, ind);
3084
1ffeb2eb
JM		 3085 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3086 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3087 ib_dma_sync_single_for_device(ibqp->device,
3088 qp->sqp_proxy_rcv[ind].map,
3089 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3090 DMA_FROM_DEVICE);
3091 scat->byte_count =
3092 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3093 /* use dma lkey from upper layer entry */
3094 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3095 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3096 scat++;
3097 max_gs--;
3098 }
3099
2242fa4f
RD		 3100 for (i = 0; i < wr->num_sge; ++i)
3101 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3102
1ffeb2eb 3103 if (i < max_gs) {
225c7b1f
RD		 3104 scat[i].byte_count = 0;
3105 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3106 scat[i].addr = 0;
3107 }
3108
3109 qp->rq.wrid[ind] = wr->wr_id;
3110
0e6e7416 3111 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3112 }
3113
3114out:
3115 if (likely(nreq)) {
3116 qp->rq.head += nreq;
3117
3118 /*
3119 * Make sure that descriptors are written before
3120 * doorbell record.
3121 */
3122 wmb();
3123
3124 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3125 }
3126
3127 spin_unlock_irqrestore(&qp->rq.lock, flags);
3128
3129 return err;
3130}
6a775e2b
JM		 3131
3132static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3133{
3134 switch (mlx4_state) {
3135 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3136 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3137 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3138 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3139 case MLX4_QP_STATE_SQ_DRAINING:
3140 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3141 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3142 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3143 default: return -1;
3144 }
3145}
3146
3147static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3148{
3149 switch (mlx4_mig_state) {
3150 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3151 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3152 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3153 default: return -1;
3154 }
3155}
3156
3157static int to_ib_qp_access_flags(int mlx4_flags)
3158{
3159 int ib_flags = 0;
3160
3161 if (mlx4_flags & MLX4_QP_BIT_RRE)
3162 ib_flags |= IB_ACCESS_REMOTE_READ;
3163 if (mlx4_flags & MLX4_QP_BIT_RWE)
3164 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3165 if (mlx4_flags & MLX4_QP_BIT_RAE)
3166 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3167
3168 return ib_flags;
3169}
3170
4c3eb3ca 3171static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
6a775e2b
JM		 3172 struct mlx4_qp_path *path)
3173{
4c3eb3ca
EC		 3174 struct mlx4_dev *dev = ibdev->dev;
3175 int is_eth;
3176
8fcea95a 3177 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 3178 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3179
3180 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3181 return;
3182
4c3eb3ca
EC		 3183 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3184 IB_LINK_LAYER_ETHERNET;
3185 if (is_eth)
3186 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3187 ((path->sched_queue & 4) << 1);
3188 else
3189 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3190
6a775e2b 3191 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
6a775e2b
JM		 3192 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3193 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3194 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3195 if (ib_ah_attr->ah_flags) {
3196 ib_ah_attr->grh.sgid_index = path->mgid_index;
3197 ib_ah_attr->grh.hop_limit = path->hop_limit;
3198 ib_ah_attr->grh.traffic_class =
3199 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3200 ib_ah_attr->grh.flow_label =
586bb586 3201 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 3202 memcpy(ib_ah_attr->grh.dgid.raw,
3203 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3204 }
3205}
3206
3207int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3208 struct ib_qp_init_attr *qp_init_attr)
3209{
3210 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3211 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3212 struct mlx4_qp_context context;
3213 int mlx4_state;
0df67030
DB		 3214 int err = 0;
3215
3216 mutex_lock(&qp->mutex);
6a775e2b
JM		 3217
3218 if (qp->state == IB_QPS_RESET) {
3219 qp_attr->qp_state = IB_QPS_RESET;
3220 goto done;
3221 }
3222
3223 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3224 if (err) {
3225 err = -EINVAL;
3226 goto out;
3227 }
6a775e2b
JM		 3228
3229 mlx4_state = be32_to_cpu(context.flags) >> 28;
3230
0df67030
DB		 3231 qp->state = to_ib_qp_state(mlx4_state);
3232 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3233 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3234 qp_attr->path_mig_state =
3235 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3236 qp_attr->qkey = be32_to_cpu(context.qkey);
3237 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3238 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3239 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3240 qp_attr->qp_access_flags =
3241 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3242
3243 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4c3eb3ca
EC		 3244 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3245 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b
JM		 3246 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3247 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3248 }
3249
3250 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3251 if (qp_attr->qp_state == IB_QPS_INIT)
3252 qp_attr->port_num = qp->port;
3253 else
3254 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3255
3256 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3257 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3258
3259 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3260
3261 qp_attr->max_dest_rd_atomic =
3262 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3263 qp_attr->min_rnr_timer =
3264 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3265 qp_attr->timeout = context.pri_path.ackto >> 3;
3266 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3267 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3268 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3269
3270done:
3271 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3272 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3273 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3274
6a775e2b 3275 if (!ibqp->uobject) {
7f5eb9bb
RD		 3276 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3277 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3278 } else {
3279 qp_attr->cap.max_send_wr = 0;
3280 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 3281 }
3282
7f5eb9bb
RD		 3283 /*
3284 * We don't support inline sends for kernel QPs (yet), and we
3285 * don't know what userspace's value should be.
3286 */
3287 qp_attr->cap.max_inline_data = 0;
3288
3289 qp_init_attr->cap = qp_attr->cap;
3290
521e575b
RL		 3291 qp_init_attr->create_flags = 0;
3292 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3293 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3294
3295 if (qp->flags & MLX4_IB_QP_LSO)
3296 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3297
c1c98501
MB		 3298 if (qp->flags & MLX4_IB_QP_NETIF)
3299 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3300
46db567d
DB		 3301 qp_init_attr->sq_sig_type =
3302 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3303 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3304
0df67030
DB		 3305out:
3306 mutex_unlock(&qp->mutex);
3307 return err;
6a775e2b
JM		 3308}
3309
Linux 6.x block layer and io_uring tree(s)