IB/mlx4: Use correct subnet-prefix in QP1 mads under SR-IOV
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / mlx4_ib.h
CommitLineData
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1/*
2 * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
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4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#ifndef MLX4_IB_H
35#define MLX4_IB_H
36
37#include <linux/compiler.h>
38#include <linux/list.h>
63019d93 39#include <linux/mutex.h>
b9c5d6a6 40#include <linux/idr.h>
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41
42#include <rdma/ib_verbs.h>
43#include <rdma/ib_umem.h>
b9c5d6a6 44#include <rdma/ib_mad.h>
a0c64a17 45#include <rdma/ib_sa.h>
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46
47#include <linux/mlx4/device.h>
48#include <linux/mlx4/doorbell.h>
49
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JM
50#define MLX4_IB_DRV_NAME "mlx4_ib"
51
52#ifdef pr_fmt
53#undef pr_fmt
54#endif
55#define pr_fmt(fmt) "<" MLX4_IB_DRV_NAME "> %s: " fmt, __func__
56
57#define mlx4_ib_warn(ibdev, format, arg...) \
58 dev_warn((ibdev)->dma_device, MLX4_IB_DRV_NAME ": " format, ## arg)
59
fc2d0044
SG
60enum {
61 MLX4_IB_SQ_MIN_WQE_SHIFT = 6,
62 MLX4_IB_MAX_HEADROOM = 2048
63};
64
65#define MLX4_IB_SQ_HEADROOM(shift) ((MLX4_IB_MAX_HEADROOM >> (shift)) + 1)
66#define MLX4_IB_SQ_MAX_SPARE (MLX4_IB_SQ_HEADROOM(MLX4_IB_SQ_MIN_WQE_SHIFT))
67
a0c64a17
JM
68/*module param to indicate if SM assigns the alias_GUID*/
69extern int mlx4_ib_sm_guid_assign;
70
c1c98501
MB
71#define MLX4_IB_UC_STEER_QPN_ALIGN 1
72#define MLX4_IB_UC_MAX_NUM_QPS 256
ae184dde
YH
73
74enum hw_bar_type {
75 HW_BAR_BF,
76 HW_BAR_DB,
77 HW_BAR_CLOCK,
78 HW_BAR_COUNT
79};
80
81struct mlx4_ib_vma_private_data {
82 struct vm_area_struct *vma;
83};
84
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85struct mlx4_ib_ucontext {
86 struct ib_ucontext ibucontext;
87 struct mlx4_uar uar;
88 struct list_head db_page_list;
89 struct mutex db_page_mutex;
ae184dde 90 struct mlx4_ib_vma_private_data hw_bar_info[HW_BAR_COUNT];
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91};
92
93struct mlx4_ib_pd {
94 struct ib_pd ibpd;
95 u32 pdn;
96};
97
012a8ff5
SH
98struct mlx4_ib_xrcd {
99 struct ib_xrcd ibxrcd;
100 u32 xrcdn;
101 struct ib_pd *pd;
102 struct ib_cq *cq;
103};
104
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105struct mlx4_ib_cq_buf {
106 struct mlx4_buf buf;
107 struct mlx4_mtt mtt;
08ff3235 108 int entry_size;
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109};
110
bbf8eed1
VS
111struct mlx4_ib_cq_resize {
112 struct mlx4_ib_cq_buf buf;
113 int cqe;
114};
115
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116struct mlx4_ib_cq {
117 struct ib_cq ibcq;
118 struct mlx4_cq mcq;
119 struct mlx4_ib_cq_buf buf;
bbf8eed1 120 struct mlx4_ib_cq_resize *resize_buf;
6296883c 121 struct mlx4_db db;
225c7b1f 122 spinlock_t lock;
bbf8eed1 123 struct mutex resize_mutex;
225c7b1f 124 struct ib_umem *umem;
bbf8eed1 125 struct ib_umem *resize_umem;
4b664c43 126 int create_flags;
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YH
127 /* List of qps that it serves.*/
128 struct list_head send_qp_list;
129 struct list_head recv_qp_list;
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130};
131
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132#define MLX4_MR_PAGES_ALIGN 0x40
133
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134struct mlx4_ib_mr {
135 struct ib_mr ibmr;
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136 __be64 *pages;
137 dma_addr_t page_map;
138 u32 npages;
139 u32 max_pages;
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140 struct mlx4_mr mmr;
141 struct ib_umem *umem;
cbc9355a 142 size_t page_map_size;
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143};
144
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SM
145struct mlx4_ib_mw {
146 struct ib_mw ibmw;
147 struct mlx4_mw mmw;
148};
149
8ad11fb6
JM
150struct mlx4_ib_fmr {
151 struct ib_fmr ibfmr;
152 struct mlx4_fmr mfmr;
153};
154
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MS
155#define MAX_REGS_PER_FLOW 2
156
157struct mlx4_flow_reg_id {
158 u64 id;
159 u64 mirror;
160};
161
f77c0162
HHZ
162struct mlx4_ib_flow {
163 struct ib_flow ibflow;
164 /* translating DMFS verbs sniffer rule to FW API requires two reg IDs */
146d6e19 165 struct mlx4_flow_reg_id reg_id[MAX_REGS_PER_FLOW];
f77c0162
HHZ
166};
167
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168struct mlx4_ib_wq {
169 u64 *wrid;
170 spinlock_t lock;
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RD
171 int wqe_cnt;
172 int max_post;
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173 int max_gs;
174 int offset;
175 int wqe_shift;
176 unsigned head;
177 unsigned tail;
178};
179
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MS
180enum {
181 MLX4_IB_QP_CREATE_ROCE_V2_GSI = IB_QP_CREATE_RESERVED_START
182};
183
b832be1e 184enum mlx4_ib_qp_flags {
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185 MLX4_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO,
186 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
c1c98501 187 MLX4_IB_QP_NETIF = IB_QP_CREATE_NETIF_QP,
40f2287b 188 MLX4_IB_QP_CREATE_USE_GFP_NOIO = IB_QP_CREATE_USE_GFP_NOIO,
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189
190 /* Mellanox specific flags start from IB_QP_CREATE_RESERVED_START */
191 MLX4_IB_ROCE_V2_GSI_QP = MLX4_IB_QP_CREATE_ROCE_V2_GSI,
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192 MLX4_IB_SRIOV_TUNNEL_QP = 1 << 30,
193 MLX4_IB_SRIOV_SQP = 1 << 31,
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194};
195
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EC
196struct mlx4_ib_gid_entry {
197 struct list_head list;
198 union ib_gid gid;
199 int added;
200 u8 port;
201};
202
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203enum mlx4_ib_qp_type {
204 /*
205 * IB_QPT_SMI and IB_QPT_GSI have to be the first two entries
206 * here (and in that order) since the MAD layer uses them as
207 * indices into a 2-entry table.
208 */
209 MLX4_IB_QPT_SMI = IB_QPT_SMI,
210 MLX4_IB_QPT_GSI = IB_QPT_GSI,
211
212 MLX4_IB_QPT_RC = IB_QPT_RC,
213 MLX4_IB_QPT_UC = IB_QPT_UC,
214 MLX4_IB_QPT_UD = IB_QPT_UD,
215 MLX4_IB_QPT_RAW_IPV6 = IB_QPT_RAW_IPV6,
216 MLX4_IB_QPT_RAW_ETHERTYPE = IB_QPT_RAW_ETHERTYPE,
217 MLX4_IB_QPT_RAW_PACKET = IB_QPT_RAW_PACKET,
218 MLX4_IB_QPT_XRC_INI = IB_QPT_XRC_INI,
219 MLX4_IB_QPT_XRC_TGT = IB_QPT_XRC_TGT,
220
221 MLX4_IB_QPT_PROXY_SMI_OWNER = 1 << 16,
222 MLX4_IB_QPT_PROXY_SMI = 1 << 17,
223 MLX4_IB_QPT_PROXY_GSI = 1 << 18,
224 MLX4_IB_QPT_TUN_SMI_OWNER = 1 << 19,
225 MLX4_IB_QPT_TUN_SMI = 1 << 20,
226 MLX4_IB_QPT_TUN_GSI = 1 << 21,
227};
228
229#define MLX4_IB_QPT_ANY_SRIOV (MLX4_IB_QPT_PROXY_SMI_OWNER | \
230 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER | \
231 MLX4_IB_QPT_TUN_SMI | MLX4_IB_QPT_TUN_GSI)
232
0a9a0188
JM
233enum mlx4_ib_mad_ifc_flags {
234 MLX4_MAD_IFC_IGNORE_MKEY = 1,
235 MLX4_MAD_IFC_IGNORE_BKEY = 2,
236 MLX4_MAD_IFC_IGNORE_KEYS = (MLX4_MAD_IFC_IGNORE_MKEY |
237 MLX4_MAD_IFC_IGNORE_BKEY),
238 MLX4_MAD_IFC_NET_VIEW = 4,
239};
240
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241enum {
242 MLX4_NUM_TUNNEL_BUFS = 256,
243};
244
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245struct mlx4_ib_tunnel_header {
246 struct mlx4_av av;
247 __be32 remote_qpn;
248 __be32 qkey;
249 __be16 vlan;
250 u8 mac[6];
251 __be16 pkey_index;
252 u8 reserved[6];
253};
254
255struct mlx4_ib_buf {
256 void *addr;
257 dma_addr_t map;
258};
259
260struct mlx4_rcv_tunnel_hdr {
261 __be32 flags_src_qp; /* flags[6:5] is defined for VLANs:
262 * 0x0 - no vlan was in the packet
263 * 0x01 - C-VLAN was in the packet */
264 u8 g_ml_path; /* gid bit stands for ipv6/4 header in RoCE */
265 u8 reserved;
266 __be16 pkey_index;
267 __be16 sl_vid;
268 __be16 slid_mac_47_32;
269 __be32 mac_31_0;
270};
271
272struct mlx4_ib_proxy_sqp_hdr {
273 struct ib_grh grh;
274 struct mlx4_rcv_tunnel_hdr tun;
275} __packed;
276
2f5bb473
JM
277struct mlx4_roce_smac_vlan_info {
278 u64 smac;
279 int smac_index;
280 int smac_port;
281 u64 candidate_smac;
282 int candidate_smac_index;
283 int candidate_smac_port;
284 u16 vid;
285 int vlan_index;
286 int vlan_port;
287 u16 candidate_vid;
288 int candidate_vlan_index;
289 int candidate_vlan_port;
290 int update_vid;
291};
292
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293struct mlx4_ib_qp {
294 struct ib_qp ibqp;
295 struct mlx4_qp mqp;
296 struct mlx4_buf buf;
297
6296883c 298 struct mlx4_db db;
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299 struct mlx4_ib_wq rq;
300
301 u32 doorbell_qpn;
302 __be32 sq_signal_bits;
ea54b10c
JM
303 unsigned sq_next_wqe;
304 int sq_max_wqes_per_wr;
0e6e7416 305 int sq_spare_wqes;
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306 struct mlx4_ib_wq sq;
307
1ffeb2eb 308 enum mlx4_ib_qp_type mlx4_ib_qp_type;
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309 struct ib_umem *umem;
310 struct mlx4_mtt mtt;
311 int buf_size;
312 struct mutex mutex;
0a1405da 313 u16 xrcdn;
b832be1e 314 u32 flags;
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315 u8 port;
316 u8 alt_port;
317 u8 atomic_rd_en;
318 u8 resp_depth;
0e6e7416 319 u8 sq_no_prefetch;
225c7b1f 320 u8 state;
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EC
321 int mlx_type;
322 struct list_head gid_list;
0ff1fb65 323 struct list_head steering_rules;
1ffeb2eb 324 struct mlx4_ib_buf *sqp_proxy_rcv;
2f5bb473
JM
325 struct mlx4_roce_smac_vlan_info pri;
326 struct mlx4_roce_smac_vlan_info alt;
c1c98501 327 u64 reg_id;
35f05dab
YH
328 struct list_head qps_list;
329 struct list_head cq_recv_list;
330 struct list_head cq_send_list;
7b59f0f9 331 struct counter_index *counter_index;
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RD
332};
333
334struct mlx4_ib_srq {
335 struct ib_srq ibsrq;
336 struct mlx4_srq msrq;
337 struct mlx4_buf buf;
6296883c 338 struct mlx4_db db;
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RD
339 u64 *wrid;
340 spinlock_t lock;
341 int head;
342 int tail;
343 u16 wqe_ctr;
344 struct ib_umem *umem;
345 struct mlx4_mtt mtt;
346 struct mutex mutex;
347};
348
349struct mlx4_ib_ah {
350 struct ib_ah ibah;
fa417f7b
EC
351 union mlx4_ext_av av;
352};
353
a0c64a17
JM
354/****************************************/
355/* alias guid support */
356/****************************************/
357#define NUM_PORT_ALIAS_GUID 2
358#define NUM_ALIAS_GUID_IN_REC 8
359#define NUM_ALIAS_GUID_REC_IN_PORT 16
360#define GUID_REC_SIZE 8
361#define NUM_ALIAS_GUID_PER_PORT 128
362#define MLX4_NOT_SET_GUID (0x00LL)
363#define MLX4_GUID_FOR_DELETE_VAL (~(0x00LL))
364
365enum mlx4_guid_alias_rec_status {
366 MLX4_GUID_INFO_STATUS_IDLE,
367 MLX4_GUID_INFO_STATUS_SET,
a0c64a17
JM
368};
369
f5479601 370#define GUID_STATE_NEED_PORT_INIT 0x01
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371
372enum mlx4_guid_alias_rec_method {
373 MLX4_GUID_INFO_RECORD_SET = IB_MGMT_METHOD_SET,
374 MLX4_GUID_INFO_RECORD_DELETE = IB_SA_METHOD_DELETE,
375};
376
377struct mlx4_sriov_alias_guid_info_rec_det {
378 u8 all_recs[GUID_REC_SIZE * NUM_ALIAS_GUID_IN_REC];
379 ib_sa_comp_mask guid_indexes; /*indicates what from the 8 records are valid*/
380 enum mlx4_guid_alias_rec_status status; /*indicates the administraively status of the record.*/
99ee4df6
YH
381 unsigned int guids_retry_schedule[NUM_ALIAS_GUID_IN_REC];
382 u64 time_to_run;
a0c64a17
JM
383};
384
385struct mlx4_sriov_alias_guid_port_rec_det {
386 struct mlx4_sriov_alias_guid_info_rec_det all_rec_per_port[NUM_ALIAS_GUID_REC_IN_PORT];
387 struct workqueue_struct *wq;
388 struct delayed_work alias_guid_work;
389 u8 port;
f5479601 390 u32 state_flags;
a0c64a17
JM
391 struct mlx4_sriov_alias_guid *parent;
392 struct list_head cb_list;
393};
394
395struct mlx4_sriov_alias_guid {
396 struct mlx4_sriov_alias_guid_port_rec_det ports_guid[MLX4_MAX_PORTS];
397 spinlock_t ag_work_lock;
398 struct ib_sa_client *sa_client;
399};
400
fc06573d
JM
401struct mlx4_ib_demux_work {
402 struct work_struct work;
403 struct mlx4_ib_dev *dev;
404 int slave;
405 int do_init;
406 u8 port;
407
408};
409
1ffeb2eb
JM
410struct mlx4_ib_tun_tx_buf {
411 struct mlx4_ib_buf buf;
412 struct ib_ah *ah;
413};
414
415struct mlx4_ib_demux_pv_qp {
416 struct ib_qp *qp;
417 enum ib_qp_type proxy_qpt;
418 struct mlx4_ib_buf *ring;
419 struct mlx4_ib_tun_tx_buf *tx_ring;
420 spinlock_t tx_lock;
421 unsigned tx_ix_head;
422 unsigned tx_ix_tail;
423};
424
fc06573d
JM
425enum mlx4_ib_demux_pv_state {
426 DEMUX_PV_STATE_DOWN,
427 DEMUX_PV_STATE_STARTING,
428 DEMUX_PV_STATE_ACTIVE,
429 DEMUX_PV_STATE_DOWNING,
430};
431
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432struct mlx4_ib_demux_pv_ctx {
433 int port;
434 int slave;
fc06573d 435 enum mlx4_ib_demux_pv_state state;
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436 int has_smi;
437 struct ib_device *ib_dev;
438 struct ib_cq *cq;
439 struct ib_pd *pd;
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440 struct work_struct work;
441 struct workqueue_struct *wq;
442 struct mlx4_ib_demux_pv_qp qp[2];
443};
444
445struct mlx4_ib_demux_ctx {
446 struct ib_device *ib_dev;
447 int port;
448 struct workqueue_struct *wq;
449 struct workqueue_struct *ud_wq;
450 spinlock_t ud_lock;
8ec07bf8 451 atomic64_t subnet_prefix;
1ffeb2eb
JM
452 __be64 guid_cache[128];
453 struct mlx4_ib_dev *dev;
b9c5d6a6
OD
454 /* the following lock protects both mcg_table and mcg_mgid0_list */
455 struct mutex mcg_table_lock;
456 struct rb_root mcg_table;
457 struct list_head mcg_mgid0_list;
458 struct workqueue_struct *mcg_wq;
1ffeb2eb 459 struct mlx4_ib_demux_pv_ctx **tun;
b9c5d6a6
OD
460 atomic_t tid;
461 int flushing; /* flushing the work queue */
1ffeb2eb
JM
462};
463
464struct mlx4_ib_sriov {
465 struct mlx4_ib_demux_ctx demux[MLX4_MAX_PORTS];
466 struct mlx4_ib_demux_pv_ctx *sqps[MLX4_MAX_PORTS];
467 /* when using this spinlock you should use "irq" because
468 * it may be called from interrupt context.*/
469 spinlock_t going_down_lock;
470 int is_going_down;
3cf69cc8 471
a0c64a17
JM
472 struct mlx4_sriov_alias_guid alias_guid;
473
3cf69cc8
AV
474 /* CM paravirtualization fields */
475 struct list_head cm_list;
476 spinlock_t id_map_lock;
477 struct rb_root sl_id_map;
478 struct idr pv_id_table;
1ffeb2eb
JM
479};
480
e26be1bf
MS
481struct gid_cache_context {
482 int real_index;
483 int refcount;
484};
485
486struct gid_entry {
487 union ib_gid gid;
b699a859 488 enum ib_gid_type gid_type;
e26be1bf
MS
489 struct gid_cache_context *ctx;
490};
491
492struct mlx4_port_gid_table {
493 struct gid_entry gids[MLX4_MAX_PORT_GIDS];
494};
495
fa417f7b
EC
496struct mlx4_ib_iboe {
497 spinlock_t lock;
498 struct net_device *netdevs[MLX4_MAX_PORTS];
3e0629cb 499 atomic64_t mac[MLX4_MAX_PORTS];
fa417f7b 500 struct notifier_block nb;
e26be1bf 501 struct mlx4_port_gid_table gids[MLX4_MAX_PORTS];
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RD
502};
503
fc06573d
JM
504struct pkey_mgt {
505 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
506 u16 phys_pkey_cache[MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
507 struct list_head pkey_port_list[MLX4_MFUNC_MAX];
508 struct kobject *device_parent[MLX4_MFUNC_MAX];
509};
510
c1e7e466
JM
511struct mlx4_ib_iov_sysfs_attr {
512 void *ctx;
513 struct kobject *kobj;
514 unsigned long data;
515 u32 entry_num;
516 char name[15];
517 struct device_attribute dentry;
518 struct device *dev;
519};
520
521struct mlx4_ib_iov_sysfs_attr_ar {
522 struct mlx4_ib_iov_sysfs_attr dentries[3 * NUM_ALIAS_GUID_PER_PORT + 1];
523};
524
525struct mlx4_ib_iov_port {
526 char name[100];
527 u8 num;
528 struct mlx4_ib_dev *dev;
529 struct list_head list;
530 struct mlx4_ib_iov_sysfs_attr_ar *dentr_ar;
531 struct ib_port_attr attr;
532 struct kobject *cur_port;
533 struct kobject *admin_alias_parent;
534 struct kobject *gids_parent;
535 struct kobject *pkeys_parent;
536 struct kobject *mcgs_parent;
537 struct mlx4_ib_iov_sysfs_attr mcg_dentry;
538};
539
c3abb51b 540struct counter_index {
3ba8e31d 541 struct list_head list;
c3abb51b
EBE
542 u32 index;
543 u8 allocated;
544};
545
3ba8e31d
EBE
546struct mlx4_ib_counters {
547 struct list_head counters_list;
548 struct mutex mutex; /* mutex for accessing counters list */
549 u32 default_counter;
550};
551
3f85f2aa
MB
552#define MLX4_DIAG_COUNTERS_TYPES 2
553
554struct mlx4_ib_diag_counters {
555 const char **name;
556 u32 *offset;
557 u32 num_counters;
558};
559
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560struct mlx4_ib_dev {
561 struct ib_device ib_dev;
562 struct mlx4_dev *dev;
7ff93f8b 563 int num_ports;
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RD
564 void __iomem *uar_map;
565
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RD
566 struct mlx4_uar priv_uar;
567 u32 priv_pdn;
568 MLX4_DECLARE_DOORBELL_LOCK(uar_lock);
569
570 struct ib_mad_agent *send_agent[MLX4_MAX_PORTS][2];
571 struct ib_ah *sm_ah[MLX4_MAX_PORTS];
572 spinlock_t sm_lock;
1ffeb2eb 573 struct mlx4_ib_sriov sriov;
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RD
574
575 struct mutex cap_mask_mutex;
3b4a8cd5 576 bool ib_active;
fa417f7b 577 struct mlx4_ib_iboe iboe;
3ba8e31d 578 struct mlx4_ib_counters counters_table[MLX4_MAX_PORTS];
e605b743 579 int *eq_table;
c1e7e466
JM
580 struct kobject *iov_parent;
581 struct kobject *ports_parent;
582 struct kobject *dev_ports_parent[MLX4_MFUNC_MAX];
583 struct mlx4_ib_iov_port iov_ports[MLX4_MAX_PORTS];
fc06573d 584 struct pkey_mgt pkeys;
c1c98501
MB
585 unsigned long *ib_uc_qpns_bitmap;
586 int steer_qpn_count;
587 int steer_qpn_base;
0a9b7d59 588 int steering_support;
9433c188
MB
589 struct mlx4_ib_qp *qp1_proxy[MLX4_MAX_PORTS];
590 /* lock when destroying qp1_proxy and getting netdev events */
591 struct mutex qp1_proxy_lock[MLX4_MAX_PORTS];
c6215745 592 u8 bond_next_port;
35f05dab
YH
593 /* protect resources needed as part of reset flow */
594 spinlock_t reset_flow_resource_lock;
595 struct list_head qp_list;
3f85f2aa 596 struct mlx4_ib_diag_counters diag_counters[MLX4_DIAG_COUNTERS_TYPES];
225c7b1f
RD
597};
598
00f5ce99
JM
599struct ib_event_work {
600 struct work_struct work;
601 struct mlx4_ib_dev *ib_dev;
602 struct mlx4_eqe ib_eqe;
603};
604
1ffeb2eb
JM
605struct mlx4_ib_qp_tunnel_init_attr {
606 struct ib_qp_init_attr init_attr;
607 int slave;
608 enum ib_qp_type proxy_qp_type;
609 u8 port;
610};
611
4b664c43
MB
612struct mlx4_uverbs_ex_query_device {
613 __u32 comp_mask;
614 __u32 reserved;
615};
616
617enum query_device_resp_mask {
618 QUERY_DEVICE_RESP_MASK_TIMESTAMP = 1UL << 0,
619};
620
621struct mlx4_uverbs_ex_query_device_resp {
622 __u32 comp_mask;
623 __u32 response_length;
624 __u64 hca_core_clock_offset;
625};
626
225c7b1f
RD
627static inline struct mlx4_ib_dev *to_mdev(struct ib_device *ibdev)
628{
629 return container_of(ibdev, struct mlx4_ib_dev, ib_dev);
630}
631
632static inline struct mlx4_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
633{
634 return container_of(ibucontext, struct mlx4_ib_ucontext, ibucontext);
635}
636
637static inline struct mlx4_ib_pd *to_mpd(struct ib_pd *ibpd)
638{
639 return container_of(ibpd, struct mlx4_ib_pd, ibpd);
640}
641
012a8ff5
SH
642static inline struct mlx4_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
643{
644 return container_of(ibxrcd, struct mlx4_ib_xrcd, ibxrcd);
645}
646
225c7b1f
RD
647static inline struct mlx4_ib_cq *to_mcq(struct ib_cq *ibcq)
648{
649 return container_of(ibcq, struct mlx4_ib_cq, ibcq);
650}
651
652static inline struct mlx4_ib_cq *to_mibcq(struct mlx4_cq *mcq)
653{
654 return container_of(mcq, struct mlx4_ib_cq, mcq);
655}
656
657static inline struct mlx4_ib_mr *to_mmr(struct ib_mr *ibmr)
658{
659 return container_of(ibmr, struct mlx4_ib_mr, ibmr);
660}
661
804d6a89
SM
662static inline struct mlx4_ib_mw *to_mmw(struct ib_mw *ibmw)
663{
664 return container_of(ibmw, struct mlx4_ib_mw, ibmw);
665}
666
8ad11fb6
JM
667static inline struct mlx4_ib_fmr *to_mfmr(struct ib_fmr *ibfmr)
668{
669 return container_of(ibfmr, struct mlx4_ib_fmr, ibfmr);
670}
f77c0162
HHZ
671
672static inline struct mlx4_ib_flow *to_mflow(struct ib_flow *ibflow)
673{
674 return container_of(ibflow, struct mlx4_ib_flow, ibflow);
675}
676
225c7b1f
RD
677static inline struct mlx4_ib_qp *to_mqp(struct ib_qp *ibqp)
678{
679 return container_of(ibqp, struct mlx4_ib_qp, ibqp);
680}
681
682static inline struct mlx4_ib_qp *to_mibqp(struct mlx4_qp *mqp)
683{
684 return container_of(mqp, struct mlx4_ib_qp, mqp);
685}
686
687static inline struct mlx4_ib_srq *to_msrq(struct ib_srq *ibsrq)
688{
689 return container_of(ibsrq, struct mlx4_ib_srq, ibsrq);
690}
691
692static inline struct mlx4_ib_srq *to_mibsrq(struct mlx4_srq *msrq)
693{
694 return container_of(msrq, struct mlx4_ib_srq, msrq);
695}
696
697static inline struct mlx4_ib_ah *to_mah(struct ib_ah *ibah)
698{
699 return container_of(ibah, struct mlx4_ib_ah, ibah);
700}
701
c6215745
MS
702static inline u8 mlx4_ib_bond_next_port(struct mlx4_ib_dev *dev)
703{
704 dev->bond_next_port = (dev->bond_next_port + 1) % dev->num_ports;
705
706 return dev->bond_next_port + 1;
707}
708
fc06573d
JM
709int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev);
710void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev);
711
225c7b1f 712int mlx4_ib_db_map_user(struct mlx4_ib_ucontext *context, unsigned long virt,
6296883c
YP
713 struct mlx4_db *db);
714void mlx4_ib_db_unmap_user(struct mlx4_ib_ucontext *context, struct mlx4_db *db);
225c7b1f
RD
715
716struct ib_mr *mlx4_ib_get_dma_mr(struct ib_pd *pd, int acc);
717int mlx4_ib_umem_write_mtt(struct mlx4_ib_dev *dev, struct mlx4_mtt *mtt,
718 struct ib_umem *umem);
719struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
720 u64 virt_addr, int access_flags,
721 struct ib_udata *udata);
722int mlx4_ib_dereg_mr(struct ib_mr *mr);
b2a239df
MB
723struct ib_mw *mlx4_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
724 struct ib_udata *udata);
804d6a89 725int mlx4_ib_dealloc_mw(struct ib_mw *mw);
679e34d1
SG
726struct ib_mr *mlx4_ib_alloc_mr(struct ib_pd *pd,
727 enum ib_mr_type mr_type,
728 u32 max_num_sg);
ff2ba993 729int mlx4_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
9aa8b321 730 unsigned int *sg_offset);
3fdcb97f 731int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
bbf8eed1 732int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
bcf4c1ea
MB
733struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev,
734 const struct ib_cq_init_attr *attr,
225c7b1f
RD
735 struct ib_ucontext *context,
736 struct ib_udata *udata);
737int mlx4_ib_destroy_cq(struct ib_cq *cq);
738int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
739int mlx4_ib_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
740void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq);
741void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq);
742
743struct ib_ah *mlx4_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr);
744int mlx4_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
745int mlx4_ib_destroy_ah(struct ib_ah *ah);
746
747struct ib_srq *mlx4_ib_create_srq(struct ib_pd *pd,
748 struct ib_srq_init_attr *init_attr,
749 struct ib_udata *udata);
750int mlx4_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
751 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
65541cb7 752int mlx4_ib_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
225c7b1f
RD
753int mlx4_ib_destroy_srq(struct ib_srq *srq);
754void mlx4_ib_free_srq_wqe(struct mlx4_ib_srq *srq, int wqe_index);
755int mlx4_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
756 struct ib_recv_wr **bad_wr);
757
758struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
759 struct ib_qp_init_attr *init_attr,
760 struct ib_udata *udata);
761int mlx4_ib_destroy_qp(struct ib_qp *qp);
762int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
763 int attr_mask, struct ib_udata *udata);
6a775e2b
JM
764int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
765 struct ib_qp_init_attr *qp_init_attr);
225c7b1f
RD
766int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
767 struct ib_send_wr **bad_wr);
768int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
769 struct ib_recv_wr **bad_wr);
770
0a9a0188 771int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags,
a97e2d86
IW
772 int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
773 const void *in_mad, void *response_mad);
225c7b1f 774int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
a97e2d86 775 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
4cd7c947
IW
776 const struct ib_mad_hdr *in, size_t in_mad_size,
777 struct ib_mad_hdr *out, size_t *out_mad_size,
778 u16 *out_mad_pkey_index);
225c7b1f
RD
779int mlx4_ib_mad_init(struct mlx4_ib_dev *dev);
780void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev);
781
8ad11fb6
JM
782struct ib_fmr *mlx4_ib_fmr_alloc(struct ib_pd *pd, int mr_access_flags,
783 struct ib_fmr_attr *fmr_attr);
784int mlx4_ib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, int npages,
785 u64 iova);
786int mlx4_ib_unmap_fmr(struct list_head *fmr_list);
787int mlx4_ib_fmr_dealloc(struct ib_fmr *fmr);
0a9a0188
JM
788int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
789 struct ib_port_attr *props, int netw_view);
790int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
791 u16 *pkey, int netw_view);
8ad11fb6 792
a0c64a17
JM
793int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
794 union ib_gid *gid, int netw_view);
795
a29bec12 796static inline bool mlx4_ib_ah_grh_present(struct mlx4_ib_ah *ah)
225c7b1f 797{
fa417f7b
EC
798 u8 port = be32_to_cpu(ah->av.ib.port_pd) >> 24 & 3;
799
800 if (rdma_port_get_link_layer(ah->ibah.device, port) == IB_LINK_LAYER_ETHERNET)
a29bec12 801 return true;
fa417f7b
EC
802
803 return !!(ah->av.ib.g_slid & 0x80);
225c7b1f
RD
804}
805
b9c5d6a6
OD
806int mlx4_ib_mcg_port_init(struct mlx4_ib_demux_ctx *ctx);
807void mlx4_ib_mcg_port_cleanup(struct mlx4_ib_demux_ctx *ctx, int destroy_wq);
808void clean_vf_mcast(struct mlx4_ib_demux_ctx *ctx, int slave);
809int mlx4_ib_mcg_init(void);
810void mlx4_ib_mcg_destroy(void);
811
812int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid);
813
814int mlx4_ib_mcg_multiplex_handler(struct ib_device *ibdev, int port, int slave,
815 struct ib_sa_mad *sa_mad);
816int mlx4_ib_mcg_demux_handler(struct ib_device *ibdev, int port, int slave,
817 struct ib_sa_mad *mad);
818
fa417f7b
EC
819int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
820 union ib_gid *gid);
821
00f5ce99
JM
822void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num,
823 enum ib_event_type type);
824
fc06573d
JM
825void mlx4_ib_tunnels_update_work(struct work_struct *work);
826
b9c5d6a6
OD
827int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port,
828 enum ib_qp_type qpt, struct ib_wc *wc,
829 struct ib_grh *grh, struct ib_mad *mad);
5ea8bbfc 830
b9c5d6a6
OD
831int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port,
832 enum ib_qp_type dest_qpt, u16 pkey_index, u32 remote_qpn,
5ea8bbfc 833 u32 qkey, struct ib_ah_attr *attr, u8 *s_mac,
dbf727de 834 u16 vlan_id, struct ib_mad *mad);
5ea8bbfc 835
b9c5d6a6
OD
836__be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx);
837
3cf69cc8
AV
838int mlx4_ib_demux_cm_handler(struct ib_device *ibdev, int port, int *slave,
839 struct ib_mad *mad);
840
841int mlx4_ib_multiplex_cm_handler(struct ib_device *ibdev, int port, int slave_id,
842 struct ib_mad *mad);
843
844void mlx4_ib_cm_paravirt_init(struct mlx4_ib_dev *dev);
845void mlx4_ib_cm_paravirt_clean(struct mlx4_ib_dev *dev, int slave_id);
846
a0c64a17
JM
847/* alias guid support */
848void mlx4_ib_init_alias_guid_work(struct mlx4_ib_dev *dev, int port);
849int mlx4_ib_init_alias_guid_service(struct mlx4_ib_dev *dev);
850void mlx4_ib_destroy_alias_guid_service(struct mlx4_ib_dev *dev);
851void mlx4_ib_invalidate_all_guid_record(struct mlx4_ib_dev *dev, int port);
852
853void mlx4_ib_notify_slaves_on_guid_change(struct mlx4_ib_dev *dev,
854 int block_num,
855 u8 port_num, u8 *p_data);
856
857void mlx4_ib_update_cache_on_guid_change(struct mlx4_ib_dev *dev,
858 int block_num, u8 port_num,
859 u8 *p_data);
860
c1e7e466
JM
861int add_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num,
862 struct attribute *attr);
863void del_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num,
864 struct attribute *attr);
865ib_sa_comp_mask mlx4_ib_get_aguid_comp_mask_from_ix(int index);
ee59fa0d
YH
866void mlx4_ib_slave_alias_guid_event(struct mlx4_ib_dev *dev, int slave,
867 int port, int slave_init);
c1e7e466
JM
868
869int mlx4_ib_device_register_sysfs(struct mlx4_ib_dev *device) ;
870
871void mlx4_ib_device_unregister_sysfs(struct mlx4_ib_dev *device);
872
afa8fd1d
JM
873__be64 mlx4_ib_gen_node_guid(void);
874
c1c98501
MB
875int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn);
876void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count);
877int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
878 int is_attach);
9376932d
MB
879int mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags,
880 u64 start, u64 length, u64 virt_addr,
881 int mr_access_flags, struct ib_pd *pd,
882 struct ib_udata *udata);
e26be1bf
MS
883int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
884 u8 port_num, int index);
afa8fd1d 885
225c7b1f 886#endif /* MLX4_IB_H */