Commit | Line | Data |
---|---|---|
d24ecfcc | 1 | /* |
bd584996 | 2 | * Blackfin On-Chip Two Wire Interface Driver |
d24ecfcc | 3 | * |
bd584996 | 4 | * Copyright 2005-2007 Analog Devices Inc. |
d24ecfcc | 5 | * |
bd584996 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
d24ecfcc | 7 | * |
bd584996 | 8 | * Licensed under the GPL-2 or later. |
d24ecfcc BW |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/i2c.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
6df263cf | 16 | #include <linux/io.h> |
d24ecfcc BW |
17 | #include <linux/mm.h> |
18 | #include <linux/timer.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/completion.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/platform_device.h> | |
540ac555 | 23 | #include <linux/delay.h> |
45126da2 | 24 | #include <linux/i2c/bfin_twi.h> |
d24ecfcc | 25 | |
d24ecfcc | 26 | #include <asm/irq.h> |
45126da2 | 27 | #include <asm/portmux.h> |
c9d87edb | 28 | #include <asm/bfin_twi.h> |
d24ecfcc | 29 | |
d24ecfcc | 30 | /* SMBus mode*/ |
4dd39bb1 SZ |
31 | #define TWI_I2C_MODE_STANDARD 1 |
32 | #define TWI_I2C_MODE_STANDARDSUB 2 | |
33 | #define TWI_I2C_MODE_COMBINED 3 | |
34 | #define TWI_I2C_MODE_REPEAT 4 | |
d24ecfcc | 35 | |
5481d075 SZ |
36 | static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface, |
37 | unsigned short twi_int_status) | |
d24ecfcc | 38 | { |
aa3d0209 | 39 | unsigned short mast_stat = read_MASTER_STAT(iface); |
d24ecfcc BW |
40 | |
41 | if (twi_int_status & XMTSERV) { | |
8419c8de SZ |
42 | if (iface->writeNum <= 0) { |
43 | /* start receive immediately after complete sending in | |
44 | * combine mode. | |
45 | */ | |
46 | if (iface->cur_mode == TWI_I2C_MODE_COMBINED) | |
47 | write_MASTER_CTL(iface, | |
48 | read_MASTER_CTL(iface) | MDIR); | |
49 | else if (iface->manual_stop) | |
50 | write_MASTER_CTL(iface, | |
51 | read_MASTER_CTL(iface) | STOP); | |
52 | else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && | |
53 | iface->cur_msg + 1 < iface->msg_num) { | |
54 | if (iface->pmsg[iface->cur_msg + 1].flags & | |
55 | I2C_M_RD) | |
56 | write_MASTER_CTL(iface, | |
57 | read_MASTER_CTL(iface) | | |
58 | MDIR); | |
59 | else | |
60 | write_MASTER_CTL(iface, | |
61 | read_MASTER_CTL(iface) & | |
62 | ~MDIR); | |
63 | } | |
64 | } | |
d24ecfcc | 65 | /* Transmit next data */ |
8419c8de SZ |
66 | while (iface->writeNum > 0 && |
67 | (read_FIFO_STAT(iface) & XMTSTAT) != XMT_FULL) { | |
aa3d0209 | 68 | write_XMT_DATA8(iface, *(iface->transPtr++)); |
d24ecfcc BW |
69 | iface->writeNum--; |
70 | } | |
d24ecfcc BW |
71 | } |
72 | if (twi_int_status & RCVSERV) { | |
8419c8de SZ |
73 | while (iface->readNum > 0 && |
74 | (read_FIFO_STAT(iface) & RCVSTAT)) { | |
d24ecfcc | 75 | /* Receive next data */ |
aa3d0209 | 76 | *(iface->transPtr) = read_RCV_DATA8(iface); |
d24ecfcc BW |
77 | if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { |
78 | /* Change combine mode into sub mode after | |
79 | * read first data. | |
80 | */ | |
81 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
82 | /* Get read number from first byte in block | |
83 | * combine mode. | |
84 | */ | |
85 | if (iface->readNum == 1 && iface->manual_stop) | |
86 | iface->readNum = *iface->transPtr + 1; | |
87 | } | |
88 | iface->transPtr++; | |
89 | iface->readNum--; | |
a20a64d2 SZ |
90 | } |
91 | ||
92 | if (iface->readNum == 0) { | |
93 | if (iface->manual_stop) { | |
94 | /* Temporary workaround to avoid possible bus stall - | |
95 | * Flush FIFO before issuing the STOP condition | |
96 | */ | |
97 | read_RCV_DATA16(iface); | |
94327d00 | 98 | write_MASTER_CTL(iface, |
a20a64d2 SZ |
99 | read_MASTER_CTL(iface) | STOP); |
100 | } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && | |
101 | iface->cur_msg + 1 < iface->msg_num) { | |
102 | if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD) | |
103 | write_MASTER_CTL(iface, | |
28a377c7 | 104 | read_MASTER_CTL(iface) | MDIR); |
a20a64d2 SZ |
105 | else |
106 | write_MASTER_CTL(iface, | |
28a377c7 | 107 | read_MASTER_CTL(iface) & ~MDIR); |
a20a64d2 | 108 | } |
d24ecfcc | 109 | } |
d24ecfcc BW |
110 | } |
111 | if (twi_int_status & MERR) { | |
aa3d0209 BW |
112 | write_INT_MASK(iface, 0); |
113 | write_MASTER_STAT(iface, 0x3e); | |
114 | write_MASTER_CTL(iface, 0); | |
4dd39bb1 | 115 | iface->result = -EIO; |
5cfafc18 MH |
116 | |
117 | if (mast_stat & LOSTARB) | |
118 | dev_dbg(&iface->adap.dev, "Lost Arbitration\n"); | |
119 | if (mast_stat & ANAK) | |
120 | dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n"); | |
121 | if (mast_stat & DNAK) | |
122 | dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n"); | |
123 | if (mast_stat & BUFRDERR) | |
124 | dev_dbg(&iface->adap.dev, "Buffer Read Error\n"); | |
125 | if (mast_stat & BUFWRERR) | |
126 | dev_dbg(&iface->adap.dev, "Buffer Write Error\n"); | |
127 | ||
540ac555 MH |
128 | /* Faulty slave devices, may drive SDA low after a transfer |
129 | * finishes. To release the bus this code generates up to 9 | |
130 | * extra clocks until SDA is released. | |
131 | */ | |
132 | ||
133 | if (read_MASTER_STAT(iface) & SDASEN) { | |
134 | int cnt = 9; | |
135 | do { | |
136 | write_MASTER_CTL(iface, SCLOVR); | |
137 | udelay(6); | |
138 | write_MASTER_CTL(iface, 0); | |
139 | udelay(6); | |
140 | } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--); | |
141 | ||
142 | write_MASTER_CTL(iface, SDAOVR | SCLOVR); | |
143 | udelay(6); | |
144 | write_MASTER_CTL(iface, SDAOVR); | |
145 | udelay(6); | |
146 | write_MASTER_CTL(iface, 0); | |
147 | } | |
148 | ||
f0ac131a SZ |
149 | /* If it is a quick transfer, only address without data, |
150 | * not an err, return 1. | |
d24ecfcc | 151 | */ |
f0ac131a SZ |
152 | if (iface->cur_mode == TWI_I2C_MODE_STANDARD && |
153 | iface->transPtr == NULL && | |
154 | (twi_int_status & MCOMP) && (mast_stat & DNAK)) | |
155 | iface->result = 1; | |
156 | ||
d24ecfcc BW |
157 | complete(&iface->complete); |
158 | return; | |
159 | } | |
160 | if (twi_int_status & MCOMP) { | |
2ee74eb9 SZ |
161 | if (twi_int_status & (XMTSERV | RCVSERV) && |
162 | (read_MASTER_CTL(iface) & MEN) == 0 && | |
4a65163e SZ |
163 | (iface->cur_mode == TWI_I2C_MODE_REPEAT || |
164 | iface->cur_mode == TWI_I2C_MODE_COMBINED)) { | |
165 | iface->result = -1; | |
166 | write_INT_MASK(iface, 0); | |
167 | write_MASTER_CTL(iface, 0); | |
168 | } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { | |
d24ecfcc BW |
169 | if (iface->readNum == 0) { |
170 | /* set the read number to 1 and ask for manual | |
171 | * stop in block combine mode | |
172 | */ | |
173 | iface->readNum = 1; | |
174 | iface->manual_stop = 1; | |
aa3d0209 BW |
175 | write_MASTER_CTL(iface, |
176 | read_MASTER_CTL(iface) | (0xff << 6)); | |
d24ecfcc BW |
177 | } else { |
178 | /* set the readd number in other | |
179 | * combine mode. | |
180 | */ | |
aa3d0209 BW |
181 | write_MASTER_CTL(iface, |
182 | (read_MASTER_CTL(iface) & | |
d24ecfcc | 183 | (~(0xff << 6))) | |
aa3d0209 | 184 | (iface->readNum << 6)); |
d24ecfcc BW |
185 | } |
186 | /* remove restart bit and enable master receive */ | |
aa3d0209 BW |
187 | write_MASTER_CTL(iface, |
188 | read_MASTER_CTL(iface) & ~RSTART); | |
4dd39bb1 | 189 | } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && |
28a377c7 | 190 | iface->cur_msg + 1 < iface->msg_num) { |
4dd39bb1 SZ |
191 | iface->cur_msg++; |
192 | iface->transPtr = iface->pmsg[iface->cur_msg].buf; | |
193 | iface->writeNum = iface->readNum = | |
194 | iface->pmsg[iface->cur_msg].len; | |
195 | /* Set Transmit device address */ | |
aa3d0209 | 196 | write_MASTER_ADDR(iface, |
4dd39bb1 SZ |
197 | iface->pmsg[iface->cur_msg].addr); |
198 | if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD) | |
199 | iface->read_write = I2C_SMBUS_READ; | |
200 | else { | |
201 | iface->read_write = I2C_SMBUS_WRITE; | |
202 | /* Transmit first data */ | |
203 | if (iface->writeNum > 0) { | |
aa3d0209 | 204 | write_XMT_DATA8(iface, |
4dd39bb1 SZ |
205 | *(iface->transPtr++)); |
206 | iface->writeNum--; | |
4dd39bb1 SZ |
207 | } |
208 | } | |
209 | ||
a20a64d2 SZ |
210 | if (iface->pmsg[iface->cur_msg].len <= 255) { |
211 | write_MASTER_CTL(iface, | |
57a8f32e SZ |
212 | (read_MASTER_CTL(iface) & |
213 | (~(0xff << 6))) | | |
a20a64d2 SZ |
214 | (iface->pmsg[iface->cur_msg].len << 6)); |
215 | iface->manual_stop = 0; | |
216 | } else { | |
57a8f32e SZ |
217 | write_MASTER_CTL(iface, |
218 | (read_MASTER_CTL(iface) | | |
219 | (0xff << 6))); | |
4dd39bb1 SZ |
220 | iface->manual_stop = 1; |
221 | } | |
28a377c7 SZ |
222 | /* remove restart bit before last message */ |
223 | if (iface->cur_msg + 1 == iface->msg_num) | |
224 | write_MASTER_CTL(iface, | |
225 | read_MASTER_CTL(iface) & ~RSTART); | |
d24ecfcc BW |
226 | } else { |
227 | iface->result = 1; | |
aa3d0209 BW |
228 | write_INT_MASK(iface, 0); |
229 | write_MASTER_CTL(iface, 0); | |
d24ecfcc | 230 | } |
a20a64d2 | 231 | complete(&iface->complete); |
d24ecfcc BW |
232 | } |
233 | } | |
234 | ||
235 | /* Interrupt handler */ | |
236 | static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id) | |
237 | { | |
238 | struct bfin_twi_iface *iface = dev_id; | |
239 | unsigned long flags; | |
5481d075 | 240 | unsigned short twi_int_status; |
d24ecfcc BW |
241 | |
242 | spin_lock_irqsave(&iface->lock, flags); | |
5481d075 SZ |
243 | while (1) { |
244 | twi_int_status = read_INT_STAT(iface); | |
245 | if (!twi_int_status) | |
246 | break; | |
247 | /* Clear interrupt status */ | |
248 | write_INT_STAT(iface, twi_int_status); | |
249 | bfin_twi_handle_interrupt(iface, twi_int_status); | |
5481d075 | 250 | } |
d24ecfcc BW |
251 | spin_unlock_irqrestore(&iface->lock, flags); |
252 | return IRQ_HANDLED; | |
253 | } | |
254 | ||
d24ecfcc | 255 | /* |
dd7319a5 | 256 | * One i2c master transfer |
d24ecfcc | 257 | */ |
dd7319a5 | 258 | static int bfin_twi_do_master_xfer(struct i2c_adapter *adap, |
d24ecfcc BW |
259 | struct i2c_msg *msgs, int num) |
260 | { | |
261 | struct bfin_twi_iface *iface = adap->algo_data; | |
262 | struct i2c_msg *pmsg; | |
d24ecfcc BW |
263 | int rc = 0; |
264 | ||
aa3d0209 | 265 | if (!(read_CONTROL(iface) & TWI_ENA)) |
d24ecfcc BW |
266 | return -ENXIO; |
267 | ||
a25733d6 SZ |
268 | if (read_MASTER_STAT(iface) & BUSBUSY) |
269 | return -EAGAIN; | |
d24ecfcc | 270 | |
4dd39bb1 SZ |
271 | iface->pmsg = msgs; |
272 | iface->msg_num = num; | |
273 | iface->cur_msg = 0; | |
d24ecfcc | 274 | |
4dd39bb1 SZ |
275 | pmsg = &msgs[0]; |
276 | if (pmsg->flags & I2C_M_TEN) { | |
277 | dev_err(&adap->dev, "10 bits addr not supported!\n"); | |
278 | return -EINVAL; | |
279 | } | |
d24ecfcc | 280 | |
28a377c7 SZ |
281 | if (iface->msg_num > 1) |
282 | iface->cur_mode = TWI_I2C_MODE_REPEAT; | |
4dd39bb1 SZ |
283 | iface->manual_stop = 0; |
284 | iface->transPtr = pmsg->buf; | |
285 | iface->writeNum = iface->readNum = pmsg->len; | |
286 | iface->result = 0; | |
afc13b76 | 287 | init_completion(&(iface->complete)); |
4dd39bb1 | 288 | /* Set Transmit device address */ |
aa3d0209 | 289 | write_MASTER_ADDR(iface, pmsg->addr); |
4dd39bb1 SZ |
290 | |
291 | /* FIFO Initiation. Data in FIFO should be | |
292 | * discarded before start a new operation. | |
293 | */ | |
aa3d0209 | 294 | write_FIFO_CTL(iface, 0x3); |
aa3d0209 | 295 | write_FIFO_CTL(iface, 0); |
4dd39bb1 SZ |
296 | |
297 | if (pmsg->flags & I2C_M_RD) | |
298 | iface->read_write = I2C_SMBUS_READ; | |
299 | else { | |
300 | iface->read_write = I2C_SMBUS_WRITE; | |
301 | /* Transmit first data */ | |
302 | if (iface->writeNum > 0) { | |
aa3d0209 | 303 | write_XMT_DATA8(iface, *(iface->transPtr++)); |
4dd39bb1 | 304 | iface->writeNum--; |
d24ecfcc | 305 | } |
4dd39bb1 | 306 | } |
d24ecfcc | 307 | |
4dd39bb1 | 308 | /* clear int stat */ |
aa3d0209 | 309 | write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); |
d24ecfcc | 310 | |
4dd39bb1 | 311 | /* Interrupt mask . Enable XMT, RCV interrupt */ |
aa3d0209 | 312 | write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); |
d24ecfcc | 313 | |
4dd39bb1 | 314 | if (pmsg->len <= 255) |
aa3d0209 | 315 | write_MASTER_CTL(iface, pmsg->len << 6); |
4dd39bb1 | 316 | else { |
aa3d0209 | 317 | write_MASTER_CTL(iface, 0xff << 6); |
4dd39bb1 SZ |
318 | iface->manual_stop = 1; |
319 | } | |
d24ecfcc | 320 | |
4dd39bb1 | 321 | /* Master enable */ |
aa3d0209 | 322 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
28a377c7 | 323 | (iface->msg_num > 1 ? RSTART : 0) | |
4dd39bb1 SZ |
324 | ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | |
325 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); | |
4dd39bb1 | 326 | |
dd7319a5 SZ |
327 | while (!iface->result) { |
328 | if (!wait_for_completion_timeout(&iface->complete, | |
329 | adap->timeout)) { | |
330 | iface->result = -1; | |
331 | dev_err(&adap->dev, "master transfer timeout\n"); | |
332 | } | |
333 | } | |
d24ecfcc | 334 | |
dd7319a5 SZ |
335 | if (iface->result == 1) |
336 | rc = iface->cur_msg + 1; | |
4dd39bb1 | 337 | else |
dd7319a5 SZ |
338 | rc = iface->result; |
339 | ||
340 | return rc; | |
d24ecfcc BW |
341 | } |
342 | ||
343 | /* | |
dd7319a5 | 344 | * Generic i2c master transfer entrypoint |
d24ecfcc | 345 | */ |
dd7319a5 SZ |
346 | static int bfin_twi_master_xfer(struct i2c_adapter *adap, |
347 | struct i2c_msg *msgs, int num) | |
348 | { | |
be2f80f0 | 349 | return bfin_twi_do_master_xfer(adap, msgs, num); |
dd7319a5 SZ |
350 | } |
351 | ||
352 | /* | |
353 | * One I2C SMBus transfer | |
354 | */ | |
355 | int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr, | |
d24ecfcc BW |
356 | unsigned short flags, char read_write, |
357 | u8 command, int size, union i2c_smbus_data *data) | |
358 | { | |
359 | struct bfin_twi_iface *iface = adap->algo_data; | |
360 | int rc = 0; | |
361 | ||
aa3d0209 | 362 | if (!(read_CONTROL(iface) & TWI_ENA)) |
d24ecfcc BW |
363 | return -ENXIO; |
364 | ||
a25733d6 SZ |
365 | if (read_MASTER_STAT(iface) & BUSBUSY) |
366 | return -EAGAIN; | |
d24ecfcc BW |
367 | |
368 | iface->writeNum = 0; | |
369 | iface->readNum = 0; | |
370 | ||
371 | /* Prepare datas & select mode */ | |
372 | switch (size) { | |
373 | case I2C_SMBUS_QUICK: | |
374 | iface->transPtr = NULL; | |
375 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
376 | break; | |
377 | case I2C_SMBUS_BYTE: | |
378 | if (data == NULL) | |
379 | iface->transPtr = NULL; | |
380 | else { | |
381 | if (read_write == I2C_SMBUS_READ) | |
382 | iface->readNum = 1; | |
383 | else | |
384 | iface->writeNum = 1; | |
385 | iface->transPtr = &data->byte; | |
386 | } | |
387 | iface->cur_mode = TWI_I2C_MODE_STANDARD; | |
388 | break; | |
389 | case I2C_SMBUS_BYTE_DATA: | |
390 | if (read_write == I2C_SMBUS_READ) { | |
391 | iface->readNum = 1; | |
392 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
393 | } else { | |
394 | iface->writeNum = 1; | |
395 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
396 | } | |
397 | iface->transPtr = &data->byte; | |
398 | break; | |
399 | case I2C_SMBUS_WORD_DATA: | |
400 | if (read_write == I2C_SMBUS_READ) { | |
401 | iface->readNum = 2; | |
402 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
403 | } else { | |
404 | iface->writeNum = 2; | |
405 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
406 | } | |
407 | iface->transPtr = (u8 *)&data->word; | |
408 | break; | |
409 | case I2C_SMBUS_PROC_CALL: | |
410 | iface->writeNum = 2; | |
411 | iface->readNum = 2; | |
412 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
413 | iface->transPtr = (u8 *)&data->word; | |
414 | break; | |
415 | case I2C_SMBUS_BLOCK_DATA: | |
416 | if (read_write == I2C_SMBUS_READ) { | |
417 | iface->readNum = 0; | |
418 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
419 | } else { | |
420 | iface->writeNum = data->block[0] + 1; | |
421 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
422 | } | |
423 | iface->transPtr = data->block; | |
424 | break; | |
e0cd2dd5 MH |
425 | case I2C_SMBUS_I2C_BLOCK_DATA: |
426 | if (read_write == I2C_SMBUS_READ) { | |
427 | iface->readNum = data->block[0]; | |
428 | iface->cur_mode = TWI_I2C_MODE_COMBINED; | |
429 | } else { | |
430 | iface->writeNum = data->block[0]; | |
431 | iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; | |
432 | } | |
433 | iface->transPtr = (u8 *)&data->block[1]; | |
434 | break; | |
d24ecfcc BW |
435 | default: |
436 | return -1; | |
437 | } | |
438 | ||
439 | iface->result = 0; | |
440 | iface->manual_stop = 0; | |
441 | iface->read_write = read_write; | |
442 | iface->command = command; | |
afc13b76 | 443 | init_completion(&(iface->complete)); |
d24ecfcc BW |
444 | |
445 | /* FIFO Initiation. Data in FIFO should be discarded before | |
446 | * start a new operation. | |
447 | */ | |
aa3d0209 | 448 | write_FIFO_CTL(iface, 0x3); |
aa3d0209 | 449 | write_FIFO_CTL(iface, 0); |
d24ecfcc BW |
450 | |
451 | /* clear int stat */ | |
aa3d0209 | 452 | write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); |
d24ecfcc BW |
453 | |
454 | /* Set Transmit device address */ | |
aa3d0209 | 455 | write_MASTER_ADDR(iface, addr); |
d24ecfcc | 456 | |
d24ecfcc BW |
457 | switch (iface->cur_mode) { |
458 | case TWI_I2C_MODE_STANDARDSUB: | |
aa3d0209 BW |
459 | write_XMT_DATA8(iface, iface->command); |
460 | write_INT_MASK(iface, MCOMP | MERR | | |
d24ecfcc BW |
461 | ((iface->read_write == I2C_SMBUS_READ) ? |
462 | RCVSERV : XMTSERV)); | |
d24ecfcc BW |
463 | |
464 | if (iface->writeNum + 1 <= 255) | |
aa3d0209 | 465 | write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); |
d24ecfcc | 466 | else { |
aa3d0209 | 467 | write_MASTER_CTL(iface, 0xff << 6); |
d24ecfcc BW |
468 | iface->manual_stop = 1; |
469 | } | |
470 | /* Master enable */ | |
aa3d0209 | 471 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
472 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); |
473 | break; | |
474 | case TWI_I2C_MODE_COMBINED: | |
aa3d0209 BW |
475 | write_XMT_DATA8(iface, iface->command); |
476 | write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); | |
d24ecfcc BW |
477 | |
478 | if (iface->writeNum > 0) | |
aa3d0209 | 479 | write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); |
d24ecfcc | 480 | else |
aa3d0209 | 481 | write_MASTER_CTL(iface, 0x1 << 6); |
d24ecfcc | 482 | /* Master enable */ |
28a377c7 | 483 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | RSTART | |
d24ecfcc BW |
484 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); |
485 | break; | |
486 | default: | |
aa3d0209 | 487 | write_MASTER_CTL(iface, 0); |
d24ecfcc BW |
488 | if (size != I2C_SMBUS_QUICK) { |
489 | /* Don't access xmit data register when this is a | |
490 | * read operation. | |
491 | */ | |
492 | if (iface->read_write != I2C_SMBUS_READ) { | |
493 | if (iface->writeNum > 0) { | |
aa3d0209 BW |
494 | write_XMT_DATA8(iface, |
495 | *(iface->transPtr++)); | |
d24ecfcc | 496 | if (iface->writeNum <= 255) |
aa3d0209 BW |
497 | write_MASTER_CTL(iface, |
498 | iface->writeNum << 6); | |
d24ecfcc | 499 | else { |
aa3d0209 BW |
500 | write_MASTER_CTL(iface, |
501 | 0xff << 6); | |
d24ecfcc BW |
502 | iface->manual_stop = 1; |
503 | } | |
504 | iface->writeNum--; | |
505 | } else { | |
aa3d0209 BW |
506 | write_XMT_DATA8(iface, iface->command); |
507 | write_MASTER_CTL(iface, 1 << 6); | |
d24ecfcc BW |
508 | } |
509 | } else { | |
510 | if (iface->readNum > 0 && iface->readNum <= 255) | |
aa3d0209 BW |
511 | write_MASTER_CTL(iface, |
512 | iface->readNum << 6); | |
d24ecfcc | 513 | else if (iface->readNum > 255) { |
aa3d0209 | 514 | write_MASTER_CTL(iface, 0xff << 6); |
d24ecfcc | 515 | iface->manual_stop = 1; |
dd7319a5 | 516 | } else |
d24ecfcc | 517 | break; |
d24ecfcc BW |
518 | } |
519 | } | |
aa3d0209 | 520 | write_INT_MASK(iface, MCOMP | MERR | |
d24ecfcc BW |
521 | ((iface->read_write == I2C_SMBUS_READ) ? |
522 | RCVSERV : XMTSERV)); | |
d24ecfcc BW |
523 | |
524 | /* Master enable */ | |
aa3d0209 | 525 | write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | |
d24ecfcc BW |
526 | ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | |
527 | ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); | |
528 | break; | |
529 | } | |
d24ecfcc | 530 | |
dd7319a5 SZ |
531 | while (!iface->result) { |
532 | if (!wait_for_completion_timeout(&iface->complete, | |
533 | adap->timeout)) { | |
534 | iface->result = -1; | |
535 | dev_err(&adap->dev, "smbus transfer timeout\n"); | |
536 | } | |
537 | } | |
d24ecfcc BW |
538 | |
539 | rc = (iface->result >= 0) ? 0 : -1; | |
540 | ||
d24ecfcc BW |
541 | return rc; |
542 | } | |
543 | ||
dd7319a5 SZ |
544 | /* |
545 | * Generic I2C SMBus transfer entrypoint | |
546 | */ | |
547 | int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr, | |
548 | unsigned short flags, char read_write, | |
549 | u8 command, int size, union i2c_smbus_data *data) | |
550 | { | |
be2f80f0 | 551 | return bfin_twi_do_smbus_xfer(adap, addr, flags, |
dd7319a5 | 552 | read_write, command, size, data); |
dd7319a5 SZ |
553 | } |
554 | ||
d24ecfcc BW |
555 | /* |
556 | * Return what the adapter supports | |
557 | */ | |
558 | static u32 bfin_twi_functionality(struct i2c_adapter *adap) | |
559 | { | |
560 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
561 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
562 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL | | |
e0cd2dd5 | 563 | I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK; |
d24ecfcc BW |
564 | } |
565 | ||
d24ecfcc BW |
566 | static struct i2c_algorithm bfin_twi_algorithm = { |
567 | .master_xfer = bfin_twi_master_xfer, | |
568 | .smbus_xfer = bfin_twi_smbus_xfer, | |
569 | .functionality = bfin_twi_functionality, | |
570 | }; | |
571 | ||
2fb9ac0c | 572 | #ifdef CONFIG_PM_SLEEP |
85777ad2 | 573 | static int i2c_bfin_twi_suspend(struct device *dev) |
d24ecfcc | 574 | { |
85777ad2 | 575 | struct bfin_twi_iface *iface = dev_get_drvdata(dev); |
958585f5 MH |
576 | |
577 | iface->saved_clkdiv = read_CLKDIV(iface); | |
578 | iface->saved_control = read_CONTROL(iface); | |
579 | ||
580 | free_irq(iface->irq, iface); | |
d24ecfcc BW |
581 | |
582 | /* Disable TWI */ | |
958585f5 | 583 | write_CONTROL(iface, iface->saved_control & ~TWI_ENA); |
d24ecfcc BW |
584 | |
585 | return 0; | |
586 | } | |
587 | ||
85777ad2 | 588 | static int i2c_bfin_twi_resume(struct device *dev) |
d24ecfcc | 589 | { |
85777ad2 | 590 | struct bfin_twi_iface *iface = dev_get_drvdata(dev); |
d24ecfcc | 591 | |
958585f5 | 592 | int rc = request_irq(iface->irq, bfin_twi_interrupt_entry, |
85777ad2 | 593 | 0, to_platform_device(dev)->name, iface); |
958585f5 | 594 | if (rc) { |
85777ad2 | 595 | dev_err(dev, "Can't get IRQ %d !\n", iface->irq); |
958585f5 MH |
596 | return -ENODEV; |
597 | } | |
598 | ||
599 | /* Resume TWI interface clock as specified */ | |
600 | write_CLKDIV(iface, iface->saved_clkdiv); | |
601 | ||
602 | /* Resume TWI */ | |
603 | write_CONTROL(iface, iface->saved_control); | |
d24ecfcc BW |
604 | |
605 | return 0; | |
606 | } | |
607 | ||
85777ad2 RW |
608 | static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm, |
609 | i2c_bfin_twi_suspend, i2c_bfin_twi_resume); | |
2fb9ac0c JH |
610 | #define I2C_BFIN_TWI_PM_OPS (&i2c_bfin_twi_pm) |
611 | #else | |
612 | #define I2C_BFIN_TWI_PM_OPS NULL | |
613 | #endif | |
85777ad2 | 614 | |
aa3d0209 | 615 | static int i2c_bfin_twi_probe(struct platform_device *pdev) |
d24ecfcc | 616 | { |
aa3d0209 | 617 | struct bfin_twi_iface *iface; |
d24ecfcc | 618 | struct i2c_adapter *p_adap; |
aa3d0209 | 619 | struct resource *res; |
d24ecfcc | 620 | int rc; |
9528d1c7 | 621 | unsigned int clkhilow; |
d24ecfcc | 622 | |
0709dc97 SZ |
623 | iface = devm_kzalloc(&pdev->dev, sizeof(struct bfin_twi_iface), |
624 | GFP_KERNEL); | |
aa3d0209 BW |
625 | if (!iface) { |
626 | dev_err(&pdev->dev, "Cannot allocate memory\n"); | |
0709dc97 | 627 | return -ENOMEM; |
aa3d0209 BW |
628 | } |
629 | ||
d24ecfcc | 630 | spin_lock_init(&(iface->lock)); |
aa3d0209 BW |
631 | |
632 | /* Find and map our resources */ | |
633 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
0709dc97 SZ |
634 | iface->regs_base = devm_ioremap_resource(&pdev->dev, res); |
635 | if (IS_ERR(iface->regs_base)) { | |
aa3d0209 | 636 | dev_err(&pdev->dev, "Cannot map IO\n"); |
0709dc97 | 637 | return PTR_ERR(iface->regs_base); |
aa3d0209 BW |
638 | } |
639 | ||
640 | iface->irq = platform_get_irq(pdev, 0); | |
641 | if (iface->irq < 0) { | |
642 | dev_err(&pdev->dev, "No IRQ specified\n"); | |
0709dc97 | 643 | return -ENOENT; |
aa3d0209 | 644 | } |
d24ecfcc | 645 | |
d24ecfcc | 646 | p_adap = &iface->adap; |
aa3d0209 BW |
647 | p_adap->nr = pdev->id; |
648 | strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name)); | |
d24ecfcc BW |
649 | p_adap->algo = &bfin_twi_algorithm; |
650 | p_adap->algo_data = iface; | |
aa5b775e | 651 | p_adap->class = I2C_CLASS_DEPRECATED; |
aa3d0209 | 652 | p_adap->dev.parent = &pdev->dev; |
dd7319a5 SZ |
653 | p_adap->timeout = 5 * HZ; |
654 | p_adap->retries = 3; | |
d24ecfcc | 655 | |
6d4028c6 | 656 | rc = peripheral_request_list( |
3c41aa71 | 657 | dev_get_platdata(&pdev->dev), |
6d4028c6 | 658 | "i2c-bfin-twi"); |
74d362e0 BW |
659 | if (rc) { |
660 | dev_err(&pdev->dev, "Can't setup pin mux!\n"); | |
0709dc97 | 661 | return -EBUSY; |
74d362e0 BW |
662 | } |
663 | ||
0709dc97 | 664 | rc = devm_request_irq(&pdev->dev, iface->irq, bfin_twi_interrupt_entry, |
4311051c | 665 | 0, pdev->name, iface); |
d24ecfcc | 666 | if (rc) { |
aa3d0209 BW |
667 | dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq); |
668 | rc = -ENODEV; | |
0709dc97 | 669 | goto out_error; |
d24ecfcc BW |
670 | } |
671 | ||
672 | /* Set TWI internal clock as 10MHz */ | |
ac07fb4d | 673 | write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F); |
d24ecfcc | 674 | |
9528d1c7 MH |
675 | /* |
676 | * We will not end up with a CLKDIV=0 because no one will specify | |
ac07fb4d | 677 | * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250) |
9528d1c7 | 678 | */ |
ac07fb4d | 679 | clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2; |
9528d1c7 | 680 | |
d24ecfcc | 681 | /* Set Twi interface clock as specified */ |
9528d1c7 | 682 | write_CLKDIV(iface, (clkhilow << 8) | clkhilow); |
d24ecfcc BW |
683 | |
684 | /* Enable TWI */ | |
aa3d0209 | 685 | write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA); |
d24ecfcc | 686 | |
991dee59 | 687 | rc = i2c_add_numbered_adapter(p_adap); |
aa3d0209 BW |
688 | if (rc < 0) { |
689 | dev_err(&pdev->dev, "Can't add i2c adapter!\n"); | |
0709dc97 | 690 | goto out_error; |
aa3d0209 BW |
691 | } |
692 | ||
693 | platform_set_drvdata(pdev, iface); | |
d24ecfcc | 694 | |
e952849a | 695 | dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Controller, " |
fa6ad222 | 696 | "regs_base@%p\n", iface->regs_base); |
aa3d0209 BW |
697 | |
698 | return 0; | |
699 | ||
0709dc97 | 700 | out_error: |
3c41aa71 | 701 | peripheral_free_list(dev_get_platdata(&pdev->dev)); |
d24ecfcc BW |
702 | return rc; |
703 | } | |
704 | ||
705 | static int i2c_bfin_twi_remove(struct platform_device *pdev) | |
706 | { | |
707 | struct bfin_twi_iface *iface = platform_get_drvdata(pdev); | |
708 | ||
d24ecfcc | 709 | i2c_del_adapter(&(iface->adap)); |
3c41aa71 | 710 | peripheral_free_list(dev_get_platdata(&pdev->dev)); |
d24ecfcc BW |
711 | |
712 | return 0; | |
713 | } | |
714 | ||
715 | static struct platform_driver i2c_bfin_twi_driver = { | |
716 | .probe = i2c_bfin_twi_probe, | |
717 | .remove = i2c_bfin_twi_remove, | |
d24ecfcc BW |
718 | .driver = { |
719 | .name = "i2c-bfin-twi", | |
2fb9ac0c | 720 | .pm = I2C_BFIN_TWI_PM_OPS, |
d24ecfcc BW |
721 | }, |
722 | }; | |
723 | ||
724 | static int __init i2c_bfin_twi_init(void) | |
725 | { | |
d24ecfcc BW |
726 | return platform_driver_register(&i2c_bfin_twi_driver); |
727 | } | |
728 | ||
729 | static void __exit i2c_bfin_twi_exit(void) | |
730 | { | |
731 | platform_driver_unregister(&i2c_bfin_twi_driver); | |
732 | } | |
733 | ||
74f56c4a | 734 | subsys_initcall(i2c_bfin_twi_init); |
d24ecfcc | 735 | module_exit(i2c_bfin_twi_exit); |
fa6ad222 BW |
736 | |
737 | MODULE_AUTHOR("Bryan Wu, Sonic Zhang"); | |
e952849a | 738 | MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Controller Driver"); |
fa6ad222 | 739 | MODULE_LICENSE("GPL"); |
add8eda7 | 740 | MODULE_ALIAS("platform:i2c-bfin-twi"); |