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drm/radeon: add vce dpm support for KV/KB
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_vce.c
CommitLineData
d93f7937
CK		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 * Authors: Christian König <christian.koenig@amd.com>
26 */
27
28#include <linux/firmware.h>
29#include <linux/module.h>
30#include <drm/drmP.h>
31#include <drm/drm.h>
32
33#include "radeon.h"
34#include "radeon_asic.h"
35#include "sid.h"
36
37/* Firmware Names */
38#define FIRMWARE_BONAIRE "radeon/BONAIRE_vce.bin"
39
40MODULE_FIRMWARE(FIRMWARE_BONAIRE);
41
42/**
43 * radeon_vce_init - allocate memory, load vce firmware
44 *
45 * @rdev: radeon_device pointer
46 *
47 * First step to get VCE online, allocate memory and load the firmware
48 */
49int radeon_vce_init(struct radeon_device *rdev)
50{
98ccc291
CK		 51 static const char *fw_version = "[ATI LIB=VCEFW,";
52 static const char *fb_version = "[ATI LIB=VCEFWSTATS,";
53 unsigned long size;
54 const char *fw_name, *c;
55 uint8_t start, mid, end;
d93f7937
CK		 56 int i, r;
57
58 switch (rdev->family) {
59 case CHIP_BONAIRE:
60 case CHIP_KAVERI:
61 case CHIP_KABINI:
62 fw_name = FIRMWARE_BONAIRE;
63 break;
64
65 default:
66 return -EINVAL;
67 }
68
69 r = request_firmware(&rdev->vce_fw, fw_name, rdev->dev);
70 if (r) {
71 dev_err(rdev->dev, "radeon_vce: Can't load firmware \"%s\"\n",
72 fw_name);
73 return r;
74 }
75
98ccc291
CK		 76 /* search for firmware version */
77
78 size = rdev->vce_fw->size - strlen(fw_version) - 9;
79 c = rdev->vce_fw->data;
80 for (;size > 0; --size, ++c)
81 if (strncmp(c, fw_version, strlen(fw_version)) == 0)
82 break;
83
84 if (size == 0)
85 return -EINVAL;
86
87 c += strlen(fw_version);
88 if (sscanf(c, "%2hhd.%2hhd.%2hhd]", &start, &mid, &end) != 3)
89 return -EINVAL;
90
91 /* search for feedback version */
92
93 size = rdev->vce_fw->size - strlen(fb_version) - 3;
94 c = rdev->vce_fw->data;
95 for (;size > 0; --size, ++c)
96 if (strncmp(c, fb_version, strlen(fb_version)) == 0)
97 break;
98
99 if (size == 0)
100 return -EINVAL;
101
102 c += strlen(fb_version);
103 if (sscanf(c, "%2u]", &rdev->vce.fb_version) != 1)
104 return -EINVAL;
105
106 DRM_INFO("Found VCE firmware/feedback version %hhd.%hhd.%hhd / %d!\n",
107 start, mid, end, rdev->vce.fb_version);
108
109 rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8);
110
111 /* we can only work with this fw version for now */
112 if (rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8)))
113 return -EINVAL;
114
115 /* load firmware into VRAM */
116
117 size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size) +
118 RADEON_VCE_STACK_SIZE + RADEON_VCE_HEAP_SIZE;
119 r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
d93f7937
CK		 120 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->vce.vcpu_bo);
121 if (r) {
122 dev_err(rdev->dev, "(%d) failed to allocate VCE bo\n", r);
123 return r;
124 }
125
126 r = radeon_vce_resume(rdev);
127 if (r)
128 return r;
129
98ccc291 130 memset(rdev->vce.cpu_addr, 0, size);
d93f7937
CK		 131 memcpy(rdev->vce.cpu_addr, rdev->vce_fw->data, rdev->vce_fw->size);
132
133 r = radeon_vce_suspend(rdev);
134 if (r)
135 return r;
136
137 for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
138 atomic_set(&rdev->vce.handles[i], 0);
139 rdev->vce.filp[i] = NULL;
140 }
141
142 return 0;
143}
144
145/**
146 * radeon_vce_fini - free memory
147 *
148 * @rdev: radeon_device pointer
149 *
150 * Last step on VCE teardown, free firmware memory
151 */
152void radeon_vce_fini(struct radeon_device *rdev)
153{
154 radeon_vce_suspend(rdev);
155 radeon_bo_unref(&rdev->vce.vcpu_bo);
156}
157
158/**
159 * radeon_vce_suspend - unpin VCE fw memory
160 *
161 * @rdev: radeon_device pointer
162 *
163 * TODO: Test VCE suspend/resume
164 */
165int radeon_vce_suspend(struct radeon_device *rdev)
166{
167 int r;
168
169 if (rdev->vce.vcpu_bo == NULL)
170 return 0;
171
172 r = radeon_bo_reserve(rdev->vce.vcpu_bo, false);
173 if (!r) {
174 radeon_bo_kunmap(rdev->vce.vcpu_bo);
175 radeon_bo_unpin(rdev->vce.vcpu_bo);
176 radeon_bo_unreserve(rdev->vce.vcpu_bo);
177 }
178 return r;
179}
180
181/**
182 * radeon_vce_resume - pin VCE fw memory
183 *
184 * @rdev: radeon_device pointer
185 *
186 * TODO: Test VCE suspend/resume
187 */
188int radeon_vce_resume(struct radeon_device *rdev)
189{
190 int r;
191
192 if (rdev->vce.vcpu_bo == NULL)
193 return -EINVAL;
194
195 r = radeon_bo_reserve(rdev->vce.vcpu_bo, false);
196 if (r) {
197 radeon_bo_unref(&rdev->vce.vcpu_bo);
198 dev_err(rdev->dev, "(%d) failed to reserve VCE bo\n", r);
199 return r;
200 }
201
202 r = radeon_bo_pin(rdev->vce.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
203 &rdev->vce.gpu_addr);
204 if (r) {
205 radeon_bo_unreserve(rdev->vce.vcpu_bo);
206 radeon_bo_unref(&rdev->vce.vcpu_bo);
207 dev_err(rdev->dev, "(%d) VCE bo pin failed\n", r);
208 return r;
209 }
210
211 r = radeon_bo_kmap(rdev->vce.vcpu_bo, &rdev->vce.cpu_addr);
212 if (r) {
213 dev_err(rdev->dev, "(%d) VCE map failed\n", r);
214 return r;
215 }
216
217 radeon_bo_unreserve(rdev->vce.vcpu_bo);
218
219 return 0;
220}
221
222/**
223 * radeon_vce_free_handles - free still open VCE handles
224 *
225 * @rdev: radeon_device pointer
226 * @filp: drm file pointer
227 *
228 * Close all VCE handles still open by this file pointer
229 */
230void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp)
231{
232 int i, r;
233 for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
234 uint32_t handle = atomic_read(&rdev->vce.handles[i]);
235 if (!handle || rdev->vce.filp[i] != filp)
236 continue;
237
238 r = radeon_vce_get_destroy_msg(rdev, TN_RING_TYPE_VCE1_INDEX,
239 handle, NULL);
240 if (r)
241 DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
242
243 rdev->vce.filp[i] = NULL;
244 atomic_set(&rdev->vce.handles[i], 0);
245 }
246}
247
248/**
249 * radeon_vce_get_create_msg - generate a VCE create msg
250 *
251 * @rdev: radeon_device pointer
252 * @ring: ring we should submit the msg to
253 * @handle: VCE session handle to use
254 * @fence: optional fence to return
255 *
256 * Open up a stream for HW test
257 */
258int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
259 uint32_t handle, struct radeon_fence **fence)
260{
261 const unsigned ib_size_dw = 1024;
262 struct radeon_ib ib;
263 uint64_t dummy;
264 int i, r;
265
266 r = radeon_ib_get(rdev, ring, &ib, NULL, ib_size_dw * 4);
267 if (r) {
268 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
269 return r;
270 }
271
272 dummy = ib.gpu_addr + 1024;
273
274 /* stitch together an VCE create msg */
275 ib.length_dw = 0;
276 ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
277 ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
278 ib.ptr[ib.length_dw++] = handle;
279
280 ib.ptr[ib.length_dw++] = 0x00000030; /* len */
281 ib.ptr[ib.length_dw++] = 0x01000001; /* create cmd */
282 ib.ptr[ib.length_dw++] = 0x00000000;
283 ib.ptr[ib.length_dw++] = 0x00000042;
284 ib.ptr[ib.length_dw++] = 0x0000000a;
285 ib.ptr[ib.length_dw++] = 0x00000001;
286 ib.ptr[ib.length_dw++] = 0x00000080;
287 ib.ptr[ib.length_dw++] = 0x00000060;
288 ib.ptr[ib.length_dw++] = 0x00000100;
289 ib.ptr[ib.length_dw++] = 0x00000100;
290 ib.ptr[ib.length_dw++] = 0x0000000c;
291 ib.ptr[ib.length_dw++] = 0x00000000;
292
293 ib.ptr[ib.length_dw++] = 0x00000014; /* len */
294 ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
295 ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
296 ib.ptr[ib.length_dw++] = dummy;
297 ib.ptr[ib.length_dw++] = 0x00000001;
298
299 for (i = ib.length_dw; i < ib_size_dw; ++i)
300 ib.ptr[i] = 0x0;
301
302 r = radeon_ib_schedule(rdev, &ib, NULL);
303 if (r) {
304 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
305 }
306
307 if (fence)
308 *fence = radeon_fence_ref(ib.fence);
309
310 radeon_ib_free(rdev, &ib);
311
312 return r;
313}
314
315/**
316 * radeon_vce_get_destroy_msg - generate a VCE destroy msg
317 *
318 * @rdev: radeon_device pointer
319 * @ring: ring we should submit the msg to
320 * @handle: VCE session handle to use
321 * @fence: optional fence to return
322 *
323 * Close up a stream for HW test or if userspace failed to do so
324 */
325int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
326 uint32_t handle, struct radeon_fence **fence)
327{
328 const unsigned ib_size_dw = 1024;
329 struct radeon_ib ib;
330 uint64_t dummy;
331 int i, r;
332
333 r = radeon_ib_get(rdev, ring, &ib, NULL, ib_size_dw * 4);
334 if (r) {
335 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
336 return r;
337 }
338
339 dummy = ib.gpu_addr + 1024;
340
341 /* stitch together an VCE destroy msg */
342 ib.length_dw = 0;
343 ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
344 ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
345 ib.ptr[ib.length_dw++] = handle;
346
347 ib.ptr[ib.length_dw++] = 0x00000014; /* len */
348 ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
349 ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
350 ib.ptr[ib.length_dw++] = dummy;
351 ib.ptr[ib.length_dw++] = 0x00000001;
352
353 ib.ptr[ib.length_dw++] = 0x00000008; /* len */
354 ib.ptr[ib.length_dw++] = 0x02000001; /* destroy cmd */
355
356 for (i = ib.length_dw; i < ib_size_dw; ++i)
357 ib.ptr[i] = 0x0;
358
359 r = radeon_ib_schedule(rdev, &ib, NULL);
360 if (r) {
361 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
362 }
363
364 if (fence)
365 *fence = radeon_fence_ref(ib.fence);
366
367 radeon_ib_free(rdev, &ib);
368
369 return r;
370}
371
372/**
373 * radeon_vce_cs_reloc - command submission relocation
374 *
375 * @p: parser context
376 * @lo: address of lower dword
377 * @hi: address of higher dword
378 *
379 * Patch relocation inside command stream with real buffer address
380 */
381int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi)
382{
383 struct radeon_cs_chunk *relocs_chunk;
384 uint64_t offset;
385 unsigned idx;
386
387 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
388 offset = radeon_get_ib_value(p, lo);
389 idx = radeon_get_ib_value(p, hi);
390
391 if (idx >= relocs_chunk->length_dw) {
392 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
393 idx, relocs_chunk->length_dw);
394 return -EINVAL;
395 }
396
397 offset += p->relocs_ptr[(idx / 4)]->lobj.gpu_offset;
398
399 p->ib.ptr[lo] = offset & 0xFFFFFFFF;
400 p->ib.ptr[hi] = offset >> 32;
401
402 return 0;
403}
404
405/**
406 * radeon_vce_cs_parse - parse and validate the command stream
407 *
408 * @p: parser context
409 *
410 */
411int radeon_vce_cs_parse(struct radeon_cs_parser *p)
412{
413 uint32_t handle = 0;
414 bool destroy = false;
415 int i, r;
416
417 while (p->idx < p->chunks[p->chunk_ib_idx].length_dw) {
418 uint32_t len = radeon_get_ib_value(p, p->idx);
419 uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);
420
421 if ((len < 8) || (len & 3)) {
422 DRM_ERROR("invalid VCE command length (%d)!\n", len);
423 return -EINVAL;
424 }
425
426 switch (cmd) {
427 case 0x00000001: // session
428 handle = radeon_get_ib_value(p, p->idx + 2);
429 break;
430
431 case 0x00000002: // task info
432 case 0x01000001: // create
433 case 0x04000001: // config extension
434 case 0x04000002: // pic control
435 case 0x04000005: // rate control
436 case 0x04000007: // motion estimation
437 case 0x04000008: // rdo
438 break;
439
440 case 0x03000001: // encode
441 r = radeon_vce_cs_reloc(p, p->idx + 10, p->idx + 9);
442 if (r)
443 return r;
444
445 r = radeon_vce_cs_reloc(p, p->idx + 12, p->idx + 11);
446 if (r)
447 return r;
448 break;
449
450 case 0x02000001: // destroy
451 destroy = true;
452 break;
453
454 case 0x05000001: // context buffer
455 case 0x05000004: // video bitstream buffer
456 case 0x05000005: // feedback buffer
457 r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2);
458 if (r)
459 return r;
460 break;
461
462 default:
463 DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
464 return -EINVAL;
465 }
466
467 p->idx += len / 4;
468 }
469
470 if (destroy) {
471 /* IB contains a destroy msg, free the handle */
472 for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i)
473 atomic_cmpxchg(&p->rdev->vce.handles[i], handle, 0);
474
475 return 0;
476 }
477
478 /* create or encode, validate the handle */
479 for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
480 if (atomic_read(&p->rdev->vce.handles[i]) == handle)
481 return 0;
482 }
483
484 /* handle not found try to alloc a new one */
485 for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
486 if (!atomic_cmpxchg(&p->rdev->vce.handles[i], 0, handle)) {
487 p->rdev->vce.filp[i] = p->filp;
488 return 0;
489 }
490 }
491
492 DRM_ERROR("No more free VCE handles!\n");
493 return -EINVAL;
494}
495
496/**
497 * radeon_vce_semaphore_emit - emit a semaphore command
498 *
499 * @rdev: radeon_device pointer
500 * @ring: engine to use
501 * @semaphore: address of semaphore
502 * @emit_wait: true=emit wait, false=emit signal
503 *
504 */
505bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
506 struct radeon_ring *ring,
507 struct radeon_semaphore *semaphore,
508 bool emit_wait)
509{
510 uint64_t addr = semaphore->gpu_addr;
511
512 radeon_ring_write(ring, VCE_CMD_SEMAPHORE);
513 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
514 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
515 radeon_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
516 if (!emit_wait)
517 radeon_ring_write(ring, VCE_CMD_END);
518
519 return true;
520}
521
522/**
523 * radeon_vce_ib_execute - execute indirect buffer
524 *
525 * @rdev: radeon_device pointer
526 * @ib: the IB to execute
527 *
528 */
529void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
530{
531 struct radeon_ring *ring = &rdev->ring[ib->ring];
532 radeon_ring_write(ring, VCE_CMD_IB);
533 radeon_ring_write(ring, ib->gpu_addr);
534 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
535 radeon_ring_write(ring, ib->length_dw);
536}
537
538/**
539 * radeon_vce_fence_emit - add a fence command to the ring
540 *
541 * @rdev: radeon_device pointer
542 * @fence: the fence
543 *
544 */
545void radeon_vce_fence_emit(struct radeon_device *rdev,
546 struct radeon_fence *fence)
547{
548 struct radeon_ring *ring = &rdev->ring[fence->ring];
549 uint32_t addr = rdev->fence_drv[fence->ring].gpu_addr;
550
551 radeon_ring_write(ring, VCE_CMD_FENCE);
552 radeon_ring_write(ring, addr);
553 radeon_ring_write(ring, upper_32_bits(addr));
554 radeon_ring_write(ring, fence->seq);
555 radeon_ring_write(ring, VCE_CMD_TRAP);
556 radeon_ring_write(ring, VCE_CMD_END);
557}
558
559/**
560 * radeon_vce_ring_test - test if VCE ring is working
561 *
562 * @rdev: radeon_device pointer
563 * @ring: the engine to test on
564 *
565 */
566int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
567{
568 uint32_t rptr = vce_v1_0_get_rptr(rdev, ring);
569 unsigned i;
570 int r;
571
572 r = radeon_ring_lock(rdev, ring, 16);
573 if (r) {
574 DRM_ERROR("radeon: vce failed to lock ring %d (%d).\n",
575 ring->idx, r);
576 return r;
577 }
578 radeon_ring_write(ring, VCE_CMD_END);
579 radeon_ring_unlock_commit(rdev, ring);
580
581 for (i = 0; i < rdev->usec_timeout; i++) {
582 if (vce_v1_0_get_rptr(rdev, ring) != rptr)
583 break;
584 DRM_UDELAY(1);
585 }
586
587 if (i < rdev->usec_timeout) {
588 DRM_INFO("ring test on %d succeeded in %d usecs\n",
589 ring->idx, i);
590 } else {
591 DRM_ERROR("radeon: ring %d test failed\n",
592 ring->idx);
593 r = -ETIMEDOUT;
594 }
595
596 return r;
597}
598
599/**
600 * radeon_vce_ib_test - test if VCE IBs are working
601 *
602 * @rdev: radeon_device pointer
603 * @ring: the engine to test on
604 *
605 */
606int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
607{
608 struct radeon_fence *fence = NULL;
609 int r;
610
611 r = radeon_vce_get_create_msg(rdev, ring->idx, 1, NULL);
612 if (r) {
613 DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
614 goto error;
615 }
616
617 r = radeon_vce_get_destroy_msg(rdev, ring->idx, 1, &fence);
618 if (r) {
619 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
620 goto error;
621 }
622
623 r = radeon_fence_wait(fence, false);
624 if (r) {
625 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
626 } else {
627 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
628 }
629error:
630 radeon_fence_unref(&fence);
631 return r;
632}
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