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drm: Rework vblank-wait handling to allow interrupt reduction.
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_cp.c
CommitLineData
f26c473c
DA		 1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2/*
1da177e4
LT		 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
45e51905 5 * Copyright 2007 Advanced Micro Devices, Inc.
1da177e4
LT		 6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32#include "drmP.h"
33#include "drm.h"
34#include "radeon_drm.h"
35#include "radeon_drv.h"
414ed537 36#include "r300_reg.h"
1da177e4 37
9f18409e
AD		 38#include "radeon_microcode.h"
39
1da177e4
LT		 40#define RADEON_FIFO_DEBUG 0
41
84b1fd10 42static int radeon_do_cleanup_cp(struct drm_device * dev);
54f961a6 43static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
1da177e4 44
45e51905 45static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
3d5e2c13
DA		 46{
47 u32 ret;
48 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
49 ret = RADEON_READ(R520_MC_IND_DATA);
50 RADEON_WRITE(R520_MC_IND_INDEX, 0);
51 return ret;
52}
53
45e51905
AD		 54static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
55{
56 u32 ret;
57 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
58 ret = RADEON_READ(RS480_NB_MC_DATA);
59 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
60 return ret;
61}
62
60f92683
MC		 63static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
64{
45e51905 65 u32 ret;
60f92683 66 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
45e51905
AD		 67 ret = RADEON_READ(RS690_MC_DATA);
68 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
69 return ret;
70}
71
72static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
73{
74 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
75 return RS690_READ_MCIND(dev_priv, addr);
76 else
77 return RS480_READ_MCIND(dev_priv, addr);
60f92683
MC		 78}
79
3d5e2c13
DA		 80u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
81{
82
83 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
45e51905 84 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
60f92683
MC		 85 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
86 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
3d5e2c13 87 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
45e51905 88 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
3d5e2c13
DA		 89 else
90 return RADEON_READ(RADEON_MC_FB_LOCATION);
91}
92
93static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
94{
95 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
45e51905 96 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
60f92683
MC		 97 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
98 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
3d5e2c13 99 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
45e51905 100 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
3d5e2c13
DA		 101 else
102 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
103}
104
105static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
106{
107 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
45e51905 108 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
60f92683
MC		 109 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
110 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
3d5e2c13 111 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
45e51905 112 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
3d5e2c13
DA		 113 else
114 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
115}
116
70b13d51
DA		 117static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
118{
119 u32 agp_base_hi = upper_32_bits(agp_base);
120 u32 agp_base_lo = agp_base & 0xffffffff;
121
122 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
123 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
124 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
125 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
126 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
127 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
128 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
129 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
130 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
5cfb6956
AD		 131 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
132 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
133 RADEON_WRITE(RS480_AGP_BASE_2, 0);
70b13d51
DA		 134 } else {
135 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
136 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
137 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
138 }
139}
140
84b1fd10 141static int RADEON_READ_PLL(struct drm_device * dev, int addr)
1da177e4
LT		 142{
143 drm_radeon_private_t *dev_priv = dev->dev_private;
144
145 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
146 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
147}
148
3d5e2c13 149static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
ea98a92f
DA		 150{
151 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
152 return RADEON_READ(RADEON_PCIE_DATA);
153}
154
1da177e4 155#if RADEON_FIFO_DEBUG
b5e89ed5 156static void radeon_status(drm_radeon_private_t * dev_priv)
1da177e4 157{
bf9d8929 158 printk("%s:\n", __func__);
b5e89ed5
DA		 159 printk("RBBM_STATUS = 0x%08x\n",
160 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
161 printk("CP_RB_RTPR = 0x%08x\n",
162 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
163 printk("CP_RB_WTPR = 0x%08x\n",
164 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
165 printk("AIC_CNTL = 0x%08x\n",
166 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
167 printk("AIC_STAT = 0x%08x\n",
168 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
169 printk("AIC_PT_BASE = 0x%08x\n",
170 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
171 printk("TLB_ADDR = 0x%08x\n",
172 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
173 printk("TLB_DATA = 0x%08x\n",
174 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
1da177e4
LT		 175}
176#endif
177
1da177e4
LT		 178/* ================================================================
179 * Engine, FIFO control
180 */
181
b5e89ed5 182static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
1da177e4
LT		 183{
184 u32 tmp;
185 int i;
186
187 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
188
259434ac
AD		 189 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
190 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
191 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
192 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
193
194 for (i = 0; i < dev_priv->usec_timeout; i++) {
195 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
196 & RADEON_RB3D_DC_BUSY)) {
197 return 0;
198 }
199 DRM_UDELAY(1);
200 }
201 } else {
54f961a6
JG		 202 /* don't flush or purge cache here or lockup */
203 return 0;
1da177e4
LT		 204 }
205
206#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 207 DRM_ERROR("failed!\n");
208 radeon_status(dev_priv);
1da177e4 209#endif
20caafa6 210 return -EBUSY;
1da177e4
LT		 211}
212
b5e89ed5 213static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
1da177e4
LT		 214{
215 int i;
216
217 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
218
b5e89ed5
DA		 219 for (i = 0; i < dev_priv->usec_timeout; i++) {
220 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
221 & RADEON_RBBM_FIFOCNT_MASK);
222 if (slots >= entries)
223 return 0;
224 DRM_UDELAY(1);
1da177e4 225 }
6c7be298 226 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
54f961a6
JG		 227 RADEON_READ(RADEON_RBBM_STATUS),
228 RADEON_READ(R300_VAP_CNTL_STATUS));
1da177e4
LT		 229
230#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 231 DRM_ERROR("failed!\n");
232 radeon_status(dev_priv);
1da177e4 233#endif
20caafa6 234 return -EBUSY;
1da177e4
LT		 235}
236
b5e89ed5 237static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 238{
239 int i, ret;
240
241 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
242
b5e89ed5
DA		 243 ret = radeon_do_wait_for_fifo(dev_priv, 64);
244 if (ret)
245 return ret;
1da177e4 246
b5e89ed5
DA		 247 for (i = 0; i < dev_priv->usec_timeout; i++) {
248 if (!(RADEON_READ(RADEON_RBBM_STATUS)
249 & RADEON_RBBM_ACTIVE)) {
250 radeon_do_pixcache_flush(dev_priv);
1da177e4
LT		 251 return 0;
252 }
b5e89ed5 253 DRM_UDELAY(1);
1da177e4 254 }
6c7be298 255 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
54f961a6
JG		 256 RADEON_READ(RADEON_RBBM_STATUS),
257 RADEON_READ(R300_VAP_CNTL_STATUS));
1da177e4
LT		 258
259#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 260 DRM_ERROR("failed!\n");
261 radeon_status(dev_priv);
1da177e4 262#endif
20caafa6 263 return -EBUSY;
1da177e4
LT		 264}
265
5b92c404
AD		 266static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
267{
268 uint32_t gb_tile_config, gb_pipe_sel = 0;
269
270 /* RS4xx/RS6xx/R4xx/R5xx */
271 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
272 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
273 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
274 } else {
275 /* R3xx */
276 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
277 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
278 dev_priv->num_gb_pipes = 2;
279 } else {
280 /* R3Vxx */
281 dev_priv->num_gb_pipes = 1;
282 }
283 }
284 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
285
286 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
287
288 switch (dev_priv->num_gb_pipes) {
289 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
290 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
291 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
292 default:
293 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
294 }
295
296 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
297 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
298 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
299 }
300 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
301 radeon_do_wait_for_idle(dev_priv);
302 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
303 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
304 R300_DC_AUTOFLUSH_ENABLE |
305 R300_DC_DC_DISABLE_IGNORE_PE));
306
307
308}
309
1da177e4
LT		 310/* ================================================================
311 * CP control, initialization
312 */
313
314/* Load the microcode for the CP */
b5e89ed5 315static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1da177e4
LT		 316{
317 int i;
b5e89ed5 318 DRM_DEBUG("\n");
1da177e4 319
b5e89ed5 320 radeon_do_wait_for_idle(dev_priv);
1da177e4 321
b5e89ed5 322 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
9f18409e
AD		 323 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
324 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
325 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
326 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
327 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
328 DRM_INFO("Loading R100 Microcode\n");
329 for (i = 0; i < 256; i++) {
330 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
331 R100_cp_microcode[i][1]);
332 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
333 R100_cp_microcode[i][0]);
334 }
335 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
336 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
337 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
338 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
1da177e4 339 DRM_INFO("Loading R200 Microcode\n");
b5e89ed5
DA		 340 for (i = 0; i < 256; i++) {
341 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
342 R200_cp_microcode[i][1]);
343 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
344 R200_cp_microcode[i][0]);
1da177e4 345 }
9f18409e
AD		 346 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
347 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
348 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
349 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
45e51905 350 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
1da177e4 351 DRM_INFO("Loading R300 Microcode\n");
b5e89ed5
DA		 352 for (i = 0; i < 256; i++) {
353 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
354 R300_cp_microcode[i][1]);
355 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
356 R300_cp_microcode[i][0]);
1da177e4 357 }
9f18409e
AD		 358 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
359 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
360 DRM_INFO("Loading R400 Microcode\n");
361 for (i = 0; i < 256; i++) {
362 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
363 R420_cp_microcode[i][1]);
364 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
365 R420_cp_microcode[i][0]);
366 }
367 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
368 DRM_INFO("Loading RS690 Microcode\n");
369 for (i = 0; i < 256; i++) {
370 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
371 RS690_cp_microcode[i][1]);
372 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
373 RS690_cp_microcode[i][0]);
374 }
375 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
376 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
377 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
378 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
379 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
380 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
381 DRM_INFO("Loading R500 Microcode\n");
b5e89ed5
DA		 382 for (i = 0; i < 256; i++) {
383 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
9f18409e 384 R520_cp_microcode[i][1]);
b5e89ed5 385 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
9f18409e 386 R520_cp_microcode[i][0]);
1da177e4
LT		 387 }
388 }
389}
390
391/* Flush any pending commands to the CP. This should only be used just
392 * prior to a wait for idle, as it informs the engine that the command
393 * stream is ending.
394 */
b5e89ed5 395static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
1da177e4 396{
b5e89ed5 397 DRM_DEBUG("\n");
1da177e4
LT		 398#if 0
399 u32 tmp;
400
b5e89ed5
DA		 401 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
402 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
1da177e4
LT		 403#endif
404}
405
406/* Wait for the CP to go idle.
407 */
b5e89ed5 408int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 409{
410 RING_LOCALS;
b5e89ed5 411 DRM_DEBUG("\n");
1da177e4 412
b5e89ed5 413 BEGIN_RING(6);
1da177e4
LT		 414
415 RADEON_PURGE_CACHE();
416 RADEON_PURGE_ZCACHE();
417 RADEON_WAIT_UNTIL_IDLE();
418
419 ADVANCE_RING();
420 COMMIT_RING();
421
b5e89ed5 422 return radeon_do_wait_for_idle(dev_priv);
1da177e4
LT		 423}
424
425/* Start the Command Processor.
426 */
b5e89ed5 427static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1da177e4
LT		 428{
429 RING_LOCALS;
b5e89ed5 430 DRM_DEBUG("\n");
1da177e4 431
b5e89ed5 432 radeon_do_wait_for_idle(dev_priv);
1da177e4 433
b5e89ed5 434 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1da177e4
LT		 435
436 dev_priv->cp_running = 1;
437
54f961a6
JG		 438 BEGIN_RING(8);
439 /* isync can only be written through cp on r5xx write it here */
440 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
441 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
442 RADEON_ISYNC_ANY3D_IDLE2D |
443 RADEON_ISYNC_WAIT_IDLEGUI |
444 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
1da177e4
LT		 445 RADEON_PURGE_CACHE();
446 RADEON_PURGE_ZCACHE();
447 RADEON_WAIT_UNTIL_IDLE();
1da177e4
LT		 448 ADVANCE_RING();
449 COMMIT_RING();
54f961a6
JG		 450
451 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
1da177e4
LT		 452}
453
454/* Reset the Command Processor. This will not flush any pending
455 * commands, so you must wait for the CP command stream to complete
456 * before calling this routine.
457 */
b5e89ed5 458static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1da177e4
LT		 459{
460 u32 cur_read_ptr;
b5e89ed5 461 DRM_DEBUG("\n");
1da177e4 462
b5e89ed5
DA		 463 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
464 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
465 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 466 dev_priv->ring.tail = cur_read_ptr;
467}
468
469/* Stop the Command Processor. This will not flush any pending
470 * commands, so you must flush the command stream and wait for the CP
471 * to go idle before calling this routine.
472 */
b5e89ed5 473static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1da177e4 474{
b5e89ed5 475 DRM_DEBUG("\n");
1da177e4 476
b5e89ed5 477 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1da177e4
LT		 478
479 dev_priv->cp_running = 0;
480}
481
482/* Reset the engine. This will stop the CP if it is running.
483 */
84b1fd10 484static int radeon_do_engine_reset(struct drm_device * dev)
1da177e4
LT		 485{
486 drm_radeon_private_t *dev_priv = dev->dev_private;
d396db32 487 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
b5e89ed5 488 DRM_DEBUG("\n");
1da177e4 489
b5e89ed5
DA		 490 radeon_do_pixcache_flush(dev_priv);
491
d396db32
AD		 492 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
493 /* may need something similar for newer chips */
3d5e2c13
DA		 494 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
495 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
496
497 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
498 RADEON_FORCEON_MCLKA |
499 RADEON_FORCEON_MCLKB |
500 RADEON_FORCEON_YCLKA |
501 RADEON_FORCEON_YCLKB |
502 RADEON_FORCEON_MC |
503 RADEON_FORCEON_AIC));
d396db32 504 }
3d5e2c13 505
d396db32
AD		 506 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
507
508 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
509 RADEON_SOFT_RESET_CP |
510 RADEON_SOFT_RESET_HI |
511 RADEON_SOFT_RESET_SE |
512 RADEON_SOFT_RESET_RE |
513 RADEON_SOFT_RESET_PP |
514 RADEON_SOFT_RESET_E2 |
515 RADEON_SOFT_RESET_RB));
516 RADEON_READ(RADEON_RBBM_SOFT_RESET);
517 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
518 ~(RADEON_SOFT_RESET_CP |
519 RADEON_SOFT_RESET_HI |
520 RADEON_SOFT_RESET_SE |
521 RADEON_SOFT_RESET_RE |
522 RADEON_SOFT_RESET_PP |
523 RADEON_SOFT_RESET_E2 |
524 RADEON_SOFT_RESET_RB)));
525 RADEON_READ(RADEON_RBBM_SOFT_RESET);
526
527 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
3d5e2c13
DA		 528 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
529 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
530 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
531 }
1da177e4 532
5b92c404
AD		 533 /* setup the raster pipes */
534 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
535 radeon_init_pipes(dev_priv);
536
1da177e4 537 /* Reset the CP ring */
b5e89ed5 538 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 539
540 /* The CP is no longer running after an engine reset */
541 dev_priv->cp_running = 0;
542
543 /* Reset any pending vertex, indirect buffers */
b5e89ed5 544 radeon_freelist_reset(dev);
1da177e4
LT		 545
546 return 0;
547}
548
84b1fd10 549static void radeon_cp_init_ring_buffer(struct drm_device * dev,
b5e89ed5 550 drm_radeon_private_t * dev_priv)
1da177e4
LT		 551{
552 u32 ring_start, cur_read_ptr;
553 u32 tmp;
bc5f4523 554
d5ea702f
DA		 555 /* Initialize the memory controller. With new memory map, the fb location
556 * is not changed, it should have been properly initialized already. Part
557 * of the problem is that the code below is bogus, assuming the GART is
558 * always appended to the fb which is not necessarily the case
559 */
560 if (!dev_priv->new_memmap)
3d5e2c13 561 radeon_write_fb_location(dev_priv,
d5ea702f
DA		 562 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
563 | (dev_priv->fb_location >> 16));
1da177e4
LT		 564
565#if __OS_HAS_AGP
54a56ac5 566 if (dev_priv->flags & RADEON_IS_AGP) {
70b13d51
DA		 567 radeon_write_agp_base(dev_priv, dev->agp->base);
568
3d5e2c13 569 radeon_write_agp_location(dev_priv,
b5e89ed5
DA		 570 (((dev_priv->gart_vm_start - 1 +
571 dev_priv->gart_size) & 0xffff0000) |
572 (dev_priv->gart_vm_start >> 16)));
1da177e4
LT		 573
574 ring_start = (dev_priv->cp_ring->offset
575 - dev->agp->base
576 + dev_priv->gart_vm_start);
b0917bd9 577 } else
1da177e4
LT		 578#endif
579 ring_start = (dev_priv->cp_ring->offset
b0917bd9 580 - (unsigned long)dev->sg->virtual
1da177e4
LT		 581 + dev_priv->gart_vm_start);
582
b5e89ed5 583 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1da177e4
LT		 584
585 /* Set the write pointer delay */
b5e89ed5 586 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1da177e4
LT		 587
588 /* Initialize the ring buffer's read and write pointers */
b5e89ed5
DA		 589 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
590 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
591 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 592 dev_priv->ring.tail = cur_read_ptr;
593
594#if __OS_HAS_AGP
54a56ac5 595 if (dev_priv->flags & RADEON_IS_AGP) {
b5e89ed5
DA		 596 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
597 dev_priv->ring_rptr->offset
598 - dev->agp->base + dev_priv->gart_vm_start);
1da177e4
LT		 599 } else
600#endif
601 {
55910517 602 struct drm_sg_mem *entry = dev->sg;
1da177e4
LT		 603 unsigned long tmp_ofs, page_ofs;
604
b0917bd9
IK		 605 tmp_ofs = dev_priv->ring_rptr->offset -
606 (unsigned long)dev->sg->virtual;
1da177e4
LT		 607 page_ofs = tmp_ofs >> PAGE_SHIFT;
608
b5e89ed5
DA		 609 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
610 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
611 (unsigned long)entry->busaddr[page_ofs],
612 entry->handle + tmp_ofs);
1da177e4
LT		 613 }
614
d5ea702f
DA		 615 /* Set ring buffer size */
616#ifdef __BIG_ENDIAN
617 RADEON_WRITE(RADEON_CP_RB_CNTL,
576cc458
RS		 618 RADEON_BUF_SWAP_32BIT |
619 (dev_priv->ring.fetch_size_l2ow << 18) |
620 (dev_priv->ring.rptr_update_l2qw << 8) |
621 dev_priv->ring.size_l2qw);
d5ea702f 622#else
576cc458
RS		 623 RADEON_WRITE(RADEON_CP_RB_CNTL,
624 (dev_priv->ring.fetch_size_l2ow << 18) |
625 (dev_priv->ring.rptr_update_l2qw << 8) |
626 dev_priv->ring.size_l2qw);
d5ea702f
DA		 627#endif
628
d5ea702f 629
1da177e4
LT		 630 /* Initialize the scratch register pointer. This will cause
631 * the scratch register values to be written out to memory
632 * whenever they are updated.
633 *
634 * We simply put this behind the ring read pointer, this works
635 * with PCI GART as well as (whatever kind of) AGP GART
636 */
b5e89ed5
DA		 637 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
638 + RADEON_SCRATCH_REG_OFFSET);
1da177e4
LT		 639
640 dev_priv->scratch = ((__volatile__ u32 *)
641 dev_priv->ring_rptr->handle +
642 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
643
b5e89ed5 644 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1da177e4 645
d5ea702f
DA		 646 /* Turn on bus mastering */
647 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
648 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1da177e4
LT		 649
650 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
b5e89ed5 651 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1da177e4
LT		 652
653 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
b5e89ed5
DA		 654 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
655 dev_priv->sarea_priv->last_dispatch);
1da177e4
LT		 656
657 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
b5e89ed5 658 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1da177e4 659
b5e89ed5 660 radeon_do_wait_for_idle(dev_priv);
1da177e4 661
1da177e4 662 /* Sync everything up */
b5e89ed5
DA		 663 RADEON_WRITE(RADEON_ISYNC_CNTL,
664 (RADEON_ISYNC_ANY2D_IDLE3D |
665 RADEON_ISYNC_ANY3D_IDLE2D |
666 RADEON_ISYNC_WAIT_IDLEGUI |
667 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
d5ea702f
DA		 668
669}
670
671static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
672{
673 u32 tmp;
674
6b79d521
DA		 675 /* Start with assuming that writeback doesn't work */
676 dev_priv->writeback_works = 0;
677
d5ea702f
DA		 678 /* Writeback doesn't seem to work everywhere, test it here and possibly
679 * enable it if it appears to work
680 */
681 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
682 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
683
684 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
685 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
686 0xdeadbeef)
687 break;
688 DRM_UDELAY(1);
689 }
690
691 if (tmp < dev_priv->usec_timeout) {
692 dev_priv->writeback_works = 1;
693 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
694 } else {
695 dev_priv->writeback_works = 0;
696 DRM_INFO("writeback test failed\n");
697 }
698 if (radeon_no_wb == 1) {
699 dev_priv->writeback_works = 0;
700 DRM_INFO("writeback forced off\n");
701 }
ae1b1a48
MD		 702
703 if (!dev_priv->writeback_works) {
704 /* Disable writeback to avoid unnecessary bus master transfer */
705 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
706 RADEON_RB_NO_UPDATE);
707 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
708 }
1da177e4
LT		 709}
710
f2b04cd2
DA		 711/* Enable or disable IGP GART on the chip */
712static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
60f92683
MC		 713{
714 u32 temp;
715
716 if (on) {
45e51905 717 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
60f92683
MC		 718 dev_priv->gart_vm_start,
719 (long)dev_priv->gart_info.bus_addr,
720 dev_priv->gart_size);
721
45e51905
AD		 722 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
723 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
724 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
725 RS690_BLOCK_GFX_D3_EN));
726 else
727 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
60f92683 728
45e51905
AD		 729 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
730 RS480_VA_SIZE_32MB));
60f92683 731
45e51905
AD		 732 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
733 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
734 RS480_TLB_ENABLE |
735 RS480_GTW_LAC_EN |
736 RS480_1LEVEL_GART));
60f92683 737
fa0d71b9
DA		 738 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
739 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
45e51905
AD		 740 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
741
742 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
743 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
744 RS480_REQ_TYPE_SNOOP_DIS));
745
5cfb6956 746 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
3722bfc6 747
60f92683
MC		 748 dev_priv->gart_size = 32*1024*1024;
749 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
750 0xffff0000) | (dev_priv->gart_vm_start >> 16));
751
45e51905 752 radeon_write_agp_location(dev_priv, temp);
60f92683 753
45e51905
AD		 754 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
755 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
756 RS480_VA_SIZE_32MB));
60f92683
MC		 757
758 do {
45e51905
AD		 759 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
760 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
60f92683
MC		 761 break;
762 DRM_UDELAY(1);
763 } while (1);
764
45e51905
AD		 765 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
766 RS480_GART_CACHE_INVALIDATE);
2735977b 767
60f92683 768 do {
45e51905
AD		 769 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
770 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
60f92683
MC		 771 break;
772 DRM_UDELAY(1);
773 } while (1);
774
45e51905 775 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
60f92683 776 } else {
45e51905 777 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
60f92683
MC		 778 }
779}
780
ea98a92f
DA		 781static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
782{
783 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
784 if (on) {
785
786 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
b5e89ed5
DA		 787 dev_priv->gart_vm_start,
788 (long)dev_priv->gart_info.bus_addr,
ea98a92f 789 dev_priv->gart_size);
b5e89ed5
DA		 790 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
791 dev_priv->gart_vm_start);
792 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
793 dev_priv->gart_info.bus_addr);
794 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
795 dev_priv->gart_vm_start);
796 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
797 dev_priv->gart_vm_start +
798 dev_priv->gart_size - 1);
799
3d5e2c13 800 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
b5e89ed5
DA		 801
802 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
803 RADEON_PCIE_TX_GART_EN);
ea98a92f 804 } else {
b5e89ed5
DA		 805 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
806 tmp & ~RADEON_PCIE_TX_GART_EN);
ea98a92f 807 }
1da177e4
LT		 808}
809
810/* Enable or disable PCI GART on the chip */
b5e89ed5 811static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1da177e4 812{
d985c108 813 u32 tmp;
1da177e4 814
45e51905
AD		 815 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
816 (dev_priv->flags & RADEON_IS_IGPGART)) {
f2b04cd2
DA		 817 radeon_set_igpgart(dev_priv, on);
818 return;
819 }
820
54a56ac5 821 if (dev_priv->flags & RADEON_IS_PCIE) {
ea98a92f
DA		 822 radeon_set_pciegart(dev_priv, on);
823 return;
824 }
1da177e4 825
bc5f4523 826 tmp = RADEON_READ(RADEON_AIC_CNTL);
d985c108 827
b5e89ed5
DA		 828 if (on) {
829 RADEON_WRITE(RADEON_AIC_CNTL,
830 tmp | RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 831
832 /* set PCI GART page-table base address
833 */
ea98a92f 834 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1da177e4
LT		 835
836 /* set address range for PCI address translate
837 */
b5e89ed5
DA		 838 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
839 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
840 + dev_priv->gart_size - 1);
1da177e4
LT		 841
842 /* Turn off AGP aperture -- is this required for PCI GART?
843 */
3d5e2c13 844 radeon_write_agp_location(dev_priv, 0xffffffc0);
b5e89ed5 845 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1da177e4 846 } else {
b5e89ed5
DA		 847 RADEON_WRITE(RADEON_AIC_CNTL,
848 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 849 }
850}
851
84b1fd10 852static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
1da177e4 853{
d985c108
DA		 854 drm_radeon_private_t *dev_priv = dev->dev_private;
855
b5e89ed5 856 DRM_DEBUG("\n");
1da177e4 857
f3dd5c37 858 /* if we require new memory map but we don't have it fail */
54a56ac5 859 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
b15ec368 860 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
f3dd5c37 861 radeon_do_cleanup_cp(dev);
20caafa6 862 return -EINVAL;
f3dd5c37
DA		 863 }
864
54a56ac5 865 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
d985c108 866 DRM_DEBUG("Forcing AGP card to PCI mode\n");
54a56ac5
DA		 867 dev_priv->flags &= ~RADEON_IS_AGP;
868 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
b15ec368
DA		 869 && !init->is_pci) {
870 DRM_DEBUG("Restoring AGP flag\n");
54a56ac5 871 dev_priv->flags |= RADEON_IS_AGP;
d985c108 872 }
1da177e4 873
54a56ac5 874 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
b5e89ed5 875 DRM_ERROR("PCI GART memory not allocated!\n");
1da177e4 876 radeon_do_cleanup_cp(dev);
20caafa6 877 return -EINVAL;
1da177e4
LT		 878 }
879
880 dev_priv->usec_timeout = init->usec_timeout;
b5e89ed5
DA		 881 if (dev_priv->usec_timeout < 1 ||
882 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
883 DRM_DEBUG("TIMEOUT problem!\n");
1da177e4 884 radeon_do_cleanup_cp(dev);
20caafa6 885 return -EINVAL;
1da177e4
LT		 886 }
887
ddbee333
DA		 888 /* Enable vblank on CRTC1 for older X servers
889 */
890 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
891
d985c108 892 switch(init->func) {
1da177e4 893 case RADEON_INIT_R200_CP:
b5e89ed5 894 dev_priv->microcode_version = UCODE_R200;
1da177e4
LT		 895 break;
896 case RADEON_INIT_R300_CP:
b5e89ed5 897 dev_priv->microcode_version = UCODE_R300;
1da177e4
LT		 898 break;
899 default:
b5e89ed5 900 dev_priv->microcode_version = UCODE_R100;
1da177e4 901 }
b5e89ed5 902
1da177e4
LT		 903 dev_priv->do_boxes = 0;
904 dev_priv->cp_mode = init->cp_mode;
905
906 /* We don't support anything other than bus-mastering ring mode,
907 * but the ring can be in either AGP or PCI space for the ring
908 * read pointer.
909 */
b5e89ed5
DA		 910 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
911 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
912 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1da177e4 913 radeon_do_cleanup_cp(dev);
20caafa6 914 return -EINVAL;
1da177e4
LT		 915 }
916
b5e89ed5 917 switch (init->fb_bpp) {
1da177e4
LT		 918 case 16:
919 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
920 break;
921 case 32:
922 default:
923 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
924 break;
925 }
b5e89ed5
DA		 926 dev_priv->front_offset = init->front_offset;
927 dev_priv->front_pitch = init->front_pitch;
928 dev_priv->back_offset = init->back_offset;
929 dev_priv->back_pitch = init->back_pitch;
1da177e4 930
b5e89ed5 931 switch (init->depth_bpp) {
1da177e4
LT		 932 case 16:
933 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
934 break;
935 case 32:
936 default:
937 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
938 break;
939 }
b5e89ed5
DA		 940 dev_priv->depth_offset = init->depth_offset;
941 dev_priv->depth_pitch = init->depth_pitch;
1da177e4
LT		 942
943 /* Hardware state for depth clears. Remove this if/when we no
944 * longer clear the depth buffer with a 3D rectangle. Hard-code
945 * all values to prevent unwanted 3D state from slipping through
946 * and screwing with the clear operation.
947 */
948 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
949 (dev_priv->color_fmt << 10) |
b5e89ed5
DA		 950 (dev_priv->microcode_version ==
951 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1da177e4 952
b5e89ed5
DA		 953 dev_priv->depth_clear.rb3d_zstencilcntl =
954 (dev_priv->depth_fmt |
955 RADEON_Z_TEST_ALWAYS |
956 RADEON_STENCIL_TEST_ALWAYS |
957 RADEON_STENCIL_S_FAIL_REPLACE |
958 RADEON_STENCIL_ZPASS_REPLACE |
959 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1da177e4
LT		 960
961 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
962 RADEON_BFACE_SOLID |
963 RADEON_FFACE_SOLID |
964 RADEON_FLAT_SHADE_VTX_LAST |
965 RADEON_DIFFUSE_SHADE_FLAT |
966 RADEON_ALPHA_SHADE_FLAT |
967 RADEON_SPECULAR_SHADE_FLAT |
968 RADEON_FOG_SHADE_FLAT |
969 RADEON_VTX_PIX_CENTER_OGL |
970 RADEON_ROUND_MODE_TRUNC |
971 RADEON_ROUND_PREC_8TH_PIX);
972
1da177e4 973
1da177e4
LT		 974 dev_priv->ring_offset = init->ring_offset;
975 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
976 dev_priv->buffers_offset = init->buffers_offset;
977 dev_priv->gart_textures_offset = init->gart_textures_offset;
b5e89ed5 978
da509d7a 979 dev_priv->sarea = drm_getsarea(dev);
b5e89ed5 980 if (!dev_priv->sarea) {
1da177e4 981 DRM_ERROR("could not find sarea!\n");
1da177e4 982 radeon_do_cleanup_cp(dev);
20caafa6 983 return -EINVAL;
1da177e4
LT		 984 }
985
1da177e4 986 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
b5e89ed5 987 if (!dev_priv->cp_ring) {
1da177e4 988 DRM_ERROR("could not find cp ring region!\n");
1da177e4 989 radeon_do_cleanup_cp(dev);
20caafa6 990 return -EINVAL;
1da177e4
LT		 991 }
992 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
b5e89ed5 993 if (!dev_priv->ring_rptr) {
1da177e4 994 DRM_ERROR("could not find ring read pointer!\n");
1da177e4 995 radeon_do_cleanup_cp(dev);
20caafa6 996 return -EINVAL;
1da177e4 997 }
d1f2b55a 998 dev->agp_buffer_token = init->buffers_offset;
1da177e4 999 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
b5e89ed5 1000 if (!dev->agp_buffer_map) {
1da177e4 1001 DRM_ERROR("could not find dma buffer region!\n");
1da177e4 1002 radeon_do_cleanup_cp(dev);
20caafa6 1003 return -EINVAL;
1da177e4
LT		 1004 }
1005
b5e89ed5
DA		 1006 if (init->gart_textures_offset) {
1007 dev_priv->gart_textures =
1008 drm_core_findmap(dev, init->gart_textures_offset);
1009 if (!dev_priv->gart_textures) {
1da177e4 1010 DRM_ERROR("could not find GART texture region!\n");
1da177e4 1011 radeon_do_cleanup_cp(dev);
20caafa6 1012 return -EINVAL;
1da177e4
LT		 1013 }
1014 }
1015
1016 dev_priv->sarea_priv =
b5e89ed5
DA		 1017 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1018 init->sarea_priv_offset);
1da177e4
LT		 1019
1020#if __OS_HAS_AGP
54a56ac5 1021 if (dev_priv->flags & RADEON_IS_AGP) {
b5e89ed5
DA		 1022 drm_core_ioremap(dev_priv->cp_ring, dev);
1023 drm_core_ioremap(dev_priv->ring_rptr, dev);
1024 drm_core_ioremap(dev->agp_buffer_map, dev);
1025 if (!dev_priv->cp_ring->handle ||
1026 !dev_priv->ring_rptr->handle ||
1027 !dev->agp_buffer_map->handle) {
1da177e4 1028 DRM_ERROR("could not find ioremap agp regions!\n");
1da177e4 1029 radeon_do_cleanup_cp(dev);
20caafa6 1030 return -EINVAL;
1da177e4
LT		 1031 }
1032 } else
1033#endif
1034 {
b5e89ed5 1035 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1da177e4 1036 dev_priv->ring_rptr->handle =
b5e89ed5
DA		 1037 (void *)dev_priv->ring_rptr->offset;
1038 dev->agp_buffer_map->handle =
1039 (void *)dev->agp_buffer_map->offset;
1040
1041 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1042 dev_priv->cp_ring->handle);
1043 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1044 dev_priv->ring_rptr->handle);
1045 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1046 dev->agp_buffer_map->handle);
1da177e4
LT		 1047 }
1048
3d5e2c13 1049 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
bc5f4523 1050 dev_priv->fb_size =
3d5e2c13 1051 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
d5ea702f 1052 - dev_priv->fb_location;
1da177e4 1053
b5e89ed5
DA		 1054 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1055 ((dev_priv->front_offset
1056 + dev_priv->fb_location) >> 10));
1da177e4 1057
b5e89ed5
DA		 1058 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1059 ((dev_priv->back_offset
1060 + dev_priv->fb_location) >> 10));
1da177e4 1061
b5e89ed5
DA		 1062 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1063 ((dev_priv->depth_offset
1064 + dev_priv->fb_location) >> 10));
1da177e4
LT		 1065
1066 dev_priv->gart_size = init->gart_size;
d5ea702f
DA		 1067
1068 /* New let's set the memory map ... */
1069 if (dev_priv->new_memmap) {
1070 u32 base = 0;
1071
1072 DRM_INFO("Setting GART location based on new memory map\n");
1073
1074 /* If using AGP, try to locate the AGP aperture at the same
1075 * location in the card and on the bus, though we have to
1076 * align it down.
1077 */
1078#if __OS_HAS_AGP
54a56ac5 1079 if (dev_priv->flags & RADEON_IS_AGP) {
d5ea702f
DA		 1080 base = dev->agp->base;
1081 /* Check if valid */
80b2c386
MD		 1082 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1083 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
d5ea702f
DA		 1084 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1085 dev->agp->base);
1086 base = 0;
1087 }
1088 }
1089#endif
1090 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1091 if (base == 0) {
1092 base = dev_priv->fb_location + dev_priv->fb_size;
80b2c386
MD		 1093 if (base < dev_priv->fb_location ||
1094 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
d5ea702f
DA		 1095 base = dev_priv->fb_location
1096 - dev_priv->gart_size;
bc5f4523 1097 }
d5ea702f
DA		 1098 dev_priv->gart_vm_start = base & 0xffc00000u;
1099 if (dev_priv->gart_vm_start != base)
1100 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1101 base, dev_priv->gart_vm_start);
1102 } else {
1103 DRM_INFO("Setting GART location based on old memory map\n");
1104 dev_priv->gart_vm_start = dev_priv->fb_location +
1105 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1106 }
1da177e4
LT		 1107
1108#if __OS_HAS_AGP
54a56ac5 1109 if (dev_priv->flags & RADEON_IS_AGP)
1da177e4 1110 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b5e89ed5
DA		 1111 - dev->agp->base
1112 + dev_priv->gart_vm_start);
1da177e4
LT		 1113 else
1114#endif
1115 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b0917bd9
IK		 1116 - (unsigned long)dev->sg->virtual
1117 + dev_priv->gart_vm_start);
1da177e4 1118
b5e89ed5
DA		 1119 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1120 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1121 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1122 dev_priv->gart_buffers_offset);
1da177e4 1123
b5e89ed5
DA		 1124 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1125 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1da177e4
LT		 1126 + init->ring_size / sizeof(u32));
1127 dev_priv->ring.size = init->ring_size;
b5e89ed5 1128 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1da177e4 1129
576cc458
RS		 1130 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1131 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1132
1133 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1134 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
b5e89ed5 1135 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1da177e4
LT		 1136
1137 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1138
1139#if __OS_HAS_AGP
54a56ac5 1140 if (dev_priv->flags & RADEON_IS_AGP) {
1da177e4 1141 /* Turn off PCI GART */
b5e89ed5 1142 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1143 } else
1144#endif
1145 {
b05c2385 1146 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
ea98a92f 1147 /* if we have an offset set from userspace */
f2b04cd2 1148 if (dev_priv->pcigart_offset_set) {
b5e89ed5
DA		 1149 dev_priv->gart_info.bus_addr =
1150 dev_priv->pcigart_offset + dev_priv->fb_location;
f26c473c 1151 dev_priv->gart_info.mapping.offset =
7fc86860 1152 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
f26c473c 1153 dev_priv->gart_info.mapping.size =
f2b04cd2 1154 dev_priv->gart_info.table_size;
f26c473c 1155
242e3df8 1156 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
b5e89ed5 1157 dev_priv->gart_info.addr =
f26c473c 1158 dev_priv->gart_info.mapping.handle;
b5e89ed5 1159
f2b04cd2
DA		 1160 if (dev_priv->flags & RADEON_IS_PCIE)
1161 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1162 else
1163 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
b5e89ed5
DA		 1164 dev_priv->gart_info.gart_table_location =
1165 DRM_ATI_GART_FB;
1166
f26c473c 1167 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
b5e89ed5
DA		 1168 dev_priv->gart_info.addr,
1169 dev_priv->pcigart_offset);
1170 } else {
f2b04cd2
DA		 1171 if (dev_priv->flags & RADEON_IS_IGPGART)
1172 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1173 else
1174 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
b5e89ed5
DA		 1175 dev_priv->gart_info.gart_table_location =
1176 DRM_ATI_GART_MAIN;
f26c473c
DA		 1177 dev_priv->gart_info.addr = NULL;
1178 dev_priv->gart_info.bus_addr = 0;
54a56ac5 1179 if (dev_priv->flags & RADEON_IS_PCIE) {
b5e89ed5
DA		 1180 DRM_ERROR
1181 ("Cannot use PCI Express without GART in FB memory\n");
ea98a92f 1182 radeon_do_cleanup_cp(dev);
20caafa6 1183 return -EINVAL;
ea98a92f
DA		 1184 }
1185 }
1186
1187 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
b5e89ed5 1188 DRM_ERROR("failed to init PCI GART!\n");
1da177e4 1189 radeon_do_cleanup_cp(dev);
20caafa6 1190 return -ENOMEM;
1da177e4
LT		 1191 }
1192
1193 /* Turn on PCI GART */
b5e89ed5 1194 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1195 }
1196
b5e89ed5
DA		 1197 radeon_cp_load_microcode(dev_priv);
1198 radeon_cp_init_ring_buffer(dev, dev_priv);
1da177e4
LT		 1199
1200 dev_priv->last_buf = 0;
1201
b5e89ed5 1202 radeon_do_engine_reset(dev);
d5ea702f 1203 radeon_test_writeback(dev_priv);
1da177e4
LT		 1204
1205 return 0;
1206}
1207
84b1fd10 1208static int radeon_do_cleanup_cp(struct drm_device * dev)
1da177e4
LT		 1209{
1210 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1211 DRM_DEBUG("\n");
1da177e4
LT		 1212
1213 /* Make sure interrupts are disabled here because the uninstall ioctl
1214 * may not have been called from userspace and after dev_private
1215 * is freed, it's too late.
1216 */
b5e89ed5
DA		 1217 if (dev->irq_enabled)
1218 drm_irq_uninstall(dev);
1da177e4
LT		 1219
1220#if __OS_HAS_AGP
54a56ac5 1221 if (dev_priv->flags & RADEON_IS_AGP) {
d985c108 1222 if (dev_priv->cp_ring != NULL) {
b5e89ed5 1223 drm_core_ioremapfree(dev_priv->cp_ring, dev);
d985c108
DA		 1224 dev_priv->cp_ring = NULL;
1225 }
1226 if (dev_priv->ring_rptr != NULL) {
b5e89ed5 1227 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
d985c108
DA		 1228 dev_priv->ring_rptr = NULL;
1229 }
b5e89ed5
DA		 1230 if (dev->agp_buffer_map != NULL) {
1231 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1da177e4
LT		 1232 dev->agp_buffer_map = NULL;
1233 }
1234 } else
1235#endif
1236 {
d985c108
DA		 1237
1238 if (dev_priv->gart_info.bus_addr) {
1239 /* Turn off PCI GART */
1240 radeon_set_pcigart(dev_priv, 0);
ea98a92f
DA		 1241 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1242 DRM_ERROR("failed to cleanup PCI GART!\n");
d985c108 1243 }
b5e89ed5 1244
d985c108
DA		 1245 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1246 {
f26c473c 1247 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
f2b04cd2 1248 dev_priv->gart_info.addr = 0;
ea98a92f 1249 }
1da177e4 1250 }
1da177e4
LT		 1251 /* only clear to the start of flags */
1252 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1253
1254 return 0;
1255}
1256
b5e89ed5
DA		 1257/* This code will reinit the Radeon CP hardware after a resume from disc.
1258 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1da177e4
LT		 1259 * here we make sure that all Radeon hardware initialisation is re-done without
1260 * affecting running applications.
1261 *
1262 * Charl P. Botha <http://cpbotha.net>
1263 */
84b1fd10 1264static int radeon_do_resume_cp(struct drm_device * dev)
1da177e4
LT		 1265{
1266 drm_radeon_private_t *dev_priv = dev->dev_private;
1267
b5e89ed5
DA		 1268 if (!dev_priv) {
1269 DRM_ERROR("Called with no initialization\n");
20caafa6 1270 return -EINVAL;
1da177e4
LT		 1271 }
1272
1273 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1274
1275#if __OS_HAS_AGP
54a56ac5 1276 if (dev_priv->flags & RADEON_IS_AGP) {
1da177e4 1277 /* Turn off PCI GART */
b5e89ed5 1278 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1279 } else
1280#endif
1281 {
1282 /* Turn on PCI GART */
b5e89ed5 1283 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1284 }
1285
b5e89ed5
DA		 1286 radeon_cp_load_microcode(dev_priv);
1287 radeon_cp_init_ring_buffer(dev, dev_priv);
1da177e4 1288
b5e89ed5 1289 radeon_do_engine_reset(dev);
0a3e67a4 1290 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1da177e4
LT		 1291
1292 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1293
1294 return 0;
1295}
1296
c153f45f 1297int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1298{
c153f45f 1299 drm_radeon_init_t *init = data;
1da177e4 1300
6c340eac 1301 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1302
c153f45f 1303 if (init->func == RADEON_INIT_R300_CP)
3d5e2c13 1304 r300_init_reg_flags(dev);
414ed537 1305
c153f45f 1306 switch (init->func) {
1da177e4
LT		 1307 case RADEON_INIT_CP:
1308 case RADEON_INIT_R200_CP:
1309 case RADEON_INIT_R300_CP:
c153f45f 1310 return radeon_do_init_cp(dev, init);
1da177e4 1311 case RADEON_CLEANUP_CP:
b5e89ed5 1312 return radeon_do_cleanup_cp(dev);
1da177e4
LT		 1313 }
1314
20caafa6 1315 return -EINVAL;
1da177e4
LT		 1316}
1317
c153f45f 1318int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1319{
1da177e4 1320 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1321 DRM_DEBUG("\n");
1da177e4 1322
6c340eac 1323 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1324
b5e89ed5 1325 if (dev_priv->cp_running) {
3e684eae 1326 DRM_DEBUG("while CP running\n");
1da177e4
LT		 1327 return 0;
1328 }
b5e89ed5 1329 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
3e684eae
MN		 1330 DRM_DEBUG("called with bogus CP mode (%d)\n",
1331 dev_priv->cp_mode);
1da177e4
LT		 1332 return 0;
1333 }
1334
b5e89ed5 1335 radeon_do_cp_start(dev_priv);
1da177e4
LT		 1336
1337 return 0;
1338}
1339
1340/* Stop the CP. The engine must have been idled before calling this
1341 * routine.
1342 */
c153f45f 1343int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1344{
1da177e4 1345 drm_radeon_private_t *dev_priv = dev->dev_private;
c153f45f 1346 drm_radeon_cp_stop_t *stop = data;
1da177e4 1347 int ret;
b5e89ed5 1348 DRM_DEBUG("\n");
1da177e4 1349
6c340eac 1350 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1351
1da177e4
LT		 1352 if (!dev_priv->cp_running)
1353 return 0;
1354
1355 /* Flush any pending CP commands. This ensures any outstanding
1356 * commands are exectuted by the engine before we turn it off.
1357 */
c153f45f 1358 if (stop->flush) {
b5e89ed5 1359 radeon_do_cp_flush(dev_priv);
1da177e4
LT		 1360 }
1361
1362 /* If we fail to make the engine go idle, we return an error
1363 * code so that the DRM ioctl wrapper can try again.
1364 */
c153f45f 1365 if (stop->idle) {
b5e89ed5
DA		 1366 ret = radeon_do_cp_idle(dev_priv);
1367 if (ret)
1368 return ret;
1da177e4
LT		 1369 }
1370
1371 /* Finally, we can turn off the CP. If the engine isn't idle,
1372 * we will get some dropped triangles as they won't be fully
1373 * rendered before the CP is shut down.
1374 */
b5e89ed5 1375 radeon_do_cp_stop(dev_priv);
1da177e4
LT		 1376
1377 /* Reset the engine */
b5e89ed5 1378 radeon_do_engine_reset(dev);
1da177e4
LT		 1379
1380 return 0;
1381}
1382
84b1fd10 1383void radeon_do_release(struct drm_device * dev)
1da177e4
LT		 1384{
1385 drm_radeon_private_t *dev_priv = dev->dev_private;
1386 int i, ret;
1387
1388 if (dev_priv) {
1389 if (dev_priv->cp_running) {
1390 /* Stop the cp */
b5e89ed5 1391 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1da177e4
LT		 1392 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1393#ifdef __linux__
1394 schedule();
1395#else
1396 tsleep(&ret, PZERO, "rdnrel", 1);
1397#endif
1398 }
b5e89ed5
DA		 1399 radeon_do_cp_stop(dev_priv);
1400 radeon_do_engine_reset(dev);
1da177e4
LT		 1401 }
1402
1403 /* Disable *all* interrupts */
1404 if (dev_priv->mmio) /* remove this after permanent addmaps */
b5e89ed5 1405 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1da177e4 1406
b5e89ed5 1407 if (dev_priv->mmio) { /* remove all surfaces */
1da177e4 1408 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
b5e89ed5
DA		 1409 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1410 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1411 16 * i, 0);
1412 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1413 16 * i, 0);
1da177e4
LT		 1414 }
1415 }
1416
1417 /* Free memory heap structures */
b5e89ed5
DA		 1418 radeon_mem_takedown(&(dev_priv->gart_heap));
1419 radeon_mem_takedown(&(dev_priv->fb_heap));
1da177e4
LT		 1420
1421 /* deallocate kernel resources */
b5e89ed5 1422 radeon_do_cleanup_cp(dev);
1da177e4
LT		 1423 }
1424}
1425
1426/* Just reset the CP ring. Called as part of an X Server engine reset.
1427 */
c153f45f 1428int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1429{
1da177e4 1430 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1431 DRM_DEBUG("\n");
1da177e4 1432
6c340eac 1433 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1434
b5e89ed5 1435 if (!dev_priv) {
3e684eae 1436 DRM_DEBUG("called before init done\n");
20caafa6 1437 return -EINVAL;
1da177e4
LT		 1438 }
1439
b5e89ed5 1440 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 1441
1442 /* The CP is no longer running after an engine reset */
1443 dev_priv->cp_running = 0;
1444
1445 return 0;
1446}
1447
c153f45f 1448int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1449{
1da177e4 1450 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1451 DRM_DEBUG("\n");
1da177e4 1452
6c340eac 1453 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1454
b5e89ed5 1455 return radeon_do_cp_idle(dev_priv);
1da177e4
LT		 1456}
1457
1458/* Added by Charl P. Botha to call radeon_do_resume_cp().
1459 */
c153f45f 1460int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1461{
1da177e4
LT		 1462
1463 return radeon_do_resume_cp(dev);
1464}
1465
c153f45f 1466int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1467{
b5e89ed5 1468 DRM_DEBUG("\n");
1da177e4 1469
6c340eac 1470 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1471
b5e89ed5 1472 return radeon_do_engine_reset(dev);
1da177e4
LT		 1473}
1474
1da177e4
LT		 1475/* ================================================================
1476 * Fullscreen mode
1477 */
1478
1479/* KW: Deprecated to say the least:
1480 */
c153f45f 1481int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4
LT		 1482{
1483 return 0;
1484}
1485
1da177e4
LT		 1486/* ================================================================
1487 * Freelist management
1488 */
1489
1490/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1491 * bufs until freelist code is used. Note this hides a problem with
1492 * the scratch register * (used to keep track of last buffer
1493 * completed) being written to before * the last buffer has actually
b5e89ed5 1494 * completed rendering.
1da177e4
LT		 1495 *
1496 * KW: It's also a good way to find free buffers quickly.
1497 *
1498 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1499 * sleep. However, bugs in older versions of radeon_accel.c mean that
1500 * we essentially have to do this, else old clients will break.
b5e89ed5 1501 *
1da177e4
LT		 1502 * However, it does leave open a potential deadlock where all the
1503 * buffers are held by other clients, which can't release them because
b5e89ed5 1504 * they can't get the lock.
1da177e4
LT		 1505 */
1506
056219e2 1507struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1da177e4 1508{
cdd55a29 1509 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 1510 drm_radeon_private_t *dev_priv = dev->dev_private;
1511 drm_radeon_buf_priv_t *buf_priv;
056219e2 1512 struct drm_buf *buf;
1da177e4
LT		 1513 int i, t;
1514 int start;
1515
b5e89ed5 1516 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 1517 dev_priv->last_buf = 0;
1518
1519 start = dev_priv->last_buf;
1520
b5e89ed5
DA		 1521 for (t = 0; t < dev_priv->usec_timeout; t++) {
1522 u32 done_age = GET_SCRATCH(1);
1523 DRM_DEBUG("done_age = %d\n", done_age);
1524 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 1525 buf = dma->buflist[i];
1526 buf_priv = buf->dev_private;
6c340eac
EA		 1527 if (buf->file_priv == NULL || (buf->pending &&
1528 buf_priv->age <=
1529 done_age)) {
1da177e4
LT		 1530 dev_priv->stats.requested_bufs++;
1531 buf->pending = 0;
1532 return buf;
1533 }
1534 start = 0;
1535 }
1536
1537 if (t) {
b5e89ed5 1538 DRM_UDELAY(1);
1da177e4
LT		 1539 dev_priv->stats.freelist_loops++;
1540 }
1541 }
1542
b5e89ed5 1543 DRM_DEBUG("returning NULL!\n");
1da177e4
LT		 1544 return NULL;
1545}
b5e89ed5 1546
1da177e4 1547#if 0
056219e2 1548struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1da177e4 1549{
cdd55a29 1550 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 1551 drm_radeon_private_t *dev_priv = dev->dev_private;
1552 drm_radeon_buf_priv_t *buf_priv;
056219e2 1553 struct drm_buf *buf;
1da177e4
LT		 1554 int i, t;
1555 int start;
1556 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1557
b5e89ed5 1558 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 1559 dev_priv->last_buf = 0;
1560
1561 start = dev_priv->last_buf;
1562 dev_priv->stats.freelist_loops++;
b5e89ed5
DA		 1563
1564 for (t = 0; t < 2; t++) {
1565 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 1566 buf = dma->buflist[i];
1567 buf_priv = buf->dev_private;
6c340eac
EA		 1568 if (buf->file_priv == 0 || (buf->pending &&
1569 buf_priv->age <=
1570 done_age)) {
1da177e4
LT		 1571 dev_priv->stats.requested_bufs++;
1572 buf->pending = 0;
1573 return buf;
1574 }
1575 }
1576 start = 0;
1577 }
1578
1579 return NULL;
1580}
1581#endif
1582
84b1fd10 1583void radeon_freelist_reset(struct drm_device * dev)
1da177e4 1584{
cdd55a29 1585 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 1586 drm_radeon_private_t *dev_priv = dev->dev_private;
1587 int i;
1588
1589 dev_priv->last_buf = 0;
b5e89ed5 1590 for (i = 0; i < dma->buf_count; i++) {
056219e2 1591 struct drm_buf *buf = dma->buflist[i];
1da177e4
LT		 1592 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1593 buf_priv->age = 0;
1594 }
1595}
1596
1da177e4
LT		 1597/* ================================================================
1598 * CP command submission
1599 */
1600
b5e89ed5 1601int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1da177e4
LT		 1602{
1603 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1604 int i;
b5e89ed5 1605 u32 last_head = GET_RING_HEAD(dev_priv);
1da177e4 1606
b5e89ed5
DA		 1607 for (i = 0; i < dev_priv->usec_timeout; i++) {
1608 u32 head = GET_RING_HEAD(dev_priv);
1da177e4
LT		 1609
1610 ring->space = (head - ring->tail) * sizeof(u32);
b5e89ed5 1611 if (ring->space <= 0)
1da177e4 1612 ring->space += ring->size;
b5e89ed5 1613 if (ring->space > n)
1da177e4 1614 return 0;
b5e89ed5 1615
1da177e4
LT		 1616 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1617
1618 if (head != last_head)
1619 i = 0;
1620 last_head = head;
1621
b5e89ed5 1622 DRM_UDELAY(1);
1da177e4
LT		 1623 }
1624
1625 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1626#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 1627 radeon_status(dev_priv);
1628 DRM_ERROR("failed!\n");
1da177e4 1629#endif
20caafa6 1630 return -EBUSY;
1da177e4
LT		 1631}
1632
6c340eac
EA		 1633static int radeon_cp_get_buffers(struct drm_device *dev,
1634 struct drm_file *file_priv,
c60ce623 1635 struct drm_dma * d)
1da177e4
LT		 1636{
1637 int i;
056219e2 1638 struct drm_buf *buf;
1da177e4 1639
b5e89ed5
DA		 1640 for (i = d->granted_count; i < d->request_count; i++) {
1641 buf = radeon_freelist_get(dev);
1642 if (!buf)
20caafa6 1643 return -EBUSY; /* NOTE: broken client */
1da177e4 1644
6c340eac 1645 buf->file_priv = file_priv;
1da177e4 1646
b5e89ed5
DA		 1647 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1648 sizeof(buf->idx)))
20caafa6 1649 return -EFAULT;
b5e89ed5
DA		 1650 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1651 sizeof(buf->total)))
20caafa6 1652 return -EFAULT;
1da177e4
LT		 1653
1654 d->granted_count++;
1655 }
1656 return 0;
1657}
1658
c153f45f 1659int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1660{
cdd55a29 1661 struct drm_device_dma *dma = dev->dma;
1da177e4 1662 int ret = 0;
c153f45f 1663 struct drm_dma *d = data;
1da177e4 1664
6c340eac 1665 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1666
1da177e4
LT		 1667 /* Please don't send us buffers.
1668 */
c153f45f 1669 if (d->send_count != 0) {
b5e89ed5 1670 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
c153f45f 1671 DRM_CURRENTPID, d->send_count);
20caafa6 1672 return -EINVAL;
1da177e4
LT		 1673 }
1674
1675 /* We'll send you buffers.
1676 */
c153f45f 1677 if (d->request_count < 0 || d->request_count > dma->buf_count) {
b5e89ed5 1678 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
c153f45f 1679 DRM_CURRENTPID, d->request_count, dma->buf_count);
20caafa6 1680 return -EINVAL;
1da177e4
LT		 1681 }
1682
c153f45f 1683 d->granted_count = 0;
1da177e4 1684
c153f45f
EA		 1685 if (d->request_count) {
1686 ret = radeon_cp_get_buffers(dev, file_priv, d);
1da177e4
LT		 1687 }
1688
1da177e4
LT		 1689 return ret;
1690}
1691
22eae947 1692int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1da177e4
LT		 1693{
1694 drm_radeon_private_t *dev_priv;
1695 int ret = 0;
1696
1697 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1698 if (dev_priv == NULL)
20caafa6 1699 return -ENOMEM;
1da177e4
LT		 1700
1701 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1702 dev->dev_private = (void *)dev_priv;
1703 dev_priv->flags = flags;
1704
54a56ac5 1705 switch (flags & RADEON_FAMILY_MASK) {
1da177e4
LT		 1706 case CHIP_R100:
1707 case CHIP_RV200:
1708 case CHIP_R200:
1709 case CHIP_R300:
b15ec368 1710 case CHIP_R350:
414ed537 1711 case CHIP_R420:
b15ec368 1712 case CHIP_RV410:
3d5e2c13
DA		 1713 case CHIP_RV515:
1714 case CHIP_R520:
1715 case CHIP_RV570:
1716 case CHIP_R580:
54a56ac5 1717 dev_priv->flags |= RADEON_HAS_HIERZ;
1da177e4
LT		 1718 break;
1719 default:
b5e89ed5 1720 /* all other chips have no hierarchical z buffer */
1da177e4
LT		 1721 break;
1722 }
414ed537
DA		 1723
1724 if (drm_device_is_agp(dev))
54a56ac5 1725 dev_priv->flags |= RADEON_IS_AGP;
b15ec368 1726 else if (drm_device_is_pcie(dev))
54a56ac5 1727 dev_priv->flags |= RADEON_IS_PCIE;
b15ec368 1728 else
54a56ac5 1729 dev_priv->flags |= RADEON_IS_PCI;
ea98a92f 1730
414ed537 1731 DRM_DEBUG("%s card detected\n",
54a56ac5 1732 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1da177e4
LT		 1733 return ret;
1734}
1735
22eae947
DA		 1736/* Create mappings for registers and framebuffer so userland doesn't necessarily
1737 * have to find them.
1738 */
1739int radeon_driver_firstopen(struct drm_device *dev)
836cf046
DA		 1740{
1741 int ret;
1742 drm_local_map_t *map;
1743 drm_radeon_private_t *dev_priv = dev->dev_private;
1744
f2b04cd2
DA		 1745 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1746
836cf046
DA		 1747 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1748 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1749 _DRM_READ_ONLY, &dev_priv->mmio);
1750 if (ret != 0)
1751 return ret;
1752
7fc86860
DA		 1753 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1754 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
836cf046
DA		 1755 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1756 _DRM_WRITE_COMBINING, &map);
1757 if (ret != 0)
1758 return ret;
1759
1760 return 0;
1761}
1762
22eae947 1763int radeon_driver_unload(struct drm_device *dev)
1da177e4
LT		 1764{
1765 drm_radeon_private_t *dev_priv = dev->dev_private;
1766
1767 DRM_DEBUG("\n");
1da177e4
LT		 1768 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1769
1770 dev->dev_private = NULL;
1771 return 0;
1772}
Linux 6.x block layer and io_uring tree(s)