[linux-2.6-block.git] / drivers / gpu / drm / radeon / dce6_afmt.c

/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/hdmi.h>
#include <drm/drmP.h>
#include "radeon.h"
#include "radeon_audio.h"
#include "sid.h"

#define DCE8_DCCG_AUDIO_DTO1_PHASE	0x05b8
#define DCE8_DCCG_AUDIO_DTO1_MODULE	0x05bc

u32 dce6_endpoint_rreg(struct radeon_device *rdev,
			      u32 block_offset, u32 reg)
{
	unsigned long flags;
	u32 r;

	spin_lock_irqsave(&rdev->end_idx_lock, flags);
	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);

	return r;
}

void dce6_endpoint_wreg(struct radeon_device *rdev,
			       u32 block_offset, u32 reg, u32 v)
{
	unsigned long flags;

	spin_lock_irqsave(&rdev->end_idx_lock, flags);
	if (ASIC_IS_DCE8(rdev))
		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	else
		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
		       AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
	WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
}

static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
{
	int i;
	u32 offset, tmp;

	for (i = 0; i < rdev->audio.num_pins; i++) {
		offset = rdev->audio.pin[i].offset;
		tmp = RREG32_ENDPOINT(offset,
				      AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
		if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
			rdev->audio.pin[i].connected = false;
		else
			rdev->audio.pin[i].connected = true;
	}
}

struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
{
	int i;

	dce6_afmt_get_connected_pins(rdev);

	for (i = 0; i < rdev->audio.num_pins; i++) {
		if (rdev->audio.pin[i].connected)
			return &rdev->audio.pin[i];
	}
	DRM_ERROR("No connected audio pins found!\n");
	return NULL;
}

void dce6_afmt_select_pin(struct drm_encoder *encoder)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 offset;

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->offset;

	WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
	       AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
}

void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
		struct drm_connector *connector, struct drm_display_mode *mode)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 tmp = 0, offset;

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		if (connector->latency_present[1])
			tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
				AUDIO_LIPSYNC(connector->audio_latency[1]);
		else
			tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
	} else {
		if (connector->latency_present[0])
			tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
				AUDIO_LIPSYNC(connector->audio_latency[0]);
		else
			tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
	}
	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
}

void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
	u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 offset, tmp;

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set HDMI mode */
	tmp |= HDMI_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
}

void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 offset, tmp;

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set DP mode */
	tmp |= DP_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
}

void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
	struct cea_sad *sads, int sad_count)
{
	u32 offset;
	int i;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	struct radeon_device *rdev = encoder->dev->dev_private;
	static const u16 eld_reg_to_type[][2] = {
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	};

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
		u32 value = 0;
		u8 stereo_freqs = 0;
		int max_channels = -1;
		int j;

		for (j = 0; j < sad_count; j++) {
			struct cea_sad *sad = &sads[j];

			if (sad->format == eld_reg_to_type[i][1]) {
				if (sad->channels > max_channels) {
					value = MAX_CHANNELS(sad->channels) |
						DESCRIPTOR_BYTE_2(sad->byte2) |
						SUPPORTED_FREQUENCIES(sad->freq);
					max_channels = sad->channels;
				}

				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
					stereo_freqs |= sad->freq;
				else
					break;
			}
		}

		value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);

		WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
	}
}

void dce6_audio_enable(struct radeon_device *rdev,
		       struct r600_audio_pin *pin,
		       u8 enable_mask)
{
	if (!pin)
		return;

	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
			enable_mask ? AUDIO_ENABLED : 0);
}

void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock)
{
	/* Two dtos; generally use dto0 for HDMI */
	u32 value = 0;

	if (crtc)
		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);

	WREG32(DCCG_AUDIO_DTO_SOURCE, value);

	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
}

void dce6_dp_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock)
{
	/* Two dtos; generally use dto1 for DP */
	u32 value = 0;
	value |= DCCG_AUDIO_DTO_SEL;

	if (crtc)
		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);

	WREG32(DCCG_AUDIO_DTO_SOURCE, value);

	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	if (ASIC_IS_DCE8(rdev)) {
		WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
		WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
	} else {
		WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
		WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
	}
}
Commit	Line	Data
b530602f AD	1	/*
	2	* Copyright 2013 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include <linux/hdmi.h>
	24	#include <drm/drmP.h>
	25	#include "radeon.h"
1a626b68	26	#include "radeon_audio.h"
b530602f AD	27	#include "sid.h"
b530602f AD	28
2afa3265 SG	29	#define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8
	30	#define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc
	31
1a626b68	32	u32 dce6_endpoint_rreg(struct radeon_device *rdev,
b530602f AD	33	u32 block_offset, u32 reg)
b530602f AD	34	{
0a5b7b0b	35	unsigned long flags;
b530602f AD	36	u32 r;
b530602f AD	37
0a5b7b0b	38	spin_lock_irqsave(&rdev->end_idx_lock, flags);
b530602f AD	39	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
b530602f AD	40	r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
0a5b7b0b AD	41	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
0a5b7b0b AD	42
b530602f AD	43	return r;
	44	}
	45
1a626b68	46	void dce6_endpoint_wreg(struct radeon_device *rdev,
b530602f AD	47	u32 block_offset, u32 reg, u32 v)
b530602f AD	48	{
0a5b7b0b AD	49	unsigned long flags;
	50
	51	spin_lock_irqsave(&rdev->end_idx_lock, flags);
b530602f AD	52	if (ASIC_IS_DCE8(rdev))
	53	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	54	else
	55	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
	56	AZ_ENDPOINT_REG_WRITE_EN \| AZ_ENDPOINT_REG_INDEX(reg));
	57	WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
0a5b7b0b	58	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
b530602f AD	59	}
b530602f AD	60
b530602f AD	61	static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
	62	{
	63	int i;
	64	u32 offset, tmp;
	65
	66	for (i = 0; i < rdev->audio.num_pins; i++) {
	67	offset = rdev->audio.pin[i].offset;
	68	tmp = RREG32_ENDPOINT(offset,
	69	AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
	70	if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
	71	rdev->audio.pin[i].connected = false;
	72	else
	73	rdev->audio.pin[i].connected = true;
	74	}
	75	}
	76
	77	struct r600_audio_pin dce6_audio_get_pin(struct radeon_device rdev)
	78	{
	79	int i;
	80
	81	dce6_afmt_get_connected_pins(rdev);
	82
	83	for (i = 0; i < rdev->audio.num_pins; i++) {
	84	if (rdev->audio.pin[i].connected)
	85	return &rdev->audio.pin[i];
	86	}
	87	DRM_ERROR("No connected audio pins found!\n");
	88	return NULL;
	89	}
	90
	91	void dce6_afmt_select_pin(struct drm_encoder *encoder)
	92	{
	93	struct radeon_device *rdev = encoder->dev->dev_private;
	94	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	95	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
53dc0b0c	96	u32 offset;
b530602f	97
53dc0b0c	98	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
b530602f AD	99	return;
b530602f AD	100
53dc0b0c AD	101	offset = dig->afmt->offset;
53dc0b0c AD	102
7cc0a3d8 AD	103	WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
7cc0a3d8 AD	104	AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
b530602f AD	105	}
b530602f AD	106
b1880258	107	void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
87654f87	108	struct drm_connector connector, struct drm_display_mode mode)
b1880258 AD	109	{
	110	struct radeon_device *rdev = encoder->dev->dev_private;
	111	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	112	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
b1880258 AD	113	u32 tmp = 0, offset;
b1880258 AD	114
53dc0b0c	115	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
b1880258 AD	116	return;
	117
	118	offset = dig->afmt->pin->offset;
	119
b1880258 AD	120	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
	121	if (connector->latency_present[1])
	122	tmp = VIDEO_LIPSYNC(connector->video_latency[1]) \|
	123	AUDIO_LIPSYNC(connector->audio_latency[1]);
	124	else
c748990b	125	tmp = VIDEO_LIPSYNC(0) \| AUDIO_LIPSYNC(0);
b1880258 AD	126	} else {
	127	if (connector->latency_present[0])
	128	tmp = VIDEO_LIPSYNC(connector->video_latency[0]) \|
	129	AUDIO_LIPSYNC(connector->audio_latency[0]);
	130	else
c748990b	131	tmp = VIDEO_LIPSYNC(0) \| AUDIO_LIPSYNC(0);
b1880258 AD	132	}
	133	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
	134	}
	135
00a9d4bc SG	136	void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
00a9d4bc SG	137	u8 *sadb, int sad_count)
b530602f AD	138	{
	139	struct radeon_device *rdev = encoder->dev->dev_private;
	140	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	141	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	142	u32 offset, tmp;
6159b65a	143
53dc0b0c	144	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
6159b65a RM	145	return;
	146
	147	offset = dig->afmt->pin->offset;
	148
6159b65a RM	149	/* program the speaker allocation */
	150	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	151	tmp &= ~(DP_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	152	/* set HDMI mode */
	153	tmp \|= HDMI_CONNECTION;
	154	if (sad_count)
	155	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	156	else
	157	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
	158	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
00a9d4bc	159	}
6159b65a	160
00a9d4bc SG	161	void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	162	u8 *sadb, int sad_count)
	163	{
	164	struct radeon_device *rdev = encoder->dev->dev_private;
	165	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	166	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	167	u32 offset, tmp;
	168
	169	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
	170	return;
	171
	172	offset = dig->afmt->pin->offset;
	173
	174	/* program the speaker allocation */
	175	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	176	tmp &= ~(HDMI_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	177	/* set DP mode */
	178	tmp \|= DP_CONNECTION;
	179	if (sad_count)
	180	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	181	else
	182	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
	183	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
6159b65a RM	184	}
6159b65a RM	185
070a2e63 AD	186	void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
070a2e63 AD	187	struct cea_sad *sads, int sad_count)
6159b65a	188	{
070a2e63 AD	189	u32 offset;
070a2e63 AD	190	int i;
6159b65a RM	191	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
6159b65a RM	192	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
070a2e63	193	struct radeon_device *rdev = encoder->dev->dev_private;
b530602f AD	194	static const u16 eld_reg_to_type[][2] = {
	195	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
	196	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
	197	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
	198	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
	199	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
	200	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
	201	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
	202	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
	203	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
	204	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
	205	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
	206	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	207	};
	208
53dc0b0c	209	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
b530602f AD	210	return;
	211
	212	offset = dig->afmt->pin->offset;
	213
b530602f AD	214	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
b530602f AD	215	u32 value = 0;
0f57bca9 AH	216	u8 stereo_freqs = 0;
0f57bca9 AH	217	int max_channels = -1;
b530602f AD	218	int j;
	219
	220	for (j = 0; j < sad_count; j++) {
	221	struct cea_sad *sad = &sads[j];
	222
	223	if (sad->format == eld_reg_to_type[i][1]) {
0f57bca9 AH	224	if (sad->channels > max_channels) {
	225	value = MAX_CHANNELS(sad->channels) \|
	226	DESCRIPTOR_BYTE_2(sad->byte2) \|
	227	SUPPORTED_FREQUENCIES(sad->freq);
	228	max_channels = sad->channels;
	229	}
	230
b530602f	231	if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
0f57bca9 AH	232	stereo_freqs \|= sad->freq;
	233	else
	234	break;
b530602f AD	235	}
b530602f AD	236	}
0f57bca9 AH	237
	238	value \|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
	239
b530602f AD	240	WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
b530602f AD	241	}
b530602f AD	242	}
b530602f AD	243
832eafaf AD	244	void dce6_audio_enable(struct radeon_device *rdev,
832eafaf AD	245	struct r600_audio_pin *pin,
d3d8c141	246	u8 enable_mask)
b530602f	247	{
832eafaf AD	248	if (!pin)
	249	return;
	250
f68fdbe4	251	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
d3d8c141	252	enable_mask ? AUDIO_ENABLED : 0);
b530602f	253	}
a85d682a SG	254
	255	void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
	256	struct radeon_crtc *crtc, unsigned int clock)
	257	{
b983a8f4	258	/* Two dtos; generally use dto0 for HDMI */
a85d682a SG	259	u32 value = 0;
a85d682a SG	260
b983a8f4	261	if (crtc)
a85d682a SG	262	value \|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
	263
	264	WREG32(DCCG_AUDIO_DTO_SOURCE, value);
	265
b983a8f4 SG	266	/* Express [24MHz / target pixel clock] as an exact rational
	267	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	268	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	269	*/
	270	WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
	271	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
a85d682a SG	272	}
	273
	274	void dce6_dp_audio_set_dto(struct radeon_device *rdev,
	275	struct radeon_crtc *crtc, unsigned int clock)
	276	{
b983a8f4	277	/* Two dtos; generally use dto1 for DP */
a85d682a SG	278	u32 value = 0;
	279	value \|= DCCG_AUDIO_DTO_SEL;
	280
b983a8f4	281	if (crtc)
a85d682a SG	282	value \|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
	283
	284	WREG32(DCCG_AUDIO_DTO_SOURCE, value);
	285
b983a8f4 SG	286	/* Express [24MHz / target pixel clock] as an exact rational
	287	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	288	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	289	*/
2afa3265 SG	290	if (ASIC_IS_DCE8(rdev)) {
	291	WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
	292	WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
	293	} else {
	294	WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
	295	WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
	296	}
a85d682a	297	}