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Merge branches 'acpi-resources', 'acpi-battery', 'acpi-doc' and 'acpi-pnp'
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_encoders.c
CommitLineData
3f03ced8
AD		 1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
3f03ced8 29#include "radeon.h"
6e72376d 30#include "radeon_audio.h"
3f03ced8 31#include "atom.h"
f3728734 32#include <linux/backlight.h>
3f03ced8
AD		 33
34extern int atom_debug;
35
f3728734
AD		 36static u8
37radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
38{
39 u8 backlight_level;
40 u32 bios_2_scratch;
41
42 if (rdev->family >= CHIP_R600)
43 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
44 else
45 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
46
47 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
48 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
49
50 return backlight_level;
51}
52
53static void
54radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
55 u8 backlight_level)
56{
57 u32 bios_2_scratch;
58
59 if (rdev->family >= CHIP_R600)
60 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
61 else
62 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
63
64 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
65 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
66 ATOM_S2_CURRENT_BL_LEVEL_MASK);
67
68 if (rdev->family >= CHIP_R600)
69 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
70 else
71 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
72}
73
6d92f81d
AD		 74u8
75atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
76{
77 struct drm_device *dev = radeon_encoder->base.dev;
78 struct radeon_device *rdev = dev->dev_private;
79
80 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
81 return 0;
82
83 return radeon_atom_get_backlight_level_from_reg(rdev);
84}
85
fda4b25c 86void
37e9b6a6 87atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
f3728734
AD		 88{
89 struct drm_encoder *encoder = &radeon_encoder->base;
90 struct drm_device *dev = radeon_encoder->base.dev;
91 struct radeon_device *rdev = dev->dev_private;
92 struct radeon_encoder_atom_dig *dig;
93 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
94 int index;
95
37e9b6a6
AD		 96 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
97 return;
98
99 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
100 radeon_encoder->enc_priv) {
f3728734 101 dig = radeon_encoder->enc_priv;
37e9b6a6 102 dig->backlight_level = level;
f3728734
AD		 103 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
104
105 switch (radeon_encoder->encoder_id) {
106 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
107 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
108 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
109 if (dig->backlight_level == 0) {
110 args.ucAction = ATOM_LCD_BLOFF;
111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
112 } else {
113 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
114 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
115 args.ucAction = ATOM_LCD_BLON;
116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
117 }
118 break;
119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
123 if (dig->backlight_level == 0)
124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
125 else {
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
128 }
129 break;
130 default:
131 break;
132 }
133 }
134}
135
bced76f2
AD		 136#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137
f3728734
AD		 138static u8 radeon_atom_bl_level(struct backlight_device *bd)
139{
140 u8 level;
141
142 /* Convert brightness to hardware level */
143 if (bd->props.brightness < 0)
144 level = 0;
145 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
146 level = RADEON_MAX_BL_LEVEL;
147 else
148 level = bd->props.brightness;
149
150 return level;
151}
152
153static int radeon_atom_backlight_update_status(struct backlight_device *bd)
154{
155 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
156 struct radeon_encoder *radeon_encoder = pdata->encoder;
157
37e9b6a6 158 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
f3728734
AD		 159
160 return 0;
161}
162
163static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
164{
165 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
166 struct radeon_encoder *radeon_encoder = pdata->encoder;
167 struct drm_device *dev = radeon_encoder->base.dev;
168 struct radeon_device *rdev = dev->dev_private;
169
170 return radeon_atom_get_backlight_level_from_reg(rdev);
171}
172
173static const struct backlight_ops radeon_atom_backlight_ops = {
174 .get_brightness = radeon_atom_backlight_get_brightness,
175 .update_status = radeon_atom_backlight_update_status,
176};
177
178void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
179 struct drm_connector *drm_connector)
180{
181 struct drm_device *dev = radeon_encoder->base.dev;
182 struct radeon_device *rdev = dev->dev_private;
183 struct backlight_device *bd;
184 struct backlight_properties props;
185 struct radeon_backlight_privdata *pdata;
186 struct radeon_encoder_atom_dig *dig;
614499b4 187 char bl_name[16];
f3728734 188
80101790
AD		 189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
191 */
192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 (rdev->pdev->device == 0x6741))
194 return;
195
f3728734
AD		 196 if (!radeon_encoder->enc_priv)
197 return;
198
199 if (!rdev->is_atom_bios)
200 return;
201
202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
203 return;
204
205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
206 if (!pdata) {
207 DRM_ERROR("Memory allocation failed\n");
208 goto error;
209 }
210
211 memset(&props, 0, sizeof(props));
212 props.max_brightness = RADEON_MAX_BL_LEVEL;
213 props.type = BACKLIGHT_RAW;
614499b4
AD		 214 snprintf(bl_name, sizeof(bl_name),
215 "radeon_bl%d", dev->primary->index);
5bdebb18 216 bd = backlight_device_register(bl_name, drm_connector->kdev,
f3728734
AD		 217 pdata, &radeon_atom_backlight_ops, &props);
218 if (IS_ERR(bd)) {
219 DRM_ERROR("Backlight registration failed\n");
220 goto error;
221 }
222
223 pdata->encoder = radeon_encoder;
224
f3728734
AD		 225 dig = radeon_encoder->enc_priv;
226 dig->bl_dev = bd;
227
228 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
201bb624
AD		 229 /* Set a reasonable default here if the level is 0 otherwise
230 * fbdev will attempt to turn the backlight on after console
231 * unblanking and it will try and restore 0 which turns the backlight
232 * off again.
233 */
234 if (bd->props.brightness == 0)
235 bd->props.brightness = RADEON_MAX_BL_LEVEL;
f3728734
AD		 236 bd->props.power = FB_BLANK_UNBLANK;
237 backlight_update_status(bd);
238
239 DRM_INFO("radeon atom DIG backlight initialized\n");
240
241 return;
242
243error:
244 kfree(pdata);
245 return;
246}
247
248static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
249{
250 struct drm_device *dev = radeon_encoder->base.dev;
251 struct radeon_device *rdev = dev->dev_private;
252 struct backlight_device *bd = NULL;
253 struct radeon_encoder_atom_dig *dig;
254
255 if (!radeon_encoder->enc_priv)
256 return;
257
258 if (!rdev->is_atom_bios)
259 return;
260
261 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
262 return;
263
264 dig = radeon_encoder->enc_priv;
265 bd = dig->bl_dev;
266 dig->bl_dev = NULL;
267
268 if (bd) {
269 struct radeon_legacy_backlight_privdata *pdata;
270
271 pdata = bl_get_data(bd);
272 backlight_device_unregister(bd);
273 kfree(pdata);
274
275 DRM_INFO("radeon atom LVDS backlight unloaded\n");
276 }
277}
278
279#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
280
281void radeon_atom_backlight_init(struct radeon_encoder *encoder)
282{
283}
284
285static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
286{
287}
288
289#endif
290
3f03ced8
AD		 291/* evil but including atombios.h is much worse */
292bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
293 struct drm_display_mode *mode);
294
3f03ced8 295static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
e811f5ae 296 const struct drm_display_mode *mode,
3f03ced8
AD		 297 struct drm_display_mode *adjusted_mode)
298{
299 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
300 struct drm_device *dev = encoder->dev;
301 struct radeon_device *rdev = dev->dev_private;
302
303 /* set the active encoder to connector routing */
304 radeon_encoder_set_active_device(encoder);
305 drm_mode_set_crtcinfo(adjusted_mode, 0);
306
307 /* hw bug */
308 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
309 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
310 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
311
da997620
AD		 312 /* get the native mode for scaling */
313 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
3f03ced8 314 radeon_panel_mode_fixup(encoder, adjusted_mode);
da997620 315 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
3f03ced8
AD		 316 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
317 if (tv_dac) {
318 if (tv_dac->tv_std == TV_STD_NTSC ||
319 tv_dac->tv_std == TV_STD_NTSC_J ||
320 tv_dac->tv_std == TV_STD_PAL_M)
321 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
322 else
323 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
324 }
da997620
AD		 325 } else if (radeon_encoder->rmx_type != RMX_OFF) {
326 radeon_panel_mode_fixup(encoder, adjusted_mode);
3f03ced8
AD		 327 }
328
329 if (ASIC_IS_DCE3(rdev) &&
330 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
331 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
332 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
93927f9c 333 radeon_dp_set_link_config(connector, adjusted_mode);
3f03ced8
AD		 334 }
335
336 return true;
337}
338
339static void
340atombios_dac_setup(struct drm_encoder *encoder, int action)
341{
342 struct drm_device *dev = encoder->dev;
343 struct radeon_device *rdev = dev->dev_private;
344 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
345 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
346 int index = 0;
347 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
348
349 memset(&args, 0, sizeof(args));
350
351 switch (radeon_encoder->encoder_id) {
352 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
353 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
354 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
355 break;
356 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
357 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
358 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
359 break;
360 }
361
362 args.ucAction = action;
363
364 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
365 args.ucDacStandard = ATOM_DAC1_PS2;
366 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
367 args.ucDacStandard = ATOM_DAC1_CV;
368 else {
369 switch (dac_info->tv_std) {
370 case TV_STD_PAL:
371 case TV_STD_PAL_M:
372 case TV_STD_SCART_PAL:
373 case TV_STD_SECAM:
374 case TV_STD_PAL_CN:
375 args.ucDacStandard = ATOM_DAC1_PAL;
376 break;
377 case TV_STD_NTSC:
378 case TV_STD_NTSC_J:
379 case TV_STD_PAL_60:
380 default:
381 args.ucDacStandard = ATOM_DAC1_NTSC;
382 break;
383 }
384 }
385 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
386
387 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
388
389}
390
391static void
392atombios_tv_setup(struct drm_encoder *encoder, int action)
393{
394 struct drm_device *dev = encoder->dev;
395 struct radeon_device *rdev = dev->dev_private;
396 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
397 TV_ENCODER_CONTROL_PS_ALLOCATION args;
398 int index = 0;
399 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
400
401 memset(&args, 0, sizeof(args));
402
403 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
404
405 args.sTVEncoder.ucAction = action;
406
407 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
408 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
409 else {
410 switch (dac_info->tv_std) {
411 case TV_STD_NTSC:
412 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
413 break;
414 case TV_STD_PAL:
415 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
416 break;
417 case TV_STD_PAL_M:
418 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
419 break;
420 case TV_STD_PAL_60:
421 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
422 break;
423 case TV_STD_NTSC_J:
424 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
425 break;
426 case TV_STD_SCART_PAL:
427 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
428 break;
429 case TV_STD_SECAM:
430 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
431 break;
432 case TV_STD_PAL_CN:
433 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
434 break;
435 default:
436 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
437 break;
438 }
439 }
440
441 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
442
443 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
444
445}
446
1f0e2943
AD		 447static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
448{
1f0e2943
AD		 449 int bpc = 8;
450
7d5a33b0
AD		 451 if (encoder->crtc) {
452 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
453 bpc = radeon_crtc->bpc;
454 }
1f0e2943
AD		 455
456 switch (bpc) {
457 case 0:
458 return PANEL_BPC_UNDEFINE;
459 case 6:
460 return PANEL_6BIT_PER_COLOR;
461 case 8:
462 default:
463 return PANEL_8BIT_PER_COLOR;
464 case 10:
465 return PANEL_10BIT_PER_COLOR;
466 case 12:
467 return PANEL_12BIT_PER_COLOR;
468 case 16:
469 return PANEL_16BIT_PER_COLOR;
470 }
471}
472
3f03ced8
AD		 473union dvo_encoder_control {
474 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
475 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
476 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
aea65641 477 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
3f03ced8
AD		 478};
479
480void
481atombios_dvo_setup(struct drm_encoder *encoder, int action)
482{
483 struct drm_device *dev = encoder->dev;
484 struct radeon_device *rdev = dev->dev_private;
485 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
486 union dvo_encoder_control args;
487 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
24153dd3 488 uint8_t frev, crev;
3f03ced8
AD		 489
490 memset(&args, 0, sizeof(args));
491
24153dd3
AD		 492 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
493 return;
494
afceb931
AD		 495 /* some R4xx chips have the wrong frev */
496 if (rdev->family <= CHIP_RV410)
497 frev = 1;
498
24153dd3
AD		 499 switch (frev) {
500 case 1:
501 switch (crev) {
502 case 1:
503 /* R4xx, R5xx */
504 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
505
9aa59993 506 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 507 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
508
509 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
510 break;
511 case 2:
512 /* RS600/690/740 */
513 args.dvo.sDVOEncoder.ucAction = action;
514 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
515 /* DFP1, CRT1, TV1 depending on the type of port */
516 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
517
9aa59993 518 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 519 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
520 break;
521 case 3:
522 /* R6xx */
523 args.dvo_v3.ucAction = action;
524 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
525 args.dvo_v3.ucDVOConfig = 0; /* XXX */
526 break;
aea65641
AD		 527 case 4:
528 /* DCE8 */
529 args.dvo_v4.ucAction = action;
530 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531 args.dvo_v4.ucDVOConfig = 0; /* XXX */
532 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
533 break;
24153dd3
AD		 534 default:
535 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
536 break;
537 }
538 break;
539 default:
540 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
541 break;
3f03ced8
AD		 542 }
543
544 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
545}
546
547union lvds_encoder_control {
548 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
549 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
550};
551
552void
553atombios_digital_setup(struct drm_encoder *encoder, int action)
554{
555 struct drm_device *dev = encoder->dev;
556 struct radeon_device *rdev = dev->dev_private;
557 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
558 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
559 union lvds_encoder_control args;
560 int index = 0;
561 int hdmi_detected = 0;
562 uint8_t frev, crev;
563
564 if (!dig)
565 return;
566
567 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
568 hdmi_detected = 1;
569
570 memset(&args, 0, sizeof(args));
571
572 switch (radeon_encoder->encoder_id) {
573 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
574 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
575 break;
576 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
578 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
579 break;
580 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
581 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
582 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
583 else
584 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
585 break;
586 }
587
588 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
589 return;
590
591 switch (frev) {
592 case 1:
593 case 2:
594 switch (crev) {
595 case 1:
596 args.v1.ucMisc = 0;
597 args.v1.ucAction = action;
598 if (hdmi_detected)
599 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
600 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
601 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
602 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
603 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
604 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
605 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
606 } else {
607 if (dig->linkb)
608 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 609 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 610 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
611 /*if (pScrn->rgbBits == 8) */
612 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
613 }
614 break;
615 case 2:
616 case 3:
617 args.v2.ucMisc = 0;
618 args.v2.ucAction = action;
619 if (crev == 3) {
620 if (dig->coherent_mode)
621 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
622 }
623 if (hdmi_detected)
624 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
625 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
626 args.v2.ucTruncate = 0;
627 args.v2.ucSpatial = 0;
628 args.v2.ucTemporal = 0;
629 args.v2.ucFRC = 0;
630 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
631 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
632 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
633 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
634 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
635 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
636 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
637 }
638 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
639 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
640 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
641 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
642 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
643 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
644 }
645 } else {
646 if (dig->linkb)
647 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 648 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 649 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
650 }
651 break;
652 default:
653 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
654 break;
655 }
656 break;
657 default:
658 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
659 break;
660 }
661
662 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
663}
664
665int
666atombios_get_encoder_mode(struct drm_encoder *encoder)
667{
e55bca26
SG		 668 struct drm_device *dev = encoder->dev;
669 struct radeon_device *rdev = dev->dev_private;
3f03ced8 670 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 671 struct drm_connector *connector;
672 struct radeon_connector *radeon_connector;
673 struct radeon_connector_atom_dig *dig_connector;
9843ead0 674 struct radeon_encoder_atom_dig *dig_enc;
3f03ced8 675
9843ead0
DA		 676 if (radeon_encoder_is_digital(encoder)) {
677 dig_enc = radeon_encoder->enc_priv;
678 if (dig_enc->active_mst_links)
679 return ATOM_ENCODER_MODE_DP_MST;
680 }
681 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
682 return ATOM_ENCODER_MODE_DP_MST;
3f03ced8
AD		 683 /* dp bridges are always DP */
684 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
685 return ATOM_ENCODER_MODE_DP;
686
687 /* DVO is always DVO */
a59fbb8e
AD		 688 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
689 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
3f03ced8
AD		 690 return ATOM_ENCODER_MODE_DVO;
691
692 connector = radeon_get_connector_for_encoder(encoder);
693 /* if we don't have an active device yet, just use one of
694 * the connectors tied to the encoder.
695 */
696 if (!connector)
697 connector = radeon_get_connector_for_encoder_init(encoder);
698 radeon_connector = to_radeon_connector(connector);
699
700 switch (connector->connector_type) {
701 case DRM_MODE_CONNECTOR_DVII:
702 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
108dc8e8
AD		 703 if (radeon_audio != 0) {
704 if (radeon_connector->use_digital &&
705 (radeon_connector->audio == RADEON_AUDIO_ENABLE))
706 return ATOM_ENCODER_MODE_HDMI;
377bd8a9 707 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
108dc8e8
AD		 708 (radeon_connector->audio == RADEON_AUDIO_AUTO))
709 return ATOM_ENCODER_MODE_HDMI;
710 else if (radeon_connector->use_digital)
711 return ATOM_ENCODER_MODE_DVI;
712 else
713 return ATOM_ENCODER_MODE_CRT;
714 } else if (radeon_connector->use_digital) {
3f03ced8 715 return ATOM_ENCODER_MODE_DVI;
108dc8e8 716 } else {
3f03ced8 717 return ATOM_ENCODER_MODE_CRT;
108dc8e8 718 }
3f03ced8
AD		 719 break;
720 case DRM_MODE_CONNECTOR_DVID:
721 case DRM_MODE_CONNECTOR_HDMIA:
722 default:
108dc8e8
AD		 723 if (radeon_audio != 0) {
724 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
725 return ATOM_ENCODER_MODE_HDMI;
377bd8a9 726 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
108dc8e8
AD		 727 (radeon_connector->audio == RADEON_AUDIO_AUTO))
728 return ATOM_ENCODER_MODE_HDMI;
729 else
730 return ATOM_ENCODER_MODE_DVI;
731 } else {
3f03ced8 732 return ATOM_ENCODER_MODE_DVI;
108dc8e8 733 }
3f03ced8
AD		 734 break;
735 case DRM_MODE_CONNECTOR_LVDS:
736 return ATOM_ENCODER_MODE_LVDS;
737 break;
738 case DRM_MODE_CONNECTOR_DisplayPort:
739 dig_connector = radeon_connector->con_priv;
740 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
108dc8e8 741 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
3473f542
AD		 742 if (radeon_audio != 0 &&
743 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
744 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
e55bca26 745 return ATOM_ENCODER_MODE_DP_AUDIO;
3f03ced8 746 return ATOM_ENCODER_MODE_DP;
108dc8e8
AD		 747 } else if (radeon_audio != 0) {
748 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
749 return ATOM_ENCODER_MODE_HDMI;
377bd8a9 750 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
108dc8e8
AD		 751 (radeon_connector->audio == RADEON_AUDIO_AUTO))
752 return ATOM_ENCODER_MODE_HDMI;
753 else
754 return ATOM_ENCODER_MODE_DVI;
755 } else {
3f03ced8 756 return ATOM_ENCODER_MODE_DVI;
108dc8e8 757 }
3f03ced8
AD		 758 break;
759 case DRM_MODE_CONNECTOR_eDP:
3473f542
AD		 760 if (radeon_audio != 0 &&
761 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
762 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
e55bca26 763 return ATOM_ENCODER_MODE_DP_AUDIO;
3f03ced8
AD		 764 return ATOM_ENCODER_MODE_DP;
765 case DRM_MODE_CONNECTOR_DVIA:
766 case DRM_MODE_CONNECTOR_VGA:
767 return ATOM_ENCODER_MODE_CRT;
768 break;
769 case DRM_MODE_CONNECTOR_Composite:
770 case DRM_MODE_CONNECTOR_SVIDEO:
771 case DRM_MODE_CONNECTOR_9PinDIN:
772 /* fix me */
773 return ATOM_ENCODER_MODE_TV;
774 /*return ATOM_ENCODER_MODE_CV;*/
775 break;
776 }
777}
778
779/*
780 * DIG Encoder/Transmitter Setup
781 *
782 * DCE 3.0/3.1
783 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
784 * Supports up to 3 digital outputs
785 * - 2 DIG encoder blocks.
786 * DIG1 can drive UNIPHY link A or link B
787 * DIG2 can drive UNIPHY link B or LVTMA
788 *
789 * DCE 3.2
790 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
791 * Supports up to 5 digital outputs
792 * - 2 DIG encoder blocks.
793 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
794 *
2d415869 795 * DCE 4.0/5.0/6.0
3f03ced8
AD		 796 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
797 * Supports up to 6 digital outputs
798 * - 6 DIG encoder blocks.
799 * - DIG to PHY mapping is hardcoded
800 * DIG1 drives UNIPHY0 link A, A+B
801 * DIG2 drives UNIPHY0 link B
802 * DIG3 drives UNIPHY1 link A, A+B
803 * DIG4 drives UNIPHY1 link B
804 * DIG5 drives UNIPHY2 link A, A+B
805 * DIG6 drives UNIPHY2 link B
806 *
807 * DCE 4.1
808 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
809 * Supports up to 6 digital outputs
810 * - 2 DIG encoder blocks.
2d415869 811 * llano
3f03ced8 812 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
2d415869
AD		 813 * ontario
814 * DIG1 drives UNIPHY0/1/2 link A
815 * DIG2 drives UNIPHY0/1/2 link B
3f03ced8
AD		 816 *
817 * Routing
818 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
819 * Examples:
820 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
821 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
822 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
823 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
824 */
825
826union dig_encoder_control {
827 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
828 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
829 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
830 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
831};
832
833void
bf071900 834atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
3f03ced8
AD		 835{
836 struct drm_device *dev = encoder->dev;
837 struct radeon_device *rdev = dev->dev_private;
838 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
839 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
840 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
841 union dig_encoder_control args;
842 int index = 0;
843 uint8_t frev, crev;
844 int dp_clock = 0;
845 int dp_lane_count = 0;
846 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 847
848 if (connector) {
849 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
850 struct radeon_connector_atom_dig *dig_connector =
851 radeon_connector->con_priv;
852
853 dp_clock = dig_connector->dp_clock;
854 dp_lane_count = dig_connector->dp_lane_count;
855 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 856 }
857
858 /* no dig encoder assigned */
859 if (dig->dig_encoder == -1)
860 return;
861
862 memset(&args, 0, sizeof(args));
863
864 if (ASIC_IS_DCE4(rdev))
865 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
866 else {
867 if (dig->dig_encoder)
868 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
869 else
870 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
871 }
872
873 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
874 return;
875
58cdcb8b
AD		 876 switch (frev) {
877 case 1:
878 switch (crev) {
879 case 1:
880 args.v1.ucAction = action;
881 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
882 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
883 args.v3.ucPanelMode = panel_mode;
884 else
885 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
886
887 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
888 args.v1.ucLaneNum = dp_lane_count;
9aa59993 889 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 890 args.v1.ucLaneNum = 8;
891 else
892 args.v1.ucLaneNum = 4;
893
894 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
895 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
896 switch (radeon_encoder->encoder_id) {
897 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
898 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
899 break;
900 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
901 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
902 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
903 break;
904 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
905 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
906 break;
907 }
908 if (dig->linkb)
909 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
910 else
911 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
3f03ced8 912 break;
58cdcb8b
AD		 913 case 2:
914 case 3:
915 args.v3.ucAction = action;
916 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
917 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
918 args.v3.ucPanelMode = panel_mode;
919 else
920 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
921
2f6fa79a 922 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
58cdcb8b 923 args.v3.ucLaneNum = dp_lane_count;
9aa59993 924 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 925 args.v3.ucLaneNum = 8;
926 else
927 args.v3.ucLaneNum = 4;
928
2f6fa79a 929 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
58cdcb8b 930 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
bf071900
DA		 931 if (enc_override != -1)
932 args.v3.acConfig.ucDigSel = enc_override;
933 else
934 args.v3.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 935 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8 936 break;
58cdcb8b
AD		 937 case 4:
938 args.v4.ucAction = action;
939 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
940 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
941 args.v4.ucPanelMode = panel_mode;
942 else
943 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
944
2f6fa79a 945 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
58cdcb8b 946 args.v4.ucLaneNum = dp_lane_count;
9aa59993 947 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 948 args.v4.ucLaneNum = 8;
949 else
950 args.v4.ucLaneNum = 4;
951
2f6fa79a 952 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
e68adef8 953 if (dp_clock == 540000)
58cdcb8b 954 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
e68adef8
AD		 955 else if (dp_clock == 324000)
956 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
957 else if (dp_clock == 270000)
958 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
959 else
960 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
58cdcb8b 961 }
bf071900
DA		 962
963 if (enc_override != -1)
964 args.v4.acConfig.ucDigSel = enc_override;
965 else
966 args.v4.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 967 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
58cdcb8b
AD		 968 if (hpd_id == RADEON_HPD_NONE)
969 args.v4.ucHPD_ID = 0;
970 else
971 args.v4.ucHPD_ID = hpd_id + 1;
3f03ced8 972 break;
3f03ced8 973 default:
58cdcb8b 974 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3f03ced8
AD		 975 break;
976 }
58cdcb8b
AD		 977 break;
978 default:
979 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
980 break;
3f03ced8
AD		 981 }
982
983 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
984
985}
986
bf071900
DA		 987void
988atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
989{
990 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
991}
992
3f03ced8
AD		 993union dig_transmitter_control {
994 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
995 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
996 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
997 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
47aef7a8 998 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
3f03ced8
AD		 999};
1000
1001void
bf071900 1002atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
3f03ced8
AD		 1003{
1004 struct drm_device *dev = encoder->dev;
1005 struct radeon_device *rdev = dev->dev_private;
1006 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1007 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1008 struct drm_connector *connector;
1009 union dig_transmitter_control args;
1010 int index = 0;
1011 uint8_t frev, crev;
1012 bool is_dp = false;
1013 int pll_id = 0;
1014 int dp_clock = 0;
1015 int dp_lane_count = 0;
1016 int connector_object_id = 0;
1017 int igp_lane_info = 0;
1018 int dig_encoder = dig->dig_encoder;
47aef7a8 1019 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 1020
1021 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1022 connector = radeon_get_connector_for_encoder_init(encoder);
1023 /* just needed to avoid bailing in the encoder check. the encoder
1024 * isn't used for init
1025 */
1026 dig_encoder = 0;
1027 } else
1028 connector = radeon_get_connector_for_encoder(encoder);
1029
1030 if (connector) {
1031 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1032 struct radeon_connector_atom_dig *dig_connector =
1033 radeon_connector->con_priv;
1034
47aef7a8 1035 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 1036 dp_clock = dig_connector->dp_clock;
1037 dp_lane_count = dig_connector->dp_lane_count;
1038 connector_object_id =
1039 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1040 igp_lane_info = dig_connector->igp_lane_info;
1041 }
1042
a3b08294
AD		 1043 if (encoder->crtc) {
1044 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1045 pll_id = radeon_crtc->pll_id;
1046 }
1047
3f03ced8
AD		 1048 /* no dig encoder assigned */
1049 if (dig_encoder == -1)
1050 return;
1051
1052 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1053 is_dp = true;
1054
1055 memset(&args, 0, sizeof(args));
1056
1057 switch (radeon_encoder->encoder_id) {
1058 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1059 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1060 break;
1061 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1062 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1063 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1064 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1065 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1066 break;
1067 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1068 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1069 break;
1070 }
1071
1072 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1073 return;
1074
a3b08294
AD		 1075 switch (frev) {
1076 case 1:
1077 switch (crev) {
1078 case 1:
1079 args.v1.ucAction = action;
1080 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1081 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1082 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1083 args.v1.asMode.ucLaneSel = lane_num;
1084 args.v1.asMode.ucLaneSet = lane_set;
1085 } else {
1086 if (is_dp)
6e76a2df 1087 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1088 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1089 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1090 else
1091 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1092 }
3f03ced8 1093
a3b08294 1094 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
3f03ced8 1095
a3b08294
AD		 1096 if (dig_encoder)
1097 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1098 else
1099 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1100
1101 if ((rdev->flags & RADEON_IS_IGP) &&
1102 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
9aa59993
AD		 1103 if (is_dp ||
1104 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
a3b08294
AD		 1105 if (igp_lane_info & 0x1)
1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1107 else if (igp_lane_info & 0x2)
1108 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1109 else if (igp_lane_info & 0x4)
1110 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1111 else if (igp_lane_info & 0x8)
1112 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1113 } else {
1114 if (igp_lane_info & 0x3)
1115 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1116 else if (igp_lane_info & 0xc)
1117 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1118 }
1119 }
1120
1121 if (dig->linkb)
1122 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1123 else
1124 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1125
1126 if (is_dp)
1127 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1128 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1129 if (dig->coherent_mode)
1130 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
9aa59993 1131 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1132 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1133 }
1134 break;
1135 case 2:
1136 args.v2.ucAction = action;
1137 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1138 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1139 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1140 args.v2.asMode.ucLaneSel = lane_num;
1141 args.v2.asMode.ucLaneSet = lane_set;
1142 } else {
1143 if (is_dp)
6e76a2df 1144 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1145 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1146 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1147 else
1148 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1149 }
1150
1151 args.v2.acConfig.ucEncoderSel = dig_encoder;
1152 if (dig->linkb)
1153 args.v2.acConfig.ucLinkSel = 1;
1154
1155 switch (radeon_encoder->encoder_id) {
1156 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1157 args.v2.acConfig.ucTransmitterSel = 0;
1158 break;
1159 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1160 args.v2.acConfig.ucTransmitterSel = 1;
1161 break;
1162 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1163 args.v2.acConfig.ucTransmitterSel = 2;
1164 break;
1165 }
3f03ced8 1166
3f03ced8 1167 if (is_dp) {
a3b08294
AD		 1168 args.v2.acConfig.fCoherentMode = 1;
1169 args.v2.acConfig.fDPConnector = 1;
1170 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1171 if (dig->coherent_mode)
1172 args.v2.acConfig.fCoherentMode = 1;
9aa59993 1173 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1174 args.v2.acConfig.fDualLinkConnector = 1;
1175 }
1176 break;
1177 case 3:
1178 args.v3.ucAction = action;
1179 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1180 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1181 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1182 args.v3.asMode.ucLaneSel = lane_num;
1183 args.v3.asMode.ucLaneSet = lane_set;
1184 } else {
1185 if (is_dp)
6e76a2df 1186 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1187 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294 1188 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
3f03ced8 1189 else
a3b08294
AD		 1190 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1191 }
1192
1193 if (is_dp)
1194 args.v3.ucLaneNum = dp_lane_count;
9aa59993 1195 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1196 args.v3.ucLaneNum = 8;
1197 else
1198 args.v3.ucLaneNum = 4;
1199
1200 if (dig->linkb)
1201 args.v3.acConfig.ucLinkSel = 1;
1202 if (dig_encoder & 1)
1203 args.v3.acConfig.ucEncoderSel = 1;
1204
1205 /* Select the PLL for the PHY
1206 * DP PHY should be clocked from external src if there is
1207 * one.
1208 */
3f03ced8
AD		 1209 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1210 if (is_dp && rdev->clock.dp_extclk)
1211 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1212 else
1213 args.v3.acConfig.ucRefClkSource = pll_id;
3f03ced8 1214
a3b08294
AD		 1215 switch (radeon_encoder->encoder_id) {
1216 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1217 args.v3.acConfig.ucTransmitterSel = 0;
1218 break;
1219 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1220 args.v3.acConfig.ucTransmitterSel = 1;
1221 break;
1222 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1223 args.v3.acConfig.ucTransmitterSel = 2;
1224 break;
1225 }
3f03ced8 1226
a3b08294
AD		 1227 if (is_dp)
1228 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1229 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1230 if (dig->coherent_mode)
1231 args.v3.acConfig.fCoherentMode = 1;
9aa59993 1232 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1233 args.v3.acConfig.fDualLinkConnector = 1;
1234 }
3f03ced8 1235 break;
a3b08294
AD		 1236 case 4:
1237 args.v4.ucAction = action;
1238 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1239 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1240 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1241 args.v4.asMode.ucLaneSel = lane_num;
1242 args.v4.asMode.ucLaneSet = lane_set;
3f03ced8 1243 } else {
a3b08294 1244 if (is_dp)
6e76a2df 1245 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1246 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1247 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1248 else
1249 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
3f03ced8 1250 }
3f03ced8 1251
a3b08294
AD		 1252 if (is_dp)
1253 args.v4.ucLaneNum = dp_lane_count;
9aa59993 1254 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1255 args.v4.ucLaneNum = 8;
1256 else
1257 args.v4.ucLaneNum = 4;
3f03ced8 1258
a3b08294
AD		 1259 if (dig->linkb)
1260 args.v4.acConfig.ucLinkSel = 1;
1261 if (dig_encoder & 1)
1262 args.v4.acConfig.ucEncoderSel = 1;
1263
1264 /* Select the PLL for the PHY
1265 * DP PHY should be clocked from external src if there is
1266 * one.
1267 */
1268 /* On DCE5 DCPLL usually generates the DP ref clock */
1269 if (is_dp) {
1270 if (rdev->clock.dp_extclk)
1271 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1272 else
1273 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1274 } else
1275 args.v4.acConfig.ucRefClkSource = pll_id;
1276
1277 switch (radeon_encoder->encoder_id) {
1278 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1279 args.v4.acConfig.ucTransmitterSel = 0;
1280 break;
1281 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1282 args.v4.acConfig.ucTransmitterSel = 1;
1283 break;
1284 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1285 args.v4.acConfig.ucTransmitterSel = 2;
1286 break;
1287 }
1288
1289 if (is_dp)
1290 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1291 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1292 if (dig->coherent_mode)
1293 args.v4.acConfig.fCoherentMode = 1;
9aa59993 1294 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1295 args.v4.acConfig.fDualLinkConnector = 1;
1296 }
1297 break;
47aef7a8
AD		 1298 case 5:
1299 args.v5.ucAction = action;
1300 if (is_dp)
1301 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1302 else
1303 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1304
1305 switch (radeon_encoder->encoder_id) {
1306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1307 if (dig->linkb)
1308 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1309 else
1310 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1311 break;
1312 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1313 if (dig->linkb)
1314 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1315 else
1316 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1317 break;
1318 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1319 if (dig->linkb)
1320 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1321 else
1322 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1323 break;
e68adef8
AD		 1324 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1325 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1326 break;
47aef7a8
AD		 1327 }
1328 if (is_dp)
1329 args.v5.ucLaneNum = dp_lane_count;
d03874c8 1330 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
47aef7a8
AD		 1331 args.v5.ucLaneNum = 8;
1332 else
1333 args.v5.ucLaneNum = 4;
1334 args.v5.ucConnObjId = connector_object_id;
1335 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1336
1337 if (is_dp && rdev->clock.dp_extclk)
1338 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1339 else
1340 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1341
1342 if (is_dp)
1343 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1344 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1345 if (dig->coherent_mode)
1346 args.v5.asConfig.ucCoherentMode = 1;
1347 }
1348 if (hpd_id == RADEON_HPD_NONE)
1349 args.v5.asConfig.ucHPDSel = 0;
1350 else
1351 args.v5.asConfig.ucHPDSel = hpd_id + 1;
bf071900 1352 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
47aef7a8
AD		 1353 args.v5.ucDPLaneSet = lane_set;
1354 break;
a3b08294
AD		 1355 default:
1356 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1357 break;
3f03ced8 1358 }
a3b08294
AD		 1359 break;
1360 default:
1361 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1362 break;
3f03ced8
AD		 1363 }
1364
1365 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1366}
1367
bf071900
DA		 1368void
1369atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1370{
1371 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1372}
1373
3f03ced8
AD		 1374bool
1375atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1376{
1377 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1378 struct drm_device *dev = radeon_connector->base.dev;
1379 struct radeon_device *rdev = dev->dev_private;
1380 union dig_transmitter_control args;
1381 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1382 uint8_t frev, crev;
1383
1384 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1385 goto done;
1386
1387 if (!ASIC_IS_DCE4(rdev))
1388 goto done;
1389
1390 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1391 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1392 goto done;
1393
1394 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1395 goto done;
1396
1397 memset(&args, 0, sizeof(args));
1398
1399 args.v1.ucAction = action;
1400
1401 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1402
1403 /* wait for the panel to power up */
1404 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1405 int i;
1406
1407 for (i = 0; i < 300; i++) {
1408 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1409 return true;
1410 mdelay(1);
1411 }
1412 return false;
1413 }
1414done:
1415 return true;
1416}
1417
1418union external_encoder_control {
1419 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1420 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1421};
1422
1423static void
1424atombios_external_encoder_setup(struct drm_encoder *encoder,
1425 struct drm_encoder *ext_encoder,
1426 int action)
1427{
1428 struct drm_device *dev = encoder->dev;
1429 struct radeon_device *rdev = dev->dev_private;
1430 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1431 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1432 union external_encoder_control args;
1433 struct drm_connector *connector;
1434 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1435 u8 frev, crev;
1436 int dp_clock = 0;
1437 int dp_lane_count = 0;
1438 int connector_object_id = 0;
1439 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
3f03ced8
AD		 1440
1441 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1442 connector = radeon_get_connector_for_encoder_init(encoder);
1443 else
1444 connector = radeon_get_connector_for_encoder(encoder);
1445
1446 if (connector) {
1447 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1448 struct radeon_connector_atom_dig *dig_connector =
1449 radeon_connector->con_priv;
1450
1451 dp_clock = dig_connector->dp_clock;
1452 dp_lane_count = dig_connector->dp_lane_count;
1453 connector_object_id =
1454 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3f03ced8
AD		 1455 }
1456
1457 memset(&args, 0, sizeof(args));
1458
1459 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1460 return;
1461
1462 switch (frev) {
1463 case 1:
1464 /* no params on frev 1 */
1465 break;
1466 case 2:
1467 switch (crev) {
1468 case 1:
1469 case 2:
1470 args.v1.sDigEncoder.ucAction = action;
1471 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1472 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1473
1474 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1475 if (dp_clock == 270000)
1476 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1477 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
9aa59993 1478 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1479 args.v1.sDigEncoder.ucLaneNum = 8;
1480 else
1481 args.v1.sDigEncoder.ucLaneNum = 4;
1482 break;
1483 case 3:
1484 args.v3.sExtEncoder.ucAction = action;
1485 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1486 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1487 else
1488 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1489 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1490
1491 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1492 if (dp_clock == 270000)
1493 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1494 else if (dp_clock == 540000)
1495 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1496 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
9aa59993 1497 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1498 args.v3.sExtEncoder.ucLaneNum = 8;
1499 else
1500 args.v3.sExtEncoder.ucLaneNum = 4;
1501 switch (ext_enum) {
1502 case GRAPH_OBJECT_ENUM_ID1:
1503 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1504 break;
1505 case GRAPH_OBJECT_ENUM_ID2:
1506 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1507 break;
1508 case GRAPH_OBJECT_ENUM_ID3:
1509 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1510 break;
1511 }
1f0e2943 1512 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8
AD		 1513 break;
1514 default:
1515 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1516 return;
1517 }
1518 break;
1519 default:
1520 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1521 return;
1522 }
1523 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1524}
1525
1526static void
1527atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1528{
1529 struct drm_device *dev = encoder->dev;
1530 struct radeon_device *rdev = dev->dev_private;
1531 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1532 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1533 ENABLE_YUV_PS_ALLOCATION args;
1534 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1535 uint32_t temp, reg;
1536
1537 memset(&args, 0, sizeof(args));
1538
1539 if (rdev->family >= CHIP_R600)
1540 reg = R600_BIOS_3_SCRATCH;
1541 else
1542 reg = RADEON_BIOS_3_SCRATCH;
1543
1544 /* XXX: fix up scratch reg handling */
1545 temp = RREG32(reg);
1546 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1547 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1548 (radeon_crtc->crtc_id << 18)));
1549 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1550 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1551 else
1552 WREG32(reg, 0);
1553
1554 if (enable)
1555 args.ucEnable = ATOM_ENABLE;
1556 args.ucCRTC = radeon_crtc->crtc_id;
1557
1558 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1559
1560 WREG32(reg, temp);
1561}
1562
1563static void
1564radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1565{
1566 struct drm_device *dev = encoder->dev;
1567 struct radeon_device *rdev = dev->dev_private;
1568 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1569 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1570 int index = 0;
1571
1572 memset(&args, 0, sizeof(args));
1573
1574 switch (radeon_encoder->encoder_id) {
1575 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1576 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1577 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1578 break;
1579 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1580 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1581 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1582 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1583 break;
1584 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1585 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1586 break;
1587 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1588 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1589 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1590 else
1591 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1592 break;
1593 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1594 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1595 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1596 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1597 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1598 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1599 else
1600 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1601 break;
1602 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1603 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1604 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1605 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1606 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1607 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1608 else
1609 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1610 break;
1611 default:
1612 return;
1613 }
1614
1615 switch (mode) {
1616 case DRM_MODE_DPMS_ON:
1617 args.ucAction = ATOM_ENABLE;
1618 /* workaround for DVOOutputControl on some RS690 systems */
1619 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1620 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1621 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1622 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1623 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1624 } else
1625 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1626 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1627 args.ucAction = ATOM_LCD_BLON;
1628 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1629 }
1630 break;
1631 case DRM_MODE_DPMS_STANDBY:
1632 case DRM_MODE_DPMS_SUSPEND:
1633 case DRM_MODE_DPMS_OFF:
1634 args.ucAction = ATOM_DISABLE;
1635 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1636 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1637 args.ucAction = ATOM_LCD_BLOFF;
1638 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1639 }
1640 break;
1641 }
1642}
1643
1644static void
1645radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1646{
1647 struct drm_device *dev = encoder->dev;
1648 struct radeon_device *rdev = dev->dev_private;
1649 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8d1af57a
AD		 1650 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1651 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1652 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1653 struct radeon_connector *radeon_connector = NULL;
1654 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
6f50e075 1655 bool travis_quirk = false;
3f03ced8
AD		 1656
1657 if (connector) {
1658 radeon_connector = to_radeon_connector(connector);
1659 radeon_dig_connector = radeon_connector->con_priv;
6f50e075
AD		 1660 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1661 ENCODER_OBJECT_ID_TRAVIS) &&
1662 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1663 !ASIC_IS_DCE5(rdev))
1664 travis_quirk = true;
3f03ced8
AD		 1665 }
1666
1667 switch (mode) {
1668 case DRM_MODE_DPMS_ON:
8d1af57a
AD		 1669 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1670 if (!connector)
1671 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1672 else
1673 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1674
1675 /* setup and enable the encoder */
1676 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1677 atombios_dig_encoder_setup(encoder,
1678 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1679 dig->panel_mode);
1680 if (ext_encoder) {
1681 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1682 atombios_external_encoder_setup(encoder, ext_encoder,
1683 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
fcedac67 1684 }
8d1af57a
AD		 1685 } else if (ASIC_IS_DCE4(rdev)) {
1686 /* setup and enable the encoder */
1687 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
8d1af57a
AD		 1688 } else {
1689 /* setup and enable the encoder and transmitter */
1690 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1691 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
fcedac67 1692 }
3f03ced8
AD		 1693 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1694 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1695 atombios_set_edp_panel_power(connector,
1696 ATOM_TRANSMITTER_ACTION_POWER_ON);
1697 radeon_dig_connector->edp_on = true;
1698 }
6f50e075
AD		 1699 }
1700 /* enable the transmitter */
1701 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1702 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1703 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
3f03ced8
AD		 1704 radeon_dp_link_train(encoder, connector);
1705 if (ASIC_IS_DCE4(rdev))
1706 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1707 }
1708 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
6f50e075
AD		 1709 atombios_dig_transmitter_setup(encoder,
1710 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1711 if (ext_encoder)
1712 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
3f03ced8
AD		 1713 break;
1714 case DRM_MODE_DPMS_STANDBY:
1715 case DRM_MODE_DPMS_SUSPEND:
1716 case DRM_MODE_DPMS_OFF:
9843ead0
DA		 1717
1718 /* don't power off encoders with active MST links */
1719 if (dig->active_mst_links)
1720 return;
1721
6f50e075
AD		 1722 if (ASIC_IS_DCE4(rdev)) {
1723 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1724 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1725 }
1726 if (ext_encoder)
1727 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1728 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1729 atombios_dig_transmitter_setup(encoder,
1730 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1731
1732 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1733 connector && !travis_quirk)
1734 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
40390961 1735 if (ASIC_IS_DCE4(rdev)) {
8d1af57a 1736 /* disable the transmitter */
6f50e075
AD		 1737 atombios_dig_transmitter_setup(encoder,
1738 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1739 } else {
1740 /* disable the encoder and transmitter */
6f50e075
AD		 1741 atombios_dig_transmitter_setup(encoder,
1742 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1743 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1744 }
3f03ced8 1745 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
6f50e075
AD		 1746 if (travis_quirk)
1747 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
3f03ced8
AD		 1748 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1749 atombios_set_edp_panel_power(connector,
1750 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1751 radeon_dig_connector->edp_on = false;
1752 }
1753 }
3f03ced8
AD		 1754 break;
1755 }
1756}
1757
1758static void
1759radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1760{
1761 struct drm_device *dev = encoder->dev;
1762 struct radeon_device *rdev = dev->dev_private;
1763 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
5c046a57 1764 int encoder_mode = atombios_get_encoder_mode(encoder);
3f03ced8
AD		 1765
1766 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1767 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1768 radeon_encoder->active_device);
5c046a57 1769
38aef154 1770 if ((radeon_audio != 0) &&
5c046a57 1771 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
38aef154 1772 ENCODER_MODE_IS_DP(encoder_mode)))
5c046a57
AD		 1773 radeon_audio_dpms(encoder, mode);
1774
3f03ced8
AD		 1775 switch (radeon_encoder->encoder_id) {
1776 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1777 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1778 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1779 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1780 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1781 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1782 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1783 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1784 radeon_atom_encoder_dpms_avivo(encoder, mode);
1785 break;
1786 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1787 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1788 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1789 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1790 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1791 radeon_atom_encoder_dpms_dig(encoder, mode);
1792 break;
1793 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1794 if (ASIC_IS_DCE5(rdev)) {
1795 switch (mode) {
1796 case DRM_MODE_DPMS_ON:
1797 atombios_dvo_setup(encoder, ATOM_ENABLE);
1798 break;
1799 case DRM_MODE_DPMS_STANDBY:
1800 case DRM_MODE_DPMS_SUSPEND:
1801 case DRM_MODE_DPMS_OFF:
1802 atombios_dvo_setup(encoder, ATOM_DISABLE);
1803 break;
1804 }
1805 } else if (ASIC_IS_DCE3(rdev))
1806 radeon_atom_encoder_dpms_dig(encoder, mode);
1807 else
1808 radeon_atom_encoder_dpms_avivo(encoder, mode);
1809 break;
1810 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1811 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1812 if (ASIC_IS_DCE5(rdev)) {
1813 switch (mode) {
1814 case DRM_MODE_DPMS_ON:
1815 atombios_dac_setup(encoder, ATOM_ENABLE);
1816 break;
1817 case DRM_MODE_DPMS_STANDBY:
1818 case DRM_MODE_DPMS_SUSPEND:
1819 case DRM_MODE_DPMS_OFF:
1820 atombios_dac_setup(encoder, ATOM_DISABLE);
1821 break;
1822 }
1823 } else
1824 radeon_atom_encoder_dpms_avivo(encoder, mode);
1825 break;
1826 default:
1827 return;
1828 }
1829
3f03ced8
AD		 1830 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1831
1832}
1833
1834union crtc_source_param {
1835 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1836 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1837};
1838
1839static void
1840atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1841{
1842 struct drm_device *dev = encoder->dev;
1843 struct radeon_device *rdev = dev->dev_private;
1844 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1845 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1846 union crtc_source_param args;
1847 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1848 uint8_t frev, crev;
1849 struct radeon_encoder_atom_dig *dig;
1850
1851 memset(&args, 0, sizeof(args));
1852
1853 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1854 return;
1855
1856 switch (frev) {
1857 case 1:
1858 switch (crev) {
1859 case 1:
1860 default:
1861 if (ASIC_IS_AVIVO(rdev))
1862 args.v1.ucCRTC = radeon_crtc->crtc_id;
1863 else {
1864 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1865 args.v1.ucCRTC = radeon_crtc->crtc_id;
1866 } else {
1867 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1868 }
1869 }
1870 switch (radeon_encoder->encoder_id) {
1871 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1872 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1873 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1874 break;
1875 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1876 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1877 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1878 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1879 else
1880 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1881 break;
1882 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1883 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1884 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1885 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1886 break;
1887 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1888 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1889 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1890 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1891 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1892 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1893 else
1894 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1895 break;
1896 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1897 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1898 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1899 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1900 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1901 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1902 else
1903 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1904 break;
1905 }
1906 break;
1907 case 2:
1908 args.v2.ucCRTC = radeon_crtc->crtc_id;
1909 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1910 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1911
1912 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1913 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1914 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1915 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1916 else
1917 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
64252835
AD		 1918 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1919 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1920 } else {
3f03ced8 1921 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
64252835 1922 }
3f03ced8
AD		 1923 switch (radeon_encoder->encoder_id) {
1924 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1925 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1926 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1927 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1928 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1929 dig = radeon_encoder->enc_priv;
1930 switch (dig->dig_encoder) {
1931 case 0:
1932 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1933 break;
1934 case 1:
1935 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1936 break;
1937 case 2:
1938 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1939 break;
1940 case 3:
1941 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1942 break;
1943 case 4:
1944 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1945 break;
1946 case 5:
1947 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1948 break;
e68adef8
AD		 1949 case 6:
1950 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1951 break;
3f03ced8
AD		 1952 }
1953 break;
1954 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1955 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1956 break;
1957 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1958 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1959 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1960 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1961 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1962 else
1963 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1964 break;
1965 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1966 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1967 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1968 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1969 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1970 else
1971 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1972 break;
1973 }
1974 break;
1975 }
1976 break;
1977 default:
1978 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1979 return;
1980 }
1981
1982 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1983
1984 /* update scratch regs with new routing */
1985 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1986}
1987
9843ead0
DA		 1988void
1989atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
1990{
1991 struct drm_device *dev = encoder->dev;
1992 struct radeon_device *rdev = dev->dev_private;
1993 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1994 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1995 uint8_t frev, crev;
1996 union crtc_source_param args;
1997
1998 memset(&args, 0, sizeof(args));
1999
2000 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2001 return;
2002
2003 if (frev != 1 && crev != 2)
2004 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2005
2006 args.v2.ucCRTC = radeon_crtc->crtc_id;
2007 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2008
2009 switch (fe) {
2010 case 0:
2011 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2012 break;
2013 case 1:
2014 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2015 break;
2016 case 2:
2017 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2018 break;
2019 case 3:
2020 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2021 break;
2022 case 4:
2023 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2024 break;
2025 case 5:
2026 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2027 break;
2028 case 6:
2029 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2030 break;
2031 }
2032 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2033}
2034
3f03ced8
AD		 2035static void
2036atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2037 struct drm_display_mode *mode)
2038{
2039 struct drm_device *dev = encoder->dev;
2040 struct radeon_device *rdev = dev->dev_private;
2041 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2042 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2043
2044 /* Funky macbooks */
2045 if ((dev->pdev->device == 0x71C5) &&
2046 (dev->pdev->subsystem_vendor == 0x106b) &&
2047 (dev->pdev->subsystem_device == 0x0080)) {
2048 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2049 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2050
2051 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2052 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2053
2054 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2055 }
2056 }
2057
2058 /* set scaler clears this on some chips */
2059 if (ASIC_IS_AVIVO(rdev) &&
2060 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
d798f2f2
AD		 2061 if (ASIC_IS_DCE8(rdev)) {
2062 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2063 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2064 CIK_INTERLEAVE_EN);
2065 else
2066 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2067 } else if (ASIC_IS_DCE4(rdev)) {
3f03ced8
AD		 2068 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2069 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2070 EVERGREEN_INTERLEAVE_EN);
2071 else
2072 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2073 } else {
2074 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2075 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2076 AVIVO_D1MODE_INTERLEAVE_EN);
2077 else
2078 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2079 }
2080 }
2081}
2082
8f0fc088
DA		 2083void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2084{
2085 if (enc_idx < 0)
2086 return;
2087 rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2088}
2089
2090int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
3f03ced8
AD		 2091{
2092 struct drm_device *dev = encoder->dev;
2093 struct radeon_device *rdev = dev->dev_private;
2094 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2095 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2096 struct drm_encoder *test_encoder;
41fa5437 2097 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8 2098 uint32_t dig_enc_in_use = 0;
8f0fc088 2099 int enc_idx = -1;
3f03ced8 2100
8f0fc088
DA		 2101 if (fe_idx >= 0) {
2102 enc_idx = fe_idx;
2103 goto assigned;
2104 }
41fa5437
AD		 2105 if (ASIC_IS_DCE6(rdev)) {
2106 /* DCE6 */
2107 switch (radeon_encoder->encoder_id) {
2108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2109 if (dig->linkb)
8f0fc088 2110 enc_idx = 1;
41fa5437 2111 else
8f0fc088 2112 enc_idx = 0;
41fa5437
AD		 2113 break;
2114 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2115 if (dig->linkb)
8f0fc088 2116 enc_idx = 3;
41fa5437 2117 else
8f0fc088 2118 enc_idx = 2;
41fa5437
AD		 2119 break;
2120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2121 if (dig->linkb)
8f0fc088 2122 enc_idx = 5;
41fa5437 2123 else
8f0fc088 2124 enc_idx = 4;
41fa5437 2125 break;
e68adef8 2126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
8f0fc088 2127 enc_idx = 6;
e68adef8 2128 break;
41fa5437 2129 }
8f0fc088 2130 goto assigned;
41fa5437
AD		 2131 } else if (ASIC_IS_DCE4(rdev)) {
2132 /* DCE4/5 */
2133 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 2134 /* ontario follows DCE4 */
2135 if (rdev->family == CHIP_PALM) {
2136 if (dig->linkb)
8f0fc088 2137 enc_idx = 1;
3f03ced8 2138 else
8f0fc088 2139 enc_idx = 0;
3f03ced8
AD		 2140 } else
2141 /* llano follows DCE3.2 */
8f0fc088 2142 enc_idx = radeon_crtc->crtc_id;
3f03ced8
AD		 2143 } else {
2144 switch (radeon_encoder->encoder_id) {
2145 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2146 if (dig->linkb)
8f0fc088 2147 enc_idx = 1;
3f03ced8 2148 else
8f0fc088 2149 enc_idx = 0;
3f03ced8
AD		 2150 break;
2151 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2152 if (dig->linkb)
8f0fc088 2153 enc_idx = 3;
3f03ced8 2154 else
8f0fc088 2155 enc_idx = 2;
3f03ced8
AD		 2156 break;
2157 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2158 if (dig->linkb)
8f0fc088 2159 enc_idx = 5;
3f03ced8 2160 else
8f0fc088 2161 enc_idx = 4;
3f03ced8
AD		 2162 break;
2163 }
2164 }
8f0fc088 2165 goto assigned;
3f03ced8
AD		 2166 }
2167
2168 /* on DCE32 and encoder can driver any block so just crtc id */
2169 if (ASIC_IS_DCE32(rdev)) {
8f0fc088
DA		 2170 enc_idx = radeon_crtc->crtc_id;
2171 goto assigned;
3f03ced8
AD		 2172 }
2173
2174 /* on DCE3 - LVTMA can only be driven by DIGB */
2175 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2176 struct radeon_encoder *radeon_test_encoder;
2177
2178 if (encoder == test_encoder)
2179 continue;
2180
2181 if (!radeon_encoder_is_digital(test_encoder))
2182 continue;
2183
2184 radeon_test_encoder = to_radeon_encoder(test_encoder);
2185 dig = radeon_test_encoder->enc_priv;
2186
2187 if (dig->dig_encoder >= 0)
2188 dig_enc_in_use |= (1 << dig->dig_encoder);
2189 }
2190
2191 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2192 if (dig_enc_in_use & 0x2)
2193 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2194 return 1;
2195 }
2196 if (!(dig_enc_in_use & 1))
2197 return 0;
2198 return 1;
8f0fc088
DA		 2199
2200assigned:
2201 if (enc_idx == -1) {
2202 DRM_ERROR("Got encoder index incorrect - returning 0\n");
2203 return 0;
2204 }
2205 if (rdev->mode_info.active_encoders & (1 << enc_idx)) {
2206 DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2207 }
2208 rdev->mode_info.active_encoders |= (1 << enc_idx);
2209 return enc_idx;
3f03ced8
AD		 2210}
2211
2212/* This only needs to be called once at startup */
2213void
2214radeon_atom_encoder_init(struct radeon_device *rdev)
2215{
2216 struct drm_device *dev = rdev->ddev;
2217 struct drm_encoder *encoder;
2218
2219 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2221 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2222
2223 switch (radeon_encoder->encoder_id) {
2224 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2225 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2226 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2227 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 2228 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2229 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2230 break;
2231 default:
2232 break;
2233 }
2234
1d3949c4 2235 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
3f03ced8
AD		 2236 atombios_external_encoder_setup(encoder, ext_encoder,
2237 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2238 }
2239}
2240
2241static void
2242radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2243 struct drm_display_mode *mode,
2244 struct drm_display_mode *adjusted_mode)
2245{
2246 struct drm_device *dev = encoder->dev;
2247 struct radeon_device *rdev = dev->dev_private;
2248 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3473f542 2249 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
6f945693 2250 int encoder_mode;
3f03ced8
AD		 2251
2252 radeon_encoder->pixel_clock = adjusted_mode->clock;
2253
8d1af57a
AD		 2254 /* need to call this here rather than in prepare() since we need some crtc info */
2255 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2256
3f03ced8
AD		 2257 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2258 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2259 atombios_yuv_setup(encoder, true);
2260 else
2261 atombios_yuv_setup(encoder, false);
2262 }
2263
2264 switch (radeon_encoder->encoder_id) {
2265 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2266 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2267 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2268 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2269 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2270 break;
2271 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2272 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2273 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2274 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8 2275 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2276 /* handled in dpms */
3f03ced8
AD		 2277 break;
2278 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2279 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2280 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2281 atombios_dvo_setup(encoder, ATOM_ENABLE);
2282 break;
2283 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2284 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2285 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2286 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2287 atombios_dac_setup(encoder, ATOM_ENABLE);
2288 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2289 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2290 atombios_tv_setup(encoder, ATOM_ENABLE);
2291 else
2292 atombios_tv_setup(encoder, ATOM_DISABLE);
2293 }
2294 break;
2295 }
2296
3f03ced8 2297 atombios_apply_encoder_quirks(encoder, adjusted_mode);
5c046a57
AD		 2298
2299 encoder_mode = atombios_get_encoder_mode(encoder);
2300 if (connector && (radeon_audio != 0) &&
2301 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2302 (ENCODER_MODE_IS_DP(encoder_mode) &&
2303 drm_detect_monitor_audio(radeon_connector_edid(connector)))))
2304 radeon_audio_mode_set(encoder, adjusted_mode);
3f03ced8
AD		 2305}
2306
2307static bool
2308atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2309{
2310 struct drm_device *dev = encoder->dev;
2311 struct radeon_device *rdev = dev->dev_private;
2312 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2313 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2314
2315 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2316 ATOM_DEVICE_CV_SUPPORT |
2317 ATOM_DEVICE_CRT_SUPPORT)) {
2318 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2319 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2320 uint8_t frev, crev;
2321
2322 memset(&args, 0, sizeof(args));
2323
2324 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2325 return false;
2326
2327 args.sDacload.ucMisc = 0;
2328
2329 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2330 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2331 args.sDacload.ucDacType = ATOM_DAC_A;
2332 else
2333 args.sDacload.ucDacType = ATOM_DAC_B;
2334
2335 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2336 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2337 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2338 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2339 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2340 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2341 if (crev >= 3)
2342 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2343 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2344 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2345 if (crev >= 3)
2346 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2347 }
2348
2349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2350
2351 return true;
2352 } else
2353 return false;
2354}
2355
2356static enum drm_connector_status
2357radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2358{
2359 struct drm_device *dev = encoder->dev;
2360 struct radeon_device *rdev = dev->dev_private;
2361 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2362 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2363 uint32_t bios_0_scratch;
2364
2365 if (!atombios_dac_load_detect(encoder, connector)) {
2366 DRM_DEBUG_KMS("detect returned false \n");
2367 return connector_status_unknown;
2368 }
2369
2370 if (rdev->family >= CHIP_R600)
2371 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2372 else
2373 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2374
2375 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2376 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2377 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2378 return connector_status_connected;
2379 }
2380 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2381 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2382 return connector_status_connected;
2383 }
2384 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2385 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2386 return connector_status_connected;
2387 }
2388 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2389 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2390 return connector_status_connected; /* CTV */
2391 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2392 return connector_status_connected; /* STV */
2393 }
2394 return connector_status_disconnected;
2395}
2396
2397static enum drm_connector_status
2398radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2399{
2400 struct drm_device *dev = encoder->dev;
2401 struct radeon_device *rdev = dev->dev_private;
2402 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2403 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2404 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2405 u32 bios_0_scratch;
2406
2407 if (!ASIC_IS_DCE4(rdev))
2408 return connector_status_unknown;
2409
2410 if (!ext_encoder)
2411 return connector_status_unknown;
2412
2413 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2414 return connector_status_unknown;
2415
2416 /* load detect on the dp bridge */
2417 atombios_external_encoder_setup(encoder, ext_encoder,
2418 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2419
2420 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2421
2422 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2423 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2424 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2425 return connector_status_connected;
2426 }
2427 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2428 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2429 return connector_status_connected;
2430 }
2431 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2432 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2433 return connector_status_connected;
2434 }
2435 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2436 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2437 return connector_status_connected; /* CTV */
2438 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2439 return connector_status_connected; /* STV */
2440 }
2441 return connector_status_disconnected;
2442}
2443
2444void
2445radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2446{
2447 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2448
2449 if (ext_encoder)
2450 /* ddc_setup on the dp bridge */
2451 atombios_external_encoder_setup(encoder, ext_encoder,
2452 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2453
2454}
2455
2456static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2457{
cfcbd6d3 2458 struct radeon_device *rdev = encoder->dev->dev_private;
3f03ced8
AD		 2459 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2460 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2461
2462 if ((radeon_encoder->active_device &
2463 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2464 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2465 ENCODER_OBJECT_ID_NONE)) {
2466 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
cfcbd6d3 2467 if (dig) {
8f0fc088
DA		 2468 if (dig->dig_encoder >= 0)
2469 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2470 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
cfcbd6d3
RM		 2471 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2472 if (rdev->family >= CHIP_R600)
2473 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2474 else
2475 /* RS600/690/740 have only 1 afmt block */
2476 dig->afmt = rdev->mode_info.afmt[0];
2477 }
2478 }
3f03ced8
AD		 2479 }
2480
2481 radeon_atom_output_lock(encoder, true);
3f03ced8
AD		 2482
2483 if (connector) {
2484 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2485
2486 /* select the clock/data port if it uses a router */
2487 if (radeon_connector->router.cd_valid)
2488 radeon_router_select_cd_port(radeon_connector);
2489
2490 /* turn eDP panel on for mode set */
2491 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2492 atombios_set_edp_panel_power(connector,
2493 ATOM_TRANSMITTER_ACTION_POWER_ON);
2494 }
2495
2496 /* this is needed for the pll/ss setup to work correctly in some cases */
2497 atombios_set_encoder_crtc_source(encoder);
134b480f
AD		 2498 /* set up the FMT blocks */
2499 if (ASIC_IS_DCE8(rdev))
2500 dce8_program_fmt(encoder);
2501 else if (ASIC_IS_DCE4(rdev))
2502 dce4_program_fmt(encoder);
2503 else if (ASIC_IS_DCE3(rdev))
2504 dce3_program_fmt(encoder);
2505 else if (ASIC_IS_AVIVO(rdev))
2506 avivo_program_fmt(encoder);
3f03ced8
AD		 2507}
2508
2509static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2510{
8d1af57a 2511 /* need to call this here as we need the crtc set up */
3f03ced8
AD		 2512 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2513 radeon_atom_output_lock(encoder, false);
2514}
2515
2516static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2517{
2518 struct drm_device *dev = encoder->dev;
2519 struct radeon_device *rdev = dev->dev_private;
2520 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2521 struct radeon_encoder_atom_dig *dig;
2522
2523 /* check for pre-DCE3 cards with shared encoders;
2524 * can't really use the links individually, so don't disable
2525 * the encoder if it's in use by another connector
2526 */
2527 if (!ASIC_IS_DCE3(rdev)) {
2528 struct drm_encoder *other_encoder;
2529 struct radeon_encoder *other_radeon_encoder;
2530
2531 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2532 other_radeon_encoder = to_radeon_encoder(other_encoder);
2533 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2534 drm_helper_encoder_in_use(other_encoder))
2535 goto disable_done;
2536 }
2537 }
2538
2539 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2540
2541 switch (radeon_encoder->encoder_id) {
2542 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2543 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2544 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2545 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2546 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2547 break;
2548 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2549 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2550 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2551 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8 2552 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2553 /* handled in dpms */
3f03ced8
AD		 2554 break;
2555 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2556 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2557 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2558 atombios_dvo_setup(encoder, ATOM_DISABLE);
2559 break;
2560 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2561 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2562 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2563 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2564 atombios_dac_setup(encoder, ATOM_DISABLE);
2565 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2566 atombios_tv_setup(encoder, ATOM_DISABLE);
2567 break;
2568 }
2569
2570disable_done:
2571 if (radeon_encoder_is_digital(encoder)) {
8f0fc088
DA		 2572 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2573 if (rdev->asic->display.hdmi_enable)
2574 radeon_hdmi_enable(rdev, encoder, false);
2575 }
2576 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2577 dig = radeon_encoder->enc_priv;
2578 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2579 dig->dig_encoder = -1;
2580 radeon_encoder->active_device = 0;
2581 }
2582 } else
2583 radeon_encoder->active_device = 0;
3f03ced8
AD		 2584}
2585
2586/* these are handled by the primary encoders */
2587static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2588{
2589
2590}
2591
2592static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2593{
2594
2595}
2596
2597static void
2598radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2599 struct drm_display_mode *mode,
2600 struct drm_display_mode *adjusted_mode)
2601{
2602
2603}
2604
2605static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2606{
2607
2608}
2609
2610static void
2611radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2612{
2613
2614}
2615
2616static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
e811f5ae 2617 const struct drm_display_mode *mode,
3f03ced8
AD		 2618 struct drm_display_mode *adjusted_mode)
2619{
2620 return true;
2621}
2622
2623static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2624 .dpms = radeon_atom_ext_dpms,
2625 .mode_fixup = radeon_atom_ext_mode_fixup,
2626 .prepare = radeon_atom_ext_prepare,
2627 .mode_set = radeon_atom_ext_mode_set,
2628 .commit = radeon_atom_ext_commit,
2629 .disable = radeon_atom_ext_disable,
2630 /* no detect for TMDS/LVDS yet */
2631};
2632
2633static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2634 .dpms = radeon_atom_encoder_dpms,
2635 .mode_fixup = radeon_atom_mode_fixup,
2636 .prepare = radeon_atom_encoder_prepare,
2637 .mode_set = radeon_atom_encoder_mode_set,
2638 .commit = radeon_atom_encoder_commit,
2639 .disable = radeon_atom_encoder_disable,
2640 .detect = radeon_atom_dig_detect,
2641};
2642
2643static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2644 .dpms = radeon_atom_encoder_dpms,
2645 .mode_fixup = radeon_atom_mode_fixup,
2646 .prepare = radeon_atom_encoder_prepare,
2647 .mode_set = radeon_atom_encoder_mode_set,
2648 .commit = radeon_atom_encoder_commit,
2649 .detect = radeon_atom_dac_detect,
2650};
2651
2652void radeon_enc_destroy(struct drm_encoder *encoder)
2653{
2654 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f3728734
AD		 2655 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2656 radeon_atom_backlight_exit(radeon_encoder);
3f03ced8
AD		 2657 kfree(radeon_encoder->enc_priv);
2658 drm_encoder_cleanup(encoder);
2659 kfree(radeon_encoder);
2660}
2661
2662static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2663 .destroy = radeon_enc_destroy,
2664};
2665
1109ca09 2666static struct radeon_encoder_atom_dac *
3f03ced8
AD		 2667radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2668{
2669 struct drm_device *dev = radeon_encoder->base.dev;
2670 struct radeon_device *rdev = dev->dev_private;
2671 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2672
2673 if (!dac)
2674 return NULL;
2675
2676 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2677 return dac;
2678}
2679
1109ca09 2680static struct radeon_encoder_atom_dig *
3f03ced8
AD		 2681radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2682{
2683 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2684 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2685
2686 if (!dig)
2687 return NULL;
2688
2689 /* coherent mode by default */
2690 dig->coherent_mode = true;
2691 dig->dig_encoder = -1;
2692
2693 if (encoder_enum == 2)
2694 dig->linkb = true;
2695 else
2696 dig->linkb = false;
2697
2698 return dig;
2699}
2700
2701void
2702radeon_add_atom_encoder(struct drm_device *dev,
2703 uint32_t encoder_enum,
2704 uint32_t supported_device,
2705 u16 caps)
2706{
2707 struct radeon_device *rdev = dev->dev_private;
2708 struct drm_encoder *encoder;
2709 struct radeon_encoder *radeon_encoder;
2710
2711 /* see if we already added it */
2712 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2713 radeon_encoder = to_radeon_encoder(encoder);
2714 if (radeon_encoder->encoder_enum == encoder_enum) {
2715 radeon_encoder->devices |= supported_device;
2716 return;
2717 }
2718
2719 }
2720
2721 /* add a new one */
2722 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2723 if (!radeon_encoder)
2724 return;
2725
2726 encoder = &radeon_encoder->base;
2727 switch (rdev->num_crtc) {
2728 case 1:
2729 encoder->possible_crtcs = 0x1;
2730 break;
2731 case 2:
2732 default:
2733 encoder->possible_crtcs = 0x3;
2734 break;
2735 case 4:
2736 encoder->possible_crtcs = 0xf;
2737 break;
2738 case 6:
2739 encoder->possible_crtcs = 0x3f;
2740 break;
2741 }
2742
2743 radeon_encoder->enc_priv = NULL;
2744
2745 radeon_encoder->encoder_enum = encoder_enum;
2746 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2747 radeon_encoder->devices = supported_device;
2748 radeon_encoder->rmx_type = RMX_OFF;
2749 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2750 radeon_encoder->is_ext_encoder = false;
2751 radeon_encoder->caps = caps;
2752
2753 switch (radeon_encoder->encoder_id) {
2754 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2755 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2756 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2757 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2758 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2759 radeon_encoder->rmx_type = RMX_FULL;
2760 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2761 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2762 } else {
2763 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2764 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2765 }
2766 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2767 break;
2768 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2769 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2770 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2771 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2772 break;
2773 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2774 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2775 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2776 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2777 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2778 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2779 break;
2780 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2781 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2782 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2783 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2784 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2785 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2786 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2787 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 2788 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2789 radeon_encoder->rmx_type = RMX_FULL;
2790 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2791 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2792 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2793 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2794 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2795 } else {
2796 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2797 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2798 }
2799 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2800 break;
2801 case ENCODER_OBJECT_ID_SI170B:
2802 case ENCODER_OBJECT_ID_CH7303:
2803 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2804 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2805 case ENCODER_OBJECT_ID_TITFP513:
2806 case ENCODER_OBJECT_ID_VT1623:
2807 case ENCODER_OBJECT_ID_HDMI_SI1930:
2808 case ENCODER_OBJECT_ID_TRAVIS:
2809 case ENCODER_OBJECT_ID_NUTMEG:
2810 /* these are handled by the primary encoders */
2811 radeon_encoder->is_ext_encoder = true;
2812 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2813 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2814 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2815 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2816 else
2817 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2818 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2819 break;
2820 }
2821}
Linux 6.x block layer and io_uring tree(s)