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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nvkm / subdev / bios / init.c
CommitLineData
d390b480
BS		 1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
cb75d97e 24#include <subdev/bios.h>
cb75d97e 25#include <subdev/bios/bit.h>
d390b480 26#include <subdev/bios/bmp.h>
1ed73166 27#include <subdev/bios/conn.h>
cb75d97e
BS		 28#include <subdev/bios/dcb.h>
29#include <subdev/bios/dp.h>
1ed73166 30#include <subdev/bios/gpio.h>
cb75d97e 31#include <subdev/bios/init.h>
0a0dc8f5 32#include <subdev/bios/ramcfg.h>
b9ec1424
BS		 33
34#include <core/device.h>
cb75d97e 35#include <subdev/devinit.h>
d390b480 36#include <subdev/gpio.h>
cb75d97e
BS		 37#include <subdev/i2c.h>
38#include <subdev/vga.h>
cb75d97e
BS		 39
40#define bioslog(lvl, fmt, args...) do { \
41 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
42 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
43} while(0)
44#define cont(fmt, args...) do { \
45 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
46 printk(fmt, ##args); \
47} while(0)
48#define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
49#define warn(fmt, args...) bioslog(WARN, fmt, ##args)
50#define error(fmt, args...) bioslog(ERROR, fmt, ##args)
51
52/******************************************************************************
53 * init parser control flow helpers
54 *****************************************************************************/
55
56static inline bool
57init_exec(struct nvbios_init *init)
58{
59 return (init->execute == 1) || ((init->execute & 5) == 5);
60}
61
62static inline void
63init_exec_set(struct nvbios_init *init, bool exec)
64{
65 if (exec) init->execute &= 0xfd;
66 else init->execute |= 0x02;
67}
68
69static inline void
70init_exec_inv(struct nvbios_init *init)
71{
72 init->execute ^= 0x02;
73}
74
75static inline void
76init_exec_force(struct nvbios_init *init, bool exec)
77{
78 if (exec) init->execute |= 0x04;
79 else init->execute &= 0xfb;
80}
81
82/******************************************************************************
83 * init parser wrappers for normal register/i2c/whatever accessors
84 *****************************************************************************/
85
86static inline int
87init_or(struct nvbios_init *init)
88{
28ec70f7
BS		 89 if (init_exec(init)) {
90 if (init->outp)
91 return ffs(init->outp->or) - 1;
92 error("script needs OR!!\n");
93 }
cb75d97e
BS		 94 return 0;
95}
96
97static inline int
98init_link(struct nvbios_init *init)
99{
28ec70f7
BS		 100 if (init_exec(init)) {
101 if (init->outp)
102 return !(init->outp->sorconf.link & 1);
103 error("script needs OR link\n");
104 }
cb75d97e
BS		 105 return 0;
106}
107
108static inline int
109init_crtc(struct nvbios_init *init)
110{
28ec70f7
BS		 111 if (init_exec(init)) {
112 if (init->crtc >= 0)
113 return init->crtc;
114 error("script needs crtc\n");
115 }
cb75d97e
BS		 116 return 0;
117}
118
119static u8
120init_conn(struct nvbios_init *init)
121{
d390b480 122 struct nvkm_bios *bios = init->bios;
20014cbe
BS		 123 struct nvbios_connE connE;
124 u8 ver, hdr;
125 u32 conn;
cb75d97e 126
28ec70f7
BS		 127 if (init_exec(init)) {
128 if (init->outp) {
129 conn = init->outp->connector;
20014cbe 130 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE);
28ec70f7 131 if (conn)
20014cbe 132 return connE.type;
28ec70f7
BS		 133 }
134
135 error("script needs connector type\n");
cb75d97e
BS		 136 }
137
28ec70f7 138 return 0xff;
cb75d97e
BS		 139}
140
141static inline u32
142init_nvreg(struct nvbios_init *init, u32 reg)
143{
d390b480 144 struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
3219adc2 145
cb75d97e
BS		 146 /* C51 (at least) sometimes has the lower bits set which the VBIOS
147 * interprets to mean that access needs to go through certain IO
148 * ports instead. The NVIDIA binary driver has been seen to access
149 * these through the NV register address, so lets assume we can
150 * do the same
151 */
152 reg &= ~0x00000003;
153
154 /* GF8+ display scripts need register addresses mangled a bit to
155 * select a specific CRTC/OR
156 */
157 if (nv_device(init->bios)->card_type >= NV_50) {
158 if (reg & 0x80000000) {
159 reg += init_crtc(init) * 0x800;
160 reg &= ~0x80000000;
161 }
162
163 if (reg & 0x40000000) {
164 reg += init_or(init) * 0x800;
165 reg &= ~0x40000000;
166 if (reg & 0x20000000) {
167 reg += init_link(init) * 0x80;
168 reg &= ~0x20000000;
169 }
170 }
171 }
172
173 if (reg & ~0x00fffffc)
174 warn("unknown bits in register 0x%08x\n", reg);
3219adc2
BS		 175
176 if (devinit->mmio)
177 reg = devinit->mmio(devinit, reg);
cb75d97e
BS		 178 return reg;
179}
180
181static u32
182init_rd32(struct nvbios_init *init, u32 reg)
183{
184 reg = init_nvreg(init, reg);
3219adc2 185 if (reg != ~0 && init_exec(init))
cb75d97e
BS		 186 return nv_rd32(init->subdev, reg);
187 return 0x00000000;
188}
189
190static void
191init_wr32(struct nvbios_init *init, u32 reg, u32 val)
192{
193 reg = init_nvreg(init, reg);
3219adc2 194 if (reg != ~0 && init_exec(init))
cb75d97e
BS		 195 nv_wr32(init->subdev, reg, val);
196}
197
198static u32
199init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
200{
201 reg = init_nvreg(init, reg);
3219adc2 202 if (reg != ~0 && init_exec(init)) {
cb75d97e
BS		 203 u32 tmp = nv_rd32(init->subdev, reg);
204 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
205 return tmp;
206 }
207 return 0x00000000;
208}
209
210static u8
211init_rdport(struct nvbios_init *init, u16 port)
212{
213 if (init_exec(init))
214 return nv_rdport(init->subdev, init->crtc, port);
215 return 0x00;
216}
217
218static void
219init_wrport(struct nvbios_init *init, u16 port, u8 value)
220{
221 if (init_exec(init))
222 nv_wrport(init->subdev, init->crtc, port, value);
223}
224
225static u8
226init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
227{
d390b480 228 struct nvkm_subdev *subdev = init->subdev;
cb75d97e
BS		 229 if (init_exec(init)) {
230 int head = init->crtc < 0 ? 0 : init->crtc;
231 return nv_rdvgai(subdev, head, port, index);
232 }
233 return 0x00;
234}
235
236static void
237init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
238{
239 /* force head 0 for updates to cr44, it only exists on first head */
240 if (nv_device(init->subdev)->card_type < NV_50) {
241 if (port == 0x03d4 && index == 0x44)
242 init->crtc = 0;
243 }
244
245 if (init_exec(init)) {
246 int head = init->crtc < 0 ? 0 : init->crtc;
247 nv_wrvgai(init->subdev, head, port, index, value);
248 }
249
250 /* select head 1 if cr44 write selected it */
251 if (nv_device(init->subdev)->card_type < NV_50) {
252 if (port == 0x03d4 && index == 0x44 && value == 3)
253 init->crtc = 1;
254 }
255}
256
d390b480 257static struct nvkm_i2c_port *
cb75d97e
BS		 258init_i2c(struct nvbios_init *init, int index)
259{
d390b480 260 struct nvkm_i2c *i2c = nvkm_i2c(init->bios);
cb75d97e
BS		 261
262 if (index == 0xff) {
263 index = NV_I2C_DEFAULT(0);
264 if (init->outp && init->outp->i2c_upper_default)
265 index = NV_I2C_DEFAULT(1);
266 } else
267 if (index < 0) {
268 if (!init->outp) {
28ec70f7
BS		 269 if (init_exec(init))
270 error("script needs output for i2c\n");
cb75d97e
BS		 271 return NULL;
272 }
273
476e84e1
BS		 274 if (index == -2 && init->outp->location) {
275 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
276 return i2c->find_type(i2c, index);
277 }
278
cb75d97e 279 index = init->outp->i2c_index;
5b34cebe
BS		 280 if (init->outp->type == DCB_OUTPUT_DP)
281 index += NV_I2C_AUX(0);
cb75d97e
BS		 282 }
283
284 return i2c->find(i2c, index);
285}
286
287static int
288init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
289{
d390b480 290 struct nvkm_i2c_port *port = init_i2c(init, index);
cb75d97e
BS		 291 if (port && init_exec(init))
292 return nv_rdi2cr(port, addr, reg);
293 return -ENODEV;
294}
295
296static int
297init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
298{
d390b480 299 struct nvkm_i2c_port *port = init_i2c(init, index);
cb75d97e
BS		 300 if (port && init_exec(init))
301 return nv_wri2cr(port, addr, reg, val);
302 return -ENODEV;
303}
304
6ef4ead1 305static u8
cb75d97e
BS		 306init_rdauxr(struct nvbios_init *init, u32 addr)
307{
d390b480 308 struct nvkm_i2c_port *port = init_i2c(init, -2);
cb75d97e
BS		 309 u8 data;
310
311 if (port && init_exec(init)) {
312 int ret = nv_rdaux(port, addr, &data, 1);
6ef4ead1
BS		 313 if (ret == 0)
314 return data;
315 trace("auxch read failed with %d\n", ret);
cb75d97e
BS		 316 }
317
6ef4ead1 318 return 0x00;
cb75d97e
BS		 319}
320
321static int
322init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
323{
d390b480 324 struct nvkm_i2c_port *port = init_i2c(init, -2);
6ef4ead1
BS		 325 if (port && init_exec(init)) {
326 int ret = nv_wraux(port, addr, &data, 1);
327 if (ret)
328 trace("auxch write failed with %d\n", ret);
329 return ret;
330 }
cb75d97e
BS		 331 return -ENODEV;
332}
333
334static void
335init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
336{
d390b480 337 struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
88524bc0
BS		 338 if (devinit->pll_set && init_exec(init)) {
339 int ret = devinit->pll_set(devinit, id, freq);
cb75d97e
BS		 340 if (ret)
341 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
342 }
343}
344
345/******************************************************************************
346 * parsing of bios structures that are required to execute init tables
347 *****************************************************************************/
348
349static u16
d390b480 350init_table(struct nvkm_bios *bios, u16 *len)
cb75d97e
BS		 351{
352 struct bit_entry bit_I;
353
354 if (!bit_entry(bios, 'I', &bit_I)) {
355 *len = bit_I.length;
356 return bit_I.offset;
357 }
358
359 if (bmp_version(bios) >= 0x0510) {
360 *len = 14;
361 return bios->bmp_offset + 75;
362 }
363
364 return 0x0000;
365}
366
367static u16
368init_table_(struct nvbios_init *init, u16 offset, const char *name)
369{
d390b480 370 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 371 u16 len, data = init_table(bios, &len);
372 if (data) {
373 if (len >= offset + 2) {
374 data = nv_ro16(bios, data + offset);
375 if (data)
376 return data;
377
378 warn("%s pointer invalid\n", name);
379 return 0x0000;
380 }
381
382 warn("init data too short for %s pointer", name);
383 return 0x0000;
384 }
385
386 warn("init data not found\n");
387 return 0x0000;
388}
389
390#define init_script_table(b) init_table_((b), 0x00, "script table")
391#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
392#define init_macro_table(b) init_table_((b), 0x04, "macro table")
393#define init_condition_table(b) init_table_((b), 0x06, "condition table")
394#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
395#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
396#define init_function_table(b) init_table_((b), 0x0c, "function table")
397#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
398
399static u16
d390b480 400init_script(struct nvkm_bios *bios, int index)
cb75d97e
BS		 401{
402 struct nvbios_init init = { .bios = bios };
5d2f4767 403 u16 bmp_ver = bmp_version(bios), data;
cb75d97e 404
5d2f4767
IM		 405 if (bmp_ver && bmp_ver < 0x0510) {
406 if (index > 1 || bmp_ver < 0x0100)
cb75d97e
BS		 407 return 0x0000;
408
5d2f4767 409 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
cb75d97e
BS		 410 return nv_ro16(bios, data + (index * 2));
411 }
412
413 data = init_script_table(&init);
414 if (data)
415 return nv_ro16(bios, data + (index * 2));
416
417 return 0x0000;
418}
419
420static u16
d390b480 421init_unknown_script(struct nvkm_bios *bios)
cb75d97e
BS		 422{
423 u16 len, data = init_table(bios, &len);
424 if (data && len >= 16)
425 return nv_ro16(bios, data + 14);
426 return 0x0000;
427}
428
cb75d97e
BS		 429static u8
430init_ram_restrict_group_count(struct nvbios_init *init)
431{
0a0dc8f5 432 return nvbios_ramcfg_count(init->bios);
cb75d97e
BS		 433}
434
5ddf4d4a 435static u8
0a0dc8f5 436init_ram_restrict(struct nvbios_init *init)
5ddf4d4a
BS		 437{
438 /* This appears to be the behaviour of the VBIOS parser, and *is*
439 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
440 * avoid fucking up the memory controller (somehow) by reading it
441 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
442 *
443 * Preserving the non-caching behaviour on earlier chipsets just
444 * in case *not* re-reading the strap causes similar breakage.
445 */
446 if (!init->ramcfg || init->bios->version.major < 0x70)
0a8649f1 447 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
0a0dc8f5 448 return (init->ramcfg & 0x7fffffff);
cb75d97e
BS		 449}
450
451static u8
452init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
453{
d390b480 454 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 455 u16 table = init_xlat_table(init);
456 if (table) {
457 u16 data = nv_ro16(bios, table + (index * 2));
458 if (data)
459 return nv_ro08(bios, data + offset);
460 warn("xlat table pointer %d invalid\n", index);
461 }
462 return 0x00;
463}
464
465/******************************************************************************
466 * utility functions used by various init opcode handlers
467 *****************************************************************************/
468
469static bool
470init_condition_met(struct nvbios_init *init, u8 cond)
471{
d390b480 472 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 473 u16 table = init_condition_table(init);
474 if (table) {
475 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
476 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
477 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
478 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
479 cond, reg, msk, val);
480 return (init_rd32(init, reg) & msk) == val;
481 }
482 return false;
483}
484
485static bool
486init_io_condition_met(struct nvbios_init *init, u8 cond)
487{
d390b480 488 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 489 u16 table = init_io_condition_table(init);
490 if (table) {
491 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
492 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
493 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
494 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
495 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
496 cond, port, index, mask, value);
497 return (init_rdvgai(init, port, index) & mask) == value;
498 }
499 return false;
500}
501
502static bool
503init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
504{
d390b480 505 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 506 u16 table = init_io_flag_condition_table(init);
507 if (table) {
508 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
509 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
510 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
511 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
512 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
513 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
514 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
515 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
516 return (nv_ro08(bios, data + ioval) & dmask) == value;
517 }
518 return false;
519}
520
521static inline u32
522init_shift(u32 data, u8 shift)
523{
524 if (shift < 0x80)
525 return data >> shift;
526 return data << (0x100 - shift);
527}
528
529static u32
530init_tmds_reg(struct nvbios_init *init, u8 tmds)
531{
532 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
533 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
534 * CR58 for CR57 = 0 to index a table of offsets to the basic
535 * 0x6808b0 address.
536 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
537 * CR58 for CR57 = 0 to index a table of offsets to the basic
538 * 0x6808b0 address, and then flip the offset by 8.
539 */
cb75d97e
BS		 540 const int pramdac_offset[13] = {
541 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
542 const u32 pramdac_table[4] = {
543 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
544
545 if (tmds >= 0x80) {
546 if (init->outp) {
547 u32 dacoffset = pramdac_offset[init->outp->or];
548 if (tmds == 0x81)
549 dacoffset ^= 8;
550 return 0x6808b0 + dacoffset;
551 }
552
28ec70f7
BS		 553 if (init_exec(init))
554 error("tmds opcodes need dcb\n");
cb75d97e
BS		 555 } else {
556 if (tmds < ARRAY_SIZE(pramdac_table))
557 return pramdac_table[tmds];
558
559 error("tmds selector 0x%02x unknown\n", tmds);
560 }
561
562 return 0;
563}
564
565/******************************************************************************
566 * init opcode handlers
567 *****************************************************************************/
568
569/**
570 * init_reserved - stub for various unknown/unused single-byte opcodes
571 *
572 */
573static void
574init_reserved(struct nvbios_init *init)
575{
576 u8 opcode = nv_ro08(init->bios, init->offset);
5495e39f
BS		 577 u8 length, i;
578
579 switch (opcode) {
580 case 0xaa:
581 length = 4;
582 break;
583 default:
584 length = 1;
585 break;
586 }
587
588 trace("RESERVED 0x%02x\t", opcode);
589 for (i = 1; i < length; i++)
590 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
591 cont("\n");
592 init->offset += length;
cb75d97e
BS		 593}
594
595/**
596 * INIT_DONE - opcode 0x71
597 *
598 */
599static void
600init_done(struct nvbios_init *init)
601{
602 trace("DONE\n");
603 init->offset = 0x0000;
604}
605
606/**
607 * INIT_IO_RESTRICT_PROG - opcode 0x32
608 *
609 */
610static void
611init_io_restrict_prog(struct nvbios_init *init)
612{
d390b480 613 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 614 u16 port = nv_ro16(bios, init->offset + 1);
615 u8 index = nv_ro08(bios, init->offset + 3);
616 u8 mask = nv_ro08(bios, init->offset + 4);
617 u8 shift = nv_ro08(bios, init->offset + 5);
618 u8 count = nv_ro08(bios, init->offset + 6);
619 u32 reg = nv_ro32(bios, init->offset + 7);
620 u8 conf, i;
621
622 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
623 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
624 reg, port, index, mask, shift);
625 init->offset += 11;
626
627 conf = (init_rdvgai(init, port, index) & mask) >> shift;
628 for (i = 0; i < count; i++) {
629 u32 data = nv_ro32(bios, init->offset);
630
631 if (i == conf) {
632 trace("\t0x%08x *\n", data);
633 init_wr32(init, reg, data);
634 } else {
635 trace("\t0x%08x\n", data);
636 }
637
638 init->offset += 4;
639 }
640 trace("}]\n");
641}
642
643/**
644 * INIT_REPEAT - opcode 0x33
645 *
646 */
647static void
648init_repeat(struct nvbios_init *init)
649{
d390b480 650 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 651 u8 count = nv_ro08(bios, init->offset + 1);
652 u16 repeat = init->repeat;
653
654 trace("REPEAT\t0x%02x\n", count);
655 init->offset += 2;
656
657 init->repeat = init->offset;
658 init->repend = init->offset;
659 while (count--) {
660 init->offset = init->repeat;
661 nvbios_exec(init);
662 if (count)
663 trace("REPEAT\t0x%02x\n", count);
664 }
665 init->offset = init->repend;
666 init->repeat = repeat;
667}
668
669/**
670 * INIT_IO_RESTRICT_PLL - opcode 0x34
671 *
672 */
673static void
674init_io_restrict_pll(struct nvbios_init *init)
675{
d390b480 676 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 677 u16 port = nv_ro16(bios, init->offset + 1);
678 u8 index = nv_ro08(bios, init->offset + 3);
679 u8 mask = nv_ro08(bios, init->offset + 4);
680 u8 shift = nv_ro08(bios, init->offset + 5);
681 s8 iofc = nv_ro08(bios, init->offset + 6);
682 u8 count = nv_ro08(bios, init->offset + 7);
683 u32 reg = nv_ro32(bios, init->offset + 8);
684 u8 conf, i;
685
686 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
687 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
688 reg, port, index, mask, shift, iofc);
689 init->offset += 12;
690
691 conf = (init_rdvgai(init, port, index) & mask) >> shift;
692 for (i = 0; i < count; i++) {
693 u32 freq = nv_ro16(bios, init->offset) * 10;
694
695 if (i == conf) {
696 trace("\t%dkHz *\n", freq);
697 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
698 freq *= 2;
699 init_prog_pll(init, reg, freq);
700 } else {
701 trace("\t%dkHz\n", freq);
702 }
703
704 init->offset += 2;
705 }
706 trace("}]\n");
707}
708
709/**
710 * INIT_END_REPEAT - opcode 0x36
711 *
712 */
713static void
714init_end_repeat(struct nvbios_init *init)
715{
716 trace("END_REPEAT\n");
717 init->offset += 1;
718
719 if (init->repeat) {
720 init->repend = init->offset;
721 init->offset = 0;
722 }
723}
724
725/**
726 * INIT_COPY - opcode 0x37
727 *
728 */
729static void
730init_copy(struct nvbios_init *init)
731{
d390b480 732 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 733 u32 reg = nv_ro32(bios, init->offset + 1);
734 u8 shift = nv_ro08(bios, init->offset + 5);
735 u8 smask = nv_ro08(bios, init->offset + 6);
736 u16 port = nv_ro16(bios, init->offset + 7);
737 u8 index = nv_ro08(bios, init->offset + 9);
738 u8 mask = nv_ro08(bios, init->offset + 10);
739 u8 data;
740
741 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
742 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
743 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
744 (shift & 0x80) ? (0x100 - shift) : shift, smask);
745 init->offset += 11;
746
747 data = init_rdvgai(init, port, index) & mask;
748 data |= init_shift(init_rd32(init, reg), shift) & smask;
749 init_wrvgai(init, port, index, data);
750}
751
752/**
753 * INIT_NOT - opcode 0x38
754 *
755 */
756static void
757init_not(struct nvbios_init *init)
758{
759 trace("NOT\n");
760 init->offset += 1;
761 init_exec_inv(init);
762}
763
764/**
765 * INIT_IO_FLAG_CONDITION - opcode 0x39
766 *
767 */
768static void
769init_io_flag_condition(struct nvbios_init *init)
770{
d390b480 771 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 772 u8 cond = nv_ro08(bios, init->offset + 1);
773
774 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
775 init->offset += 2;
776
777 if (!init_io_flag_condition_met(init, cond))
778 init_exec_set(init, false);
779}
780
781/**
782 * INIT_DP_CONDITION - opcode 0x3a
783 *
784 */
785static void
786init_dp_condition(struct nvbios_init *init)
787{
d390b480 788 struct nvkm_bios *bios = init->bios;
65c78660 789 struct nvbios_dpout info;
cb75d97e
BS		 790 u8 cond = nv_ro08(bios, init->offset + 1);
791 u8 unkn = nv_ro08(bios, init->offset + 2);
65c78660 792 u8 ver, hdr, cnt, len;
cb75d97e
BS		 793 u16 data;
794
795 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
796 init->offset += 3;
797
798 switch (cond) {
799 case 0:
800 if (init_conn(init) != DCB_CONNECTOR_eDP)
801 init_exec_set(init, false);
802 break;
803 case 1:
804 case 2:
805 if ( init->outp &&
65c78660
BS		 806 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
807 (init->outp->or << 0) |
808 (init->outp->sorconf.link << 6),
809 &ver, &hdr, &cnt, &len, &info)))
810 {
811 if (!(info.flags & cond))
cb75d97e
BS		 812 init_exec_set(init, false);
813 break;
814 }
815
28ec70f7
BS		 816 if (init_exec(init))
817 warn("script needs dp output table data\n");
cb75d97e
BS		 818 break;
819 case 5:
820 if (!(init_rdauxr(init, 0x0d) & 1))
821 init_exec_set(init, false);
822 break;
823 default:
824 warn("unknown dp condition 0x%02x\n", cond);
825 break;
826 }
827}
828
829/**
830 * INIT_IO_MASK_OR - opcode 0x3b
831 *
832 */
833static void
834init_io_mask_or(struct nvbios_init *init)
835{
d390b480 836 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 837 u8 index = nv_ro08(bios, init->offset + 1);
838 u8 or = init_or(init);
839 u8 data;
840
b9a3140c 841 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
cb75d97e
BS		 842 init->offset += 2;
843
844 data = init_rdvgai(init, 0x03d4, index);
845 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
846}
847
848/**
849 * INIT_IO_OR - opcode 0x3c
850 *
851 */
852static void
853init_io_or(struct nvbios_init *init)
854{
d390b480 855 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 856 u8 index = nv_ro08(bios, init->offset + 1);
857 u8 or = init_or(init);
858 u8 data;
859
b9a3140c 860 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
cb75d97e
BS		 861 init->offset += 2;
862
863 data = init_rdvgai(init, 0x03d4, index);
864 init_wrvgai(init, 0x03d4, index, data | (1 << or));
865}
866
c79965d8
BS		 867/**
868 * INIT_ANDN_REG - opcode 0x47
869 *
870 */
871static void
872init_andn_reg(struct nvbios_init *init)
873{
d390b480 874 struct nvkm_bios *bios = init->bios;
c79965d8
BS		 875 u32 reg = nv_ro32(bios, init->offset + 1);
876 u32 mask = nv_ro32(bios, init->offset + 5);
877
878 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask);
879 init->offset += 9;
880
881 init_mask(init, reg, mask, 0);
882}
883
884/**
885 * INIT_OR_REG - opcode 0x48
886 *
887 */
888static void
889init_or_reg(struct nvbios_init *init)
890{
d390b480 891 struct nvkm_bios *bios = init->bios;
c79965d8
BS		 892 u32 reg = nv_ro32(bios, init->offset + 1);
893 u32 mask = nv_ro32(bios, init->offset + 5);
894
895 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask);
896 init->offset += 9;
897
898 init_mask(init, reg, 0, mask);
899}
900
cb75d97e
BS		 901/**
902 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
903 *
904 */
905static void
906init_idx_addr_latched(struct nvbios_init *init)
907{
d390b480 908 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 909 u32 creg = nv_ro32(bios, init->offset + 1);
910 u32 dreg = nv_ro32(bios, init->offset + 5);
911 u32 mask = nv_ro32(bios, init->offset + 9);
912 u32 data = nv_ro32(bios, init->offset + 13);
913 u8 count = nv_ro08(bios, init->offset + 17);
914
8db3a740
IM		 915 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
916 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
cb75d97e
BS		 917 init->offset += 18;
918
919 while (count--) {
920 u8 iaddr = nv_ro08(bios, init->offset + 0);
921 u8 idata = nv_ro08(bios, init->offset + 1);
922
923 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
924 init->offset += 2;
925
926 init_wr32(init, dreg, idata);
f6853faa 927 init_mask(init, creg, ~mask, data | iaddr);
cb75d97e
BS		 928 }
929}
930
931/**
932 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
933 *
934 */
935static void
936init_io_restrict_pll2(struct nvbios_init *init)
937{
d390b480 938 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 939 u16 port = nv_ro16(bios, init->offset + 1);
940 u8 index = nv_ro08(bios, init->offset + 3);
941 u8 mask = nv_ro08(bios, init->offset + 4);
942 u8 shift = nv_ro08(bios, init->offset + 5);
943 u8 count = nv_ro08(bios, init->offset + 6);
944 u32 reg = nv_ro32(bios, init->offset + 7);
945 u8 conf, i;
946
947 trace("IO_RESTRICT_PLL2\t"
948 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
949 reg, port, index, mask, shift);
950 init->offset += 11;
951
952 conf = (init_rdvgai(init, port, index) & mask) >> shift;
953 for (i = 0; i < count; i++) {
954 u32 freq = nv_ro32(bios, init->offset);
955 if (i == conf) {
956 trace("\t%dkHz *\n", freq);
957 init_prog_pll(init, reg, freq);
958 } else {
959 trace("\t%dkHz\n", freq);
960 }
961 init->offset += 4;
962 }
963 trace("}]\n");
964}
965
966/**
967 * INIT_PLL2 - opcode 0x4b
968 *
969 */
970static void
971init_pll2(struct nvbios_init *init)
972{
d390b480 973 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 974 u32 reg = nv_ro32(bios, init->offset + 1);
975 u32 freq = nv_ro32(bios, init->offset + 5);
976
977 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
978 init->offset += 9;
979
980 init_prog_pll(init, reg, freq);
981}
982
983/**
984 * INIT_I2C_BYTE - opcode 0x4c
985 *
986 */
987static void
988init_i2c_byte(struct nvbios_init *init)
989{
d390b480 990 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 991 u8 index = nv_ro08(bios, init->offset + 1);
992 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
993 u8 count = nv_ro08(bios, init->offset + 3);
994
995 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
996 init->offset += 4;
997
998 while (count--) {
999 u8 reg = nv_ro08(bios, init->offset + 0);
1000 u8 mask = nv_ro08(bios, init->offset + 1);
1001 u8 data = nv_ro08(bios, init->offset + 2);
1002 int val;
1003
1004 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
1005 init->offset += 3;
1006
1007 val = init_rdi2cr(init, index, addr, reg);
1008 if (val < 0)
1009 continue;
1010 init_wri2cr(init, index, addr, reg, (val & mask) | data);
1011 }
1012}
1013
1014/**
1015 * INIT_ZM_I2C_BYTE - opcode 0x4d
1016 *
1017 */
1018static void
1019init_zm_i2c_byte(struct nvbios_init *init)
1020{
d390b480 1021 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1022 u8 index = nv_ro08(bios, init->offset + 1);
1023 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1024 u8 count = nv_ro08(bios, init->offset + 3);
1025
1026 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1027 init->offset += 4;
1028
1029 while (count--) {
1030 u8 reg = nv_ro08(bios, init->offset + 0);
1031 u8 data = nv_ro08(bios, init->offset + 1);
1032
1033 trace("\t[0x%02x] = 0x%02x\n", reg, data);
1034 init->offset += 2;
1035
1036 init_wri2cr(init, index, addr, reg, data);
1037 }
cb75d97e
BS		 1038}
1039
1040/**
1041 * INIT_ZM_I2C - opcode 0x4e
1042 *
1043 */
1044static void
1045init_zm_i2c(struct nvbios_init *init)
1046{
d390b480 1047 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1048 u8 index = nv_ro08(bios, init->offset + 1);
1049 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1050 u8 count = nv_ro08(bios, init->offset + 3);
1051 u8 data[256], i;
1052
1053 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1054 init->offset += 4;
1055
1056 for (i = 0; i < count; i++) {
1057 data[i] = nv_ro08(bios, init->offset);
1058 trace("\t0x%02x\n", data[i]);
1059 init->offset++;
1060 }
1061
1062 if (init_exec(init)) {
d390b480 1063 struct nvkm_i2c_port *port = init_i2c(init, index);
cb75d97e
BS		 1064 struct i2c_msg msg = {
1065 .addr = addr, .flags = 0, .len = count, .buf = data,
1066 };
1067 int ret;
1068
1069 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1070 warn("i2c wr failed, %d\n", ret);
1071 }
1072}
1073
1074/**
1075 * INIT_TMDS - opcode 0x4f
1076 *
1077 */
1078static void
1079init_tmds(struct nvbios_init *init)
1080{
d390b480 1081 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1082 u8 tmds = nv_ro08(bios, init->offset + 1);
1083 u8 addr = nv_ro08(bios, init->offset + 2);
1084 u8 mask = nv_ro08(bios, init->offset + 3);
1085 u8 data = nv_ro08(bios, init->offset + 4);
1086 u32 reg = init_tmds_reg(init, tmds);
1087
1088 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1089 tmds, addr, mask, data);
1090 init->offset += 5;
1091
1092 if (reg == 0)
1093 return;
1094
1095 init_wr32(init, reg + 0, addr | 0x00010000);
1096 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1097 init_wr32(init, reg + 0, addr);
1098}
1099
1100/**
1101 * INIT_ZM_TMDS_GROUP - opcode 0x50
1102 *
1103 */
1104static void
1105init_zm_tmds_group(struct nvbios_init *init)
1106{
d390b480 1107 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1108 u8 tmds = nv_ro08(bios, init->offset + 1);
1109 u8 count = nv_ro08(bios, init->offset + 2);
1110 u32 reg = init_tmds_reg(init, tmds);
1111
1112 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1113 init->offset += 3;
1114
1115 while (count--) {
1116 u8 addr = nv_ro08(bios, init->offset + 0);
1117 u8 data = nv_ro08(bios, init->offset + 1);
1118
1119 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1120 init->offset += 2;
1121
1122 init_wr32(init, reg + 4, data);
1123 init_wr32(init, reg + 0, addr);
1124 }
1125}
1126
1127/**
1128 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1129 *
1130 */
1131static void
1132init_cr_idx_adr_latch(struct nvbios_init *init)
1133{
d390b480 1134 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1135 u8 addr0 = nv_ro08(bios, init->offset + 1);
1136 u8 addr1 = nv_ro08(bios, init->offset + 2);
1137 u8 base = nv_ro08(bios, init->offset + 3);
1138 u8 count = nv_ro08(bios, init->offset + 4);
1139 u8 save0;
1140
1141 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1142 init->offset += 5;
1143
1144 save0 = init_rdvgai(init, 0x03d4, addr0);
1145 while (count--) {
1146 u8 data = nv_ro08(bios, init->offset);
1147
1148 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1149 init->offset += 1;
1150
1151 init_wrvgai(init, 0x03d4, addr0, base++);
1152 init_wrvgai(init, 0x03d4, addr1, data);
1153 }
1154 init_wrvgai(init, 0x03d4, addr0, save0);
1155}
1156
1157/**
1158 * INIT_CR - opcode 0x52
1159 *
1160 */
1161static void
1162init_cr(struct nvbios_init *init)
1163{
d390b480 1164 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1165 u8 addr = nv_ro08(bios, init->offset + 1);
1166 u8 mask = nv_ro08(bios, init->offset + 2);
1167 u8 data = nv_ro08(bios, init->offset + 3);
1168 u8 val;
1169
1170 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1171 init->offset += 4;
1172
1173 val = init_rdvgai(init, 0x03d4, addr) & mask;
1174 init_wrvgai(init, 0x03d4, addr, val | data);
1175}
1176
1177/**
1178 * INIT_ZM_CR - opcode 0x53
1179 *
1180 */
1181static void
1182init_zm_cr(struct nvbios_init *init)
1183{
d390b480 1184 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1185 u8 addr = nv_ro08(bios, init->offset + 1);
1186 u8 data = nv_ro08(bios, init->offset + 2);
1187
1188 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1189 init->offset += 3;
1190
1191 init_wrvgai(init, 0x03d4, addr, data);
1192}
1193
1194/**
1195 * INIT_ZM_CR_GROUP - opcode 0x54
1196 *
1197 */
1198static void
1199init_zm_cr_group(struct nvbios_init *init)
1200{
d390b480 1201 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1202 u8 count = nv_ro08(bios, init->offset + 1);
1203
1204 trace("ZM_CR_GROUP\n");
1205 init->offset += 2;
1206
1207 while (count--) {
1208 u8 addr = nv_ro08(bios, init->offset + 0);
1209 u8 data = nv_ro08(bios, init->offset + 1);
1210
1211 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1212 init->offset += 2;
1213
1214 init_wrvgai(init, 0x03d4, addr, data);
1215 }
1216}
1217
1218/**
1219 * INIT_CONDITION_TIME - opcode 0x56
1220 *
1221 */
1222static void
1223init_condition_time(struct nvbios_init *init)
1224{
d390b480 1225 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1226 u8 cond = nv_ro08(bios, init->offset + 1);
1227 u8 retry = nv_ro08(bios, init->offset + 2);
1228 u8 wait = min((u16)retry * 50, 100);
1229
1230 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1231 init->offset += 3;
1232
1233 if (!init_exec(init))
1234 return;
1235
1236 while (wait--) {
1237 if (init_condition_met(init, cond))
1238 return;
1239 mdelay(20);
1240 }
1241
1242 init_exec_set(init, false);
1243}
1244
1245/**
1246 * INIT_LTIME - opcode 0x57
1247 *
1248 */
1249static void
1250init_ltime(struct nvbios_init *init)
1251{
d390b480 1252 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1253 u16 msec = nv_ro16(bios, init->offset + 1);
1254
1255 trace("LTIME\t0x%04x\n", msec);
1256 init->offset += 3;
1257
1258 if (init_exec(init))
1259 mdelay(msec);
1260}
1261
1262/**
1263 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1264 *
1265 */
1266static void
1267init_zm_reg_sequence(struct nvbios_init *init)
1268{
d390b480 1269 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1270 u32 base = nv_ro32(bios, init->offset + 1);
1271 u8 count = nv_ro08(bios, init->offset + 5);
1272
1273 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1274 init->offset += 6;
1275
1276 while (count--) {
1277 u32 data = nv_ro32(bios, init->offset);
1278
1279 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1280 init->offset += 4;
1281
1282 init_wr32(init, base, data);
1283 base += 4;
1284 }
1285}
1286
d31b11d8
IM		 1287/**
1288 * INIT_PLL_INDIRECT - opcode 0x59
1289 *
1290 */
1291static void
1292init_pll_indirect(struct nvbios_init *init)
1293{
1294 struct nvkm_bios *bios = init->bios;
1295 u32 reg = nv_ro32(bios, init->offset + 1);
1296 u16 addr = nv_ro16(bios, init->offset + 5);
1297 u32 freq = (u32)nv_ro16(bios, addr) * 1000;
1298
1299 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n",
1300 reg, addr, freq);
1301 init->offset += 7;
1302
1303 init_prog_pll(init, reg, freq);
1304}
1305
360ccb84
IM		 1306/**
1307 * INIT_ZM_REG_INDIRECT - opcode 0x5a
1308 *
1309 */
1310static void
1311init_zm_reg_indirect(struct nvbios_init *init)
1312{
1313 struct nvkm_bios *bios = init->bios;
1314 u32 reg = nv_ro32(bios, init->offset + 1);
1315 u16 addr = nv_ro16(bios, init->offset + 5);
1316 u32 data = nv_ro32(bios, addr);
1317
1318 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n",
1319 reg, addr, data);
1320 init->offset += 7;
1321
1322 init_wr32(init, addr, data);
1323}
1324
cb75d97e
BS		 1325/**
1326 * INIT_SUB_DIRECT - opcode 0x5b
1327 *
1328 */
1329static void
1330init_sub_direct(struct nvbios_init *init)
1331{
d390b480 1332 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1333 u16 addr = nv_ro16(bios, init->offset + 1);
1334 u16 save;
1335
1336 trace("SUB_DIRECT\t0x%04x\n", addr);
1337
1338 if (init_exec(init)) {
1339 save = init->offset;
1340 init->offset = addr;
1341 if (nvbios_exec(init)) {
1342 error("error parsing sub-table\n");
1343 return;
1344 }
1345 init->offset = save;
1346 }
1347
1348 init->offset += 3;
1349}
1350
1351/**
1352 * INIT_JUMP - opcode 0x5c
1353 *
1354 */
1355static void
1356init_jump(struct nvbios_init *init)
1357{
d390b480 1358 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1359 u16 offset = nv_ro16(bios, init->offset + 1);
1360
1361 trace("JUMP\t0x%04x\n", offset);
6d60792e
IM		 1362
1363 if (init_exec(init))
1364 init->offset = offset;
1365 else
1366 init->offset += 3;
cb75d97e
BS		 1367}
1368
1369/**
1370 * INIT_I2C_IF - opcode 0x5e
1371 *
1372 */
1373static void
1374init_i2c_if(struct nvbios_init *init)
1375{
d390b480 1376 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1377 u8 index = nv_ro08(bios, init->offset + 1);
1378 u8 addr = nv_ro08(bios, init->offset + 2);
1379 u8 reg = nv_ro08(bios, init->offset + 3);
1380 u8 mask = nv_ro08(bios, init->offset + 4);
1381 u8 data = nv_ro08(bios, init->offset + 5);
1382 u8 value;
1383
1384 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1385 index, addr, reg, mask, data);
1386 init->offset += 6;
1387 init_exec_force(init, true);
1388
1389 value = init_rdi2cr(init, index, addr, reg);
1390 if ((value & mask) != data)
1391 init_exec_set(init, false);
1392
1393 init_exec_force(init, false);
1394}
1395
1396/**
1397 * INIT_COPY_NV_REG - opcode 0x5f
1398 *
1399 */
1400static void
1401init_copy_nv_reg(struct nvbios_init *init)
1402{
d390b480 1403 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1404 u32 sreg = nv_ro32(bios, init->offset + 1);
1405 u8 shift = nv_ro08(bios, init->offset + 5);
1406 u32 smask = nv_ro32(bios, init->offset + 6);
1407 u32 sxor = nv_ro32(bios, init->offset + 10);
1408 u32 dreg = nv_ro32(bios, init->offset + 14);
1409 u32 dmask = nv_ro32(bios, init->offset + 18);
1410 u32 data;
1411
1412 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1413 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1414 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1415 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1416 init->offset += 22;
1417
1418 data = init_shift(init_rd32(init, sreg), shift);
1419 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1420}
1421
1422/**
1423 * INIT_ZM_INDEX_IO - opcode 0x62
1424 *
1425 */
1426static void
1427init_zm_index_io(struct nvbios_init *init)
1428{
d390b480 1429 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1430 u16 port = nv_ro16(bios, init->offset + 1);
1431 u8 index = nv_ro08(bios, init->offset + 3);
1432 u8 data = nv_ro08(bios, init->offset + 4);
1433
1434 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1435 init->offset += 5;
1436
1437 init_wrvgai(init, port, index, data);
1438}
1439
1440/**
1441 * INIT_COMPUTE_MEM - opcode 0x63
1442 *
1443 */
1444static void
1445init_compute_mem(struct nvbios_init *init)
1446{
d390b480 1447 struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
cb75d97e
BS		 1448
1449 trace("COMPUTE_MEM\n");
1450 init->offset += 1;
1451
1452 init_exec_force(init, true);
1453 if (init_exec(init) && devinit->meminit)
1454 devinit->meminit(devinit);
1455 init_exec_force(init, false);
1456}
1457
1458/**
1459 * INIT_RESET - opcode 0x65
1460 *
1461 */
1462static void
1463init_reset(struct nvbios_init *init)
1464{
d390b480 1465 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1466 u32 reg = nv_ro32(bios, init->offset + 1);
1467 u32 data1 = nv_ro32(bios, init->offset + 5);
1468 u32 data2 = nv_ro32(bios, init->offset + 9);
1469 u32 savepci19;
1470
1471 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1472 init->offset += 13;
1473 init_exec_force(init, true);
1474
1475 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1476 init_wr32(init, reg, data1);
1477 udelay(10);
1478 init_wr32(init, reg, data2);
1479 init_wr32(init, 0x00184c, savepci19);
1480 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1481
1482 init_exec_force(init, false);
1483}
1484
1485/**
1486 * INIT_CONFIGURE_MEM - opcode 0x66
1487 *
1488 */
1489static u16
1490init_configure_mem_clk(struct nvbios_init *init)
1491{
1492 u16 mdata = bmp_mem_init_table(init->bios);
1493 if (mdata)
1494 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1495 return mdata;
1496}
1497
1498static void
1499init_configure_mem(struct nvbios_init *init)
1500{
d390b480 1501 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1502 u16 mdata, sdata;
1503 u32 addr, data;
1504
1505 trace("CONFIGURE_MEM\n");
1506 init->offset += 1;
1507
1508 if (bios->version.major > 2) {
1509 init_done(init);
1510 return;
1511 }
1512 init_exec_force(init, true);
1513
1514 mdata = init_configure_mem_clk(init);
1515 sdata = bmp_sdr_seq_table(bios);
1516 if (nv_ro08(bios, mdata) & 0x01)
1517 sdata = bmp_ddr_seq_table(bios);
1518 mdata += 6; /* skip to data */
1519
1520 data = init_rdvgai(init, 0x03c4, 0x01);
1521 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1522
6b19e47d 1523 for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
cb75d97e
BS		 1524 switch (addr) {
1525 case 0x10021c: /* CKE_NORMAL */
1526 case 0x1002d0: /* CMD_REFRESH */
1527 case 0x1002d4: /* CMD_PRECHARGE */
1528 data = 0x00000001;
1529 break;
1530 default:
1531 data = nv_ro32(bios, mdata);
1532 mdata += 4;
1533 if (data == 0xffffffff)
1534 continue;
1535 break;
1536 }
1537
1538 init_wr32(init, addr, data);
1539 }
1540
1541 init_exec_force(init, false);
1542}
1543
1544/**
1545 * INIT_CONFIGURE_CLK - opcode 0x67
1546 *
1547 */
1548static void
1549init_configure_clk(struct nvbios_init *init)
1550{
d390b480 1551 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1552 u16 mdata, clock;
1553
1554 trace("CONFIGURE_CLK\n");
1555 init->offset += 1;
1556
1557 if (bios->version.major > 2) {
1558 init_done(init);
1559 return;
1560 }
1561 init_exec_force(init, true);
1562
1563 mdata = init_configure_mem_clk(init);
1564
1565 /* NVPLL */
1566 clock = nv_ro16(bios, mdata + 4) * 10;
1567 init_prog_pll(init, 0x680500, clock);
1568
1569 /* MPLL */
1570 clock = nv_ro16(bios, mdata + 2) * 10;
1571 if (nv_ro08(bios, mdata) & 0x01)
1572 clock *= 2;
1573 init_prog_pll(init, 0x680504, clock);
1574
1575 init_exec_force(init, false);
1576}
1577
1578/**
1579 * INIT_CONFIGURE_PREINIT - opcode 0x68
1580 *
1581 */
1582static void
1583init_configure_preinit(struct nvbios_init *init)
1584{
d390b480 1585 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1586 u32 strap;
1587
1588 trace("CONFIGURE_PREINIT\n");
1589 init->offset += 1;
1590
1591 if (bios->version.major > 2) {
1592 init_done(init);
1593 return;
1594 }
1595 init_exec_force(init, true);
1596
1597 strap = init_rd32(init, 0x101000);
1598 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1599 init_wrvgai(init, 0x03d4, 0x3c, strap);
1600
1601 init_exec_force(init, false);
1602}
1603
1604/**
1605 * INIT_IO - opcode 0x69
1606 *
1607 */
1608static void
1609init_io(struct nvbios_init *init)
1610{
d390b480 1611 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1612 u16 port = nv_ro16(bios, init->offset + 1);
1613 u8 mask = nv_ro16(bios, init->offset + 3);
1614 u8 data = nv_ro16(bios, init->offset + 4);
1615 u8 value;
1616
1617 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1618 init->offset += 5;
1619
1620 /* ummm.. yes.. should really figure out wtf this is and why it's
1621 * needed some day.. it's almost certainly wrong, but, it also
1622 * somehow makes things work...
1623 */
1624 if (nv_device(init->bios)->card_type >= NV_50 &&
1625 port == 0x03c3 && data == 0x01) {
1626 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1627 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1628 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1629 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1630 mdelay(10);
1631 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1632 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1633 init_wr32(init, 0x614100, 0x00800018);
1634 init_wr32(init, 0x614900, 0x00800018);
1635 mdelay(10);
1636 init_wr32(init, 0x614100, 0x10000018);
1637 init_wr32(init, 0x614900, 0x10000018);
cb75d97e
BS		 1638 }
1639
1640 value = init_rdport(init, port) & mask;
1641 init_wrport(init, port, data | value);
1642}
1643
1644/**
1645 * INIT_SUB - opcode 0x6b
1646 *
1647 */
1648static void
1649init_sub(struct nvbios_init *init)
1650{
d390b480 1651 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1652 u8 index = nv_ro08(bios, init->offset + 1);
1653 u16 addr, save;
1654
1655 trace("SUB\t0x%02x\n", index);
1656
1657 addr = init_script(bios, index);
1658 if (addr && init_exec(init)) {
1659 save = init->offset;
1660 init->offset = addr;
1661 if (nvbios_exec(init)) {
1662 error("error parsing sub-table\n");
1663 return;
1664 }
1665 init->offset = save;
1666 }
1667
1668 init->offset += 2;
1669}
1670
1671/**
1672 * INIT_RAM_CONDITION - opcode 0x6d
1673 *
1674 */
1675static void
1676init_ram_condition(struct nvbios_init *init)
1677{
d390b480 1678 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1679 u8 mask = nv_ro08(bios, init->offset + 1);
1680 u8 value = nv_ro08(bios, init->offset + 2);
1681
1682 trace("RAM_CONDITION\t"
1683 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1684 init->offset += 3;
1685
1686 if ((init_rd32(init, 0x100000) & mask) != value)
1687 init_exec_set(init, false);
1688}
1689
1690/**
1691 * INIT_NV_REG - opcode 0x6e
1692 *
1693 */
1694static void
1695init_nv_reg(struct nvbios_init *init)
1696{
d390b480 1697 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1698 u32 reg = nv_ro32(bios, init->offset + 1);
1699 u32 mask = nv_ro32(bios, init->offset + 5);
1700 u32 data = nv_ro32(bios, init->offset + 9);
1701
1702 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1703 init->offset += 13;
1704
1705 init_mask(init, reg, ~mask, data);
1706}
1707
1708/**
1709 * INIT_MACRO - opcode 0x6f
1710 *
1711 */
1712static void
1713init_macro(struct nvbios_init *init)
1714{
d390b480 1715 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1716 u8 macro = nv_ro08(bios, init->offset + 1);
1717 u16 table;
1718
1719 trace("MACRO\t0x%02x\n", macro);
1720
1721 table = init_macro_table(init);
1722 if (table) {
1723 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1724 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1725 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1726 init_wr32(init, addr, data);
1727 }
1728
1729 init->offset += 2;
1730}
1731
1732/**
1733 * INIT_RESUME - opcode 0x72
1734 *
1735 */
1736static void
1737init_resume(struct nvbios_init *init)
1738{
1739 trace("RESUME\n");
1740 init->offset += 1;
1741 init_exec_set(init, true);
1742}
1743
1744/**
1745 * INIT_TIME - opcode 0x74
1746 *
1747 */
1748static void
1749init_time(struct nvbios_init *init)
1750{
d390b480 1751 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1752 u16 usec = nv_ro16(bios, init->offset + 1);
1753
1754 trace("TIME\t0x%04x\n", usec);
1755 init->offset += 3;
1756
1757 if (init_exec(init)) {
1758 if (usec < 1000)
1759 udelay(usec);
1760 else
1761 mdelay((usec + 900) / 1000);
1762 }
1763}
1764
1765/**
1766 * INIT_CONDITION - opcode 0x75
1767 *
1768 */
1769static void
1770init_condition(struct nvbios_init *init)
1771{
d390b480 1772 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1773 u8 cond = nv_ro08(bios, init->offset + 1);
1774
1775 trace("CONDITION\t0x%02x\n", cond);
1776 init->offset += 2;
1777
1778 if (!init_condition_met(init, cond))
1779 init_exec_set(init, false);
1780}
1781
1782/**
1783 * INIT_IO_CONDITION - opcode 0x76
1784 *
1785 */
1786static void
1787init_io_condition(struct nvbios_init *init)
1788{
d390b480 1789 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1790 u8 cond = nv_ro08(bios, init->offset + 1);
1791
1792 trace("IO_CONDITION\t0x%02x\n", cond);
1793 init->offset += 2;
1794
1795 if (!init_io_condition_met(init, cond))
1796 init_exec_set(init, false);
1797}
1798
1799/**
1800 * INIT_INDEX_IO - opcode 0x78
1801 *
1802 */
1803static void
1804init_index_io(struct nvbios_init *init)
1805{
d390b480 1806 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1807 u16 port = nv_ro16(bios, init->offset + 1);
1808 u8 index = nv_ro16(bios, init->offset + 3);
1809 u8 mask = nv_ro08(bios, init->offset + 4);
1810 u8 data = nv_ro08(bios, init->offset + 5);
1811 u8 value;
1812
1813 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1814 port, index, mask, data);
1815 init->offset += 6;
1816
1817 value = init_rdvgai(init, port, index) & mask;
1818 init_wrvgai(init, port, index, data | value);
1819}
1820
1821/**
1822 * INIT_PLL - opcode 0x79
1823 *
1824 */
1825static void
1826init_pll(struct nvbios_init *init)
1827{
d390b480 1828 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1829 u32 reg = nv_ro32(bios, init->offset + 1);
1830 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1831
1832 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1833 init->offset += 7;
1834
1835 init_prog_pll(init, reg, freq);
1836}
1837
1838/**
1839 * INIT_ZM_REG - opcode 0x7a
1840 *
1841 */
1842static void
1843init_zm_reg(struct nvbios_init *init)
1844{
d390b480 1845 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1846 u32 addr = nv_ro32(bios, init->offset + 1);
1847 u32 data = nv_ro32(bios, init->offset + 5);
1848
1849 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1850 init->offset += 9;
1851
1852 if (addr == 0x000200)
1853 data |= 0x00000001;
1854
1855 init_wr32(init, addr, data);
1856}
1857
1858/**
1859 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1860 *
1861 */
1862static void
1863init_ram_restrict_pll(struct nvbios_init *init)
1864{
d390b480 1865 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1866 u8 type = nv_ro08(bios, init->offset + 1);
1867 u8 count = init_ram_restrict_group_count(init);
1868 u8 strap = init_ram_restrict(init);
1869 u8 cconf;
1870
1871 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1872 init->offset += 2;
1873
1874 for (cconf = 0; cconf < count; cconf++) {
1875 u32 freq = nv_ro32(bios, init->offset);
1876
1877 if (cconf == strap) {
1878 trace("%dkHz *\n", freq);
1879 init_prog_pll(init, type, freq);
1880 } else {
1881 trace("%dkHz\n", freq);
1882 }
1883
1884 init->offset += 4;
1885 }
1886}
1887
1888/**
1889 * INIT_GPIO - opcode 0x8e
1890 *
1891 */
1892static void
1893init_gpio(struct nvbios_init *init)
1894{
d390b480 1895 struct nvkm_gpio *gpio = nvkm_gpio(init->bios);
cb75d97e
BS		 1896
1897 trace("GPIO\n");
1898 init->offset += 1;
1899
1900 if (init_exec(init) && gpio && gpio->reset)
1ed73166 1901 gpio->reset(gpio, DCB_GPIO_UNUSED);
cb75d97e
BS		 1902}
1903
1904/**
1905 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1906 *
1907 */
1908static void
1909init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1910{
d390b480 1911 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1912 u32 addr = nv_ro32(bios, init->offset + 1);
1913 u8 incr = nv_ro08(bios, init->offset + 5);
1914 u8 num = nv_ro08(bios, init->offset + 6);
1915 u8 count = init_ram_restrict_group_count(init);
1916 u8 index = init_ram_restrict(init);
1917 u8 i, j;
1918
1919 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
bfd8bd1f 1920 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
cb75d97e
BS		 1921 init->offset += 7;
1922
1923 for (i = 0; i < num; i++) {
1924 trace("\tR[0x%06x] = {\n", addr);
1925 for (j = 0; j < count; j++) {
1926 u32 data = nv_ro32(bios, init->offset);
1927
1928 if (j == index) {
1929 trace("\t\t0x%08x *\n", data);
1930 init_wr32(init, addr, data);
1931 } else {
1932 trace("\t\t0x%08x\n", data);
1933 }
1934
1935 init->offset += 4;
1936 }
1937 trace("\t}\n");
1938 addr += incr;
1939 }
1940}
1941
1942/**
1943 * INIT_COPY_ZM_REG - opcode 0x90
1944 *
1945 */
1946static void
1947init_copy_zm_reg(struct nvbios_init *init)
1948{
d390b480 1949 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1950 u32 sreg = nv_ro32(bios, init->offset + 1);
1951 u32 dreg = nv_ro32(bios, init->offset + 5);
1952
bfd8bd1f 1953 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
cb75d97e
BS		 1954 init->offset += 9;
1955
1956 init_wr32(init, dreg, init_rd32(init, sreg));
1957}
1958
1959/**
1960 * INIT_ZM_REG_GROUP - opcode 0x91
1961 *
1962 */
1963static void
1964init_zm_reg_group(struct nvbios_init *init)
1965{
d390b480 1966 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1967 u32 addr = nv_ro32(bios, init->offset + 1);
1968 u8 count = nv_ro08(bios, init->offset + 5);
1969
950fbfab 1970 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
cb75d97e
BS		 1971 init->offset += 6;
1972
1973 while (count--) {
1974 u32 data = nv_ro32(bios, init->offset);
1975 trace("\t0x%08x\n", data);
1976 init_wr32(init, addr, data);
1977 init->offset += 4;
1978 }
1979}
1980
1981/**
1982 * INIT_XLAT - opcode 0x96
1983 *
1984 */
1985static void
1986init_xlat(struct nvbios_init *init)
1987{
d390b480 1988 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 1989 u32 saddr = nv_ro32(bios, init->offset + 1);
1990 u8 sshift = nv_ro08(bios, init->offset + 5);
1991 u8 smask = nv_ro08(bios, init->offset + 6);
1992 u8 index = nv_ro08(bios, init->offset + 7);
1993 u32 daddr = nv_ro32(bios, init->offset + 8);
1994 u32 dmask = nv_ro32(bios, init->offset + 12);
1995 u8 shift = nv_ro08(bios, init->offset + 16);
1996 u32 data;
1997
1998 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1999 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
2000 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
2001 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
2002 init->offset += 17;
2003
2004 data = init_shift(init_rd32(init, saddr), sshift) & smask;
2005 data = init_xlat_(init, index, data) << shift;
2006 init_mask(init, daddr, ~dmask, data);
2007}
2008
2009/**
2010 * INIT_ZM_MASK_ADD - opcode 0x97
2011 *
2012 */
2013static void
2014init_zm_mask_add(struct nvbios_init *init)
2015{
d390b480 2016 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 2017 u32 addr = nv_ro32(bios, init->offset + 1);
2018 u32 mask = nv_ro32(bios, init->offset + 5);
2019 u32 add = nv_ro32(bios, init->offset + 9);
2020 u32 data;
2021
2022 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
2023 init->offset += 13;
2024
46b47b8a
BS		 2025 data = init_rd32(init, addr);
2026 data = (data & mask) | ((data + add) & ~mask);
cb75d97e
BS		 2027 init_wr32(init, addr, data);
2028}
2029
2030/**
2031 * INIT_AUXCH - opcode 0x98
2032 *
2033 */
2034static void
2035init_auxch(struct nvbios_init *init)
2036{
d390b480 2037 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 2038 u32 addr = nv_ro32(bios, init->offset + 1);
2039 u8 count = nv_ro08(bios, init->offset + 5);
2040
2041 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2042 init->offset += 6;
2043
2044 while (count--) {
2045 u8 mask = nv_ro08(bios, init->offset + 0);
2046 u8 data = nv_ro08(bios, init->offset + 1);
2047 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
2048 mask = init_rdauxr(init, addr) & mask;
2049 init_wrauxr(init, addr, mask | data);
2050 init->offset += 2;
2051 }
2052}
2053
2054/**
2055 * INIT_AUXCH - opcode 0x99
2056 *
2057 */
2058static void
2059init_zm_auxch(struct nvbios_init *init)
2060{
d390b480 2061 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 2062 u32 addr = nv_ro32(bios, init->offset + 1);
2063 u8 count = nv_ro08(bios, init->offset + 5);
2064
2065 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2066 init->offset += 6;
2067
2068 while (count--) {
2069 u8 data = nv_ro08(bios, init->offset + 0);
2070 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
2071 init_wrauxr(init, addr, data);
2072 init->offset += 1;
2073 }
2074}
2075
2076/**
2077 * INIT_I2C_LONG_IF - opcode 0x9a
2078 *
2079 */
2080static void
2081init_i2c_long_if(struct nvbios_init *init)
2082{
d390b480 2083 struct nvkm_bios *bios = init->bios;
cb75d97e
BS		 2084 u8 index = nv_ro08(bios, init->offset + 1);
2085 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
2086 u8 reglo = nv_ro08(bios, init->offset + 3);
2087 u8 reghi = nv_ro08(bios, init->offset + 4);
2088 u8 mask = nv_ro08(bios, init->offset + 5);
2089 u8 data = nv_ro08(bios, init->offset + 6);
d390b480 2090 struct nvkm_i2c_port *port;
cb75d97e
BS		 2091
2092 trace("I2C_LONG_IF\t"
2093 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2094 index, addr, reglo, reghi, mask, data);
2095 init->offset += 7;
2096
2097 port = init_i2c(init, index);
2098 if (port) {
2099 u8 i[2] = { reghi, reglo };
2100 u8 o[1] = {};
2101 struct i2c_msg msg[] = {
2102 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2103 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2104 };
2105 int ret;
2106
2107 ret = i2c_transfer(&port->adapter, msg, 2);
2108 if (ret == 2 && ((o[0] & mask) == data))
2109 return;
2110 }
2111
2112 init_exec_set(init, false);
2113}
2114
1ed73166
BS		 2115/**
2116 * INIT_GPIO_NE - opcode 0xa9
2117 *
2118 */
2119static void
2120init_gpio_ne(struct nvbios_init *init)
2121{
d390b480
BS		 2122 struct nvkm_bios *bios = init->bios;
2123 struct nvkm_gpio *gpio = nvkm_gpio(bios);
1ed73166
BS		 2124 struct dcb_gpio_func func;
2125 u8 count = nv_ro08(bios, init->offset + 1);
2126 u8 idx = 0, ver, len;
2127 u16 data, i;
2128
2129 trace("GPIO_NE\t");
2130 init->offset += 2;
2131
2132 for (i = init->offset; i < init->offset + count; i++)
2133 cont("0x%02x ", nv_ro08(bios, i));
2134 cont("\n");
2135
2136 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2137 if (func.func != DCB_GPIO_UNUSED) {
2138 for (i = init->offset; i < init->offset + count; i++) {
2139 if (func.func == nv_ro08(bios, i))
2140 break;
2141 }
2142
2143 trace("\tFUNC[0x%02x]", func.func);
2144 if (i == (init->offset + count)) {
2145 cont(" *");
2146 if (init_exec(init) && gpio && gpio->reset)
2147 gpio->reset(gpio, func.func);
2148 }
2149 cont("\n");
2150 }
2151 }
2152
2153 init->offset += count;
2154}
2155
cb75d97e
BS		 2156static struct nvbios_init_opcode {
2157 void (*exec)(struct nvbios_init *);
2158} init_opcode[] = {
2159 [0x32] = { init_io_restrict_prog },
2160 [0x33] = { init_repeat },
2161 [0x34] = { init_io_restrict_pll },
2162 [0x36] = { init_end_repeat },
2163 [0x37] = { init_copy },
2164 [0x38] = { init_not },
2165 [0x39] = { init_io_flag_condition },
2166 [0x3a] = { init_dp_condition },
2167 [0x3b] = { init_io_mask_or },
2168 [0x3c] = { init_io_or },
c79965d8
BS		 2169 [0x47] = { init_andn_reg },
2170 [0x48] = { init_or_reg },
cb75d97e
BS		 2171 [0x49] = { init_idx_addr_latched },
2172 [0x4a] = { init_io_restrict_pll2 },
2173 [0x4b] = { init_pll2 },
2174 [0x4c] = { init_i2c_byte },
2175 [0x4d] = { init_zm_i2c_byte },
2176 [0x4e] = { init_zm_i2c },
2177 [0x4f] = { init_tmds },
2178 [0x50] = { init_zm_tmds_group },
2179 [0x51] = { init_cr_idx_adr_latch },
2180 [0x52] = { init_cr },
2181 [0x53] = { init_zm_cr },
2182 [0x54] = { init_zm_cr_group },
2183 [0x56] = { init_condition_time },
2184 [0x57] = { init_ltime },
2185 [0x58] = { init_zm_reg_sequence },
d31b11d8 2186 [0x59] = { init_pll_indirect },
360ccb84 2187 [0x5a] = { init_zm_reg_indirect },
cb75d97e
BS		 2188 [0x5b] = { init_sub_direct },
2189 [0x5c] = { init_jump },
2190 [0x5e] = { init_i2c_if },
2191 [0x5f] = { init_copy_nv_reg },
2192 [0x62] = { init_zm_index_io },
2193 [0x63] = { init_compute_mem },
2194 [0x65] = { init_reset },
2195 [0x66] = { init_configure_mem },
2196 [0x67] = { init_configure_clk },
2197 [0x68] = { init_configure_preinit },
2198 [0x69] = { init_io },
2199 [0x6b] = { init_sub },
2200 [0x6d] = { init_ram_condition },
2201 [0x6e] = { init_nv_reg },
2202 [0x6f] = { init_macro },
2203 [0x71] = { init_done },
2204 [0x72] = { init_resume },
2205 [0x74] = { init_time },
2206 [0x75] = { init_condition },
2207 [0x76] = { init_io_condition },
2208 [0x78] = { init_index_io },
2209 [0x79] = { init_pll },
2210 [0x7a] = { init_zm_reg },
2211 [0x87] = { init_ram_restrict_pll },
2212 [0x8c] = { init_reserved },
2213 [0x8d] = { init_reserved },
2214 [0x8e] = { init_gpio },
2215 [0x8f] = { init_ram_restrict_zm_reg_group },
2216 [0x90] = { init_copy_zm_reg },
2217 [0x91] = { init_zm_reg_group },
2218 [0x92] = { init_reserved },
2219 [0x96] = { init_xlat },
2220 [0x97] = { init_zm_mask_add },
2221 [0x98] = { init_auxch },
2222 [0x99] = { init_zm_auxch },
2223 [0x9a] = { init_i2c_long_if },
1ed73166 2224 [0xa9] = { init_gpio_ne },
5495e39f 2225 [0xaa] = { init_reserved },
cb75d97e
BS		 2226};
2227
2228#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2229
2230int
2231nvbios_exec(struct nvbios_init *init)
2232{
2233 init->nested++;
2234 while (init->offset) {
2235 u8 opcode = nv_ro08(init->bios, init->offset);
2236 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2237 error("unknown opcode 0x%02x\n", opcode);
2238 return -EINVAL;
2239 }
2240
2241 init_opcode[opcode].exec(init);
2242 }
2243 init->nested--;
2244 return 0;
2245}
2246
2247int
d390b480 2248nvbios_init(struct nvkm_subdev *subdev, bool execute)
cb75d97e 2249{
d390b480 2250 struct nvkm_bios *bios = nvkm_bios(subdev);
cb75d97e
BS		 2251 int ret = 0;
2252 int i = -1;
2253 u16 data;
2254
2255 if (execute)
c52f4fa6 2256 nv_info(bios, "running init tables\n");
cb75d97e
BS		 2257 while (!ret && (data = (init_script(bios, ++i)))) {
2258 struct nvbios_init init = {
2259 .subdev = subdev,
2260 .bios = bios,
2261 .offset = data,
2262 .outp = NULL,
2263 .crtc = -1,
2264 .execute = execute ? 1 : 0,
2265 };
2266
2267 ret = nvbios_exec(&init);
2268 }
2269
2270 /* the vbios parser will run this right after the normal init
2271 * tables, whereas the binary driver appears to run it later.
2272 */
2273 if (!ret && (data = init_unknown_script(bios))) {
2274 struct nvbios_init init = {
2275 .subdev = subdev,
2276 .bios = bios,
2277 .offset = data,
2278 .outp = NULL,
2279 .crtc = -1,
2280 .execute = execute ? 1 : 0,
2281 };
2282
2283 ret = nvbios_exec(&init);
2284 }
2285
3db0fdb4 2286 return ret;
cb75d97e 2287}
Linux 6.x block layer and io_uring tree(s)