drm/nouveau/kms/nv04-nv4x: move a bunch of pre-nv50 page flip code to dispnv04
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_drm.c
CommitLineData
94580299
BS
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
77145f1c 25#include <linux/console.h>
c5fd936e 26#include <linux/delay.h>
94580299
BS
27#include <linux/module.h>
28#include <linux/pci.h>
5addcf0a
DA
29#include <linux/pm_runtime.h>
30#include <linux/vga_switcheroo.h>
fdb751ef 31
ae95621b
MY
32#include <drm/drmP.h>
33#include <drm/drm_crtc_helper.h>
fdb751ef 34
ebb945a9 35#include <core/gpuobj.h>
c33e05a1 36#include <core/option.h>
7974dd1b
BS
37#include <core/pci.h>
38#include <core/tegra.h>
94580299 39
04b88677 40#include <nvif/driver.h>
a7cf0180 41#include <nvif/fifo.h>
37e1c45a 42#include <nvif/user.h>
04b88677 43
923bc416 44#include <nvif/class.h>
845f2725 45#include <nvif/cl0002.h>
8ed1730c 46#include <nvif/cla06f.h>
538b269b 47
4dc28134 48#include "nouveau_drv.h"
ebb945a9 49#include "nouveau_dma.h"
77145f1c
BS
50#include "nouveau_ttm.h"
51#include "nouveau_gem.h"
77145f1c 52#include "nouveau_vga.h"
8d021d71 53#include "nouveau_led.h"
b9ed919f 54#include "nouveau_hwmon.h"
77145f1c
BS
55#include "nouveau_acpi.h"
56#include "nouveau_bios.h"
57#include "nouveau_ioctl.h"
ebb945a9
BS
58#include "nouveau_abi16.h"
59#include "nouveau_fbcon.h"
60#include "nouveau_fence.h"
33b903e8 61#include "nouveau_debugfs.h"
27111a23 62#include "nouveau_usif.h"
703fa264 63#include "nouveau_connector.h"
055a65d5 64#include "nouveau_platform.h"
ebb945a9 65
94580299
BS
66MODULE_PARM_DESC(config, "option string to pass to driver core");
67static char *nouveau_config;
68module_param_named(config, nouveau_config, charp, 0400);
69
70MODULE_PARM_DESC(debug, "debug string to pass to driver core");
71static char *nouveau_debug;
72module_param_named(debug, nouveau_debug, charp, 0400);
73
ebb945a9
BS
74MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
75static int nouveau_noaccel = 0;
76module_param_named(noaccel, nouveau_noaccel, int, 0400);
77
9430738d
BS
78MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
79 "0 = disabled, 1 = enabled, 2 = headless)");
80int nouveau_modeset = -1;
77145f1c
BS
81module_param_named(modeset, nouveau_modeset, int, 0400);
82
eb493fbc
LP
83MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
84static int nouveau_atomic = 0;
85module_param_named(atomic, nouveau_atomic, int, 0400);
86
5addcf0a 87MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
321f5c5f 88static int nouveau_runtime_pm = -1;
5addcf0a
DA
89module_param_named(runpm, nouveau_runtime_pm, int, 0400);
90
915b4d11
DH
91static struct drm_driver driver_stub;
92static struct drm_driver driver_pci;
93static struct drm_driver driver_platform;
77145f1c 94
94580299 95static u64
420b9469 96nouveau_pci_name(struct pci_dev *pdev)
94580299
BS
97{
98 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
99 name |= pdev->bus->number << 16;
100 name |= PCI_SLOT(pdev->devfn) << 8;
101 return name | PCI_FUNC(pdev->devfn);
102}
103
420b9469
AC
104static u64
105nouveau_platform_name(struct platform_device *platformdev)
106{
107 return platformdev->id;
108}
109
110static u64
111nouveau_name(struct drm_device *dev)
112{
113 if (dev->pdev)
114 return nouveau_pci_name(dev->pdev);
115 else
76adb460 116 return nouveau_platform_name(to_platform_device(dev->dev));
420b9469
AC
117}
118
814a2324 119static inline bool
11e451e7 120nouveau_cli_work_ready(struct dma_fence *fence)
814a2324 121{
11e451e7
BS
122 if (!dma_fence_is_signaled(fence))
123 return false;
814a2324
BS
124 dma_fence_put(fence);
125 return true;
126}
127
128static void
11e451e7 129nouveau_cli_work(struct work_struct *w)
814a2324 130{
11e451e7 131 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
814a2324
BS
132 struct nouveau_cli_work *work, *wtmp;
133 mutex_lock(&cli->lock);
134 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
11e451e7 135 if (!work->fence || nouveau_cli_work_ready(work->fence)) {
814a2324
BS
136 list_del(&work->head);
137 work->func(work);
138 }
139 }
140 mutex_unlock(&cli->lock);
141}
142
143static void
144nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
145{
146 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
147 schedule_work(&work->cli->work);
148}
149
150void
151nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
152 struct nouveau_cli_work *work)
153{
154 work->fence = dma_fence_get(fence);
155 work->cli = cli;
156 mutex_lock(&cli->lock);
157 list_add_tail(&work->head, &cli->worker);
814a2324
BS
158 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
159 nouveau_cli_work_fence(fence, &work->cb);
b26a2319 160 mutex_unlock(&cli->lock);
814a2324
BS
161}
162
20d8a88e
BS
163static void
164nouveau_cli_fini(struct nouveau_cli *cli)
165{
11e451e7
BS
166 /* All our channels are dead now, which means all the fences they
167 * own are signalled, and all callback functions have been called.
168 *
169 * So, after flushing the workqueue, there should be nothing left.
170 */
171 flush_work(&cli->work);
172 WARN_ON(!list_empty(&cli->worker));
173
20d8a88e 174 usif_client_fini(cli);
24e8375b 175 nouveau_vmm_fini(&cli->vmm);
01670a79 176 nvif_mmu_fini(&cli->mmu);
1167c6bc 177 nvif_device_fini(&cli->device);
cb7e88e7 178 mutex_lock(&cli->drm->master.lock);
20d8a88e 179 nvif_client_fini(&cli->base);
cb7e88e7 180 mutex_unlock(&cli->drm->master.lock);
20d8a88e
BS
181}
182
94580299 183static int
20d8a88e
BS
184nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
185 struct nouveau_cli *cli)
94580299 186{
7f507624
BS
187 static const struct nvif_mclass
188 mems[] = {
189 { NVIF_CLASS_MEM_GF100, -1 },
190 { NVIF_CLASS_MEM_NV50 , -1 },
191 { NVIF_CLASS_MEM_NV04 , -1 },
192 {}
193 };
01670a79
BS
194 static const struct nvif_mclass
195 mmus[] = {
196 { NVIF_CLASS_MMU_GF100, -1 },
197 { NVIF_CLASS_MMU_NV50 , -1 },
198 { NVIF_CLASS_MMU_NV04 , -1 },
199 {}
200 };
96da0bcd
BS
201 static const struct nvif_mclass
202 vmms[] = {
203 { NVIF_CLASS_VMM_GP100, -1 },
204 { NVIF_CLASS_VMM_GM200, -1 },
205 { NVIF_CLASS_VMM_GF100, -1 },
206 { NVIF_CLASS_VMM_NV50 , -1 },
207 { NVIF_CLASS_VMM_NV04 , -1 },
208 {}
209 };
20d8a88e 210 u64 device = nouveau_name(drm->dev);
9ad97ede 211 int ret;
9ad97ede 212
20d8a88e 213 snprintf(cli->name, sizeof(cli->name), "%s", sname);
e75c091b 214 cli->drm = drm;
20d8a88e
BS
215 mutex_init(&cli->mutex);
216 usif_client_init(cli);
217
814a2324
BS
218 INIT_WORK(&cli->work, nouveau_cli_work);
219 INIT_LIST_HEAD(&cli->worker);
cb7e88e7
BS
220 mutex_init(&cli->lock);
221
222 if (cli == &drm->master) {
80e60973
BS
223 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
224 cli->name, device, &cli->base);
225 } else {
cb7e88e7
BS
226 mutex_lock(&drm->master.lock);
227 ret = nvif_client_init(&drm->master.base, cli->name, device,
9ad97ede 228 &cli->base);
cb7e88e7 229 mutex_unlock(&drm->master.lock);
dd5700ea 230 }
20d8a88e 231 if (ret) {
a43b16dd 232 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
20d8a88e 233 goto done;
dd5700ea 234 }
94580299 235
1167c6bc
BS
236 ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE,
237 &(struct nv_device_v0) {
238 .device = ~0,
239 }, sizeof(struct nv_device_v0),
240 &cli->device);
241 if (ret) {
a43b16dd 242 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
1167c6bc
BS
243 goto done;
244 }
245
01670a79
BS
246 ret = nvif_mclass(&cli->device.object, mmus);
247 if (ret < 0) {
a43b16dd 248 NV_PRINTK(err, cli, "No supported MMU class\n");
01670a79
BS
249 goto done;
250 }
251
252 ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu);
253 if (ret) {
a43b16dd 254 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
01670a79
BS
255 goto done;
256 }
257
96da0bcd
BS
258 ret = nvif_mclass(&cli->mmu.object, vmms);
259 if (ret < 0) {
a43b16dd 260 NV_PRINTK(err, cli, "No supported VMM class\n");
96da0bcd
BS
261 goto done;
262 }
263
264 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
265 if (ret) {
a43b16dd 266 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
96da0bcd
BS
267 goto done;
268 }
269
7f507624
BS
270 ret = nvif_mclass(&cli->mmu.object, mems);
271 if (ret < 0) {
a43b16dd 272 NV_PRINTK(err, cli, "No supported MEM class\n");
7f507624
BS
273 goto done;
274 }
275
276 cli->mem = &mems[ret];
7f507624 277 return 0;
20d8a88e
BS
278done:
279 if (ret)
280 nouveau_cli_fini(cli);
281 return ret;
94580299
BS
282}
283
ebb945a9
BS
284static void
285nouveau_accel_fini(struct nouveau_drm *drm)
286{
fbd58ebd 287 nouveau_channel_idle(drm->channel);
0ad72863 288 nvif_object_fini(&drm->ntfy);
f027f491 289 nvkm_gpuobj_del(&drm->notify);
0ad72863 290 nvif_object_fini(&drm->nvsw);
fbd58ebd
BS
291 nouveau_channel_del(&drm->channel);
292
293 nouveau_channel_idle(drm->cechan);
0ad72863 294 nvif_object_fini(&drm->ttm.copy);
fbd58ebd
BS
295 nouveau_channel_del(&drm->cechan);
296
ebb945a9
BS
297 if (drm->fence)
298 nouveau_fence(drm)->dtor(drm);
299}
300
301static void
302nouveau_accel_init(struct nouveau_drm *drm)
303{
1167c6bc 304 struct nvif_device *device = &drm->client.device;
41a63406 305 struct nvif_sclass *sclass;
49981046 306 u32 arg0, arg1;
41a63406 307 int ret, i, n;
ebb945a9 308
967e7bde 309 if (nouveau_noaccel)
ebb945a9
BS
310 return;
311
eb47db4f
BS
312 ret = nouveau_channels_init(drm);
313 if (ret)
314 return;
315
37e1c45a
BS
316 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
317 ret = nvif_user_init(device);
318 if (ret)
319 return;
320 }
321
ebb945a9 322 /* initialise synchronisation routines */
967e7bde
BS
323 /*XXX: this is crap, but the fence/channel stuff is a little
324 * backwards in some places. this will be fixed.
325 */
41a63406 326 ret = n = nvif_object_sclass_get(&device->object, &sclass);
967e7bde
BS
327 if (ret < 0)
328 return;
329
41a63406
BS
330 for (ret = -ENOSYS, i = 0; i < n; i++) {
331 switch (sclass[i].oclass) {
bbf8906b 332 case NV03_CHANNEL_DMA:
967e7bde
BS
333 ret = nv04_fence_create(drm);
334 break;
bbf8906b 335 case NV10_CHANNEL_DMA:
967e7bde
BS
336 ret = nv10_fence_create(drm);
337 break;
bbf8906b
BS
338 case NV17_CHANNEL_DMA:
339 case NV40_CHANNEL_DMA:
967e7bde
BS
340 ret = nv17_fence_create(drm);
341 break;
bbf8906b 342 case NV50_CHANNEL_GPFIFO:
967e7bde
BS
343 ret = nv50_fence_create(drm);
344 break;
bbf8906b 345 case G82_CHANNEL_GPFIFO:
967e7bde
BS
346 ret = nv84_fence_create(drm);
347 break;
bbf8906b
BS
348 case FERMI_CHANNEL_GPFIFO:
349 case KEPLER_CHANNEL_GPFIFO_A:
63f8c9b7 350 case KEPLER_CHANNEL_GPFIFO_B:
a1020afe 351 case MAXWELL_CHANNEL_GPFIFO_A:
e8ff9794 352 case PASCAL_CHANNEL_GPFIFO_A:
37e1c45a 353 case VOLTA_CHANNEL_GPFIFO_A:
641d0b30 354 case TURING_CHANNEL_GPFIFO_A:
967e7bde
BS
355 ret = nvc0_fence_create(drm);
356 break;
357 default:
358 break;
359 }
360 }
361
41a63406 362 nvif_object_sclass_put(&sclass);
ebb945a9
BS
363 if (ret) {
364 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
365 nouveau_accel_fini(drm);
366 return;
367 }
368
967e7bde 369 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
1167c6bc 370 ret = nouveau_channel_new(drm, &drm->client.device,
a7cf0180 371 nvif_fifo_runlist_ce(device), 0,
85532bd9 372 true, &drm->cechan);
49981046
BS
373 if (ret)
374 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
375
a7cf0180 376 arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR);
49469800 377 arg1 = 1;
00fc6f6f 378 } else
967e7bde
BS
379 if (device->info.chipset >= 0xa3 &&
380 device->info.chipset != 0xaa &&
381 device->info.chipset != 0xac) {
1167c6bc 382 ret = nouveau_channel_new(drm, &drm->client.device,
85532bd9
BS
383 NvDmaFB, NvDmaTT, false,
384 &drm->cechan);
00fc6f6f
BS
385 if (ret)
386 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
387
388 arg0 = NvDmaFB;
389 arg1 = NvDmaTT;
49981046
BS
390 } else {
391 arg0 = NvDmaFB;
392 arg1 = NvDmaTT;
393 }
394
1167c6bc 395 ret = nouveau_channel_new(drm, &drm->client.device,
85532bd9 396 arg0, arg1, false, &drm->channel);
ebb945a9
BS
397 if (ret) {
398 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
399 nouveau_accel_fini(drm);
400 return;
401 }
402
512fa0b8
BS
403 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
404 ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW,
405 nouveau_abi16_swclass(drm), NULL, 0,
406 &drm->nvsw);
69a6146d 407 if (ret == 0) {
512fa0b8
BS
408 ret = RING_SPACE(drm->channel, 2);
409 if (ret == 0) {
69a6146d 410 BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
512fa0b8
BS
411 OUT_RING (drm->channel, drm->nvsw.handle);
412 }
69a6146d 413 }
898a2b32 414
898a2b32 415 if (ret) {
512fa0b8 416 NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
898a2b32
BS
417 nouveau_accel_fini(drm);
418 return;
419 }
69a6146d
BS
420 }
421
967e7bde 422 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
1167c6bc
BS
423 ret = nvkm_gpuobj_new(nvxx_device(&drm->client.device), 32, 0,
424 false, NULL, &drm->notify);
ebb945a9
BS
425 if (ret) {
426 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
427 nouveau_accel_fini(drm);
428 return;
429 }
430
a01ca78c 431 ret = nvif_object_init(&drm->channel->user, NvNotify0,
4acfd707
BS
432 NV_DMA_IN_MEMORY,
433 &(struct nv_dma_v0) {
434 .target = NV_DMA_V0_TARGET_VRAM,
435 .access = NV_DMA_V0_ACCESS_RDWR,
ebb945a9
BS
436 .start = drm->notify->addr,
437 .limit = drm->notify->addr + 31
4acfd707 438 }, sizeof(struct nv_dma_v0),
0ad72863 439 &drm->ntfy);
ebb945a9
BS
440 if (ret) {
441 nouveau_accel_fini(drm);
442 return;
443 }
444 }
445
446
49981046 447 nouveau_bo_move_init(drm);
ebb945a9
BS
448}
449
5b8a43ae 450static int
cfea88a4 451nouveau_drm_device_init(struct drm_device *dev)
94580299 452{
94580299
BS
453 struct nouveau_drm *drm;
454 int ret;
455
20d8a88e
BS
456 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
457 return -ENOMEM;
458 dev->dev_private = drm;
459 drm->dev = dev;
460
cb7e88e7
BS
461 ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
462 if (ret)
c4cee69a 463 goto fail_alloc;
cb7e88e7 464
20d8a88e 465 ret = nouveau_cli_init(drm, "DRM", &drm->client);
94580299 466 if (ret)
c4cee69a 467 goto fail_master;
94580299 468
1167c6bc
BS
469 dev->irq_enabled = true;
470
989aa5b7 471 nvxx_client(&drm->client.base)->debug =
be83cd4e 472 nvkm_dbgopt(nouveau_debug, "DRM");
77145f1c 473
94580299 474 INIT_LIST_HEAD(&drm->clients);
ebb945a9 475 spin_lock_init(&drm->tile.lock);
94580299 476
77145f1c
BS
477 /* workaround an odd issue on nvc1 by disabling the device's
478 * nosnoop capability. hopefully won't cause issues until a
479 * better fix is found - assuming there is one...
480 */
1167c6bc
BS
481 if (drm->client.device.info.chipset == 0xc1)
482 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
ebb945a9 483
77145f1c 484 nouveau_vga_init(drm);
cb75d97e 485
ebb945a9 486 ret = nouveau_ttm_init(drm);
94580299 487 if (ret)
77145f1c
BS
488 goto fail_ttm;
489
490 ret = nouveau_bios_init(dev);
491 if (ret)
492 goto fail_bios;
493
d7f9bb65
BS
494 nouveau_accel_init(drm);
495
77145f1c 496 ret = nouveau_display_create(dev);
ebb945a9 497 if (ret)
77145f1c
BS
498 goto fail_dispctor;
499
500 if (dev->mode_config.num_crtc) {
501 ret = nouveau_display_init(dev);
502 if (ret)
503 goto fail_dispinit;
504 }
505
b126a200 506 nouveau_debugfs_init(drm);
b9ed919f 507 nouveau_hwmon_init(dev);
ebb945a9 508 nouveau_fbcon_init(dev);
8d021d71 509 nouveau_led_init(dev);
5addcf0a 510
8fa4338a 511 if (nouveau_pmops_runtime()) {
5addcf0a
DA
512 pm_runtime_use_autosuspend(dev->dev);
513 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
514 pm_runtime_set_active(dev->dev);
515 pm_runtime_allow(dev->dev);
516 pm_runtime_mark_last_busy(dev->dev);
517 pm_runtime_put(dev->dev);
518 }
7326ead9 519
94580299
BS
520 return 0;
521
77145f1c
BS
522fail_dispinit:
523 nouveau_display_destroy(dev);
524fail_dispctor:
d7f9bb65 525 nouveau_accel_fini(drm);
77145f1c
BS
526 nouveau_bios_takedown(dev);
527fail_bios:
ebb945a9 528 nouveau_ttm_fini(drm);
77145f1c 529fail_ttm:
77145f1c 530 nouveau_vga_fini(drm);
20d8a88e 531 nouveau_cli_fini(&drm->client);
c4cee69a 532fail_master:
cb7e88e7 533 nouveau_cli_fini(&drm->master);
c4cee69a 534fail_alloc:
20d8a88e 535 kfree(drm);
94580299
BS
536 return ret;
537}
538
11b3c20b 539static void
cfea88a4 540nouveau_drm_device_fini(struct drm_device *dev)
94580299 541{
77145f1c 542 struct nouveau_drm *drm = nouveau_drm(dev);
94580299 543
8fa4338a 544 if (nouveau_pmops_runtime()) {
c1b16b45 545 pm_runtime_get_sync(dev->dev);
55c868a3 546 pm_runtime_forbid(dev->dev);
c1b16b45
LW
547 }
548
8d021d71 549 nouveau_led_fini(dev);
ebb945a9 550 nouveau_fbcon_fini(dev);
b9ed919f 551 nouveau_hwmon_fini(dev);
b126a200 552 nouveau_debugfs_fini(drm);
77145f1c 553
9430738d 554 if (dev->mode_config.num_crtc)
2f7ca781 555 nouveau_display_fini(dev, false, false);
77145f1c
BS
556 nouveau_display_destroy(dev);
557
d7f9bb65 558 nouveau_accel_fini(drm);
77145f1c 559 nouveau_bios_takedown(dev);
94580299 560
ebb945a9 561 nouveau_ttm_fini(drm);
77145f1c 562 nouveau_vga_fini(drm);
cb75d97e 563
20d8a88e 564 nouveau_cli_fini(&drm->client);
cb7e88e7 565 nouveau_cli_fini(&drm->master);
20d8a88e 566 kfree(drm);
94580299
BS
567}
568
cfea88a4
LP
569static int nouveau_drm_probe(struct pci_dev *pdev,
570 const struct pci_device_id *pent)
571{
572 struct nvkm_device *device;
573 struct drm_device *drm_dev;
574 struct apertures_struct *aper;
575 bool boot = false;
576 int ret;
577
578 if (vga_switcheroo_client_probe_defer(pdev))
579 return -EPROBE_DEFER;
580
581 /* We need to check that the chipset is supported before booting
582 * fbdev off the hardware, as there's no way to put it back.
583 */
584 ret = nvkm_device_pci_new(pdev, NULL, "error", true, false, 0, &device);
585 if (ret)
586 return ret;
587
588 nvkm_device_del(&device);
589
590 /* Remove conflicting drivers (vesafb, efifb etc). */
591 aper = alloc_apertures(3);
592 if (!aper)
593 return -ENOMEM;
594
595 aper->ranges[0].base = pci_resource_start(pdev, 1);
596 aper->ranges[0].size = pci_resource_len(pdev, 1);
597 aper->count = 1;
598
599 if (pci_resource_len(pdev, 2)) {
600 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
601 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
602 aper->count++;
603 }
604
605 if (pci_resource_len(pdev, 3)) {
606 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
607 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
608 aper->count++;
609 }
610
611#ifdef CONFIG_X86
612 boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
613#endif
614 if (nouveau_modeset != 2)
615 drm_fb_helper_remove_conflicting_framebuffers(aper, "nouveaufb", boot);
616 kfree(aper);
617
618 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
619 true, true, ~0ULL, &device);
620 if (ret)
621 return ret;
622
623 pci_set_master(pdev);
624
625 if (nouveau_atomic)
626 driver_pci.driver_features |= DRIVER_ATOMIC;
627
628 drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev);
629 if (IS_ERR(drm_dev)) {
630 ret = PTR_ERR(drm_dev);
631 goto fail_nvkm;
632 }
633
634 ret = pci_enable_device(pdev);
635 if (ret)
636 goto fail_drm;
637
638 drm_dev->pdev = pdev;
639 pci_set_drvdata(pdev, drm_dev);
640
641 ret = nouveau_drm_device_init(drm_dev);
642 if (ret)
643 goto fail_pci;
644
645 ret = drm_dev_register(drm_dev, pent->driver_data);
646 if (ret)
647 goto fail_drm_dev_init;
648
649 return 0;
650
651fail_drm_dev_init:
652 nouveau_drm_device_fini(drm_dev);
653fail_pci:
654 pci_disable_device(pdev);
655fail_drm:
656 drm_dev_put(drm_dev);
657fail_nvkm:
658 nvkm_device_del(&device);
659 return ret;
660}
661
8ba9ff11
AC
662void
663nouveau_drm_device_remove(struct drm_device *dev)
94580299 664{
cfea88a4 665 struct pci_dev *pdev = dev->pdev;
77145f1c 666 struct nouveau_drm *drm = nouveau_drm(dev);
be83cd4e 667 struct nvkm_client *client;
76ecea5b 668 struct nvkm_device *device;
77145f1c 669
cfea88a4
LP
670 drm_dev_unregister(dev);
671
7d3428cd 672 dev->irq_enabled = false;
989aa5b7 673 client = nvxx_client(&drm->client.base);
4e7e62d6 674 device = nvkm_device_find(client->device);
77145f1c 675
cfea88a4
LP
676 nouveau_drm_device_fini(dev);
677 pci_disable_device(pdev);
678 drm_dev_put(dev);
e781dc8f 679 nvkm_device_del(&device);
94580299 680}
8ba9ff11
AC
681
682static void
683nouveau_drm_remove(struct pci_dev *pdev)
684{
685 struct drm_device *dev = pci_get_drvdata(pdev);
686
687 nouveau_drm_device_remove(dev);
688}
94580299 689
cd897837 690static int
05c63c2f 691nouveau_do_suspend(struct drm_device *dev, bool runtime)
94580299 692{
77145f1c 693 struct nouveau_drm *drm = nouveau_drm(dev);
94580299
BS
694 int ret;
695
8d021d71
MP
696 nouveau_led_suspend(dev);
697
6fbb702e 698 if (dev->mode_config.num_crtc) {
2d38a535 699 NV_DEBUG(drm, "suspending console...\n");
6fbb702e 700 nouveau_fbcon_set_suspend(dev, 1);
2d38a535 701 NV_DEBUG(drm, "suspending display...\n");
6fbb702e 702 ret = nouveau_display_suspend(dev, runtime);
9430738d
BS
703 if (ret)
704 return ret;
705 }
94580299 706
2d38a535 707 NV_DEBUG(drm, "evicting buffers...\n");
ebb945a9
BS
708 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
709
2d38a535 710 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
81dff21b
BS
711 if (drm->cechan) {
712 ret = nouveau_channel_idle(drm->cechan);
713 if (ret)
f3980dc5 714 goto fail_display;
81dff21b
BS
715 }
716
717 if (drm->channel) {
718 ret = nouveau_channel_idle(drm->channel);
719 if (ret)
f3980dc5 720 goto fail_display;
81dff21b
BS
721 }
722
2d38a535 723 NV_DEBUG(drm, "suspending fence...\n");
ebb945a9 724 if (drm->fence && nouveau_fence(drm)->suspend) {
f3980dc5
IM
725 if (!nouveau_fence(drm)->suspend(drm)) {
726 ret = -ENOMEM;
727 goto fail_display;
728 }
ebb945a9
BS
729 }
730
2d38a535 731 NV_DEBUG(drm, "suspending object tree...\n");
cb7e88e7 732 ret = nvif_client_suspend(&drm->master.base);
94580299
BS
733 if (ret)
734 goto fail_client;
735
94580299
BS
736 return 0;
737
738fail_client:
f3980dc5
IM
739 if (drm->fence && nouveau_fence(drm)->resume)
740 nouveau_fence(drm)->resume(drm);
741
742fail_display:
9430738d 743 if (dev->mode_config.num_crtc) {
2d38a535 744 NV_DEBUG(drm, "resuming display...\n");
6fbb702e 745 nouveau_display_resume(dev, runtime);
9430738d 746 }
94580299
BS
747 return ret;
748}
749
cd897837 750static int
6fbb702e 751nouveau_do_resume(struct drm_device *dev, bool runtime)
2d8b9ccb
DA
752{
753 struct nouveau_drm *drm = nouveau_drm(dev);
2d8b9ccb 754
2d38a535 755 NV_DEBUG(drm, "resuming object tree...\n");
cb7e88e7 756 nvif_client_resume(&drm->master.base);
94580299 757
2d38a535 758 NV_DEBUG(drm, "resuming fence...\n");
81dff21b
BS
759 if (drm->fence && nouveau_fence(drm)->resume)
760 nouveau_fence(drm)->resume(drm);
761
77145f1c 762 nouveau_run_vbios_init(dev);
77145f1c 763
9430738d 764 if (dev->mode_config.num_crtc) {
2d38a535 765 NV_DEBUG(drm, "resuming display...\n");
6fbb702e 766 nouveau_display_resume(dev, runtime);
2d38a535 767 NV_DEBUG(drm, "resuming console...\n");
6fbb702e 768 nouveau_fbcon_set_suspend(dev, 0);
9430738d 769 }
5addcf0a 770
8d021d71
MP
771 nouveau_led_resume(dev);
772
77145f1c 773 return 0;
94580299
BS
774}
775
7bb6d442
BS
776int
777nouveau_pmops_suspend(struct device *dev)
778{
779 struct pci_dev *pdev = to_pci_dev(dev);
780 struct drm_device *drm_dev = pci_get_drvdata(pdev);
781 int ret;
782
783 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
784 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
785 return 0;
786
787 ret = nouveau_do_suspend(drm_dev, false);
788 if (ret)
789 return ret;
790
791 pci_save_state(pdev);
792 pci_disable_device(pdev);
7bb6d442 793 pci_set_power_state(pdev, PCI_D3hot);
c5fd936e 794 udelay(200);
7bb6d442
BS
795 return 0;
796}
797
798int
799nouveau_pmops_resume(struct device *dev)
2d8b9ccb
DA
800{
801 struct pci_dev *pdev = to_pci_dev(dev);
802 struct drm_device *drm_dev = pci_get_drvdata(pdev);
803 int ret;
804
5addcf0a
DA
805 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
806 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
2d8b9ccb
DA
807 return 0;
808
809 pci_set_power_state(pdev, PCI_D0);
810 pci_restore_state(pdev);
811 ret = pci_enable_device(pdev);
812 if (ret)
813 return ret;
814 pci_set_master(pdev);
815
0b2fe659
HG
816 ret = nouveau_do_resume(drm_dev, false);
817
818 /* Monitors may have been connected / disconnected during suspend */
819 schedule_work(&nouveau_drm(drm_dev)->hpd_work);
820
821 return ret;
2d8b9ccb
DA
822}
823
7bb6d442
BS
824static int
825nouveau_pmops_freeze(struct device *dev)
2d8b9ccb
DA
826{
827 struct pci_dev *pdev = to_pci_dev(dev);
828 struct drm_device *drm_dev = pci_get_drvdata(pdev);
6fbb702e 829 return nouveau_do_suspend(drm_dev, false);
2d8b9ccb
DA
830}
831
7bb6d442
BS
832static int
833nouveau_pmops_thaw(struct device *dev)
2d8b9ccb
DA
834{
835 struct pci_dev *pdev = to_pci_dev(dev);
836 struct drm_device *drm_dev = pci_get_drvdata(pdev);
6fbb702e 837 return nouveau_do_resume(drm_dev, false);
2d8b9ccb
DA
838}
839
321f5c5f 840bool
5499473c 841nouveau_pmops_runtime(void)
321f5c5f
BS
842{
843 if (nouveau_runtime_pm == -1)
844 return nouveau_is_optimus() || nouveau_is_v1_dsm();
845 return nouveau_runtime_pm == 1;
846}
847
7bb6d442
BS
848static int
849nouveau_pmops_runtime_suspend(struct device *dev)
850{
851 struct pci_dev *pdev = to_pci_dev(dev);
852 struct drm_device *drm_dev = pci_get_drvdata(pdev);
853 int ret;
854
321f5c5f 855 if (!nouveau_pmops_runtime()) {
7bb6d442
BS
856 pm_runtime_forbid(dev);
857 return -EBUSY;
858 }
859
7bb6d442
BS
860 nouveau_switcheroo_optimus_dsm();
861 ret = nouveau_do_suspend(drm_dev, true);
862 pci_save_state(pdev);
863 pci_disable_device(pdev);
8c863944 864 pci_ignore_hotplug(pdev);
7bb6d442
BS
865 pci_set_power_state(pdev, PCI_D3cold);
866 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
867 return ret;
868}
869
870static int
871nouveau_pmops_runtime_resume(struct device *dev)
872{
873 struct pci_dev *pdev = to_pci_dev(dev);
874 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1167c6bc 875 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
7bb6d442
BS
876 int ret;
877
321f5c5f
BS
878 if (!nouveau_pmops_runtime()) {
879 pm_runtime_forbid(dev);
880 return -EBUSY;
881 }
7bb6d442
BS
882
883 pci_set_power_state(pdev, PCI_D0);
884 pci_restore_state(pdev);
885 ret = pci_enable_device(pdev);
886 if (ret)
887 return ret;
888 pci_set_master(pdev);
889
890 ret = nouveau_do_resume(drm_dev, true);
cae9ff03 891
7bb6d442 892 /* do magic */
a01ca78c 893 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
7bb6d442 894 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
0b2fe659
HG
895
896 /* Monitors may have been connected / disconnected during suspend */
897 schedule_work(&nouveau_drm(drm_dev)->hpd_work);
898
7bb6d442
BS
899 return ret;
900}
901
902static int
903nouveau_pmops_runtime_idle(struct device *dev)
904{
321f5c5f 905 if (!nouveau_pmops_runtime()) {
7bb6d442
BS
906 pm_runtime_forbid(dev);
907 return -EBUSY;
908 }
909
7bb6d442
BS
910 pm_runtime_mark_last_busy(dev);
911 pm_runtime_autosuspend(dev);
912 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
913 return 1;
914}
2d8b9ccb 915
5b8a43ae 916static int
ebb945a9
BS
917nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
918{
ebb945a9
BS
919 struct nouveau_drm *drm = nouveau_drm(dev);
920 struct nouveau_cli *cli;
a2896ced 921 char name[32], tmpname[TASK_COMM_LEN];
ebb945a9
BS
922 int ret;
923
5addcf0a
DA
924 /* need to bring up power immediately if opening device */
925 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 926 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
927 return ret;
928
a2896ced
MS
929 get_task_comm(tmpname, current);
930 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
fa6df8c1 931
922a8c82
LP
932 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
933 ret = -ENOMEM;
934 goto done;
935 }
420b9469 936
20d8a88e 937 ret = nouveau_cli_init(drm, name, cli);
ebb945a9 938 if (ret)
20d8a88e 939 goto done;
ebb945a9 940
0ad72863
BS
941 cli->base.super = false;
942
ebb945a9
BS
943 fpriv->driver_priv = cli;
944
945 mutex_lock(&drm->client.mutex);
946 list_add(&cli->head, &drm->clients);
947 mutex_unlock(&drm->client.mutex);
5addcf0a 948
20d8a88e
BS
949done:
950 if (ret && cli) {
951 nouveau_cli_fini(cli);
952 kfree(cli);
953 }
954
5addcf0a
DA
955 pm_runtime_mark_last_busy(dev->dev);
956 pm_runtime_put_autosuspend(dev->dev);
5addcf0a 957 return ret;
ebb945a9
BS
958}
959
5b8a43ae 960static void
f0e73ff3 961nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
ebb945a9
BS
962{
963 struct nouveau_cli *cli = nouveau_cli(fpriv);
964 struct nouveau_drm *drm = nouveau_drm(dev);
965
5addcf0a
DA
966 pm_runtime_get_sync(dev->dev);
967
ac8c7930 968 mutex_lock(&cli->mutex);
ebb945a9
BS
969 if (cli->abi16)
970 nouveau_abi16_fini(cli->abi16);
ac8c7930 971 mutex_unlock(&cli->mutex);
ebb945a9
BS
972
973 mutex_lock(&drm->client.mutex);
974 list_del(&cli->head);
975 mutex_unlock(&drm->client.mutex);
5addcf0a 976
20d8a88e
BS
977 nouveau_cli_fini(cli);
978 kfree(cli);
5addcf0a
DA
979 pm_runtime_mark_last_busy(dev->dev);
980 pm_runtime_put_autosuspend(dev->dev);
ebb945a9
BS
981}
982
baa70943 983static const struct drm_ioctl_desc
77145f1c 984nouveau_ioctls[] = {
f8c47144
DV
985 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
986 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
987 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
988 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_AUTH|DRM_RENDER_ALLOW),
989 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
990 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
991 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_AUTH|DRM_RENDER_ALLOW),
992 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH|DRM_RENDER_ALLOW),
993 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH|DRM_RENDER_ALLOW),
994 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
995 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
996 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW),
77145f1c
BS
997};
998
27111a23
BS
999long
1000nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
5addcf0a 1001{
27111a23
BS
1002 struct drm_file *filp = file->private_data;
1003 struct drm_device *dev = filp->minor->dev;
5addcf0a 1004 long ret;
5addcf0a
DA
1005
1006 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 1007 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
1008 return ret;
1009
27111a23
BS
1010 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1011 case DRM_NOUVEAU_NVIF:
1012 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1013 break;
1014 default:
1015 ret = drm_ioctl(file, cmd, arg);
1016 break;
1017 }
5addcf0a
DA
1018
1019 pm_runtime_mark_last_busy(dev->dev);
1020 pm_runtime_put_autosuspend(dev->dev);
1021 return ret;
1022}
27111a23 1023
77145f1c
BS
1024static const struct file_operations
1025nouveau_driver_fops = {
1026 .owner = THIS_MODULE,
1027 .open = drm_open,
1028 .release = drm_release,
5addcf0a 1029 .unlocked_ioctl = nouveau_drm_ioctl,
77145f1c
BS
1030 .mmap = nouveau_ttm_mmap,
1031 .poll = drm_poll,
77145f1c
BS
1032 .read = drm_read,
1033#if defined(CONFIG_COMPAT)
1034 .compat_ioctl = nouveau_compat_ioctl,
1035#endif
1036 .llseek = noop_llseek,
1037};
1038
1039static struct drm_driver
915b4d11 1040driver_stub = {
77145f1c 1041 .driver_features =
0e975980
PA
1042 DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER |
1043 DRIVER_KMS_LEGACY_CONTEXT,
77145f1c 1044
77145f1c 1045 .open = nouveau_drm_open,
77145f1c
BS
1046 .postclose = nouveau_drm_postclose,
1047 .lastclose = nouveau_vga_lastclose,
1048
33b903e8 1049#if defined(CONFIG_DEBUG_FS)
56c101af 1050 .debugfs_init = nouveau_drm_debugfs_init,
33b903e8
MS
1051#endif
1052
51cb4b39
BS
1053 .enable_vblank = nouveau_display_vblank_enable,
1054 .disable_vblank = nouveau_display_vblank_disable,
d83ef853 1055 .get_scanout_position = nouveau_display_scanoutpos,
1bf6ad62 1056 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
77145f1c
BS
1057
1058 .ioctls = nouveau_ioctls,
baa70943 1059 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
77145f1c
BS
1060 .fops = &nouveau_driver_fops,
1061
1062 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1063 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
ab9ccb96
AP
1064 .gem_prime_export = drm_gem_prime_export,
1065 .gem_prime_import = drm_gem_prime_import,
1066 .gem_prime_pin = nouveau_gem_prime_pin,
3aac4502 1067 .gem_prime_res_obj = nouveau_gem_prime_res_obj,
1af7c7dd 1068 .gem_prime_unpin = nouveau_gem_prime_unpin,
ab9ccb96
AP
1069 .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
1070 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1071 .gem_prime_vmap = nouveau_gem_prime_vmap,
1072 .gem_prime_vunmap = nouveau_gem_prime_vunmap,
77145f1c 1073
a51e6ac4 1074 .gem_free_object_unlocked = nouveau_gem_object_del,
77145f1c
BS
1075 .gem_open_object = nouveau_gem_object_open,
1076 .gem_close_object = nouveau_gem_object_close,
1077
1078 .dumb_create = nouveau_display_dumb_create,
1079 .dumb_map_offset = nouveau_display_dumb_map_offset,
77145f1c
BS
1080
1081 .name = DRIVER_NAME,
1082 .desc = DRIVER_DESC,
1083#ifdef GIT_REVISION
1084 .date = GIT_REVISION,
1085#else
1086 .date = DRIVER_DATE,
1087#endif
1088 .major = DRIVER_MAJOR,
1089 .minor = DRIVER_MINOR,
1090 .patchlevel = DRIVER_PATCHLEVEL,
1091};
1092
94580299
BS
1093static struct pci_device_id
1094nouveau_drm_pci_table[] = {
1095 {
1096 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1097 .class = PCI_BASE_CLASS_DISPLAY << 16,
1098 .class_mask = 0xff << 16,
1099 },
1100 {
1101 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1102 .class = PCI_BASE_CLASS_DISPLAY << 16,
1103 .class_mask = 0xff << 16,
1104 },
1105 {}
1106};
1107
703fa264
PM
1108static void nouveau_display_options(void)
1109{
1110 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1111
1112 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1113 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1114 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1115 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
1116 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1117 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1118 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1119 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1120 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1121 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
f3a8b664 1122 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
703fa264
PM
1123}
1124
2d8b9ccb
DA
1125static const struct dev_pm_ops nouveau_pm_ops = {
1126 .suspend = nouveau_pmops_suspend,
1127 .resume = nouveau_pmops_resume,
1128 .freeze = nouveau_pmops_freeze,
1129 .thaw = nouveau_pmops_thaw,
1130 .poweroff = nouveau_pmops_freeze,
1131 .restore = nouveau_pmops_resume,
5addcf0a
DA
1132 .runtime_suspend = nouveau_pmops_runtime_suspend,
1133 .runtime_resume = nouveau_pmops_runtime_resume,
1134 .runtime_idle = nouveau_pmops_runtime_idle,
2d8b9ccb
DA
1135};
1136
94580299
BS
1137static struct pci_driver
1138nouveau_drm_pci_driver = {
1139 .name = "nouveau",
1140 .id_table = nouveau_drm_pci_table,
1141 .probe = nouveau_drm_probe,
1142 .remove = nouveau_drm_remove,
2d8b9ccb 1143 .driver.pm = &nouveau_pm_ops,
94580299
BS
1144};
1145
8ba9ff11 1146struct drm_device *
e396ecd1
AC
1147nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1148 struct platform_device *pdev,
47b2505e 1149 struct nvkm_device **pdevice)
420b9469 1150{
8ba9ff11
AC
1151 struct drm_device *drm;
1152 int err;
420b9469 1153
e396ecd1 1154 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
7974dd1b 1155 true, true, ~0ULL, pdevice);
8ba9ff11 1156 if (err)
e781dc8f 1157 goto err_free;
8ba9ff11 1158
915b4d11 1159 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
0f288605
TG
1160 if (IS_ERR(drm)) {
1161 err = PTR_ERR(drm);
8ba9ff11 1162 goto err_free;
420b9469
AC
1163 }
1164
4ac0a807
TR
1165 err = nouveau_drm_device_init(drm);
1166 if (err)
1167 goto err_put;
1168
8ba9ff11
AC
1169 platform_set_drvdata(pdev, drm);
1170
1171 return drm;
1172
4ac0a807
TR
1173err_put:
1174 drm_dev_put(drm);
8ba9ff11 1175err_free:
e781dc8f 1176 nvkm_device_del(pdevice);
8ba9ff11
AC
1177
1178 return ERR_PTR(err);
420b9469
AC
1179}
1180
94580299
BS
1181static int __init
1182nouveau_drm_init(void)
1183{
915b4d11 1184 driver_pci = driver_stub;
915b4d11 1185 driver_platform = driver_stub;
915b4d11 1186
703fa264
PM
1187 nouveau_display_options();
1188
77145f1c 1189 if (nouveau_modeset == -1) {
77145f1c
BS
1190 if (vgacon_text_force())
1191 nouveau_modeset = 0;
77145f1c
BS
1192 }
1193
1194 if (!nouveau_modeset)
1195 return 0;
1196
055a65d5
AC
1197#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1198 platform_driver_register(&nouveau_platform_driver);
1199#endif
1200
77145f1c 1201 nouveau_register_dsm_handler();
db1a0ae2 1202 nouveau_backlight_ctor();
10631d72
DV
1203
1204#ifdef CONFIG_PCI
1205 return pci_register_driver(&nouveau_drm_pci_driver);
1206#else
1207 return 0;
1208#endif
94580299
BS
1209}
1210
1211static void __exit
1212nouveau_drm_exit(void)
1213{
77145f1c
BS
1214 if (!nouveau_modeset)
1215 return;
1216
10631d72
DV
1217#ifdef CONFIG_PCI
1218 pci_unregister_driver(&nouveau_drm_pci_driver);
1219#endif
db1a0ae2 1220 nouveau_backlight_dtor();
77145f1c 1221 nouveau_unregister_dsm_handler();
055a65d5
AC
1222
1223#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1224 platform_driver_unregister(&nouveau_platform_driver);
1225#endif
94580299
BS
1226}
1227
1228module_init(nouveau_drm_init);
1229module_exit(nouveau_drm_exit);
1230
1231MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
77145f1c
BS
1232MODULE_AUTHOR(DRIVER_AUTHOR);
1233MODULE_DESCRIPTION(DRIVER_DESC);
94580299 1234MODULE_LICENSE("GPL and additional rights");