Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_drm.c
CommitLineData
94580299
BS
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
77145f1c 25#include <linux/console.h>
c5fd936e 26#include <linux/delay.h>
94580299
BS
27#include <linux/module.h>
28#include <linux/pci.h>
5addcf0a
DA
29#include <linux/pm_runtime.h>
30#include <linux/vga_switcheroo.h>
fdb751ef 31
5addcf0a
DA
32#include "drmP.h"
33#include "drm_crtc_helper.h"
fdb751ef 34
94580299 35#include <core/device.h>
ebb945a9 36#include <core/gpuobj.h>
c33e05a1 37#include <core/option.h>
94580299 38
94580299 39#include "nouveau_drm.h"
ebb945a9 40#include "nouveau_dma.h"
77145f1c
BS
41#include "nouveau_ttm.h"
42#include "nouveau_gem.h"
cb75d97e 43#include "nouveau_agp.h"
77145f1c 44#include "nouveau_vga.h"
26fdd78c 45#include "nouveau_sysfs.h"
b9ed919f 46#include "nouveau_hwmon.h"
77145f1c
BS
47#include "nouveau_acpi.h"
48#include "nouveau_bios.h"
49#include "nouveau_ioctl.h"
ebb945a9
BS
50#include "nouveau_abi16.h"
51#include "nouveau_fbcon.h"
52#include "nouveau_fence.h"
33b903e8 53#include "nouveau_debugfs.h"
27111a23 54#include "nouveau_usif.h"
703fa264 55#include "nouveau_connector.h"
055a65d5 56#include "nouveau_platform.h"
ebb945a9 57
94580299
BS
58MODULE_PARM_DESC(config, "option string to pass to driver core");
59static char *nouveau_config;
60module_param_named(config, nouveau_config, charp, 0400);
61
62MODULE_PARM_DESC(debug, "debug string to pass to driver core");
63static char *nouveau_debug;
64module_param_named(debug, nouveau_debug, charp, 0400);
65
ebb945a9
BS
66MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
67static int nouveau_noaccel = 0;
68module_param_named(noaccel, nouveau_noaccel, int, 0400);
69
9430738d
BS
70MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
71 "0 = disabled, 1 = enabled, 2 = headless)");
72int nouveau_modeset = -1;
77145f1c
BS
73module_param_named(modeset, nouveau_modeset, int, 0400);
74
5addcf0a
DA
75MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
76int nouveau_runtime_pm = -1;
77module_param_named(runpm, nouveau_runtime_pm, int, 0400);
78
915b4d11
DH
79static struct drm_driver driver_stub;
80static struct drm_driver driver_pci;
81static struct drm_driver driver_platform;
77145f1c 82
94580299 83static u64
420b9469 84nouveau_pci_name(struct pci_dev *pdev)
94580299
BS
85{
86 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
87 name |= pdev->bus->number << 16;
88 name |= PCI_SLOT(pdev->devfn) << 8;
89 return name | PCI_FUNC(pdev->devfn);
90}
91
420b9469
AC
92static u64
93nouveau_platform_name(struct platform_device *platformdev)
94{
95 return platformdev->id;
96}
97
98static u64
99nouveau_name(struct drm_device *dev)
100{
101 if (dev->pdev)
102 return nouveau_pci_name(dev->pdev);
103 else
104 return nouveau_platform_name(dev->platformdev);
105}
106
94580299 107static int
420b9469 108nouveau_cli_create(u64 name, const char *sname,
fa6df8c1 109 int size, void **pcli)
94580299 110{
0ad72863
BS
111 struct nouveau_cli *cli = *pcli = kzalloc(size, GFP_KERNEL);
112 if (cli) {
113 int ret = nvif_client_init(NULL, NULL, sname, name,
114 nouveau_config, nouveau_debug,
115 &cli->base);
27111a23 116 if (ret == 0) {
0ad72863 117 mutex_init(&cli->mutex);
27111a23
BS
118 usif_client_init(cli);
119 }
94580299 120 return ret;
dd5700ea 121 }
0ad72863 122 return -ENOMEM;
94580299
BS
123}
124
125static void
126nouveau_cli_destroy(struct nouveau_cli *cli)
127{
be83cd4e 128 nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL);
0ad72863 129 nvif_client_fini(&cli->base);
27111a23 130 usif_client_fini(cli);
f5654d95 131 kfree(cli);
94580299
BS
132}
133
ebb945a9
BS
134static void
135nouveau_accel_fini(struct nouveau_drm *drm)
136{
ebb945a9 137 nouveau_channel_del(&drm->channel);
0ad72863 138 nvif_object_fini(&drm->ntfy);
be83cd4e 139 nvkm_gpuobj_ref(NULL, &drm->notify);
0ad72863 140 nvif_object_fini(&drm->nvsw);
49981046 141 nouveau_channel_del(&drm->cechan);
0ad72863 142 nvif_object_fini(&drm->ttm.copy);
ebb945a9
BS
143 if (drm->fence)
144 nouveau_fence(drm)->dtor(drm);
145}
146
147static void
148nouveau_accel_init(struct nouveau_drm *drm)
149{
967e7bde 150 struct nvif_device *device = &drm->device;
49981046 151 u32 arg0, arg1;
967e7bde
BS
152 u32 sclass[16];
153 int ret, i;
ebb945a9 154
967e7bde 155 if (nouveau_noaccel)
ebb945a9
BS
156 return;
157
158 /* initialise synchronisation routines */
967e7bde
BS
159 /*XXX: this is crap, but the fence/channel stuff is a little
160 * backwards in some places. this will be fixed.
161 */
0ad72863 162 ret = nvif_object_sclass(&device->base, sclass, ARRAY_SIZE(sclass));
967e7bde
BS
163 if (ret < 0)
164 return;
165
166 for (ret = -ENOSYS, i = 0; ret && i < ARRAY_SIZE(sclass); i++) {
167 switch (sclass[i]) {
bbf8906b 168 case NV03_CHANNEL_DMA:
967e7bde
BS
169 ret = nv04_fence_create(drm);
170 break;
bbf8906b 171 case NV10_CHANNEL_DMA:
967e7bde
BS
172 ret = nv10_fence_create(drm);
173 break;
bbf8906b
BS
174 case NV17_CHANNEL_DMA:
175 case NV40_CHANNEL_DMA:
967e7bde
BS
176 ret = nv17_fence_create(drm);
177 break;
bbf8906b 178 case NV50_CHANNEL_GPFIFO:
967e7bde
BS
179 ret = nv50_fence_create(drm);
180 break;
bbf8906b 181 case G82_CHANNEL_GPFIFO:
967e7bde
BS
182 ret = nv84_fence_create(drm);
183 break;
bbf8906b
BS
184 case FERMI_CHANNEL_GPFIFO:
185 case KEPLER_CHANNEL_GPFIFO_A:
a1020afe 186 case MAXWELL_CHANNEL_GPFIFO_A:
967e7bde
BS
187 ret = nvc0_fence_create(drm);
188 break;
189 default:
190 break;
191 }
192 }
193
ebb945a9
BS
194 if (ret) {
195 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
196 nouveau_accel_fini(drm);
197 return;
198 }
199
967e7bde 200 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
0ad72863 201 ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1,
bbf8906b
BS
202 KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0|
203 KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1,
204 0, &drm->cechan);
49981046
BS
205 if (ret)
206 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
207
bbf8906b 208 arg0 = KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR;
49469800 209 arg1 = 1;
00fc6f6f 210 } else
967e7bde
BS
211 if (device->info.chipset >= 0xa3 &&
212 device->info.chipset != 0xaa &&
213 device->info.chipset != 0xac) {
0ad72863
BS
214 ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1,
215 NvDmaFB, NvDmaTT, &drm->cechan);
00fc6f6f
BS
216 if (ret)
217 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
218
219 arg0 = NvDmaFB;
220 arg1 = NvDmaTT;
49981046
BS
221 } else {
222 arg0 = NvDmaFB;
223 arg1 = NvDmaTT;
224 }
225
0ad72863
BS
226 ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN, arg0, arg1,
227 &drm->channel);
ebb945a9
BS
228 if (ret) {
229 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
230 nouveau_accel_fini(drm);
231 return;
232 }
233
0ad72863
BS
234 ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW,
235 nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw);
69a6146d 236 if (ret == 0) {
be83cd4e 237 struct nvkm_sw_chan *swch;
69a6146d
BS
238 ret = RING_SPACE(drm->channel, 2);
239 if (ret == 0) {
967e7bde 240 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
69a6146d
BS
241 BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
242 OUT_RING (drm->channel, NVDRM_NVSW);
243 } else
967e7bde 244 if (device->info.family < NV_DEVICE_INFO_V0_KEPLER) {
69a6146d
BS
245 BEGIN_NVC0(drm->channel, FermiSw, 0, 1);
246 OUT_RING (drm->channel, 0x001f0000);
247 }
248 }
989aa5b7 249 swch = (void *)nvxx_object(&drm->nvsw)->parent;
69a6146d
BS
250 swch->flip = nouveau_flip_complete;
251 swch->flip_data = drm->channel;
252 }
253
254 if (ret) {
255 NV_ERROR(drm, "failed to allocate software object, %d\n", ret);
256 nouveau_accel_fini(drm);
257 return;
258 }
259
967e7bde 260 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
be83cd4e
BS
261 ret = nvkm_gpuobj_new(nvxx_object(&drm->device), NULL, 32,
262 0, 0, &drm->notify);
ebb945a9
BS
263 if (ret) {
264 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
265 nouveau_accel_fini(drm);
266 return;
267 }
268
0ad72863 269 ret = nvif_object_init(drm->channel->object, NULL, NvNotify0,
4acfd707
BS
270 NV_DMA_IN_MEMORY,
271 &(struct nv_dma_v0) {
272 .target = NV_DMA_V0_TARGET_VRAM,
273 .access = NV_DMA_V0_ACCESS_RDWR,
ebb945a9
BS
274 .start = drm->notify->addr,
275 .limit = drm->notify->addr + 31
4acfd707 276 }, sizeof(struct nv_dma_v0),
0ad72863 277 &drm->ntfy);
ebb945a9
BS
278 if (ret) {
279 nouveau_accel_fini(drm);
280 return;
281 }
282 }
283
284
49981046 285 nouveau_bo_move_init(drm);
ebb945a9
BS
286}
287
56550d94
GKH
288static int nouveau_drm_probe(struct pci_dev *pdev,
289 const struct pci_device_id *pent)
94580299 290{
be83cd4e 291 struct nvkm_device *device;
ebb945a9
BS
292 struct apertures_struct *aper;
293 bool boot = false;
94580299
BS
294 int ret;
295
ebb945a9
BS
296 /* remove conflicting drivers (vesafb, efifb etc) */
297 aper = alloc_apertures(3);
298 if (!aper)
299 return -ENOMEM;
300
301 aper->ranges[0].base = pci_resource_start(pdev, 1);
302 aper->ranges[0].size = pci_resource_len(pdev, 1);
303 aper->count = 1;
304
305 if (pci_resource_len(pdev, 2)) {
306 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
307 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
308 aper->count++;
309 }
310
311 if (pci_resource_len(pdev, 3)) {
312 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
313 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
314 aper->count++;
315 }
316
317#ifdef CONFIG_X86
318 boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
319#endif
771fa0e4
BS
320 if (nouveau_modeset != 2)
321 remove_conflicting_framebuffers(aper, "nouveaufb", boot);
83ef7777 322 kfree(aper);
ebb945a9 323
be83cd4e
BS
324 ret = nvkm_device_create(pdev, NVKM_BUS_PCI,
325 nouveau_pci_name(pdev), pci_name(pdev),
326 nouveau_config, nouveau_debug, &device);
94580299
BS
327 if (ret)
328 return ret;
329
330 pci_set_master(pdev);
331
915b4d11 332 ret = drm_get_pci_dev(pdev, pent, &driver_pci);
94580299 333 if (ret) {
be83cd4e 334 nvkm_object_ref(NULL, (struct nvkm_object **)&device);
94580299
BS
335 return ret;
336 }
337
338 return 0;
339}
340
5addcf0a
DA
341#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
342
343static void
46941b0f 344nouveau_get_hdmi_dev(struct nouveau_drm *drm)
5addcf0a 345{
46941b0f 346 struct pci_dev *pdev = drm->dev->pdev;
5addcf0a 347
420b9469 348 if (!pdev) {
40189b0c 349 DRM_INFO("not a PCI device; no HDMI\n");
420b9469
AC
350 drm->hdmi_device = NULL;
351 return;
352 }
353
5addcf0a
DA
354 /* subfunction one is a hdmi audio device? */
355 drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
356 PCI_DEVFN(PCI_SLOT(pdev->devfn), 1));
357
358 if (!drm->hdmi_device) {
46941b0f 359 NV_DEBUG(drm, "hdmi device not found %d %d %d\n", pdev->bus->number, PCI_SLOT(pdev->devfn), 1);
5addcf0a
DA
360 return;
361 }
362
363 if ((drm->hdmi_device->class >> 8) != PCI_CLASS_MULTIMEDIA_HD_AUDIO) {
46941b0f 364 NV_DEBUG(drm, "possible hdmi device not audio %d\n", drm->hdmi_device->class);
5addcf0a
DA
365 pci_dev_put(drm->hdmi_device);
366 drm->hdmi_device = NULL;
367 return;
368 }
369}
370
5b8a43ae 371static int
94580299
BS
372nouveau_drm_load(struct drm_device *dev, unsigned long flags)
373{
374 struct pci_dev *pdev = dev->pdev;
375 struct nouveau_drm *drm;
376 int ret;
377
420b9469
AC
378 ret = nouveau_cli_create(nouveau_name(dev), "DRM", sizeof(*drm),
379 (void **)&drm);
94580299
BS
380 if (ret)
381 return ret;
382
77145f1c
BS
383 dev->dev_private = drm;
384 drm->dev = dev;
989aa5b7 385 nvxx_client(&drm->client.base)->debug =
be83cd4e 386 nvkm_dbgopt(nouveau_debug, "DRM");
77145f1c 387
94580299 388 INIT_LIST_HEAD(&drm->clients);
ebb945a9 389 spin_lock_init(&drm->tile.lock);
94580299 390
46941b0f 391 nouveau_get_hdmi_dev(drm);
5addcf0a 392
cb75d97e
BS
393 /* make sure AGP controller is in a consistent state before we
394 * (possibly) execute vbios init tables (see nouveau_agp.h)
395 */
420b9469 396 if (pdev && drm_pci_device_is_agp(dev) && dev->agp) {
586491e6
BS
397 const u64 enables = NV_DEVICE_V0_DISABLE_IDENTIFY |
398 NV_DEVICE_V0_DISABLE_MMIO;
cb75d97e
BS
399 /* dummy device object, doesn't init anything, but allows
400 * agp code access to registers
401 */
0ad72863 402 ret = nvif_device_init(&drm->client.base.base, NULL,
586491e6
BS
403 NVDRM_DEVICE, NV_DEVICE,
404 &(struct nv_device_v0) {
cb75d97e 405 .device = ~0,
586491e6 406 .disable = ~enables,
cb75d97e 407 .debug0 = ~0,
586491e6 408 }, sizeof(struct nv_device_v0),
0ad72863 409 &drm->device);
cb75d97e 410 if (ret)
ebb945a9 411 goto fail_device;
cb75d97e
BS
412
413 nouveau_agp_reset(drm);
0ad72863 414 nvif_device_fini(&drm->device);
cb75d97e
BS
415 }
416
0ad72863 417 ret = nvif_device_init(&drm->client.base.base, NULL, NVDRM_DEVICE,
586491e6
BS
418 NV_DEVICE,
419 &(struct nv_device_v0) {
94580299
BS
420 .device = ~0,
421 .disable = 0,
422 .debug0 = 0,
586491e6 423 }, sizeof(struct nv_device_v0),
0ad72863 424 &drm->device);
94580299
BS
425 if (ret)
426 goto fail_device;
427
7d3428cd
IM
428 dev->irq_enabled = true;
429
77145f1c
BS
430 /* workaround an odd issue on nvc1 by disabling the device's
431 * nosnoop capability. hopefully won't cause issues until a
432 * better fix is found - assuming there is one...
433 */
967e7bde
BS
434 if (drm->device.info.chipset == 0xc1)
435 nvif_mask(&drm->device, 0x00088080, 0x00000800, 0x00000000);
ebb945a9 436
77145f1c 437 nouveau_vga_init(drm);
cb75d97e
BS
438 nouveau_agp_init(drm);
439
967e7bde 440 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
be83cd4e
BS
441 ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
442 0x1000, &drm->client.vm);
ebb945a9
BS
443 if (ret)
444 goto fail_device;
3ee6f5b5 445
989aa5b7 446 nvxx_client(&drm->client.base)->vm = drm->client.vm;
ebb945a9
BS
447 }
448
449 ret = nouveau_ttm_init(drm);
94580299 450 if (ret)
77145f1c
BS
451 goto fail_ttm;
452
453 ret = nouveau_bios_init(dev);
454 if (ret)
455 goto fail_bios;
456
77145f1c 457 ret = nouveau_display_create(dev);
ebb945a9 458 if (ret)
77145f1c
BS
459 goto fail_dispctor;
460
461 if (dev->mode_config.num_crtc) {
462 ret = nouveau_display_init(dev);
463 if (ret)
464 goto fail_dispinit;
465 }
466
26fdd78c 467 nouveau_sysfs_init(dev);
b9ed919f 468 nouveau_hwmon_init(dev);
ebb945a9
BS
469 nouveau_accel_init(drm);
470 nouveau_fbcon_init(dev);
5addcf0a
DA
471
472 if (nouveau_runtime_pm != 0) {
473 pm_runtime_use_autosuspend(dev->dev);
474 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
475 pm_runtime_set_active(dev->dev);
476 pm_runtime_allow(dev->dev);
477 pm_runtime_mark_last_busy(dev->dev);
478 pm_runtime_put(dev->dev);
479 }
94580299
BS
480 return 0;
481
77145f1c
BS
482fail_dispinit:
483 nouveau_display_destroy(dev);
484fail_dispctor:
77145f1c
BS
485 nouveau_bios_takedown(dev);
486fail_bios:
ebb945a9 487 nouveau_ttm_fini(drm);
77145f1c
BS
488fail_ttm:
489 nouveau_agp_fini(drm);
490 nouveau_vga_fini(drm);
94580299 491fail_device:
0ad72863 492 nvif_device_fini(&drm->device);
94580299
BS
493 nouveau_cli_destroy(&drm->client);
494 return ret;
495}
496
5b8a43ae 497static int
94580299
BS
498nouveau_drm_unload(struct drm_device *dev)
499{
77145f1c 500 struct nouveau_drm *drm = nouveau_drm(dev);
94580299 501
5addcf0a 502 pm_runtime_get_sync(dev->dev);
ebb945a9
BS
503 nouveau_fbcon_fini(dev);
504 nouveau_accel_fini(drm);
b9ed919f 505 nouveau_hwmon_fini(dev);
26fdd78c 506 nouveau_sysfs_fini(dev);
77145f1c 507
9430738d
BS
508 if (dev->mode_config.num_crtc)
509 nouveau_display_fini(dev);
77145f1c
BS
510 nouveau_display_destroy(dev);
511
77145f1c 512 nouveau_bios_takedown(dev);
94580299 513
ebb945a9 514 nouveau_ttm_fini(drm);
cb75d97e 515 nouveau_agp_fini(drm);
77145f1c 516 nouveau_vga_fini(drm);
cb75d97e 517
0ad72863 518 nvif_device_fini(&drm->device);
5addcf0a
DA
519 if (drm->hdmi_device)
520 pci_dev_put(drm->hdmi_device);
94580299
BS
521 nouveau_cli_destroy(&drm->client);
522 return 0;
523}
524
8ba9ff11
AC
525void
526nouveau_drm_device_remove(struct drm_device *dev)
94580299 527{
77145f1c 528 struct nouveau_drm *drm = nouveau_drm(dev);
be83cd4e
BS
529 struct nvkm_client *client;
530 struct nvkm_object *device;
77145f1c 531
7d3428cd 532 dev->irq_enabled = false;
989aa5b7 533 client = nvxx_client(&drm->client.base);
0ad72863 534 device = client->device;
77145f1c
BS
535 drm_put_dev(dev);
536
be83cd4e
BS
537 nvkm_object_ref(NULL, &device);
538 nvkm_object_debug();
94580299 539}
8ba9ff11
AC
540
541static void
542nouveau_drm_remove(struct pci_dev *pdev)
543{
544 struct drm_device *dev = pci_get_drvdata(pdev);
545
546 nouveau_drm_device_remove(dev);
547}
94580299 548
cd897837 549static int
05c63c2f 550nouveau_do_suspend(struct drm_device *dev, bool runtime)
94580299 551{
77145f1c 552 struct nouveau_drm *drm = nouveau_drm(dev);
94580299
BS
553 struct nouveau_cli *cli;
554 int ret;
555
6fbb702e
BS
556 if (dev->mode_config.num_crtc) {
557 NV_INFO(drm, "suspending console...\n");
558 nouveau_fbcon_set_suspend(dev, 1);
c52f4fa6 559 NV_INFO(drm, "suspending display...\n");
6fbb702e 560 ret = nouveau_display_suspend(dev, runtime);
9430738d
BS
561 if (ret)
562 return ret;
563 }
94580299 564
c52f4fa6 565 NV_INFO(drm, "evicting buffers...\n");
ebb945a9
BS
566 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
567
c52f4fa6 568 NV_INFO(drm, "waiting for kernel channels to go idle...\n");
81dff21b
BS
569 if (drm->cechan) {
570 ret = nouveau_channel_idle(drm->cechan);
571 if (ret)
f3980dc5 572 goto fail_display;
81dff21b
BS
573 }
574
575 if (drm->channel) {
576 ret = nouveau_channel_idle(drm->channel);
577 if (ret)
f3980dc5 578 goto fail_display;
81dff21b
BS
579 }
580
c52f4fa6 581 NV_INFO(drm, "suspending client object trees...\n");
ebb945a9 582 if (drm->fence && nouveau_fence(drm)->suspend) {
f3980dc5
IM
583 if (!nouveau_fence(drm)->suspend(drm)) {
584 ret = -ENOMEM;
585 goto fail_display;
586 }
ebb945a9
BS
587 }
588
94580299 589 list_for_each_entry(cli, &drm->clients, head) {
0ad72863 590 ret = nvif_client_suspend(&cli->base);
94580299
BS
591 if (ret)
592 goto fail_client;
593 }
594
c52f4fa6 595 NV_INFO(drm, "suspending kernel object tree...\n");
0ad72863 596 ret = nvif_client_suspend(&drm->client.base);
94580299
BS
597 if (ret)
598 goto fail_client;
599
cb75d97e 600 nouveau_agp_fini(drm);
94580299
BS
601 return 0;
602
603fail_client:
604 list_for_each_entry_continue_reverse(cli, &drm->clients, head) {
0ad72863 605 nvif_client_resume(&cli->base);
94580299
BS
606 }
607
f3980dc5
IM
608 if (drm->fence && nouveau_fence(drm)->resume)
609 nouveau_fence(drm)->resume(drm);
610
611fail_display:
9430738d 612 if (dev->mode_config.num_crtc) {
c52f4fa6 613 NV_INFO(drm, "resuming display...\n");
6fbb702e 614 nouveau_display_resume(dev, runtime);
9430738d 615 }
94580299
BS
616 return ret;
617}
618
cd897837 619static int
6fbb702e 620nouveau_do_resume(struct drm_device *dev, bool runtime)
2d8b9ccb
DA
621{
622 struct nouveau_drm *drm = nouveau_drm(dev);
623 struct nouveau_cli *cli;
624
c52f4fa6 625 NV_INFO(drm, "re-enabling device...\n");
94580299 626
cb75d97e
BS
627 nouveau_agp_reset(drm);
628
c52f4fa6 629 NV_INFO(drm, "resuming kernel object tree...\n");
0ad72863 630 nvif_client_resume(&drm->client.base);
ebb945a9 631 nouveau_agp_init(drm);
94580299 632
c52f4fa6 633 NV_INFO(drm, "resuming client object trees...\n");
81dff21b
BS
634 if (drm->fence && nouveau_fence(drm)->resume)
635 nouveau_fence(drm)->resume(drm);
636
94580299 637 list_for_each_entry(cli, &drm->clients, head) {
0ad72863 638 nvif_client_resume(&cli->base);
94580299 639 }
cb75d97e 640
77145f1c 641 nouveau_run_vbios_init(dev);
77145f1c 642
9430738d 643 if (dev->mode_config.num_crtc) {
c52f4fa6 644 NV_INFO(drm, "resuming display...\n");
6fbb702e
BS
645 nouveau_display_resume(dev, runtime);
646 NV_INFO(drm, "resuming console...\n");
647 nouveau_fbcon_set_suspend(dev, 0);
9430738d 648 }
5addcf0a 649
77145f1c 650 return 0;
94580299
BS
651}
652
7bb6d442
BS
653int
654nouveau_pmops_suspend(struct device *dev)
655{
656 struct pci_dev *pdev = to_pci_dev(dev);
657 struct drm_device *drm_dev = pci_get_drvdata(pdev);
658 int ret;
659
660 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
661 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
662 return 0;
663
664 ret = nouveau_do_suspend(drm_dev, false);
665 if (ret)
666 return ret;
667
668 pci_save_state(pdev);
669 pci_disable_device(pdev);
7bb6d442 670 pci_set_power_state(pdev, PCI_D3hot);
c5fd936e 671 udelay(200);
7bb6d442
BS
672 return 0;
673}
674
675int
676nouveau_pmops_resume(struct device *dev)
2d8b9ccb
DA
677{
678 struct pci_dev *pdev = to_pci_dev(dev);
679 struct drm_device *drm_dev = pci_get_drvdata(pdev);
680 int ret;
681
5addcf0a
DA
682 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
683 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
2d8b9ccb
DA
684 return 0;
685
686 pci_set_power_state(pdev, PCI_D0);
687 pci_restore_state(pdev);
688 ret = pci_enable_device(pdev);
689 if (ret)
690 return ret;
691 pci_set_master(pdev);
692
6fbb702e 693 return nouveau_do_resume(drm_dev, false);
2d8b9ccb
DA
694}
695
7bb6d442
BS
696static int
697nouveau_pmops_freeze(struct device *dev)
2d8b9ccb
DA
698{
699 struct pci_dev *pdev = to_pci_dev(dev);
700 struct drm_device *drm_dev = pci_get_drvdata(pdev);
6fbb702e 701 return nouveau_do_suspend(drm_dev, false);
2d8b9ccb
DA
702}
703
7bb6d442
BS
704static int
705nouveau_pmops_thaw(struct device *dev)
2d8b9ccb
DA
706{
707 struct pci_dev *pdev = to_pci_dev(dev);
708 struct drm_device *drm_dev = pci_get_drvdata(pdev);
6fbb702e 709 return nouveau_do_resume(drm_dev, false);
2d8b9ccb
DA
710}
711
7bb6d442
BS
712static int
713nouveau_pmops_runtime_suspend(struct device *dev)
714{
715 struct pci_dev *pdev = to_pci_dev(dev);
716 struct drm_device *drm_dev = pci_get_drvdata(pdev);
717 int ret;
718
719 if (nouveau_runtime_pm == 0) {
720 pm_runtime_forbid(dev);
721 return -EBUSY;
722 }
723
724 /* are we optimus enabled? */
725 if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
726 DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
727 pm_runtime_forbid(dev);
728 return -EBUSY;
729 }
730
731 nv_debug_level(SILENT);
732 drm_kms_helper_poll_disable(drm_dev);
733 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
734 nouveau_switcheroo_optimus_dsm();
735 ret = nouveau_do_suspend(drm_dev, true);
736 pci_save_state(pdev);
737 pci_disable_device(pdev);
8c863944 738 pci_ignore_hotplug(pdev);
7bb6d442
BS
739 pci_set_power_state(pdev, PCI_D3cold);
740 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
741 return ret;
742}
743
744static int
745nouveau_pmops_runtime_resume(struct device *dev)
746{
747 struct pci_dev *pdev = to_pci_dev(dev);
748 struct drm_device *drm_dev = pci_get_drvdata(pdev);
749 struct nvif_device *device = &nouveau_drm(drm_dev)->device;
750 int ret;
751
752 if (nouveau_runtime_pm == 0)
753 return -EINVAL;
754
755 pci_set_power_state(pdev, PCI_D0);
756 pci_restore_state(pdev);
757 ret = pci_enable_device(pdev);
758 if (ret)
759 return ret;
760 pci_set_master(pdev);
761
762 ret = nouveau_do_resume(drm_dev, true);
763 drm_kms_helper_poll_enable(drm_dev);
764 /* do magic */
765 nvif_mask(device, 0x88488, (1 << 25), (1 << 25));
766 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
767 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
768 nv_debug_level(NORMAL);
769 return ret;
770}
771
772static int
773nouveau_pmops_runtime_idle(struct device *dev)
774{
775 struct pci_dev *pdev = to_pci_dev(dev);
776 struct drm_device *drm_dev = pci_get_drvdata(pdev);
777 struct nouveau_drm *drm = nouveau_drm(drm_dev);
778 struct drm_crtc *crtc;
779
780 if (nouveau_runtime_pm == 0) {
781 pm_runtime_forbid(dev);
782 return -EBUSY;
783 }
784
785 /* are we optimus enabled? */
786 if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
787 DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
788 pm_runtime_forbid(dev);
789 return -EBUSY;
790 }
791
792 /* if we have a hdmi audio device - make sure it has a driver loaded */
793 if (drm->hdmi_device) {
794 if (!drm->hdmi_device->driver) {
795 DRM_DEBUG_DRIVER("failing to power off - no HDMI audio driver loaded\n");
796 pm_runtime_mark_last_busy(dev);
797 return -EBUSY;
798 }
799 }
800
801 list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) {
802 if (crtc->enabled) {
803 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
804 return -EBUSY;
805 }
806 }
807 pm_runtime_mark_last_busy(dev);
808 pm_runtime_autosuspend(dev);
809 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
810 return 1;
811}
2d8b9ccb 812
5b8a43ae 813static int
ebb945a9
BS
814nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
815{
ebb945a9
BS
816 struct nouveau_drm *drm = nouveau_drm(dev);
817 struct nouveau_cli *cli;
a2896ced 818 char name[32], tmpname[TASK_COMM_LEN];
ebb945a9
BS
819 int ret;
820
5addcf0a
DA
821 /* need to bring up power immediately if opening device */
822 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 823 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
824 return ret;
825
a2896ced
MS
826 get_task_comm(tmpname, current);
827 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
fa6df8c1 828
420b9469
AC
829 ret = nouveau_cli_create(nouveau_name(dev), name, sizeof(*cli),
830 (void **)&cli);
831
ebb945a9 832 if (ret)
5addcf0a 833 goto out_suspend;
ebb945a9 834
0ad72863
BS
835 cli->base.super = false;
836
967e7bde 837 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
be83cd4e
BS
838 ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
839 0x1000, &cli->vm);
ebb945a9
BS
840 if (ret) {
841 nouveau_cli_destroy(cli);
5addcf0a 842 goto out_suspend;
ebb945a9 843 }
3ee6f5b5 844
989aa5b7 845 nvxx_client(&cli->base)->vm = cli->vm;
ebb945a9
BS
846 }
847
848 fpriv->driver_priv = cli;
849
850 mutex_lock(&drm->client.mutex);
851 list_add(&cli->head, &drm->clients);
852 mutex_unlock(&drm->client.mutex);
5addcf0a
DA
853
854out_suspend:
855 pm_runtime_mark_last_busy(dev->dev);
856 pm_runtime_put_autosuspend(dev->dev);
857
858 return ret;
ebb945a9
BS
859}
860
5b8a43ae 861static void
ebb945a9
BS
862nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv)
863{
864 struct nouveau_cli *cli = nouveau_cli(fpriv);
865 struct nouveau_drm *drm = nouveau_drm(dev);
866
5addcf0a
DA
867 pm_runtime_get_sync(dev->dev);
868
ac8c7930 869 mutex_lock(&cli->mutex);
ebb945a9
BS
870 if (cli->abi16)
871 nouveau_abi16_fini(cli->abi16);
ac8c7930 872 mutex_unlock(&cli->mutex);
ebb945a9
BS
873
874 mutex_lock(&drm->client.mutex);
875 list_del(&cli->head);
876 mutex_unlock(&drm->client.mutex);
5addcf0a 877
ebb945a9
BS
878}
879
5b8a43ae 880static void
ebb945a9
BS
881nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
882{
883 struct nouveau_cli *cli = nouveau_cli(fpriv);
884 nouveau_cli_destroy(cli);
5addcf0a
DA
885 pm_runtime_mark_last_busy(dev->dev);
886 pm_runtime_put_autosuspend(dev->dev);
ebb945a9
BS
887}
888
baa70943 889static const struct drm_ioctl_desc
77145f1c 890nouveau_ioctls[] = {
7d761258 891 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
77145f1c 892 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
7d761258
MP
893 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
894 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
895 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
896 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
897 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
898 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
899 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
900 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
901 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
902 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
77145f1c
BS
903};
904
27111a23
BS
905long
906nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
5addcf0a 907{
27111a23
BS
908 struct drm_file *filp = file->private_data;
909 struct drm_device *dev = filp->minor->dev;
5addcf0a 910 long ret;
5addcf0a
DA
911
912 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 913 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
914 return ret;
915
27111a23
BS
916 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
917 case DRM_NOUVEAU_NVIF:
918 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
919 break;
920 default:
921 ret = drm_ioctl(file, cmd, arg);
922 break;
923 }
5addcf0a
DA
924
925 pm_runtime_mark_last_busy(dev->dev);
926 pm_runtime_put_autosuspend(dev->dev);
927 return ret;
928}
27111a23 929
77145f1c
BS
930static const struct file_operations
931nouveau_driver_fops = {
932 .owner = THIS_MODULE,
933 .open = drm_open,
934 .release = drm_release,
5addcf0a 935 .unlocked_ioctl = nouveau_drm_ioctl,
77145f1c
BS
936 .mmap = nouveau_ttm_mmap,
937 .poll = drm_poll,
77145f1c
BS
938 .read = drm_read,
939#if defined(CONFIG_COMPAT)
940 .compat_ioctl = nouveau_compat_ioctl,
941#endif
942 .llseek = noop_llseek,
943};
944
945static struct drm_driver
915b4d11 946driver_stub = {
77145f1c 947 .driver_features =
4cb4ea39 948 DRIVER_USE_AGP |
7d761258 949 DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
77145f1c
BS
950
951 .load = nouveau_drm_load,
952 .unload = nouveau_drm_unload,
953 .open = nouveau_drm_open,
954 .preclose = nouveau_drm_preclose,
955 .postclose = nouveau_drm_postclose,
956 .lastclose = nouveau_vga_lastclose,
957
33b903e8
MS
958#if defined(CONFIG_DEBUG_FS)
959 .debugfs_init = nouveau_debugfs_init,
960 .debugfs_cleanup = nouveau_debugfs_takedown,
961#endif
962
77145f1c 963 .get_vblank_counter = drm_vblank_count,
51cb4b39
BS
964 .enable_vblank = nouveau_display_vblank_enable,
965 .disable_vblank = nouveau_display_vblank_disable,
d83ef853
BS
966 .get_scanout_position = nouveau_display_scanoutpos,
967 .get_vblank_timestamp = nouveau_display_vblstamp,
77145f1c
BS
968
969 .ioctls = nouveau_ioctls,
baa70943 970 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
77145f1c
BS
971 .fops = &nouveau_driver_fops,
972
973 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
974 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
ab9ccb96
AP
975 .gem_prime_export = drm_gem_prime_export,
976 .gem_prime_import = drm_gem_prime_import,
977 .gem_prime_pin = nouveau_gem_prime_pin,
3aac4502 978 .gem_prime_res_obj = nouveau_gem_prime_res_obj,
1af7c7dd 979 .gem_prime_unpin = nouveau_gem_prime_unpin,
ab9ccb96
AP
980 .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
981 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
982 .gem_prime_vmap = nouveau_gem_prime_vmap,
983 .gem_prime_vunmap = nouveau_gem_prime_vunmap,
77145f1c 984
77145f1c
BS
985 .gem_free_object = nouveau_gem_object_del,
986 .gem_open_object = nouveau_gem_object_open,
987 .gem_close_object = nouveau_gem_object_close,
988
989 .dumb_create = nouveau_display_dumb_create,
990 .dumb_map_offset = nouveau_display_dumb_map_offset,
43387b37 991 .dumb_destroy = drm_gem_dumb_destroy,
77145f1c
BS
992
993 .name = DRIVER_NAME,
994 .desc = DRIVER_DESC,
995#ifdef GIT_REVISION
996 .date = GIT_REVISION,
997#else
998 .date = DRIVER_DATE,
999#endif
1000 .major = DRIVER_MAJOR,
1001 .minor = DRIVER_MINOR,
1002 .patchlevel = DRIVER_PATCHLEVEL,
1003};
1004
94580299
BS
1005static struct pci_device_id
1006nouveau_drm_pci_table[] = {
1007 {
1008 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1009 .class = PCI_BASE_CLASS_DISPLAY << 16,
1010 .class_mask = 0xff << 16,
1011 },
1012 {
1013 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1014 .class = PCI_BASE_CLASS_DISPLAY << 16,
1015 .class_mask = 0xff << 16,
1016 },
1017 {}
1018};
1019
703fa264
PM
1020static void nouveau_display_options(void)
1021{
1022 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1023
1024 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1025 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1026 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1027 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
1028 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1029 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1030 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1031 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1032 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1033 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
1034 DRM_DEBUG_DRIVER("... pstate : %d\n", nouveau_pstate);
1035}
1036
2d8b9ccb
DA
1037static const struct dev_pm_ops nouveau_pm_ops = {
1038 .suspend = nouveau_pmops_suspend,
1039 .resume = nouveau_pmops_resume,
1040 .freeze = nouveau_pmops_freeze,
1041 .thaw = nouveau_pmops_thaw,
1042 .poweroff = nouveau_pmops_freeze,
1043 .restore = nouveau_pmops_resume,
5addcf0a
DA
1044 .runtime_suspend = nouveau_pmops_runtime_suspend,
1045 .runtime_resume = nouveau_pmops_runtime_resume,
1046 .runtime_idle = nouveau_pmops_runtime_idle,
2d8b9ccb
DA
1047};
1048
94580299
BS
1049static struct pci_driver
1050nouveau_drm_pci_driver = {
1051 .name = "nouveau",
1052 .id_table = nouveau_drm_pci_table,
1053 .probe = nouveau_drm_probe,
1054 .remove = nouveau_drm_remove,
2d8b9ccb 1055 .driver.pm = &nouveau_pm_ops,
94580299
BS
1056};
1057
8ba9ff11
AC
1058struct drm_device *
1059nouveau_platform_device_create_(struct platform_device *pdev, int size,
1060 void **pobject)
420b9469 1061{
8ba9ff11
AC
1062 struct drm_device *drm;
1063 int err;
420b9469 1064
be83cd4e
BS
1065 err = nvkm_device_create_(pdev, NVKM_BUS_PLATFORM,
1066 nouveau_platform_name(pdev),
1067 dev_name(&pdev->dev), nouveau_config,
1068 nouveau_debug, size, pobject);
8ba9ff11
AC
1069 if (err)
1070 return ERR_PTR(err);
1071
915b4d11 1072 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
8ba9ff11
AC
1073 if (!drm) {
1074 err = -ENOMEM;
1075 goto err_free;
420b9469
AC
1076 }
1077
8ba9ff11
AC
1078 err = drm_dev_set_unique(drm, "%s", dev_name(&pdev->dev));
1079 if (err < 0)
1080 goto err_free;
1081
1082 drm->platformdev = pdev;
1083 platform_set_drvdata(pdev, drm);
1084
1085 return drm;
1086
1087err_free:
be83cd4e 1088 nvkm_object_ref(NULL, (struct nvkm_object **)pobject);
8ba9ff11
AC
1089
1090 return ERR_PTR(err);
420b9469
AC
1091}
1092
94580299
BS
1093static int __init
1094nouveau_drm_init(void)
1095{
915b4d11
DH
1096 driver_pci = driver_stub;
1097 driver_pci.set_busid = drm_pci_set_busid;
1098 driver_platform = driver_stub;
1099 driver_platform.set_busid = drm_platform_set_busid;
1100
703fa264
PM
1101 nouveau_display_options();
1102
77145f1c
BS
1103 if (nouveau_modeset == -1) {
1104#ifdef CONFIG_VGA_CONSOLE
1105 if (vgacon_text_force())
1106 nouveau_modeset = 0;
77145f1c 1107#endif
77145f1c
BS
1108 }
1109
1110 if (!nouveau_modeset)
1111 return 0;
1112
055a65d5
AC
1113#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1114 platform_driver_register(&nouveau_platform_driver);
1115#endif
1116
77145f1c 1117 nouveau_register_dsm_handler();
915b4d11 1118 return drm_pci_init(&driver_pci, &nouveau_drm_pci_driver);
94580299
BS
1119}
1120
1121static void __exit
1122nouveau_drm_exit(void)
1123{
77145f1c
BS
1124 if (!nouveau_modeset)
1125 return;
1126
915b4d11 1127 drm_pci_exit(&driver_pci, &nouveau_drm_pci_driver);
77145f1c 1128 nouveau_unregister_dsm_handler();
055a65d5
AC
1129
1130#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1131 platform_driver_unregister(&nouveau_platform_driver);
1132#endif
94580299
BS
1133}
1134
1135module_init(nouveau_drm_init);
1136module_exit(nouveau_drm_exit);
1137
1138MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
77145f1c
BS
1139MODULE_AUTHOR(DRIVER_AUTHOR);
1140MODULE_DESCRIPTION(DRIVER_DESC);
94580299 1141MODULE_LICENSE("GPL and additional rights");