[linux-2.6-block.git] / drivers / gpu / drm / nouveau / include / nvkm / core / tegra.h

#ifndef __NVKM_DEVICE_TEGRA_H__
#define __NVKM_DEVICE_TEGRA_H__
#include <core/device.h>
#include <core/mm.h>

struct nvkm_device_tegra {
	const struct nvkm_device_tegra_func *func;
	struct nvkm_device device;
	struct platform_device *pdev;
	int irq;

	struct reset_control *rst;
	struct clk *clk;
	struct clk *clk_ref;
	struct clk *clk_pwr;

	struct regulator *vdd;

	struct {
		/*
		 * Protects accesses to mm from subsystems
		 */
		struct mutex mutex;

		struct nvkm_mm mm;
		struct iommu_domain *domain;
		unsigned long pgshift;
	} iommu;

	int gpu_speedo;
};

struct nvkm_device_tegra_func {
	/*
	 * If an IOMMU is used, indicates which address bit will trigger a
	 * IOMMU translation when set (when this bit is not set, IOMMU is
	 * bypassed). A value of 0 means an IOMMU is never used.
	 */
	u8 iommu_bit;
	/*
	 * Whether the chip requires a reference clock
	 */
	bool require_ref_clk;
};

int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *,
			  struct platform_device *,
			  const char *cfg, const char *dbg,
			  bool detect, bool mmio, u64 subdev_mask,
			  struct nvkm_device **);
#endif
Commit	Line	Data
7974dd1b BS	1	#ifndef __NVKM_DEVICE_TEGRA_H__
	2	#define __NVKM_DEVICE_TEGRA_H__
	3	#include <core/device.h>
43a70661	4	#include <core/mm.h>
7974dd1b BS	5
7974dd1b BS	6	struct nvkm_device_tegra {
e396ecd1	7	const struct nvkm_device_tegra_func *func;
7974dd1b BS	8	struct nvkm_device device;
7974dd1b BS	9	struct platform_device *pdev;
2b700825	10	int irq;
43a70661 BS	11
	12	struct reset_control *rst;
	13	struct clk *clk;
34440ed6	14	struct clk *clk_ref;
43a70661 BS	15	struct clk *clk_pwr;
	16
	17	struct regulator *vdd;
	18
	19	struct {
	20	/*
	21	* Protects accesses to mm from subsystems
	22	*/
	23	struct mutex mutex;
	24
	25	struct nvkm_mm mm;
	26	struct iommu_domain *domain;
	27	unsigned long pgshift;
	28	} iommu;
	29
	30	int gpu_speedo;
7974dd1b BS	31	};
7974dd1b BS	32
e396ecd1 AC	33	struct nvkm_device_tegra_func {
	34	/*
	35	* If an IOMMU is used, indicates which address bit will trigger a
	36	* IOMMU translation when set (when this bit is not set, IOMMU is
	37	* bypassed). A value of 0 means an IOMMU is never used.
	38	*/
	39	u8 iommu_bit;
34440ed6 AC	40	/*
	41	* Whether the chip requires a reference clock
	42	*/
	43	bool require_ref_clk;
e396ecd1 AC	44	};
	45
	46	int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *,
	47	struct platform_device *,
7974dd1b BS	48	const char cfg, const char dbg,
	49	bool detect, bool mmio, u64 subdev_mask,
	50	struct nvkm_device **);
	51	#endif