[linux-2.6-block.git] / drivers / gpu / drm / nouveau / dispnv04 / disp.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __NV04_DISPLAY_H__
#define __NV04_DISPLAY_H__
#include <subdev/bios.h>
#include <subdev/bios/pll.h>

#include "nouveau_display.h"

enum nv04_fp_display_regs {
	FP_DISPLAY_END,
	FP_TOTAL,
	FP_CRTC,
	FP_SYNC_START,
	FP_SYNC_END,
	FP_VALID_START,
	FP_VALID_END
};

struct nv04_crtc_reg {
	unsigned char MiscOutReg;
	uint8_t CRTC[0xa0];
	uint8_t CR58[0x10];
	uint8_t Sequencer[5];
	uint8_t Graphics[9];
	uint8_t Attribute[21];
	unsigned char DAC[768];

	/* PCRTC regs */
	uint32_t fb_start;
	uint32_t crtc_cfg;
	uint32_t cursor_cfg;
	uint32_t gpio_ext;
	uint32_t crtc_830;
	uint32_t crtc_834;
	uint32_t crtc_850;
	uint32_t crtc_eng_ctrl;

	/* PRAMDAC regs */
	uint32_t nv10_cursync;
	struct nvkm_pll_vals pllvals;
	uint32_t ramdac_gen_ctrl;
	uint32_t ramdac_630;
	uint32_t ramdac_634;
	uint32_t tv_setup;
	uint32_t tv_vtotal;
	uint32_t tv_vskew;
	uint32_t tv_vsync_delay;
	uint32_t tv_htotal;
	uint32_t tv_hskew;
	uint32_t tv_hsync_delay;
	uint32_t tv_hsync_delay2;
	uint32_t fp_horiz_regs[7];
	uint32_t fp_vert_regs[7];
	uint32_t dither;
	uint32_t fp_control;
	uint32_t dither_regs[6];
	uint32_t fp_debug_0;
	uint32_t fp_debug_1;
	uint32_t fp_debug_2;
	uint32_t fp_margin_color;
	uint32_t ramdac_8c0;
	uint32_t ramdac_a20;
	uint32_t ramdac_a24;
	uint32_t ramdac_a34;
	uint32_t ctv_regs[38];
};

struct nv04_output_reg {
	uint32_t output;
	int head;
};

struct nv04_mode_state {
	struct nv04_crtc_reg crtc_reg[2];
	uint32_t pllsel;
	uint32_t sel_clk;
};

struct nv04_display {
	struct nv04_mode_state mode_reg;
	struct nv04_mode_state saved_reg;
	uint32_t saved_vga_font[4][16384];
	uint32_t dac_users[4];
	struct nouveau_bo *image[2];
	struct nvif_notify flip;
};

static inline struct nv04_display *
nv04_display(struct drm_device *dev)
{
	return nouveau_display(dev)->priv;
}

/* nv04_display.c */
int nv04_display_create(struct drm_device *);

/* nv04_crtc.c */
int nv04_crtc_create(struct drm_device *, int index);

/* nv04_dac.c */
int nv04_dac_create(struct drm_connector *, struct dcb_output *);
uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
int nv04_dac_output_offset(struct drm_encoder *encoder);
void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
bool nv04_dac_in_use(struct drm_encoder *encoder);

/* nv04_dfp.c */
int nv04_dfp_create(struct drm_connector *, struct dcb_output *);
int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent);
void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
			       int head, bool dl);
void nv04_dfp_disable(struct drm_device *dev, int head);
void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);

/* nv04_tv.c */
int nv04_tv_identify(struct drm_device *dev, int i2c_index);
int nv04_tv_create(struct drm_connector *, struct dcb_output *);

/* nv17_tv.c */
int nv17_tv_create(struct drm_connector *, struct dcb_output *);

/* overlay.c */
void nouveau_overlay_init(struct drm_device *dev);

static inline bool
nv_two_heads(struct drm_device *dev)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	const int impl = dev->pdev->device & 0x0ff0;

	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 &&
	    impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
		return true;

	return false;
}

static inline bool
nv_gf4_disp_arch(struct drm_device *dev)
{
	return nv_two_heads(dev) && (dev->pdev->device & 0x0ff0) != 0x0110;
}

static inline bool
nv_two_reg_pll(struct drm_device *dev)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	const int impl = dev->pdev->device & 0x0ff0;

	if (impl == 0x0310 || impl == 0x0340 || drm->client.device.info.family >= NV_DEVICE_INFO_V0_CURIE)
		return true;
	return false;
}

static inline bool
nv_match_device(struct drm_device *dev, unsigned device,
		unsigned sub_vendor, unsigned sub_device)
{
	return dev->pdev->device == device &&
		dev->pdev->subsystem_vendor == sub_vendor &&
		dev->pdev->subsystem_device == sub_device;
}

#include <subdev/bios.h>
#include <subdev/bios/init.h>

static inline void
nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
			    struct dcb_output *outp, int crtc)
{
	nvbios_init(&nvxx_bios(&nouveau_drm(dev)->client.device)->subdev, table,
		init.outp = outp;
		init.head = crtc;
	);
}

int nv04_flip_complete(struct nvif_notify *);
#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
017e6e29 BS	2	#ifndef __NV04_DISPLAY_H__
017e6e29 BS	3	#define __NV04_DISPLAY_H__
4dc28134	4	#include <subdev/bios.h>
51a3d342 BS	5	#include <subdev/bios/pll.h>
51a3d342 BS	6
77145f1c BS	7	#include "nouveau_display.h"
77145f1c BS	8
017e6e29 BS	9	enum nv04_fp_display_regs {
	10	FP_DISPLAY_END,
	11	FP_TOTAL,
	12	FP_CRTC,
	13	FP_SYNC_START,
	14	FP_SYNC_END,
	15	FP_VALID_START,
	16	FP_VALID_END
	17	};
	18
	19	struct nv04_crtc_reg {
	20	unsigned char MiscOutReg;
	21	uint8_t CRTC[0xa0];
	22	uint8_t CR58[0x10];
	23	uint8_t Sequencer[5];
	24	uint8_t Graphics[9];
	25	uint8_t Attribute[21];
	26	unsigned char DAC[768];
	27
	28	/* PCRTC regs */
	29	uint32_t fb_start;
	30	uint32_t crtc_cfg;
	31	uint32_t cursor_cfg;
	32	uint32_t gpio_ext;
	33	uint32_t crtc_830;
	34	uint32_t crtc_834;
	35	uint32_t crtc_850;
	36	uint32_t crtc_eng_ctrl;
	37
	38	/* PRAMDAC regs */
	39	uint32_t nv10_cursync;
be83cd4e	40	struct nvkm_pll_vals pllvals;
017e6e29 BS	41	uint32_t ramdac_gen_ctrl;
	42	uint32_t ramdac_630;
	43	uint32_t ramdac_634;
	44	uint32_t tv_setup;
	45	uint32_t tv_vtotal;
	46	uint32_t tv_vskew;
	47	uint32_t tv_vsync_delay;
	48	uint32_t tv_htotal;
	49	uint32_t tv_hskew;
	50	uint32_t tv_hsync_delay;
	51	uint32_t tv_hsync_delay2;
	52	uint32_t fp_horiz_regs[7];
	53	uint32_t fp_vert_regs[7];
	54	uint32_t dither;
	55	uint32_t fp_control;
	56	uint32_t dither_regs[6];
	57	uint32_t fp_debug_0;
	58	uint32_t fp_debug_1;
	59	uint32_t fp_debug_2;
	60	uint32_t fp_margin_color;
	61	uint32_t ramdac_8c0;
	62	uint32_t ramdac_a20;
	63	uint32_t ramdac_a24;
	64	uint32_t ramdac_a34;
	65	uint32_t ctv_regs[38];
	66	};
	67
	68	struct nv04_output_reg {
	69	uint32_t output;
	70	int head;
	71	};
	72
	73	struct nv04_mode_state {
	74	struct nv04_crtc_reg crtc_reg[2];
	75	uint32_t pllsel;
	76	uint32_t sel_clk;
	77	};
	78
	79	struct nv04_display {
	80	struct nv04_mode_state mode_reg;
	81	struct nv04_mode_state saved_reg;
	82	uint32_t saved_vga_font[4][16384];
	83	uint32_t dac_users[4];
78ae0ad4	84	struct nouveau_bo *image[2];
fcd6f048	85	struct nvif_notify flip;
017e6e29 BS	86	};
017e6e29 BS	87
77145f1c BS	88	static inline struct nv04_display *
	89	nv04_display(struct drm_device *dev)
	90	{
	91	return nouveau_display(dev)->priv;
	92	}
	93
017e6e29	94	/* nv04_display.c */
017e6e29	95	int nv04_display_create(struct drm_device *);
017e6e29 BS	96
	97	/* nv04_crtc.c */
	98	int nv04_crtc_create(struct drm_device *, int index);
	99
	100	/* nv04_dac.c */
	101	int nv04_dac_create(struct drm_connector , struct dcb_output );
	102	uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
	103	int nv04_dac_output_offset(struct drm_encoder *encoder);
	104	void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
	105	bool nv04_dac_in_use(struct drm_encoder *encoder);
	106
	107	/* nv04_dfp.c */
	108	int nv04_dfp_create(struct drm_connector , struct dcb_output );
	109	int nv04_dfp_get_bound_head(struct drm_device dev, struct dcb_output dcbent);
	110	void nv04_dfp_bind_head(struct drm_device dev, struct dcb_output dcbent,
	111	int head, bool dl);
	112	void nv04_dfp_disable(struct drm_device *dev, int head);
	113	void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
	114
	115	/* nv04_tv.c */
	116	int nv04_tv_identify(struct drm_device *dev, int i2c_index);
	117	int nv04_tv_create(struct drm_connector , struct dcb_output );
	118
	119	/* nv17_tv.c */
	120	int nv17_tv_create(struct drm_connector , struct dcb_output );
	121
515de6b2 IM	122	/* overlay.c */
	123	void nouveau_overlay_init(struct drm_device *dev);
	124
77145f1c BS	125	static inline bool
	126	nv_two_heads(struct drm_device *dev)
	127	{
	128	struct nouveau_drm *drm = nouveau_drm(dev);
ffbab09b	129	const int impl = dev->pdev->device & 0x0ff0;
77145f1c	130
1167c6bc	131	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 &&
77145f1c BS	132	impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
	133	return true;
	134
	135	return false;
	136	}
	137
	138	static inline bool
	139	nv_gf4_disp_arch(struct drm_device *dev)
	140	{
ffbab09b	141	return nv_two_heads(dev) && (dev->pdev->device & 0x0ff0) != 0x0110;
77145f1c BS	142	}
	143
	144	static inline bool
	145	nv_two_reg_pll(struct drm_device *dev)
	146	{
	147	struct nouveau_drm *drm = nouveau_drm(dev);
ffbab09b	148	const int impl = dev->pdev->device & 0x0ff0;
77145f1c	149
1167c6bc	150	if (impl == 0x0310 \|\| impl == 0x0340 \|\| drm->client.device.info.family >= NV_DEVICE_INFO_V0_CURIE)
77145f1c BS	151	return true;
	152	return false;
	153	}
	154
	155	static inline bool
	156	nv_match_device(struct drm_device *dev, unsigned device,
	157	unsigned sub_vendor, unsigned sub_device)
	158	{
	159	return dev->pdev->device == device &&
	160	dev->pdev->subsystem_vendor == sub_vendor &&
	161	dev->pdev->subsystem_device == sub_device;
	162	}
	163
	164	#include <subdev/bios.h>
	165	#include <subdev/bios/init.h>
	166
	167	static inline void
	168	nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
	169	struct dcb_output *outp, int crtc)
	170	{
639d72e2 BS	171	nvbios_init(&nvxx_bios(&nouveau_drm(dev)->client.device)->subdev, table,
	172	init.outp = outp;
	173	init.head = crtc;
	174	);
77145f1c BS	175	}
77145f1c BS	176
fcd6f048	177	int nv04_flip_complete(struct nvif_notify *);
017e6e29	178	#endif