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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski...
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_crt.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
8ca4013d 27#include <linux/dmi.h>
79e53945 28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
760285e7 30#include <drm/drmP.h>
c6f95f27 31#include <drm/drm_atomic_helper.h>
760285e7
DH		 32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
79e53945 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38
e7dbb2f2
KP		 39/* Here's the desired hotplug mode */
40#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
41 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
42 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
43 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
44 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
45 ADPA_CRT_HOTPLUG_ENABLE)
46
c9a1c4cd
CW		 47struct intel_crt {
48 struct intel_encoder base;
637f44d2
AJ		 49 /* DPMS state is stored in the connector, which we need in the
50 * encoder's enable/disable callbacks */
51 struct intel_connector *connector;
e7dbb2f2 52 bool force_hotplug_required;
f0f59a00 53 i915_reg_t adpa_reg;
c9a1c4cd
CW		 54};
55
eebe6f0b 56static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
c9a1c4cd 57{
eebe6f0b 58 return container_of(encoder, struct intel_crt, base);
c9a1c4cd
CW		 59}
60
eebe6f0b 61static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
79e53945 62{
eebe6f0b 63 return intel_encoder_to_crt(intel_attached_encoder(connector));
540a8950
DV		 64}
65
e403fc94
DV		 66static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
67 enum pipe *pipe)
79e53945 68{
e403fc94 69 struct drm_device *dev = encoder->base.dev;
79e53945 70 struct drm_i915_private *dev_priv = dev->dev_private;
e403fc94 71 struct intel_crt *crt = intel_encoder_to_crt(encoder);
6d129bea 72 enum intel_display_power_domain power_domain;
e403fc94 73 u32 tmp;
1c8fdda1 74 bool ret;
e403fc94 75
6d129bea 76 power_domain = intel_display_port_power_domain(encoder);
1c8fdda1 77 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 78 return false;
79
1c8fdda1
ID		 80 ret = false;
81
e403fc94
DV		 82 tmp = I915_READ(crt->adpa_reg);
83
84 if (!(tmp & ADPA_DAC_ENABLE))
1c8fdda1 85 goto out;
e403fc94
DV		 86
87 if (HAS_PCH_CPT(dev))
88 *pipe = PORT_TO_PIPE_CPT(tmp);
89 else
90 *pipe = PORT_TO_PIPE(tmp);
91
1c8fdda1
ID		 92 ret = true;
93out:
94 intel_display_power_put(dev_priv, power_domain);
95
96 return ret;
e403fc94
DV		 97}
98
6801c18c 99static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
045ac3b5
JB		 100{
101 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
102 struct intel_crt *crt = intel_encoder_to_crt(encoder);
103 u32 tmp, flags = 0;
104
105 tmp = I915_READ(crt->adpa_reg);
106
107 if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
108 flags |= DRM_MODE_FLAG_PHSYNC;
109 else
110 flags |= DRM_MODE_FLAG_NHSYNC;
111
112 if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
113 flags |= DRM_MODE_FLAG_PVSYNC;
114 else
115 flags |= DRM_MODE_FLAG_NVSYNC;
116
6801c18c
VS		 117 return flags;
118}
119
120static void intel_crt_get_config(struct intel_encoder *encoder,
5cec258b 121 struct intel_crtc_state *pipe_config)
6801c18c
VS		 122{
123 struct drm_device *dev = encoder->base.dev;
124 int dotclock;
125
2d112de7 126 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
18442d08
VS		 127
128 dotclock = pipe_config->port_clock;
129
6801c18c 130 if (HAS_PCH_SPLIT(dev))
18442d08
VS		 131 ironlake_check_encoder_dotclock(pipe_config, dotclock);
132
2d112de7 133 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
045ac3b5
JB		 134}
135
6801c18c 136static void hsw_crt_get_config(struct intel_encoder *encoder,
5cec258b 137 struct intel_crtc_state *pipe_config)
6801c18c
VS		 138{
139 intel_ddi_get_config(encoder, pipe_config);
140
2d112de7 141 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
6801c18c
VS		 142 DRM_MODE_FLAG_NHSYNC |
143 DRM_MODE_FLAG_PVSYNC |
144 DRM_MODE_FLAG_NVSYNC);
2d112de7 145 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
6801c18c
VS		 146}
147
b2cabb0e
DV		 148/* Note: The caller is required to filter out dpms modes not supported by the
149 * platform. */
150static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
df0323c4 151{
b2cabb0e 152 struct drm_device *dev = encoder->base.dev;
df0323c4 153 struct drm_i915_private *dev_priv = dev->dev_private;
b2cabb0e 154 struct intel_crt *crt = intel_encoder_to_crt(encoder);
894ed1ec 155 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 156 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
894ed1ec
DV		 157 u32 adpa;
158
159 if (INTEL_INFO(dev)->gen >= 5)
160 adpa = ADPA_HOTPLUG_BITS;
161 else
162 adpa = 0;
df0323c4 163
894ed1ec
DV		 164 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
165 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
166 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
167 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
168
169 /* For CPT allow 3 pipe config, for others just use A or B */
170 if (HAS_PCH_LPT(dev))
171 ; /* Those bits don't exist here */
172 else if (HAS_PCH_CPT(dev))
173 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
174 else if (crtc->pipe == 0)
175 adpa |= ADPA_PIPE_A_SELECT;
176 else
177 adpa |= ADPA_PIPE_B_SELECT;
178
179 if (!HAS_PCH_SPLIT(dev))
180 I915_WRITE(BCLRPAT(crtc->pipe), 0);
79e53945 181
0206e353 182 switch (mode) {
79e53945 183 case DRM_MODE_DPMS_ON:
894ed1ec 184 adpa |= ADPA_DAC_ENABLE;
79e53945
JB		 185 break;
186 case DRM_MODE_DPMS_STANDBY:
894ed1ec 187 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
79e53945
JB		 188 break;
189 case DRM_MODE_DPMS_SUSPEND:
894ed1ec 190 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
79e53945
JB		 191 break;
192 case DRM_MODE_DPMS_OFF:
894ed1ec 193 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
79e53945
JB		 194 break;
195 }
196
894ed1ec 197 I915_WRITE(crt->adpa_reg, adpa);
df0323c4 198}
2c07245f 199
637f44d2
AJ		 200static void intel_disable_crt(struct intel_encoder *encoder)
201{
202 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
203}
204
1ea56e26
VS		 205static void pch_disable_crt(struct intel_encoder *encoder)
206{
207}
208
209static void pch_post_disable_crt(struct intel_encoder *encoder)
210{
211 intel_disable_crt(encoder);
212}
abfdc1e3 213
637f44d2
AJ		 214static void intel_enable_crt(struct intel_encoder *encoder)
215{
7bb4afb4 216 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_ON);
637f44d2
AJ		 217}
218
c19de8eb
DL		 219static enum drm_mode_status
220intel_crt_mode_valid(struct drm_connector *connector,
221 struct drm_display_mode *mode)
79e53945 222{
6bcdcd9e 223 struct drm_device *dev = connector->dev;
f8700b34 224 int max_dotclk = to_i915(dev)->max_dotclk_freq;
6bcdcd9e
ZY		 225
226 int max_clock = 0;
79e53945
JB		 227 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
228 return MODE_NO_DBLESCAN;
229
6bcdcd9e
ZY		 230 if (mode->clock < 25000)
231 return MODE_CLOCK_LOW;
232
a6c45cf0 233 if (IS_GEN2(dev))
6bcdcd9e
ZY		 234 max_clock = 350000;
235 else
236 max_clock = 400000;
237 if (mode->clock > max_clock)
238 return MODE_CLOCK_HIGH;
79e53945 239
f8700b34
MK		 240 if (mode->clock > max_dotclk)
241 return MODE_CLOCK_HIGH;
242
d4b1931c
PZ		 243 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
244 if (HAS_PCH_LPT(dev) &&
245 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
246 return MODE_CLOCK_HIGH;
247
79e53945
JB		 248 return MODE_OK;
249}
250
5bfe2ac0 251static bool intel_crt_compute_config(struct intel_encoder *encoder,
5cec258b 252 struct intel_crtc_state *pipe_config)
79e53945 253{
5bfe2ac0
DV		 254 struct drm_device *dev = encoder->base.dev;
255
256 if (HAS_PCH_SPLIT(dev))
257 pipe_config->has_pch_encoder = true;
258
2a7aceec 259 /* LPT FDI RX only supports 8bpc. */
2700818a
DV		 260 if (HAS_PCH_LPT(dev)) {
261 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
262 DRM_DEBUG_KMS("LPT only supports 24bpp\n");
263 return false;
264 }
265
2a7aceec 266 pipe_config->pipe_bpp = 24;
2700818a 267 }
2a7aceec 268
8f7abfd8 269 /* FDI must always be 2.7 GHz */
0e50338c
DV		 270 if (HAS_DDI(dev)) {
271 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
8f7abfd8 272 pipe_config->port_clock = 135000 * 2;
00490c22
ML		 273
274 pipe_config->dpll_hw_state.wrpll = 0;
275 pipe_config->dpll_hw_state.spll =
276 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
0e50338c 277 }
8f7abfd8 278
79e53945
JB		 279 return true;
280}
281
f2b115e6 282static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
2c07245f
ZW		 283{
284 struct drm_device *dev = connector->dev;
e7dbb2f2 285 struct intel_crt *crt = intel_attached_crt(connector);
2c07245f 286 struct drm_i915_private *dev_priv = dev->dev_private;
e7dbb2f2 287 u32 adpa;
2c07245f
ZW		 288 bool ret;
289
e7dbb2f2
KP		 290 /* The first time through, trigger an explicit detection cycle */
291 if (crt->force_hotplug_required) {
292 bool turn_off_dac = HAS_PCH_SPLIT(dev);
293 u32 save_adpa;
67941da2 294
e7dbb2f2
KP		 295 crt->force_hotplug_required = 0;
296
ca54b810 297 save_adpa = adpa = I915_READ(crt->adpa_reg);
e7dbb2f2
KP		 298 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
299
300 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
301 if (turn_off_dac)
302 adpa &= ~ADPA_DAC_ENABLE;
303
ca54b810 304 I915_WRITE(crt->adpa_reg, adpa);
e7dbb2f2 305
ca54b810 306 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
e7dbb2f2
KP		 307 1000))
308 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
309
310 if (turn_off_dac) {
ca54b810
VS		 311 I915_WRITE(crt->adpa_reg, save_adpa);
312 POSTING_READ(crt->adpa_reg);
e7dbb2f2 313 }
a4a6b901
ZW		 314 }
315
2c07245f 316 /* Check the status to see if both blue and green are on now */
ca54b810 317 adpa = I915_READ(crt->adpa_reg);
e7dbb2f2 318 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
2c07245f
ZW		 319 ret = true;
320 else
321 ret = false;
e7dbb2f2 322 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
2c07245f 323
2c07245f 324 return ret;
79e53945
JB		 325}
326
7d2c24e8
JB		 327static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
328{
329 struct drm_device *dev = connector->dev;
ca54b810 330 struct intel_crt *crt = intel_attached_crt(connector);
7d2c24e8
JB		 331 struct drm_i915_private *dev_priv = dev->dev_private;
332 u32 adpa;
333 bool ret;
334 u32 save_adpa;
335
ca54b810 336 save_adpa = adpa = I915_READ(crt->adpa_reg);
7d2c24e8
JB		 337 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
338
339 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
340
ca54b810 341 I915_WRITE(crt->adpa_reg, adpa);
7d2c24e8 342
ca54b810 343 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
7d2c24e8
JB		 344 1000)) {
345 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
ca54b810 346 I915_WRITE(crt->adpa_reg, save_adpa);
7d2c24e8
JB		 347 }
348
349 /* Check the status to see if both blue and green are on now */
ca54b810 350 adpa = I915_READ(crt->adpa_reg);
7d2c24e8
JB		 351 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
352 ret = true;
353 else
354 ret = false;
355
356 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
357
7d2c24e8
JB		 358 return ret;
359}
360
79e53945
JB		 361/**
362 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
363 *
364 * Not for i915G/i915GM
365 *
366 * \return true if CRT is connected.
367 * \return false if CRT is disconnected.
368 */
369static bool intel_crt_detect_hotplug(struct drm_connector *connector)
370{
371 struct drm_device *dev = connector->dev;
372 struct drm_i915_private *dev_priv = dev->dev_private;
0706f17c 373 u32 stat;
7a772c49 374 bool ret = false;
771cb081 375 int i, tries = 0;
2c07245f 376
bad720ff 377 if (HAS_PCH_SPLIT(dev))
f2b115e6 378 return intel_ironlake_crt_detect_hotplug(connector);
2c07245f 379
7d2c24e8
JB		 380 if (IS_VALLEYVIEW(dev))
381 return valleyview_crt_detect_hotplug(connector);
382
771cb081
ZY		 383 /*
384 * On 4 series desktop, CRT detect sequence need to be done twice
385 * to get a reliable result.
386 */
79e53945 387
771cb081
ZY		 388 if (IS_G4X(dev) && !IS_GM45(dev))
389 tries = 2;
390 else
391 tries = 1;
771cb081 392
771cb081 393 for (i = 0; i < tries ; i++) {
771cb081 394 /* turn on the FORCE_DETECT */
0706f17c
EE		 395 i915_hotplug_interrupt_update(dev_priv,
396 CRT_HOTPLUG_FORCE_DETECT,
397 CRT_HOTPLUG_FORCE_DETECT);
771cb081 398 /* wait for FORCE_DETECT to go off */
913d8d11
CW		 399 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
400 CRT_HOTPLUG_FORCE_DETECT) == 0,
481b6af3 401 1000))
79077319 402 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
771cb081 403 }
79e53945 404
7a772c49
AJ		 405 stat = I915_READ(PORT_HOTPLUG_STAT);
406 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
407 ret = true;
408
409 /* clear the interrupt we just generated, if any */
410 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
79e53945 411
0706f17c 412 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
7a772c49
AJ		 413
414 return ret;
79e53945
JB		 415}
416
f1a2f5b7
JN		 417static struct edid *intel_crt_get_edid(struct drm_connector *connector,
418 struct i2c_adapter *i2c)
419{
420 struct edid *edid;
421
422 edid = drm_get_edid(connector, i2c);
423
424 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
425 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
426 intel_gmbus_force_bit(i2c, true);
427 edid = drm_get_edid(connector, i2c);
428 intel_gmbus_force_bit(i2c, false);
429 }
430
431 return edid;
432}
433
434/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
435static int intel_crt_ddc_get_modes(struct drm_connector *connector,
436 struct i2c_adapter *adapter)
437{
438 struct edid *edid;
ebda95a9 439 int ret;
f1a2f5b7
JN		 440
441 edid = intel_crt_get_edid(connector, adapter);
442 if (!edid)
443 return 0;
444
ebda95a9
JN		 445 ret = intel_connector_update_modes(connector, edid);
446 kfree(edid);
447
448 return ret;
f1a2f5b7
JN		 449}
450
f5afcd3d 451static bool intel_crt_detect_ddc(struct drm_connector *connector)
79e53945 452{
f5afcd3d 453 struct intel_crt *crt = intel_attached_crt(connector);
c9a1c4cd 454 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
a2bd1f54
DV		 455 struct edid *edid;
456 struct i2c_adapter *i2c;
79e53945 457
a2bd1f54 458 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
79e53945 459
41aa3448 460 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
f1a2f5b7 461 edid = intel_crt_get_edid(connector, i2c);
a2bd1f54
DV		 462
463 if (edid) {
464 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
f5afcd3d 465
f5afcd3d
DM		 466 /*
467 * This may be a DVI-I connector with a shared DDC
468 * link between analog and digital outputs, so we
469 * have to check the EDID input spec of the attached device.
470 */
f5afcd3d
DM		 471 if (!is_digital) {
472 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
473 return true;
474 }
a2bd1f54
DV		 475
476 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
477 } else {
478 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
6ec3d0c0
CW		 479 }
480
a2bd1f54
DV		 481 kfree(edid);
482
6ec3d0c0 483 return false;
79e53945
JB		 484}
485
e4a5d54f 486static enum drm_connector_status
c8ecb2f1 487intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
e4a5d54f 488{
7173188d 489 struct drm_device *dev = crt->base.base.dev;
e4a5d54f 490 struct drm_i915_private *dev_priv = dev->dev_private;
e4a5d54f
ML		 491 uint32_t save_bclrpat;
492 uint32_t save_vtotal;
493 uint32_t vtotal, vactive;
494 uint32_t vsample;
495 uint32_t vblank, vblank_start, vblank_end;
496 uint32_t dsl;
f0f59a00
VS		 497 i915_reg_t bclrpat_reg, vtotal_reg,
498 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
e4a5d54f
ML		 499 uint8_t st00;
500 enum drm_connector_status status;
501
6ec3d0c0
CW		 502 DRM_DEBUG_KMS("starting load-detect on CRT\n");
503
9db4a9c7
JB		 504 bclrpat_reg = BCLRPAT(pipe);
505 vtotal_reg = VTOTAL(pipe);
506 vblank_reg = VBLANK(pipe);
507 vsync_reg = VSYNC(pipe);
508 pipeconf_reg = PIPECONF(pipe);
509 pipe_dsl_reg = PIPEDSL(pipe);
e4a5d54f
ML		 510
511 save_bclrpat = I915_READ(bclrpat_reg);
512 save_vtotal = I915_READ(vtotal_reg);
513 vblank = I915_READ(vblank_reg);
514
515 vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
516 vactive = (save_vtotal & 0x7ff) + 1;
517
518 vblank_start = (vblank & 0xfff) + 1;
519 vblank_end = ((vblank >> 16) & 0xfff) + 1;
520
521 /* Set the border color to purple. */
522 I915_WRITE(bclrpat_reg, 0x500050);
523
a6c45cf0 524 if (!IS_GEN2(dev)) {
e4a5d54f
ML		 525 uint32_t pipeconf = I915_READ(pipeconf_reg);
526 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
19c55da1 527 POSTING_READ(pipeconf_reg);
e4a5d54f
ML		 528 /* Wait for next Vblank to substitue
529 * border color for Color info */
9d0498a2 530 intel_wait_for_vblank(dev, pipe);
f0f59a00 531 st00 = I915_READ8(_VGA_MSR_WRITE);
e4a5d54f
ML		 532 status = ((st00 & (1 << 4)) != 0) ?
533 connector_status_connected :
534 connector_status_disconnected;
535
536 I915_WRITE(pipeconf_reg, pipeconf);
537 } else {
538 bool restore_vblank = false;
539 int count, detect;
540
541 /*
542 * If there isn't any border, add some.
543 * Yes, this will flicker
544 */
545 if (vblank_start <= vactive && vblank_end >= vtotal) {
546 uint32_t vsync = I915_READ(vsync_reg);
547 uint32_t vsync_start = (vsync & 0xffff) + 1;
548
549 vblank_start = vsync_start;
550 I915_WRITE(vblank_reg,
551 (vblank_start - 1) |
552 ((vblank_end - 1) << 16));
553 restore_vblank = true;
554 }
555 /* sample in the vertical border, selecting the larger one */
556 if (vblank_start - vactive >= vtotal - vblank_end)
557 vsample = (vblank_start + vactive) >> 1;
558 else
559 vsample = (vtotal + vblank_end) >> 1;
560
561 /*
562 * Wait for the border to be displayed
563 */
564 while (I915_READ(pipe_dsl_reg) >= vactive)
565 ;
566 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
567 ;
568 /*
569 * Watch ST00 for an entire scanline
570 */
571 detect = 0;
572 count = 0;
573 do {
574 count++;
575 /* Read the ST00 VGA status register */
f0f59a00 576 st00 = I915_READ8(_VGA_MSR_WRITE);
e4a5d54f
ML		 577 if (st00 & (1 << 4))
578 detect++;
579 } while ((I915_READ(pipe_dsl_reg) == dsl));
580
581 /* restore vblank if necessary */
582 if (restore_vblank)
583 I915_WRITE(vblank_reg, vblank);
584 /*
585 * If more than 3/4 of the scanline detected a monitor,
586 * then it is assumed to be present. This works even on i830,
587 * where there isn't any way to force the border color across
588 * the screen
589 */
590 status = detect * 4 > count * 3 ?
591 connector_status_connected :
592 connector_status_disconnected;
593 }
594
595 /* Restore previous settings */
596 I915_WRITE(bclrpat_reg, save_bclrpat);
597
598 return status;
599}
600
7b334fcb 601static enum drm_connector_status
930a9e28 602intel_crt_detect(struct drm_connector *connector, bool force)
79e53945
JB		 603{
604 struct drm_device *dev = connector->dev;
c19a0df2 605 struct drm_i915_private *dev_priv = dev->dev_private;
c9a1c4cd 606 struct intel_crt *crt = intel_attached_crt(connector);
671dedd2
ID		 607 struct intel_encoder *intel_encoder = &crt->base;
608 enum intel_display_power_domain power_domain;
e4a5d54f 609 enum drm_connector_status status;
e95c8438 610 struct intel_load_detect_pipe tmp;
51fd371b 611 struct drm_modeset_acquire_ctx ctx;
79e53945 612
164c8598 613 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
c23cc417 614 connector->base.id, connector->name,
164c8598
CW		 615 force);
616
671dedd2
ID		 617 power_domain = intel_display_port_power_domain(intel_encoder);
618 intel_display_power_get(dev_priv, power_domain);
619
a6c45cf0 620 if (I915_HAS_HOTPLUG(dev)) {
aaa37730
DV		 621 /* We can not rely on the HPD pin always being correctly wired
622 * up, for example many KVM do not pass it through, and so
623 * only trust an assertion that the monitor is connected.
624 */
6ec3d0c0
CW		 625 if (intel_crt_detect_hotplug(connector)) {
626 DRM_DEBUG_KMS("CRT detected via hotplug\n");
c19a0df2
PZ		 627 status = connector_status_connected;
628 goto out;
aaa37730 629 } else
e7dbb2f2 630 DRM_DEBUG_KMS("CRT not detected via hotplug\n");
79e53945
JB		 631 }
632
c19a0df2
PZ		 633 if (intel_crt_detect_ddc(connector)) {
634 status = connector_status_connected;
635 goto out;
636 }
79e53945 637
aaa37730
DV		 638 /* Load detection is broken on HPD capable machines. Whoever wants a
639 * broken monitor (without edid) to work behind a broken kvm (that fails
640 * to have the right resistors for HP detection) needs to fix this up.
641 * For now just bail out. */
5bedeb2d 642 if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
c19a0df2
PZ		 643 status = connector_status_disconnected;
644 goto out;
645 }
aaa37730 646
c19a0df2
PZ		 647 if (!force) {
648 status = connector->status;
649 goto out;
650 }
7b334fcb 651
208bf9fd
VS		 652 drm_modeset_acquire_init(&ctx, 0);
653
e4a5d54f 654 /* for pre-945g platforms use load detect */
51fd371b 655 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
e95c8438
DV		 656 if (intel_crt_detect_ddc(connector))
657 status = connector_status_connected;
5bedeb2d 658 else if (INTEL_INFO(dev)->gen < 4)
c8ecb2f1
ML		 659 status = intel_crt_load_detect(crt,
660 to_intel_crtc(connector->state->crtc)->pipe);
5bedeb2d
DV		 661 else
662 status = connector_status_unknown;
49172fee 663 intel_release_load_detect_pipe(connector, &tmp, &ctx);
e95c8438
DV		 664 } else
665 status = connector_status_unknown;
e4a5d54f 666
208bf9fd
VS		 667 drm_modeset_drop_locks(&ctx);
668 drm_modeset_acquire_fini(&ctx);
669
c19a0df2 670out:
671dedd2 671 intel_display_power_put(dev_priv, power_domain);
e4a5d54f 672 return status;
79e53945
JB		 673}
674
675static void intel_crt_destroy(struct drm_connector *connector)
676{
79e53945
JB		 677 drm_connector_cleanup(connector);
678 kfree(connector);
679}
680
681static int intel_crt_get_modes(struct drm_connector *connector)
682{
8e4d36b9 683 struct drm_device *dev = connector->dev;
f899fc64 684 struct drm_i915_private *dev_priv = dev->dev_private;
671dedd2
ID		 685 struct intel_crt *crt = intel_attached_crt(connector);
686 struct intel_encoder *intel_encoder = &crt->base;
687 enum intel_display_power_domain power_domain;
890f3359 688 int ret;
3bd7d909 689 struct i2c_adapter *i2c;
8e4d36b9 690
671dedd2
ID		 691 power_domain = intel_display_port_power_domain(intel_encoder);
692 intel_display_power_get(dev_priv, power_domain);
693
41aa3448 694 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
f1a2f5b7 695 ret = intel_crt_ddc_get_modes(connector, i2c);
8e4d36b9 696 if (ret || !IS_G4X(dev))
671dedd2 697 goto out;
8e4d36b9 698
8e4d36b9 699 /* Try to probe digital port for output in DVI-I -> VGA mode. */
988c7015 700 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
671dedd2
ID		 701 ret = intel_crt_ddc_get_modes(connector, i2c);
702
703out:
704 intel_display_power_put(dev_priv, power_domain);
705
706 return ret;
79e53945
JB		 707}
708
709static int intel_crt_set_property(struct drm_connector *connector,
710 struct drm_property *property,
711 uint64_t value)
712{
79e53945
JB		 713 return 0;
714}
715
f3269058
CW		 716static void intel_crt_reset(struct drm_connector *connector)
717{
718 struct drm_device *dev = connector->dev;
2e938892 719 struct drm_i915_private *dev_priv = dev->dev_private;
f3269058
CW		 720 struct intel_crt *crt = intel_attached_crt(connector);
721
10603caa 722 if (INTEL_INFO(dev)->gen >= 5) {
2e938892
DV		 723 u32 adpa;
724
ca54b810 725 adpa = I915_READ(crt->adpa_reg);
2e938892
DV		 726 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
727 adpa |= ADPA_HOTPLUG_BITS;
ca54b810
VS		 728 I915_WRITE(crt->adpa_reg, adpa);
729 POSTING_READ(crt->adpa_reg);
2e938892 730
0039a4b3 731 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
f3269058 732 crt->force_hotplug_required = 1;
2e938892
DV		 733 }
734
f3269058
CW		 735}
736
79e53945
JB		 737/*
738 * Routines for controlling stuff on the analog port
739 */
740
79e53945 741static const struct drm_connector_funcs intel_crt_connector_funcs = {
f3269058 742 .reset = intel_crt_reset,
4d688a2a 743 .dpms = drm_atomic_helper_connector_dpms,
79e53945
JB		 744 .detect = intel_crt_detect,
745 .fill_modes = drm_helper_probe_single_connector_modes,
746 .destroy = intel_crt_destroy,
747 .set_property = intel_crt_set_property,
c6f95f27 748 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 749 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2545e4a6 750 .atomic_get_property = intel_connector_atomic_get_property,
79e53945
JB		 751};
752
753static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
754 .mode_valid = intel_crt_mode_valid,
755 .get_modes = intel_crt_get_modes,
df0e9248 756 .best_encoder = intel_best_encoder,
79e53945
JB		 757};
758
79e53945 759static const struct drm_encoder_funcs intel_crt_enc_funcs = {
ea5b213a 760 .destroy = intel_encoder_destroy,
79e53945
JB		 761};
762
bbe1c274 763static int intel_no_crt_dmi_callback(const struct dmi_system_id *id)
8ca4013d 764{
bc0daf48 765 DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
8ca4013d
DL		 766 return 1;
767}
768
769static const struct dmi_system_id intel_no_crt[] = {
770 {
771 .callback = intel_no_crt_dmi_callback,
772 .ident = "ACER ZGB",
773 .matches = {
774 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
775 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
776 },
777 },
10b6ee4a
GC		 778 {
779 .callback = intel_no_crt_dmi_callback,
780 .ident = "DELL XPS 8700",
781 .matches = {
782 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
783 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"),
784 },
785 },
8ca4013d
DL		 786 { }
787};
788
79e53945
JB		 789void intel_crt_init(struct drm_device *dev)
790{
791 struct drm_connector *connector;
c9a1c4cd 792 struct intel_crt *crt;
454c1ca8 793 struct intel_connector *intel_connector;
db545019 794 struct drm_i915_private *dev_priv = dev->dev_private;
6c03a6bd
VS		 795 i915_reg_t adpa_reg;
796 u32 adpa;
79e53945 797
8ca4013d
DL		 798 /* Skip machines without VGA that falsely report hotplug events */
799 if (dmi_check_system(intel_no_crt))
800 return;
801
6c03a6bd
VS		 802 if (HAS_PCH_SPLIT(dev))
803 adpa_reg = PCH_ADPA;
804 else if (IS_VALLEYVIEW(dev))
805 adpa_reg = VLV_ADPA;
806 else
807 adpa_reg = ADPA;
808
809 adpa = I915_READ(adpa_reg);
810 if ((adpa & ADPA_DAC_ENABLE) == 0) {
811 /*
812 * On some machines (some IVB at least) CRT can be
813 * fused off, but there's no known fuse bit to
814 * indicate that. On these machine the ADPA register
815 * works normally, except the DAC enable bit won't
816 * take. So the only way to tell is attempt to enable
817 * it and see what happens.
818 */
819 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
820 ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
821 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
822 return;
823 I915_WRITE(adpa_reg, adpa);
824 }
825
c9a1c4cd
CW		 826 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
827 if (!crt)
79e53945
JB		 828 return;
829
9bdbd0b9 830 intel_connector = intel_connector_alloc();
454c1ca8 831 if (!intel_connector) {
c9a1c4cd 832 kfree(crt);
454c1ca8
ZW		 833 return;
834 }
835
836 connector = &intel_connector->base;
637f44d2 837 crt->connector = intel_connector;
454c1ca8 838 drm_connector_init(dev, &intel_connector->base,
79e53945
JB		 839 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
840
c9a1c4cd 841 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
13a3d91f 842 DRM_MODE_ENCODER_DAC, NULL);
79e53945 843
c9a1c4cd 844 intel_connector_attach_encoder(intel_connector, &crt->base);
79e53945 845
c9a1c4cd 846 crt->base.type = INTEL_OUTPUT_ANALOG;
301ea74a 847 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
d63fa0dc 848 if (IS_I830(dev))
59c859d6
ED		 849 crt->base.crtc_mask = (1 << 0);
850 else
0826874a 851 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
59c859d6 852
dbb02575
DV		 853 if (IS_GEN2(dev))
854 connector->interlace_allowed = 0;
855 else
856 connector->interlace_allowed = 1;
79e53945
JB		 857 connector->doublescan_allowed = 0;
858
6c03a6bd 859 crt->adpa_reg = adpa_reg;
540a8950 860
5bfe2ac0 861 crt->base.compute_config = intel_crt_compute_config;
92966a37 862 if (HAS_PCH_SPLIT(dev)) {
1ea56e26
VS		 863 crt->base.disable = pch_disable_crt;
864 crt->base.post_disable = pch_post_disable_crt;
865 } else {
866 crt->base.disable = intel_disable_crt;
867 }
2124604b 868 crt->base.enable = intel_enable_crt;
1d843f9d
EE		 869 if (I915_HAS_HOTPLUG(dev))
870 crt->base.hpd_pin = HPD_CRT;
a2985791
VS		 871 if (HAS_DDI(dev)) {
872 crt->base.get_config = hsw_crt_get_config;
4eda01b2 873 crt->base.get_hw_state = intel_ddi_get_hw_state;
a2985791
VS		 874 } else {
875 crt->base.get_config = intel_crt_get_config;
4eda01b2 876 crt->base.get_hw_state = intel_crt_get_hw_state;
a2985791 877 }
e403fc94 878 intel_connector->get_hw_state = intel_connector_get_hw_state;
4932e2c3 879 intel_connector->unregister = intel_connector_unregister;
df0323c4 880
79e53945
JB		 881 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
882
34ea3d38 883 drm_connector_register(connector);
b01f2c3a 884
821450c6
EE		 885 if (!I915_HAS_HOTPLUG(dev))
886 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
eb1f8e4f 887
e7dbb2f2
KP		 888 /*
889 * Configure the automatic hotplug detection stuff
890 */
891 crt->force_hotplug_required = 0;
e7dbb2f2 892
68d18ad7 893 /*
3e68320e
DL		 894 * TODO: find a proper way to discover whether we need to set the the
895 * polarity and link reversal bits or not, instead of relying on the
896 * BIOS.
68d18ad7 897 */
3e68320e
DL		 898 if (HAS_PCH_LPT(dev)) {
899 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
900 FDI_RX_LINK_REVERSAL_OVERRIDE;
901
eede3b53 902 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
3e68320e 903 }
754970ee
DV		 904
905 intel_crt_reset(connector);
79e53945 906}
Linux 6.x block layer and io_uring tree(s)