Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 JB |
33 | #include "i915_reg.h" |
34 | ||
1da177e4 LT |
35 | /* General customization: |
36 | */ | |
37 | ||
38 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
39 | ||
40 | #define DRIVER_NAME "i915" | |
41 | #define DRIVER_DESC "Intel Graphics" | |
de227f5f | 42 | #define DRIVER_DATE "20060119" |
1da177e4 | 43 | |
317c35d1 JB |
44 | enum pipe { |
45 | PIPE_A = 0, | |
46 | PIPE_B, | |
47 | }; | |
48 | ||
1da177e4 LT |
49 | /* Interface history: |
50 | * | |
51 | * 1.1: Original. | |
0d6aa60b DA |
52 | * 1.2: Add Power Management |
53 | * 1.3: Add vblank support | |
de227f5f | 54 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 55 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
56 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
57 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
58 | */ |
59 | #define DRIVER_MAJOR 1 | |
2228ed67 | 60 | #define DRIVER_MINOR 6 |
1da177e4 LT |
61 | #define DRIVER_PATCHLEVEL 0 |
62 | ||
1da177e4 LT |
63 | typedef struct _drm_i915_ring_buffer { |
64 | int tail_mask; | |
65 | unsigned long Start; | |
66 | unsigned long End; | |
67 | unsigned long Size; | |
68 | u8 *virtual_start; | |
69 | int head; | |
70 | int tail; | |
71 | int space; | |
72 | drm_local_map_t map; | |
73 | } drm_i915_ring_buffer_t; | |
74 | ||
75 | struct mem_block { | |
76 | struct mem_block *next; | |
77 | struct mem_block *prev; | |
78 | int start; | |
79 | int size; | |
6c340eac | 80 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
81 | }; |
82 | ||
a6b54f3f MCA |
83 | typedef struct _drm_i915_vbl_swap { |
84 | struct list_head head; | |
85 | drm_drawable_t drw_id; | |
0a3e67a4 | 86 | unsigned int plane; |
a6b54f3f MCA |
87 | unsigned int sequence; |
88 | } drm_i915_vbl_swap_t; | |
89 | ||
0a3e67a4 JB |
90 | struct opregion_header; |
91 | struct opregion_acpi; | |
92 | struct opregion_swsci; | |
93 | struct opregion_asle; | |
94 | ||
8ee1c3db MG |
95 | struct intel_opregion { |
96 | struct opregion_header *header; | |
97 | struct opregion_acpi *acpi; | |
98 | struct opregion_swsci *swsci; | |
99 | struct opregion_asle *asle; | |
100 | int enabled; | |
101 | }; | |
102 | ||
1da177e4 LT |
103 | typedef struct drm_i915_private { |
104 | drm_local_map_t *sarea; | |
105 | drm_local_map_t *mmio_map; | |
106 | ||
107 | drm_i915_sarea_t *sarea_priv; | |
108 | drm_i915_ring_buffer_t ring; | |
109 | ||
9c8da5eb | 110 | drm_dma_handle_t *status_page_dmah; |
1da177e4 | 111 | void *hw_status_page; |
1da177e4 | 112 | dma_addr_t dma_status_page; |
0a3e67a4 | 113 | uint32_t counter; |
dc7a9319 WZ |
114 | unsigned int status_gfx_addr; |
115 | drm_local_map_t hws_map; | |
1da177e4 | 116 | |
a6b54f3f | 117 | unsigned int cpp; |
1da177e4 LT |
118 | int back_offset; |
119 | int front_offset; | |
120 | int current_page; | |
121 | int page_flipping; | |
1da177e4 LT |
122 | |
123 | wait_queue_head_t irq_queue; | |
124 | atomic_t irq_received; | |
af6061af | 125 | atomic_t irq_emitted; |
ed4cb414 EA |
126 | /** Protects user_irq_refcount and irq_mask_reg */ |
127 | spinlock_t user_irq_lock; | |
128 | /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ | |
129 | int user_irq_refcount; | |
130 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
131 | u32 irq_mask_reg; | |
1da177e4 LT |
132 | |
133 | int tex_lru_log_granularity; | |
134 | int allow_batchbuffer; | |
135 | struct mem_block *agp_heap; | |
0d6aa60b | 136 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 137 | int vblank_pipe; |
a6b54f3f MCA |
138 | |
139 | spinlock_t swaps_lock; | |
140 | drm_i915_vbl_swap_t vbl_swaps; | |
141 | unsigned int swaps_pending; | |
ba8bbcf6 | 142 | |
8ee1c3db MG |
143 | struct intel_opregion opregion; |
144 | ||
ba8bbcf6 JB |
145 | /* Register state */ |
146 | u8 saveLBB; | |
147 | u32 saveDSPACNTR; | |
148 | u32 saveDSPBCNTR; | |
e948e994 | 149 | u32 saveDSPARB; |
ba8bbcf6 JB |
150 | u32 savePIPEACONF; |
151 | u32 savePIPEBCONF; | |
152 | u32 savePIPEASRC; | |
153 | u32 savePIPEBSRC; | |
154 | u32 saveFPA0; | |
155 | u32 saveFPA1; | |
156 | u32 saveDPLL_A; | |
157 | u32 saveDPLL_A_MD; | |
158 | u32 saveHTOTAL_A; | |
159 | u32 saveHBLANK_A; | |
160 | u32 saveHSYNC_A; | |
161 | u32 saveVTOTAL_A; | |
162 | u32 saveVBLANK_A; | |
163 | u32 saveVSYNC_A; | |
164 | u32 saveBCLRPAT_A; | |
0da3ea12 | 165 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
166 | u32 saveDSPASTRIDE; |
167 | u32 saveDSPASIZE; | |
168 | u32 saveDSPAPOS; | |
585fb111 | 169 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
170 | u32 saveDSPASURF; |
171 | u32 saveDSPATILEOFF; | |
172 | u32 savePFIT_PGM_RATIOS; | |
173 | u32 saveBLC_PWM_CTL; | |
174 | u32 saveBLC_PWM_CTL2; | |
175 | u32 saveFPB0; | |
176 | u32 saveFPB1; | |
177 | u32 saveDPLL_B; | |
178 | u32 saveDPLL_B_MD; | |
179 | u32 saveHTOTAL_B; | |
180 | u32 saveHBLANK_B; | |
181 | u32 saveHSYNC_B; | |
182 | u32 saveVTOTAL_B; | |
183 | u32 saveVBLANK_B; | |
184 | u32 saveVSYNC_B; | |
185 | u32 saveBCLRPAT_B; | |
0da3ea12 | 186 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
187 | u32 saveDSPBSTRIDE; |
188 | u32 saveDSPBSIZE; | |
189 | u32 saveDSPBPOS; | |
585fb111 | 190 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
191 | u32 saveDSPBSURF; |
192 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
193 | u32 saveVGA0; |
194 | u32 saveVGA1; | |
195 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
196 | u32 saveVGACNTRL; |
197 | u32 saveADPA; | |
198 | u32 saveLVDS; | |
585fb111 JB |
199 | u32 savePP_ON_DELAYS; |
200 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
201 | u32 saveDVOA; |
202 | u32 saveDVOB; | |
203 | u32 saveDVOC; | |
204 | u32 savePP_ON; | |
205 | u32 savePP_OFF; | |
206 | u32 savePP_CONTROL; | |
585fb111 | 207 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
208 | u32 savePFIT_CONTROL; |
209 | u32 save_palette_a[256]; | |
210 | u32 save_palette_b[256]; | |
211 | u32 saveFBC_CFB_BASE; | |
212 | u32 saveFBC_LL_BASE; | |
213 | u32 saveFBC_CONTROL; | |
214 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
215 | u32 saveIER; |
216 | u32 saveIIR; | |
217 | u32 saveIMR; | |
1f84e550 | 218 | u32 saveCACHE_MODE_0; |
e948e994 | 219 | u32 saveD_STATE; |
585fb111 | 220 | u32 saveCG_2D_DIS; |
1f84e550 | 221 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
222 | u32 saveSWF0[16]; |
223 | u32 saveSWF1[16]; | |
224 | u32 saveSWF2[3]; | |
225 | u8 saveMSR; | |
226 | u8 saveSR[8]; | |
123f794f | 227 | u8 saveGR[25]; |
ba8bbcf6 | 228 | u8 saveAR_INDEX; |
a59e122a | 229 | u8 saveAR[21]; |
ba8bbcf6 JB |
230 | u8 saveDACMASK; |
231 | u8 saveDACDATA[256*3]; /* 256 3-byte colors */ | |
a59e122a | 232 | u8 saveCR[37]; |
1da177e4 LT |
233 | } drm_i915_private_t; |
234 | ||
c153f45f | 235 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
236 | extern int i915_max_ioctl; |
237 | ||
1da177e4 | 238 | /* i915_dma.c */ |
84b1fd10 | 239 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 240 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 241 | extern int i915_driver_unload(struct drm_device *); |
84b1fd10 | 242 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
243 | extern void i915_driver_preclose(struct drm_device *dev, |
244 | struct drm_file *file_priv); | |
84b1fd10 | 245 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
246 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
247 | unsigned long arg); | |
af6061af | 248 | |
1da177e4 | 249 | /* i915_irq.c */ |
c153f45f EA |
250 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
251 | struct drm_file *file_priv); | |
252 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
253 | struct drm_file *file_priv); | |
1da177e4 LT |
254 | |
255 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 256 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 257 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 258 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
259 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
260 | struct drm_file *file_priv); | |
261 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
262 | struct drm_file *file_priv); | |
0a3e67a4 JB |
263 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
264 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
265 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
c153f45f EA |
266 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
267 | struct drm_file *file_priv); | |
8ee1c3db | 268 | extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); |
1da177e4 LT |
269 | |
270 | /* i915_mem.c */ | |
c153f45f EA |
271 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
272 | struct drm_file *file_priv); | |
273 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
274 | struct drm_file *file_priv); | |
275 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
276 | struct drm_file *file_priv); | |
277 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
278 | struct drm_file *file_priv); | |
1da177e4 | 279 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 280 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 281 | struct drm_file *file_priv, struct mem_block *heap); |
1da177e4 | 282 | |
317c35d1 JB |
283 | /* i915_suspend.c */ |
284 | extern int i915_save_state(struct drm_device *dev); | |
285 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
286 | |
287 | /* i915_suspend.c */ | |
288 | extern int i915_save_state(struct drm_device *dev); | |
289 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 290 | |
8ee1c3db MG |
291 | /* i915_opregion.c */ |
292 | extern int intel_opregion_init(struct drm_device *dev); | |
293 | extern void intel_opregion_free(struct drm_device *dev); | |
294 | extern void opregion_asle_intr(struct drm_device *dev); | |
295 | extern void opregion_enable_asle(struct drm_device *dev); | |
296 | ||
0d6aa60b DA |
297 | #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) |
298 | #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) | |
bc5f4523 | 299 | #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) |
0d6aa60b | 300 | #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) |
317c35d1 JB |
301 | #define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg)) |
302 | #define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val)) | |
1da177e4 LT |
303 | |
304 | #define I915_VERBOSE 0 | |
305 | ||
306 | #define RING_LOCALS unsigned int outring, ringmask, outcount; \ | |
307 | volatile char *virt; | |
308 | ||
309 | #define BEGIN_LP_RING(n) do { \ | |
310 | if (I915_VERBOSE) \ | |
3e684eae MN |
311 | DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ |
312 | if (dev_priv->ring.space < (n)*4) \ | |
bf9d8929 | 313 | i915_wait_ring(dev, (n)*4, __func__); \ |
1da177e4 LT |
314 | outcount = 0; \ |
315 | outring = dev_priv->ring.tail; \ | |
316 | ringmask = dev_priv->ring.tail_mask; \ | |
317 | virt = dev_priv->ring.virtual_start; \ | |
318 | } while (0) | |
319 | ||
320 | #define OUT_RING(n) do { \ | |
321 | if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ | |
c29b669c | 322 | *(volatile unsigned int *)(virt + outring) = (n); \ |
1da177e4 LT |
323 | outcount++; \ |
324 | outring += 4; \ | |
325 | outring &= ringmask; \ | |
326 | } while (0) | |
327 | ||
328 | #define ADVANCE_LP_RING() do { \ | |
329 | if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ | |
330 | dev_priv->ring.tail = outring; \ | |
331 | dev_priv->ring.space -= outcount * 4; \ | |
585fb111 | 332 | I915_WRITE(PRB0_TAIL, outring); \ |
1da177e4 LT |
333 | } while(0) |
334 | ||
ba8bbcf6 | 335 | /** |
585fb111 JB |
336 | * Reads a dword out of the status page, which is written to from the command |
337 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
338 | * MI_STORE_DATA_IMM. | |
ba8bbcf6 | 339 | * |
585fb111 JB |
340 | * The following dwords have a reserved meaning: |
341 | * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
342 | * 4: ring 0 head pointer | |
343 | * 5: ring 1 head pointer (915-class) | |
344 | * 6: ring 2 head pointer (915-class) | |
ba8bbcf6 | 345 | * |
585fb111 | 346 | * The area from dword 0x10 to 0x3ff is available for driver usage. |
ba8bbcf6 | 347 | */ |
585fb111 JB |
348 | #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) |
349 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5) | |
ba8bbcf6 | 350 | |
585fb111 | 351 | extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); |
ba8bbcf6 JB |
352 | |
353 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
354 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
355 | #define IS_I85X(dev) ((dev)->pci_device == 0x3582) | |
356 | #define IS_I855(dev) ((dev)->pci_device == 0x3582) | |
357 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
358 | ||
4d1f7888 | 359 | #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) |
ba8bbcf6 JB |
360 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
361 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
3bf48468 JB |
362 | #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ |
363 | (dev)->pci_device == 0x27AE) | |
ba8bbcf6 JB |
364 | #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ |
365 | (dev)->pci_device == 0x2982 || \ | |
366 | (dev)->pci_device == 0x2992 || \ | |
367 | (dev)->pci_device == 0x29A2 || \ | |
368 | (dev)->pci_device == 0x2A02 || \ | |
5f5f9d4c | 369 | (dev)->pci_device == 0x2A12 || \ |
d3adbc0c ZW |
370 | (dev)->pci_device == 0x2A42 || \ |
371 | (dev)->pci_device == 0x2E02 || \ | |
372 | (dev)->pci_device == 0x2E12 || \ | |
373 | (dev)->pci_device == 0x2E22) | |
ba8bbcf6 JB |
374 | |
375 | #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) | |
376 | ||
b9bfdfe6 | 377 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
5f5f9d4c | 378 | |
d3adbc0c ZW |
379 | #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ |
380 | (dev)->pci_device == 0x2E12 || \ | |
381 | (dev)->pci_device == 0x2E22) | |
382 | ||
ba8bbcf6 JB |
383 | #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ |
384 | (dev)->pci_device == 0x29B2 || \ | |
385 | (dev)->pci_device == 0x29D2) | |
386 | ||
387 | #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ | |
388 | IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) | |
389 | ||
390 | #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ | |
b9bfdfe6 | 391 | IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) |
ba8bbcf6 | 392 | |
b9bfdfe6 | 393 | #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) |
b39d50e5 | 394 | |
ba8bbcf6 | 395 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
0d6aa60b | 396 | |
1da177e4 | 397 | #endif |