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drm/i915: Clean up encoder->crtc_mask setup
[linux-2.6-block.git] / drivers / gpu / drm / i915 / display / intel_tv.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 *
27 */
28
29/** @file
30 * Integrated TV-out support for the 915GM and 945GM.
31 */
32
c6f95f27 33#include <drm/drm_atomic_helper.h>
760285e7
DH		 34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
760285e7 36#include <drm/i915_drm.h>
ec7f29ff 37
79e53945 38#include "i915_drv.h"
ec7f29ff 39#include "intel_connector.h"
1d455f8d 40#include "intel_display_types.h"
dbeb38d9 41#include "intel_hotplug.h"
efe57eea 42#include "intel_tv.h"
79e53945
JB		 43
44enum tv_margin {
45 TV_MARGIN_LEFT, TV_MARGIN_TOP,
46 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
47};
48
ea5b213a
CW		 49struct intel_tv {
50 struct intel_encoder base;
51
79e53945 52 int type;
79e53945
JB		 53};
54
55struct video_levels {
db49296b
TU		 56 u16 blank, black;
57 u8 burst;
79e53945
JB		 58};
59
60struct color_conversion {
61 u16 ry, gy, by, ay;
62 u16 ru, gu, bu, au;
63 u16 rv, gv, bv, av;
64};
65
66static const u32 filter_table[] = {
67 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
68 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
69 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
70 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
71 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
72 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
73 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
74 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
75 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
76 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
77 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
78 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
79 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
80 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
81 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
82 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
83 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
84 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
85 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
86 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
87 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
88 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
89 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
90 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
91 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
92 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
93 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
94 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
95 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
96 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
97 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
98 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
99 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
100 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
101 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
102 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
103 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
104 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
105 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
106 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
107 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
108 0x2D002CC0, 0x30003640, 0x2D0036C0,
109 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
110 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
111 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
112 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
113 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
114 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
115 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
116 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
117 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
118 0x28003100, 0x28002F00, 0x00003100,
119};
120
121/*
122 * Color conversion values have 3 separate fixed point formats:
123 *
124 * 10 bit fields (ay, au)
125 * 1.9 fixed point (b.bbbbbbbbb)
126 * 11 bit fields (ry, by, ru, gu, gv)
127 * exp.mantissa (ee.mmmmmmmmm)
128 * ee = 00 = 10^-1 (0.mmmmmmmmm)
129 * ee = 01 = 10^-2 (0.0mmmmmmmmm)
130 * ee = 10 = 10^-3 (0.00mmmmmmmmm)
131 * ee = 11 = 10^-4 (0.000mmmmmmmmm)
132 * 12 bit fields (gy, rv, bu)
133 * exp.mantissa (eee.mmmmmmmmm)
134 * eee = 000 = 10^-1 (0.mmmmmmmmm)
135 * eee = 001 = 10^-2 (0.0mmmmmmmmm)
136 * eee = 010 = 10^-3 (0.00mmmmmmmmm)
137 * eee = 011 = 10^-4 (0.000mmmmmmmmm)
138 * eee = 100 = reserved
139 * eee = 101 = reserved
140 * eee = 110 = reserved
141 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
142 *
143 * Saturation and contrast are 8 bits, with their own representation:
144 * 8 bit field (saturation, contrast)
145 * exp.mantissa (ee.mmmmmm)
146 * ee = 00 = 10^-1 (0.mmmmmm)
147 * ee = 01 = 10^0 (m.mmmmm)
148 * ee = 10 = 10^1 (mm.mmmm)
149 * ee = 11 = 10^2 (mmm.mmm)
150 *
151 * Simple conversion function:
152 *
153 * static u32
154 * float_to_csc_11(float f)
155 * {
156 * u32 exp;
157 * u32 mant;
158 * u32 ret;
159 *
160 * if (f < 0)
161 * f = -f;
162 *
163 * if (f >= 1) {
164 * exp = 0x7;
0206e353 165 * mant = 1 << 8;
79e53945
JB		 166 * } else {
167 * for (exp = 0; exp < 3 && f < 0.5; exp++)
0206e353 168 * f *= 2.0;
79e53945
JB		 169 * mant = (f * (1 << 9) + 0.5);
170 * if (mant >= (1 << 9))
171 * mant = (1 << 9) - 1;
172 * }
173 * ret = (exp << 9) | mant;
174 * return ret;
175 * }
176 */
177
178/*
179 * Behold, magic numbers! If we plant them they might grow a big
180 * s-video cable to the sky... or something.
181 *
182 * Pre-converted to appropriate hex value.
183 */
184
185/*
186 * PAL & NTSC values for composite & s-video connections
187 */
188static const struct color_conversion ntsc_m_csc_composite = {
189 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 190 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
191 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 192};
193
194static const struct video_levels ntsc_m_levels_composite = {
195 .blank = 225, .black = 267, .burst = 113,
196};
197
198static const struct color_conversion ntsc_m_csc_svideo = {
ba01079c
ZW		 199 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
200 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
201 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 202};
203
204static const struct video_levels ntsc_m_levels_svideo = {
205 .blank = 266, .black = 316, .burst = 133,
206};
207
208static const struct color_conversion ntsc_j_csc_composite = {
209 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
ba01079c
ZW		 210 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
211 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
79e53945
JB		 212};
213
214static const struct video_levels ntsc_j_levels_composite = {
215 .blank = 225, .black = 225, .burst = 113,
216};
217
218static const struct color_conversion ntsc_j_csc_svideo = {
219 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
ba01079c
ZW		 220 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
221 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
79e53945
JB		 222};
223
224static const struct video_levels ntsc_j_levels_svideo = {
225 .blank = 266, .black = 266, .burst = 133,
226};
227
228static const struct color_conversion pal_csc_composite = {
229 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
ba01079c
ZW		 230 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
231 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
79e53945
JB		 232};
233
234static const struct video_levels pal_levels_composite = {
235 .blank = 237, .black = 237, .burst = 118,
236};
237
238static const struct color_conversion pal_csc_svideo = {
239 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
ba01079c
ZW		 240 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
241 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
79e53945
JB		 242};
243
244static const struct video_levels pal_levels_svideo = {
245 .blank = 280, .black = 280, .burst = 139,
246};
247
248static const struct color_conversion pal_m_csc_composite = {
249 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 250 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
251 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 252};
253
254static const struct video_levels pal_m_levels_composite = {
255 .blank = 225, .black = 267, .burst = 113,
256};
257
258static const struct color_conversion pal_m_csc_svideo = {
ba01079c
ZW		 259 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
260 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
261 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 262};
263
264static const struct video_levels pal_m_levels_svideo = {
265 .blank = 266, .black = 316, .burst = 133,
266};
267
268static const struct color_conversion pal_n_csc_composite = {
269 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 270 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
271 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 272};
273
274static const struct video_levels pal_n_levels_composite = {
275 .blank = 225, .black = 267, .burst = 118,
276};
277
278static const struct color_conversion pal_n_csc_svideo = {
ba01079c
ZW		 279 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
280 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
281 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 282};
283
284static const struct video_levels pal_n_levels_svideo = {
285 .blank = 266, .black = 316, .burst = 139,
286};
287
288/*
289 * Component connections
290 */
291static const struct color_conversion sdtv_csc_yprpb = {
ba01079c
ZW		 292 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
293 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
294 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
79e53945
JB		 295};
296
79e53945 297static const struct color_conversion hdtv_csc_yprpb = {
ba01079c
ZW		 298 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
299 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
300 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
79e53945
JB		 301};
302
79e53945
JB		 303static const struct video_levels component_levels = {
304 .blank = 279, .black = 279, .burst = 0,
305};
306
307
308struct tv_mode {
763a4a01 309 const char *name;
db49296b
TU		 310
311 u32 clock;
312 u16 refresh; /* in millihertz (for precision) */
4f503798 313 u8 oversample;
db49296b
TU		 314 u8 hsync_end;
315 u16 hblank_start, hblank_end, htotal;
316 bool progressive : 1, trilevel_sync : 1, component_only : 1;
317 u8 vsync_start_f1, vsync_start_f2, vsync_len;
318 bool veq_ena : 1;
319 u8 veq_start_f1, veq_start_f2, veq_len;
320 u8 vi_end_f1, vi_end_f2;
321 u16 nbr_end;
322 bool burst_ena : 1;
323 u8 hburst_start, hburst_len;
324 u8 vburst_start_f1;
325 u16 vburst_end_f1;
326 u8 vburst_start_f2;
327 u16 vburst_end_f2;
328 u8 vburst_start_f3;
329 u16 vburst_end_f3;
330 u8 vburst_start_f4;
331 u16 vburst_end_f4;
79e53945
JB		 332 /*
333 * subcarrier programming
334 */
db49296b
TU		 335 u16 dda2_size, dda3_size;
336 u8 dda1_inc;
337 u16 dda2_inc, dda3_inc;
79e53945 338 u32 sc_reset;
db49296b 339 bool pal_burst : 1;
79e53945
JB		 340 /*
341 * blank/black levels
342 */
343 const struct video_levels *composite_levels, *svideo_levels;
344 const struct color_conversion *composite_color, *svideo_color;
345 const u32 *filter_table;
79e53945
JB		 346};
347
348
349/*
350 * Sub carrier DDA
351 *
352 * I think this works as follows:
353 *
354 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
355 *
356 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
357 *
358 * So,
359 * dda1_ideal = subcarrier/pixel * 4096
360 * dda1_inc = floor (dda1_ideal)
361 * dda2 = dda1_ideal - dda1_inc
362 *
363 * then pick a ratio for dda2 that gives the closest approximation. If
364 * you can't get close enough, you can play with dda3 as well. This
365 * seems likely to happen when dda2 is small as the jumps would be larger
366 *
367 * To invert this,
368 *
369 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
370 *
371 * The constants below were all computed using a 107.520MHz clock
372 */
373
3930f18a 374/*
79e53945
JB		 375 * Register programming values for TV modes.
376 *
377 * These values account for -1s required.
378 */
005568be 379static const struct tv_mode tv_modes[] = {
79e53945
JB		 380 {
381 .name = "NTSC-M",
ba01079c 382 .clock = 108000,
23bd15ec 383 .refresh = 59940,
4f503798 384 .oversample = 8,
56f62308 385 .component_only = false,
79e53945
JB		 386 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
387
388 .hsync_end = 64, .hblank_end = 124,
389 .hblank_start = 836, .htotal = 857,
390
391 .progressive = false, .trilevel_sync = false,
392
393 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
394 .vsync_len = 6,
395
0206e353 396 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 397 .veq_start_f2 = 1, .veq_len = 18,
398
399 .vi_end_f1 = 20, .vi_end_f2 = 21,
400 .nbr_end = 240,
401
402 .burst_ena = true,
403 .hburst_start = 72, .hburst_len = 34,
404 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
405 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
406 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
407 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
408
409 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 410 .dda1_inc = 135,
411 .dda2_inc = 20800, .dda2_size = 27456,
79e53945
JB		 412 .dda3_inc = 0, .dda3_size = 0,
413 .sc_reset = TV_SC_RESET_EVERY_4,
414 .pal_burst = false,
415
416 .composite_levels = &ntsc_m_levels_composite,
417 .composite_color = &ntsc_m_csc_composite,
418 .svideo_levels = &ntsc_m_levels_svideo,
419 .svideo_color = &ntsc_m_csc_svideo,
420
421 .filter_table = filter_table,
422 },
423 {
424 .name = "NTSC-443",
ba01079c 425 .clock = 108000,
23bd15ec 426 .refresh = 59940,
4f503798 427 .oversample = 8,
56f62308 428 .component_only = false,
79e53945
JB		 429 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
430 .hsync_end = 64, .hblank_end = 124,
431 .hblank_start = 836, .htotal = 857,
432
433 .progressive = false, .trilevel_sync = false,
434
435 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
436 .vsync_len = 6,
437
0206e353 438 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 439 .veq_start_f2 = 1, .veq_len = 18,
440
441 .vi_end_f1 = 20, .vi_end_f2 = 21,
442 .nbr_end = 240,
443
3ca87e82 444 .burst_ena = true,
79e53945
JB		 445 .hburst_start = 72, .hburst_len = 34,
446 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
447 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
448 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
449 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
450
451 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
452 .dda1_inc = 168,
ba01079c
ZW		 453 .dda2_inc = 4093, .dda2_size = 27456,
454 .dda3_inc = 310, .dda3_size = 525,
455 .sc_reset = TV_SC_RESET_NEVER,
456 .pal_burst = false,
79e53945
JB		 457
458 .composite_levels = &ntsc_m_levels_composite,
459 .composite_color = &ntsc_m_csc_composite,
460 .svideo_levels = &ntsc_m_levels_svideo,
461 .svideo_color = &ntsc_m_csc_svideo,
462
463 .filter_table = filter_table,
464 },
465 {
466 .name = "NTSC-J",
ba01079c 467 .clock = 108000,
23bd15ec 468 .refresh = 59940,
4f503798 469 .oversample = 8,
56f62308 470 .component_only = false,
79e53945
JB		 471
472 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
473 .hsync_end = 64, .hblank_end = 124,
474 .hblank_start = 836, .htotal = 857,
475
476 .progressive = false, .trilevel_sync = false,
477
478 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
479 .vsync_len = 6,
480
0206e353 481 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 482 .veq_start_f2 = 1, .veq_len = 18,
483
484 .vi_end_f1 = 20, .vi_end_f2 = 21,
485 .nbr_end = 240,
486
487 .burst_ena = true,
488 .hburst_start = 72, .hburst_len = 34,
489 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
490 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
491 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
492 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
493
494 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 495 .dda1_inc = 135,
496 .dda2_inc = 20800, .dda2_size = 27456,
79e53945
JB		 497 .dda3_inc = 0, .dda3_size = 0,
498 .sc_reset = TV_SC_RESET_EVERY_4,
499 .pal_burst = false,
500
501 .composite_levels = &ntsc_j_levels_composite,
502 .composite_color = &ntsc_j_csc_composite,
503 .svideo_levels = &ntsc_j_levels_svideo,
504 .svideo_color = &ntsc_j_csc_svideo,
505
506 .filter_table = filter_table,
507 },
508 {
509 .name = "PAL-M",
ba01079c 510 .clock = 108000,
23bd15ec 511 .refresh = 59940,
4f503798 512 .oversample = 8,
56f62308 513 .component_only = false,
79e53945
JB		 514
515 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
516 .hsync_end = 64, .hblank_end = 124,
517 .hblank_start = 836, .htotal = 857,
518
519 .progressive = false, .trilevel_sync = false,
520
521 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
522 .vsync_len = 6,
523
0206e353 524 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 525 .veq_start_f2 = 1, .veq_len = 18,
526
527 .vi_end_f1 = 20, .vi_end_f2 = 21,
528 .nbr_end = 240,
529
530 .burst_ena = true,
531 .hburst_start = 72, .hburst_len = 34,
532 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
533 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
534 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
535 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
536
537 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 538 .dda1_inc = 135,
539 .dda2_inc = 16704, .dda2_size = 27456,
79e53945 540 .dda3_inc = 0, .dda3_size = 0,
ba01079c
ZW		 541 .sc_reset = TV_SC_RESET_EVERY_8,
542 .pal_burst = true,
79e53945
JB		 543
544 .composite_levels = &pal_m_levels_composite,
545 .composite_color = &pal_m_csc_composite,
546 .svideo_levels = &pal_m_levels_svideo,
547 .svideo_color = &pal_m_csc_svideo,
548
549 .filter_table = filter_table,
550 },
551 {
552 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
553 .name = "PAL-N",
ba01079c 554 .clock = 108000,
23bd15ec 555 .refresh = 50000,
4f503798 556 .oversample = 8,
56f62308 557 .component_only = false,
79e53945
JB		 558
559 .hsync_end = 64, .hblank_end = 128,
560 .hblank_start = 844, .htotal = 863,
561
562 .progressive = false, .trilevel_sync = false,
563
564
565 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
566 .vsync_len = 6,
567
0206e353 568 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 569 .veq_start_f2 = 1, .veq_len = 18,
570
571 .vi_end_f1 = 24, .vi_end_f2 = 25,
572 .nbr_end = 286,
573
574 .burst_ena = true,
0206e353 575 .hburst_start = 73, .hburst_len = 34,
79e53945
JB		 576 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
577 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
578 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
579 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
580
581
582 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
ba01079c
ZW		 583 .dda1_inc = 135,
584 .dda2_inc = 23578, .dda2_size = 27648,
585 .dda3_inc = 134, .dda3_size = 625,
79e53945
JB		 586 .sc_reset = TV_SC_RESET_EVERY_8,
587 .pal_burst = true,
588
589 .composite_levels = &pal_n_levels_composite,
590 .composite_color = &pal_n_csc_composite,
591 .svideo_levels = &pal_n_levels_svideo,
592 .svideo_color = &pal_n_csc_svideo,
593
594 .filter_table = filter_table,
595 },
596 {
597 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
598 .name = "PAL",
ba01079c 599 .clock = 108000,
23bd15ec 600 .refresh = 50000,
4f503798 601 .oversample = 8,
56f62308 602 .component_only = false,
79e53945 603
ba01079c 604 .hsync_end = 64, .hblank_end = 142,
79e53945
JB		 605 .hblank_start = 844, .htotal = 863,
606
607 .progressive = false, .trilevel_sync = false,
608
609 .vsync_start_f1 = 5, .vsync_start_f2 = 6,
610 .vsync_len = 5,
611
0206e353 612 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 613 .veq_start_f2 = 1, .veq_len = 15,
614
615 .vi_end_f1 = 24, .vi_end_f2 = 25,
616 .nbr_end = 286,
617
618 .burst_ena = true,
619 .hburst_start = 73, .hburst_len = 32,
620 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
621 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
622 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
623 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
624
625 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
626 .dda1_inc = 168,
ba01079c
ZW		 627 .dda2_inc = 4122, .dda2_size = 27648,
628 .dda3_inc = 67, .dda3_size = 625,
79e53945
JB		 629 .sc_reset = TV_SC_RESET_EVERY_8,
630 .pal_burst = true,
631
632 .composite_levels = &pal_levels_composite,
633 .composite_color = &pal_csc_composite,
634 .svideo_levels = &pal_levels_svideo,
635 .svideo_color = &pal_csc_svideo,
636
637 .filter_table = filter_table,
638 },
9589919f
RV		 639 {
640 .name = "480p",
d5152823 641 .clock = 108000,
9589919f 642 .refresh = 59940,
4f503798 643 .oversample = 4,
56f62308 644 .component_only = true,
9589919f
RV		 645
646 .hsync_end = 64, .hblank_end = 122,
647 .hblank_start = 842, .htotal = 857,
648
649 .progressive = true, .trilevel_sync = false,
650
651 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
652 .vsync_len = 12,
653
654 .veq_ena = false,
655
656 .vi_end_f1 = 44, .vi_end_f2 = 44,
657 .nbr_end = 479,
658
659 .burst_ena = false,
660
661 .filter_table = filter_table,
662 },
663 {
664 .name = "576p",
d5152823 665 .clock = 108000,
9589919f 666 .refresh = 50000,
4f503798 667 .oversample = 4,
56f62308 668 .component_only = true,
9589919f
RV		 669
670 .hsync_end = 64, .hblank_end = 139,
671 .hblank_start = 859, .htotal = 863,
672
673 .progressive = true, .trilevel_sync = false,
674
675 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
676 .vsync_len = 10,
677
678 .veq_ena = false,
679
680 .vi_end_f1 = 48, .vi_end_f2 = 48,
681 .nbr_end = 575,
682
683 .burst_ena = false,
684
685 .filter_table = filter_table,
686 },
79e53945
JB		 687 {
688 .name = "720p@60Hz",
d5152823 689 .clock = 148500,
79e53945 690 .refresh = 60000,
4f503798 691 .oversample = 2,
56f62308 692 .component_only = true,
79e53945
JB		 693
694 .hsync_end = 80, .hblank_end = 300,
695 .hblank_start = 1580, .htotal = 1649,
696
0206e353 697 .progressive = true, .trilevel_sync = true,
79e53945
JB		 698
699 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
700 .vsync_len = 10,
701
702 .veq_ena = false,
703
704 .vi_end_f1 = 29, .vi_end_f2 = 29,
705 .nbr_end = 719,
706
707 .burst_ena = false,
708
709 .filter_table = filter_table,
710 },
79e53945
JB		 711 {
712 .name = "720p@50Hz",
d5152823 713 .clock = 148500,
79e53945 714 .refresh = 50000,
4f503798 715 .oversample = 2,
56f62308 716 .component_only = true,
79e53945
JB		 717
718 .hsync_end = 80, .hblank_end = 300,
719 .hblank_start = 1580, .htotal = 1979,
720
0206e353 721 .progressive = true, .trilevel_sync = true,
79e53945
JB		 722
723 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
724 .vsync_len = 10,
725
726 .veq_ena = false,
727
728 .vi_end_f1 = 29, .vi_end_f2 = 29,
729 .nbr_end = 719,
730
731 .burst_ena = false,
732
733 .filter_table = filter_table,
79e53945
JB		 734 },
735 {
736 .name = "1080i@50Hz",
d5152823 737 .clock = 148500,
23bd15ec 738 .refresh = 50000,
4f503798 739 .oversample = 2,
56f62308 740 .component_only = true,
79e53945
JB		 741
742 .hsync_end = 88, .hblank_end = 235,
743 .hblank_start = 2155, .htotal = 2639,
744
0206e353 745 .progressive = false, .trilevel_sync = true,
79e53945
JB		 746
747 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
748 .vsync_len = 10,
749
0206e353 750 .veq_ena = true, .veq_start_f1 = 4,
79e53945
JB		 751 .veq_start_f2 = 4, .veq_len = 10,
752
753
754 .vi_end_f1 = 21, .vi_end_f2 = 22,
755 .nbr_end = 539,
756
757 .burst_ena = false,
758
759 .filter_table = filter_table,
760 },
761 {
762 .name = "1080i@60Hz",
d5152823 763 .clock = 148500,
23bd15ec 764 .refresh = 60000,
4f503798 765 .oversample = 2,
56f62308 766 .component_only = true,
79e53945
JB		 767
768 .hsync_end = 88, .hblank_end = 235,
769 .hblank_start = 2155, .htotal = 2199,
770
0206e353 771 .progressive = false, .trilevel_sync = true,
79e53945
JB		 772
773 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
774 .vsync_len = 10,
775
0206e353 776 .veq_ena = true, .veq_start_f1 = 4,
79e53945
JB		 777 .veq_start_f2 = 4, .veq_len = 10,
778
779
780 .vi_end_f1 = 21, .vi_end_f2 = 22,
781 .nbr_end = 539,
782
783 .burst_ena = false,
784
79e53945
JB		 785 .filter_table = filter_table,
786 },
a0ff6779
VS		 787
788 {
789 .name = "1080p@30Hz",
790 .clock = 148500,
791 .refresh = 30000,
792 .oversample = 2,
793 .component_only = true,
794
795 .hsync_end = 88, .hblank_end = 235,
796 .hblank_start = 2155, .htotal = 2199,
797
798 .progressive = true, .trilevel_sync = true,
799
800 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
801 .vsync_len = 10,
802
803 .veq_ena = false, .veq_start_f1 = 0,
804 .veq_start_f2 = 0, .veq_len = 0,
805
806 .vi_end_f1 = 44, .vi_end_f2 = 44,
807 .nbr_end = 1079,
808
809 .burst_ena = false,
810
811 .filter_table = filter_table,
812 },
813
814 {
815 .name = "1080p@50Hz",
816 .clock = 148500,
817 .refresh = 50000,
818 .oversample = 1,
819 .component_only = true,
820
821 .hsync_end = 88, .hblank_end = 235,
822 .hblank_start = 2155, .htotal = 2639,
823
824 .progressive = true, .trilevel_sync = true,
825
826 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
827 .vsync_len = 10,
828
829 .veq_ena = false, .veq_start_f1 = 0,
830 .veq_start_f2 = 0, .veq_len = 0,
831
832 .vi_end_f1 = 44, .vi_end_f2 = 44,
833 .nbr_end = 1079,
834
835 .burst_ena = false,
836
837 .filter_table = filter_table,
838 },
839
840 {
841 .name = "1080p@60Hz",
842 .clock = 148500,
843 .refresh = 60000,
844 .oversample = 1,
845 .component_only = true,
846
847 .hsync_end = 88, .hblank_end = 235,
848 .hblank_start = 2155, .htotal = 2199,
849
850 .progressive = true, .trilevel_sync = true,
851
852 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
853 .vsync_len = 10,
854
855 .veq_ena = false, .veq_start_f1 = 0,
856 .veq_start_f2 = 0, .veq_len = 0,
857
858 .vi_end_f1 = 44, .vi_end_f2 = 44,
859 .nbr_end = 1079,
860
861 .burst_ena = false,
862
863 .filter_table = filter_table,
864 },
79e53945
JB		 865};
866
690157f0
VS		 867struct intel_tv_connector_state {
868 struct drm_connector_state base;
869
870 /*
871 * May need to override the user margins for
872 * gen3 >1024 wide source vertical centering.
873 */
874 struct {
875 u16 top, bottom;
876 } margins;
877
878 bool bypass_vfilter;
879};
880
881#define to_intel_tv_connector_state(x) container_of(x, struct intel_tv_connector_state, base)
882
883static struct drm_connector_state *
884intel_tv_connector_duplicate_state(struct drm_connector *connector)
885{
886 struct intel_tv_connector_state *state;
887
888 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
889 if (!state)
890 return NULL;
891
892 __drm_atomic_helper_connector_duplicate_state(connector, &state->base);
893 return &state->base;
894}
895
cd91ef23 896static struct intel_tv *enc_to_tv(struct intel_encoder *encoder)
ea5b213a 897{
cd91ef23 898 return container_of(encoder, struct intel_tv, base);
ea5b213a
CW		 899}
900
df0e9248
CW		 901static struct intel_tv *intel_attached_tv(struct drm_connector *connector)
902{
cd91ef23 903 return enc_to_tv(intel_attached_encoder(connector));
df0e9248
CW		 904}
905
9a8ee983
DV		 906static bool
907intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
908{
4add0f6b 909 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
9a8ee983
DV		 910 u32 tmp = I915_READ(TV_CTL);
911
4add0f6b 912 *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
9a8ee983 913
4add0f6b 914 return tmp & TV_ENC_ENABLE;
9a8ee983
DV		 915}
916
79e53945 917static void
fd6bbda9 918intel_enable_tv(struct intel_encoder *encoder,
5f88a9c6
VS		 919 const struct intel_crtc_state *pipe_config,
920 const struct drm_connector_state *conn_state)
79e53945 921{
6b5756a0 922 struct drm_device *dev = encoder->base.dev;
fac5e23e 923 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 924
7a98948f 925 /* Prevents vblank waits from timing out in intel_tv_detect_type() */
0f0f74bc 926 intel_wait_for_vblank(dev_priv,
a7f519ba 927 to_intel_crtc(pipe_config->base.crtc)->pipe);
7a98948f 928
6b5756a0
DV		 929 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
930}
931
932static void
fd6bbda9 933intel_disable_tv(struct intel_encoder *encoder,
5f88a9c6
VS		 934 const struct intel_crtc_state *old_crtc_state,
935 const struct drm_connector_state *old_conn_state)
6b5756a0
DV		 936{
937 struct drm_device *dev = encoder->base.dev;
fac5e23e 938 struct drm_i915_private *dev_priv = to_i915(dev);
6b5756a0
DV		 939
940 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
79e53945
JB		 941}
942
5f88a9c6 943static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
79e53945 944{
0e891b3f 945 int format = conn_state->tv.mode;
79e53945 946
0e891b3f 947 return &tv_modes[format];
79e53945
JB		 948}
949
950static enum drm_mode_status
763a4a01
CW		 951intel_tv_mode_valid(struct drm_connector *connector,
952 struct drm_display_mode *mode)
79e53945 953{
0e891b3f 954 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
54c032b3
MK		 955 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
956
e4dd27aa
VS		 957 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
958 return MODE_NO_DBLESCAN;
959
54c032b3
MK		 960 if (mode->clock > max_dotclk)
961 return MODE_CLOCK_HIGH;
79e53945
JB		 962
963 /* Ensure TV refresh is close to desired refresh */
15de0889
VS		 964 if (abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) >= 1000)
965 return MODE_CLOCK_RANGE;
763a4a01 966
15de0889 967 return MODE_OK;
79e53945
JB		 968}
969
65ddf7f9
VS		 970static int
971intel_tv_mode_vdisplay(const struct tv_mode *tv_mode)
972{
973 if (tv_mode->progressive)
974 return tv_mode->nbr_end + 1;
975 else
976 return 2 * (tv_mode->nbr_end + 1);
977}
79e53945 978
e3bb355c
VS		 979static void
980intel_tv_mode_to_mode(struct drm_display_mode *mode,
981 const struct tv_mode *tv_mode)
982{
983 mode->clock = tv_mode->clock /
984 (tv_mode->oversample >> !tv_mode->progressive);
985
986 /*
987 * tv_mode horizontal timings:
988 *
989 * hsync_end
990 * | hblank_end
991 * | | hblank_start
992 * | | | htotal
993 * | _______ |
994 * ____/ \___
995 * \__/ \
996 */
997 mode->hdisplay =
998 tv_mode->hblank_start - tv_mode->hblank_end;
999 mode->hsync_start = mode->hdisplay +
1000 tv_mode->htotal - tv_mode->hblank_start;
1001 mode->hsync_end = mode->hsync_start +
1002 tv_mode->hsync_end;
1003 mode->htotal = tv_mode->htotal + 1;
1004
1005 /*
1006 * tv_mode vertical timings:
1007 *
1008 * vsync_start
1009 * | vsync_end
1010 * | | vi_end nbr_end
1011 * | | | |
1012 * | | _______
1013 * \__ ____/ \
1014 * \__/
1015 */
1016 mode->vdisplay = intel_tv_mode_vdisplay(tv_mode);
1017 if (tv_mode->progressive) {
1018 mode->vsync_start = mode->vdisplay +
1019 tv_mode->vsync_start_f1 + 1;
1020 mode->vsync_end = mode->vsync_start +
1021 tv_mode->vsync_len;
1022 mode->vtotal = mode->vdisplay +
1023 tv_mode->vi_end_f1 + 1;
1024 } else {
1025 mode->vsync_start = mode->vdisplay +
1026 tv_mode->vsync_start_f1 + 1 +
1027 tv_mode->vsync_start_f2 + 1;
1028 mode->vsync_end = mode->vsync_start +
1029 2 * tv_mode->vsync_len;
1030 mode->vtotal = mode->vdisplay +
1031 tv_mode->vi_end_f1 + 1 +
1032 tv_mode->vi_end_f2 + 1;
1033 }
1034
1035 /* TV has it's own notion of sync and other mode flags, so clear them. */
1036 mode->flags = 0;
1037
1038 mode->vrefresh = 0;
1039 mode->vrefresh = drm_mode_vrefresh(mode);
1040
1041 snprintf(mode->name, sizeof(mode->name),
1042 "%dx%d%c (%s)",
1043 mode->hdisplay, mode->vdisplay,
1044 tv_mode->progressive ? 'p' : 'i',
1045 tv_mode->name);
1046}
1047
1048static void intel_tv_scale_mode_horiz(struct drm_display_mode *mode,
1049 int hdisplay, int left_margin,
1050 int right_margin)
1051{
1052 int hsync_start = mode->hsync_start - mode->hdisplay + right_margin;
1053 int hsync_end = mode->hsync_end - mode->hdisplay + right_margin;
1054 int new_htotal = mode->htotal * hdisplay /
1055 (mode->hdisplay - left_margin - right_margin);
1056
1057 mode->clock = mode->clock * new_htotal / mode->htotal;
1058
1059 mode->hdisplay = hdisplay;
1060 mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal;
1061 mode->hsync_end = hdisplay + hsync_end * new_htotal / mode->htotal;
1062 mode->htotal = new_htotal;
1063}
1064
1065static void intel_tv_scale_mode_vert(struct drm_display_mode *mode,
1066 int vdisplay, int top_margin,
1067 int bottom_margin)
1068{
1069 int vsync_start = mode->vsync_start - mode->vdisplay + bottom_margin;
1070 int vsync_end = mode->vsync_end - mode->vdisplay + bottom_margin;
1071 int new_vtotal = mode->vtotal * vdisplay /
1072 (mode->vdisplay - top_margin - bottom_margin);
1073
1074 mode->clock = mode->clock * new_vtotal / mode->vtotal;
1075
1076 mode->vdisplay = vdisplay;
1077 mode->vsync_start = vdisplay + vsync_start * new_vtotal / mode->vtotal;
1078 mode->vsync_end = vdisplay + vsync_end * new_vtotal / mode->vtotal;
1079 mode->vtotal = new_vtotal;
1080}
1081
7a495cfd
DV		 1082static void
1083intel_tv_get_config(struct intel_encoder *encoder,
5cec258b 1084 struct intel_crtc_state *pipe_config)
7a495cfd 1085{
e3bb355c
VS		 1086 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1087 struct drm_display_mode *adjusted_mode =
1088 &pipe_config->base.adjusted_mode;
1089 struct drm_display_mode mode = {};
1090 u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
1091 struct tv_mode tv_mode = {};
1092 int hdisplay = adjusted_mode->crtc_hdisplay;
1093 int vdisplay = adjusted_mode->crtc_vdisplay;
1094 int xsize, ysize, xpos, ypos;
1095
e1214b95
VS		 1096 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
1097
e3bb355c
VS		 1098 tv_ctl = I915_READ(TV_CTL);
1099 hctl1 = I915_READ(TV_H_CTL_1);
1100 hctl3 = I915_READ(TV_H_CTL_3);
1101 vctl1 = I915_READ(TV_V_CTL_1);
1102 vctl2 = I915_READ(TV_V_CTL_2);
1103
1104 tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT;
1105 tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT;
1106
1107 tv_mode.hblank_start = (hctl3 & TV_HBLANK_START_MASK) >> TV_HBLANK_START_SHIFT;
1108 tv_mode.hblank_end = (hctl3 & TV_HSYNC_END_MASK) >> TV_HBLANK_END_SHIFT;
1109
1110 tv_mode.nbr_end = (vctl1 & TV_NBR_END_MASK) >> TV_NBR_END_SHIFT;
1111 tv_mode.vi_end_f1 = (vctl1 & TV_VI_END_F1_MASK) >> TV_VI_END_F1_SHIFT;
1112 tv_mode.vi_end_f2 = (vctl1 & TV_VI_END_F2_MASK) >> TV_VI_END_F2_SHIFT;
1113
1114 tv_mode.vsync_len = (vctl2 & TV_VSYNC_LEN_MASK) >> TV_VSYNC_LEN_SHIFT;
1115 tv_mode.vsync_start_f1 = (vctl2 & TV_VSYNC_START_F1_MASK) >> TV_VSYNC_START_F1_SHIFT;
1116 tv_mode.vsync_start_f2 = (vctl2 & TV_VSYNC_START_F2_MASK) >> TV_VSYNC_START_F2_SHIFT;
1117
1118 tv_mode.clock = pipe_config->port_clock;
1119
1120 tv_mode.progressive = tv_ctl & TV_PROGRESSIVE;
1121
1122 switch (tv_ctl & TV_OVERSAMPLE_MASK) {
1123 case TV_OVERSAMPLE_8X:
1124 tv_mode.oversample = 8;
1125 break;
1126 case TV_OVERSAMPLE_4X:
1127 tv_mode.oversample = 4;
1128 break;
1129 case TV_OVERSAMPLE_2X:
1130 tv_mode.oversample = 2;
1131 break;
1132 default:
1133 tv_mode.oversample = 1;
1134 break;
1135 }
1136
1137 tmp = I915_READ(TV_WIN_POS);
1138 xpos = tmp >> 16;
1139 ypos = tmp & 0xffff;
1140
1141 tmp = I915_READ(TV_WIN_SIZE);
1142 xsize = tmp >> 16;
1143 ysize = tmp & 0xffff;
1144
1145 intel_tv_mode_to_mode(&mode, &tv_mode);
1146
1147 DRM_DEBUG_KMS("TV mode:\n");
1148 drm_mode_debug_printmodeline(&mode);
1149
1150 intel_tv_scale_mode_horiz(&mode, hdisplay,
1151 xpos, mode.hdisplay - xsize - xpos);
1152 intel_tv_scale_mode_vert(&mode, vdisplay,
1153 ypos, mode.vdisplay - ysize - ypos);
1154
1155 adjusted_mode->crtc_clock = mode.clock;
addc80f0
VS		 1156 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1157 adjusted_mode->crtc_clock /= 2;
8a920e24
VS		 1158
1159 /* pixel counter doesn't work on i965gm TV output */
1160 if (IS_I965GM(dev_priv))
1161 adjusted_mode->private_flags |=
1162 I915_MODE_FLAG_USE_SCANLINE_COUNTER;
7a495cfd
DV		 1163}
1164
68e94f62
VS		 1165static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv,
1166 int hdisplay)
1167{
1168 return IS_GEN(dev_priv, 3) && hdisplay > 1024;
1169}
1170
1171static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
1172 const struct drm_connector_state *conn_state,
1173 int vdisplay)
1174{
1175 return tv_mode->crtc_vdisplay -
1176 conn_state->tv.margins.top -
1177 conn_state->tv.margins.bottom !=
1178 vdisplay;
1179}
1180
204474a6 1181static int
5d2d38dd 1182intel_tv_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1183 struct intel_crtc_state *pipe_config,
1184 struct drm_connector_state *conn_state)
79e53945 1185{
690157f0
VS		 1186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1187 struct intel_tv_connector_state *tv_conn_state =
1188 to_intel_tv_connector_state(conn_state);
0e891b3f 1189 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
e4dd27aa
VS		 1190 struct drm_display_mode *adjusted_mode =
1191 &pipe_config->base.adjusted_mode;
e3bb355c
VS		 1192 int hdisplay = adjusted_mode->crtc_hdisplay;
1193 int vdisplay = adjusted_mode->crtc_vdisplay;
79e53945
JB		 1194
1195 if (!tv_mode)
204474a6 1196 return -EINVAL;
79e53945 1197
e4dd27aa 1198 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
204474a6 1199 return -EINVAL;
e4dd27aa 1200
d9facae6 1201 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
e3bb355c 1202
5d2d38dd
DV		 1203 DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
1204 pipe_config->pipe_bpp = 8*3;
1205
e3bb355c
VS		 1206 pipe_config->port_clock = tv_mode->clock;
1207
1208 intel_tv_mode_to_mode(adjusted_mode, tv_mode);
690157f0
VS		 1209 drm_mode_set_crtcinfo(adjusted_mode, 0);
1210
68e94f62
VS		 1211 if (intel_tv_source_too_wide(dev_priv, hdisplay) ||
1212 !intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) {
690157f0
VS		 1213 int extra, top, bottom;
1214
1215 extra = adjusted_mode->crtc_vdisplay - vdisplay;
1216
1217 if (extra < 0) {
1218 DRM_DEBUG_KMS("No vertical scaling for >1024 pixel wide modes\n");
6a2a9404 1219 return -EINVAL;
690157f0
VS		 1220 }
1221
1222 /* Need to turn off the vertical filter and center the image */
1223
1224 /* Attempt to maintain the relative sizes of the margins */
1225 top = conn_state->tv.margins.top;
1226 bottom = conn_state->tv.margins.bottom;
1227
1228 if (top + bottom)
1229 top = extra * top / (top + bottom);
1230 else
1231 top = extra / 2;
1232 bottom = extra - top;
1233
1234 tv_conn_state->margins.top = top;
1235 tv_conn_state->margins.bottom = bottom;
1236
1237 tv_conn_state->bypass_vfilter = true;
1238
addc80f0
VS		 1239 if (!tv_mode->progressive) {
1240 adjusted_mode->clock /= 2;
1241 adjusted_mode->crtc_clock /= 2;
690157f0 1242 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
addc80f0 1243 }
690157f0
VS		 1244 } else {
1245 tv_conn_state->margins.top = conn_state->tv.margins.top;
1246 tv_conn_state->margins.bottom = conn_state->tv.margins.bottom;
1247
1248 tv_conn_state->bypass_vfilter = false;
1249 }
e3bb355c
VS		 1250
1251 DRM_DEBUG_KMS("TV mode:\n");
1252 drm_mode_debug_printmodeline(adjusted_mode);
1062b815
DV		 1253
1254 /*
e3bb355c
VS		 1255 * The pipe scanline counter behaviour looks as follows when
1256 * using the TV encoder:
1257 *
1258 * time ->
1259 *
1260 * dsl=vtotal-1 | |
1261 * || ||
1262 * ___| | ___| |
1263 * / | / |
1264 * / | / |
1265 * dsl=0 ___/ |_____/ |
1266 * | | | | | |
1267 * ^ ^ ^ ^ ^
1268 * | | | | pipe vblank/first part of tv vblank
1269 * | | | bottom margin
1270 * | | active
1271 * | top margin
1272 * remainder of tv vblank
1273 *
1274 * When the TV encoder is used the pipe wants to run faster
1275 * than expected rate. During the active portion the TV
1276 * encoder stalls the pipe every few lines to keep it in
1277 * check. When the TV encoder reaches the bottom margin the
1278 * pipe simply stops. Once we reach the TV vblank the pipe is
1279 * no longer stalled and it runs at the max rate (apparently
1280 * oversample clock on gen3, cdclk on gen4). Once the pipe
1281 * reaches the pipe vtotal the pipe stops for the remainder
1282 * of the TV vblank/top margin. The pipe starts up again when
1283 * the TV encoder exits the top margin.
1284 *
1285 * To avoid huge hassles for vblank timestamping we scale
1286 * the pipe timings as if the pipe always runs at the average
1287 * rate it maintains during the active period. This also
1288 * gives us a reasonable guesstimate as to the pixel rate.
1289 * Due to the variation in the actual pipe speed the scanline
1290 * counter will give us slightly erroneous results during the
1291 * TV vblank/margins. But since vtotal was selected such that
1292 * it matches the average rate of the pipe during the active
1293 * portion the error shouldn't cause any serious grief to
1294 * vblank timestamps.
1295 *
1296 * For posterity here is the empirically derived formula
1297 * that gives us the maximum length of the pipe vblank
1298 * we can use without causing display corruption. Following
1299 * this would allow us to have a ticking scanline counter
1300 * everywhere except during the bottom margin (there the
1301 * pipe always stops). Ie. this would eliminate the second
1302 * flat portion of the above graph. However this would also
1303 * complicate vblank timestamping as the pipe vtotal would
1304 * no longer match the average rate the pipe runs at during
1305 * the active portion. Hence following this formula seems
1306 * more trouble that it's worth.
1307 *
1308 * if (IS_GEN(dev_priv, 4)) {
1309 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive);
1310 * den = tv_mode->clock;
1311 * } else {
1312 * num = tv_mode->oversample >> !tv_mode->progressive;
1313 * den = 1;
1314 * }
1315 * max_pipe_vblank_len ~=
1316 * (num * tv_htotal * (tv_vblank_len + top_margin)) /
1317 * (den * pipe_htotal);
1062b815 1318 */
e3bb355c
VS		 1319 intel_tv_scale_mode_horiz(adjusted_mode, hdisplay,
1320 conn_state->tv.margins.left,
1321 conn_state->tv.margins.right);
1322 intel_tv_scale_mode_vert(adjusted_mode, vdisplay,
690157f0
VS		 1323 tv_conn_state->margins.top,
1324 tv_conn_state->margins.bottom);
e3bb355c
VS		 1325 drm_mode_set_crtcinfo(adjusted_mode, 0);
1326 adjusted_mode->name[0] = '\0';
1062b815 1327
8a920e24
VS		 1328 /* pixel counter doesn't work on i965gm TV output */
1329 if (IS_I965GM(dev_priv))
1330 adjusted_mode->private_flags |=
1331 I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1332
204474a6 1333 return 0;
79e53945
JB		 1334}
1335
8cb92203
DV		 1336static void
1337set_tv_mode_timings(struct drm_i915_private *dev_priv,
1338 const struct tv_mode *tv_mode,
1339 bool burst_ena)
1340{
1341 u32 hctl1, hctl2, hctl3;
1342 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
1343
1344 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
1345 (tv_mode->htotal << TV_HTOTAL_SHIFT);
1346
1347 hctl2 = (tv_mode->hburst_start << 16) |
1348 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
1349
1350 if (burst_ena)
1351 hctl2 |= TV_BURST_ENA;
1352
1353 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
1354 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
1355
1356 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
1357 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
1358 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
1359
1360 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
1361 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
1362 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
1363
1364 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
1365 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
1366 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
1367
1368 if (tv_mode->veq_ena)
1369 vctl3 |= TV_EQUAL_ENA;
1370
1371 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
1372 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
1373
1374 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
1375 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
1376
1377 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
1378 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
1379
1380 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
1381 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
1382
1383 I915_WRITE(TV_H_CTL_1, hctl1);
1384 I915_WRITE(TV_H_CTL_2, hctl2);
1385 I915_WRITE(TV_H_CTL_3, hctl3);
1386 I915_WRITE(TV_V_CTL_1, vctl1);
1387 I915_WRITE(TV_V_CTL_2, vctl2);
1388 I915_WRITE(TV_V_CTL_3, vctl3);
1389 I915_WRITE(TV_V_CTL_4, vctl4);
1390 I915_WRITE(TV_V_CTL_5, vctl5);
1391 I915_WRITE(TV_V_CTL_6, vctl6);
1392 I915_WRITE(TV_V_CTL_7, vctl7);
1393}
1394
b8866ef8
DV		 1395static void set_color_conversion(struct drm_i915_private *dev_priv,
1396 const struct color_conversion *color_conversion)
1397{
1398 if (!color_conversion)
1399 return;
1400
1401 I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
1402 color_conversion->gy);
1403 I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) |
1404 color_conversion->ay);
1405 I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
1406 color_conversion->gu);
1407 I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) |
1408 color_conversion->au);
1409 I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) |
1410 color_conversion->gv);
1411 I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) |
1412 color_conversion->av);
1413}
1414
fd6bbda9 1415static void intel_tv_pre_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 1416 const struct intel_crtc_state *pipe_config,
1417 const struct drm_connector_state *conn_state)
79e53945 1418{
66478475 1419 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
a7f519ba 1420 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
cd91ef23 1421 struct intel_tv *intel_tv = enc_to_tv(encoder);
690157f0
VS		 1422 const struct intel_tv_connector_state *tv_conn_state =
1423 to_intel_tv_connector_state(conn_state);
0e891b3f 1424 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
690157f0 1425 u32 tv_ctl, tv_filter_ctl;
79e53945
JB		 1426 u32 scctl1, scctl2, scctl3;
1427 int i, j;
1428 const struct video_levels *video_levels;
1429 const struct color_conversion *color_conversion;
1430 bool burst_ena;
bda5f532 1431 int xpos, ypos;
3fa2dd14 1432 unsigned int xsize, ysize;
79e53945
JB		 1433
1434 if (!tv_mode)
1435 return; /* can't happen (mode_prepare prevents this) */
1436
d2d9f232
ZW		 1437 tv_ctl = I915_READ(TV_CTL);
1438 tv_ctl &= TV_CTL_SAVE;
79e53945 1439
ea5b213a 1440 switch (intel_tv->type) {
79e53945
JB		 1441 default:
1442 case DRM_MODE_CONNECTOR_Unknown:
1443 case DRM_MODE_CONNECTOR_Composite:
1444 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
1445 video_levels = tv_mode->composite_levels;
1446 color_conversion = tv_mode->composite_color;
1447 burst_ena = tv_mode->burst_ena;
1448 break;
1449 case DRM_MODE_CONNECTOR_Component:
1450 tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
1451 video_levels = &component_levels;
1452 if (tv_mode->burst_ena)
1453 color_conversion = &sdtv_csc_yprpb;
1454 else
1455 color_conversion = &hdtv_csc_yprpb;
1456 burst_ena = false;
1457 break;
1458 case DRM_MODE_CONNECTOR_SVIDEO:
1459 tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
1460 video_levels = tv_mode->svideo_levels;
1461 color_conversion = tv_mode->svideo_color;
1462 burst_ena = tv_mode->burst_ena;
1463 break;
1464 }
79e53945 1465
4add0f6b 1466 tv_ctl |= TV_ENC_PIPE_SEL(intel_crtc->pipe);
4f503798
VS		 1467
1468 switch (tv_mode->oversample) {
1469 case 8:
1470 tv_ctl |= TV_OVERSAMPLE_8X;
1471 break;
1472 case 4:
1473 tv_ctl |= TV_OVERSAMPLE_4X;
1474 break;
1475 case 2:
1476 tv_ctl |= TV_OVERSAMPLE_2X;
1477 break;
1478 default:
1479 tv_ctl |= TV_OVERSAMPLE_NONE;
1480 break;
1481 }
79e53945
JB		 1482
1483 if (tv_mode->progressive)
1484 tv_ctl |= TV_PROGRESSIVE;
1485 if (tv_mode->trilevel_sync)
1486 tv_ctl |= TV_TRILEVEL_SYNC;
1487 if (tv_mode->pal_burst)
1488 tv_ctl |= TV_PAL_BURST;
d271817b 1489
79e53945 1490 scctl1 = 0;
d271817b 1491 if (tv_mode->dda1_inc)
79e53945 1492 scctl1 |= TV_SC_DDA1_EN;
79e53945
JB		 1493 if (tv_mode->dda2_inc)
1494 scctl1 |= TV_SC_DDA2_EN;
79e53945
JB		 1495 if (tv_mode->dda3_inc)
1496 scctl1 |= TV_SC_DDA3_EN;
79e53945 1497 scctl1 |= tv_mode->sc_reset;
d271817b
CW		 1498 if (video_levels)
1499 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
79e53945
JB		 1500 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
1501
1502 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
1503 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;
1504
1505 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
1506 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
1507
1508 /* Enable two fixes for the chips that need them. */
50a0bc90 1509 if (IS_I915GM(dev_priv))
79e53945
JB		 1510 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
1511
8cb92203
DV		 1512 set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
1513
79e53945
JB		 1514 I915_WRITE(TV_SC_CTL_1, scctl1);
1515 I915_WRITE(TV_SC_CTL_2, scctl2);
1516 I915_WRITE(TV_SC_CTL_3, scctl3);
1517
b8866ef8 1518 set_color_conversion(dev_priv, color_conversion);
79e53945 1519
66478475 1520 if (INTEL_GEN(dev_priv) >= 4)
d2d9f232
ZW		 1521 I915_WRITE(TV_CLR_KNOBS, 0x00404000);
1522 else
1523 I915_WRITE(TV_CLR_KNOBS, 0x00606000);
1524
79e53945
JB		 1525 if (video_levels)
1526 I915_WRITE(TV_CLR_LEVEL,
1527 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
1528 (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
3fa2dd14
DV		 1529
1530 assert_pipe_disabled(dev_priv, intel_crtc->pipe);
1531
1532 /* Filter ctl must be set before TV_WIN_SIZE */
690157f0
VS		 1533 tv_filter_ctl = TV_AUTO_SCALE;
1534 if (tv_conn_state->bypass_vfilter)
1535 tv_filter_ctl |= TV_V_FILTER_BYPASS;
1536 I915_WRITE(TV_FILTER_CTL_1, tv_filter_ctl);
1537
3fa2dd14 1538 xsize = tv_mode->hblank_start - tv_mode->hblank_end;
65ddf7f9 1539 ysize = intel_tv_mode_vdisplay(tv_mode);
3fa2dd14 1540
bda5f532 1541 xpos = conn_state->tv.margins.left;
690157f0 1542 ypos = tv_conn_state->margins.top;
0e891b3f
ML		 1543 xsize -= (conn_state->tv.margins.left +
1544 conn_state->tv.margins.right);
690157f0
VS		 1545 ysize -= (tv_conn_state->margins.top +
1546 tv_conn_state->margins.bottom);
3fa2dd14
DV		 1547 I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
1548 I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
79e53945
JB		 1549
1550 j = 0;
1551 for (i = 0; i < 60; i++)
184d7c06 1552 I915_WRITE(TV_H_LUMA(i), tv_mode->filter_table[j++]);
79e53945 1553 for (i = 0; i < 60; i++)
184d7c06 1554 I915_WRITE(TV_H_CHROMA(i), tv_mode->filter_table[j++]);
79e53945 1555 for (i = 0; i < 43; i++)
184d7c06 1556 I915_WRITE(TV_V_LUMA(i), tv_mode->filter_table[j++]);
79e53945 1557 for (i = 0; i < 43; i++)
184d7c06 1558 I915_WRITE(TV_V_CHROMA(i), tv_mode->filter_table[j++]);
b8ed2a4f 1559 I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
79e53945
JB		 1560 I915_WRITE(TV_CTL, tv_ctl);
1561}
1562
79e53945 1563static int
0206e353 1564intel_tv_detect_type(struct intel_tv *intel_tv,
8102e126 1565 struct drm_connector *connector)
79e53945 1566{
0eadc624 1567 struct drm_crtc *crtc = connector->state->crtc;
835bff7e 1568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0eadc624 1569 struct drm_device *dev = connector->dev;
fac5e23e 1570 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945
JB		 1571 u32 tv_ctl, save_tv_ctl;
1572 u32 tv_dac, save_tv_dac;
974b9331 1573 int type;
79e53945
JB		 1574
1575 /* Disable TV interrupts around load detect or we'll recurse */
8102e126 1576 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
2795aa48 1577 spin_lock_irq(&dev_priv->irq_lock);
8102e126 1578 i915_disable_pipestat(dev_priv, 0,
755e9019
ID		 1579 PIPE_HOTPLUG_INTERRUPT_STATUS |
1580 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
2795aa48 1581 spin_unlock_irq(&dev_priv->irq_lock);
8102e126 1582 }
79e53945 1583
974b9331
CW		 1584 save_tv_dac = tv_dac = I915_READ(TV_DAC);
1585 save_tv_ctl = tv_ctl = I915_READ(TV_CTL);
1586
1587 /* Poll for TV detection */
4add0f6b 1588 tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK);
8ed9a5bc 1589 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
4add0f6b 1590 tv_ctl |= TV_ENC_PIPE_SEL(intel_crtc->pipe);
974b9331
CW		 1591
1592 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
8ed9a5bc 1593 tv_dac |= (TVDAC_STATE_CHG_EN |
1594 TVDAC_A_SENSE_CTL |
1595 TVDAC_B_SENSE_CTL |
1596 TVDAC_C_SENSE_CTL |
1597 DAC_CTL_OVERRIDE |
1598 DAC_A_0_7_V |
1599 DAC_B_0_7_V |
1600 DAC_C_0_7_V);
974b9331 1601
d42c9e2c
DV		 1602
1603 /*
1604 * The TV sense state should be cleared to zero on cantiga platform. Otherwise
1605 * the TV is misdetected. This is hardware requirement.
1606 */
50a0bc90 1607 if (IS_GM45(dev_priv))
d42c9e2c
DV		 1608 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1609 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1610
8ed9a5bc 1611 I915_WRITE(TV_CTL, tv_ctl);
1612 I915_WRITE(TV_DAC, tv_dac);
4f233eff 1613 POSTING_READ(TV_DAC);
4f233eff 1614
0f0f74bc 1615 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
29e1316a 1616
974b9331 1617 type = -1;
2bf71160
KP		 1618 tv_dac = I915_READ(TV_DAC);
1619 DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl, tv_dac);
1620 /*
1621 * A B C
1622 * 0 1 1 Composite
1623 * 1 0 X svideo
1624 * 0 0 0 Component
1625 */
1626 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
1627 DRM_DEBUG_KMS("Detected Composite TV connection\n");
1628 type = DRM_MODE_CONNECTOR_Composite;
1629 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
1630 DRM_DEBUG_KMS("Detected S-Video TV connection\n");
1631 type = DRM_MODE_CONNECTOR_SVIDEO;
1632 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
1633 DRM_DEBUG_KMS("Detected Component TV connection\n");
1634 type = DRM_MODE_CONNECTOR_Component;
1635 } else {
1636 DRM_DEBUG_KMS("Unrecognised TV connection\n");
1637 type = -1;
79e53945
JB		 1638 }
1639
974b9331
CW		 1640 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1641 I915_WRITE(TV_CTL, save_tv_ctl);
bf2125e2
DV		 1642 POSTING_READ(TV_CTL);
1643
1644 /* For unknown reasons the hw barfs if we don't do this vblank wait. */
0f0f74bc 1645 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
974b9331 1646
79e53945 1647 /* Restore interrupt config */
8102e126 1648 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
2795aa48 1649 spin_lock_irq(&dev_priv->irq_lock);
8102e126 1650 i915_enable_pipestat(dev_priv, 0,
755e9019
ID		 1651 PIPE_HOTPLUG_INTERRUPT_STATUS |
1652 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
2795aa48 1653 spin_unlock_irq(&dev_priv->irq_lock);
8102e126 1654 }
79e53945
JB		 1655
1656 return type;
1657}
1658
213c2e64
ML		 1659/*
1660 * Here we set accurate tv format according to connector type
1661 * i.e Component TV should not be assigned by NTSC or PAL
1662 */
1663static void intel_tv_find_better_format(struct drm_connector *connector)
1664{
df0e9248 1665 struct intel_tv *intel_tv = intel_attached_tv(connector);
0e891b3f 1666 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
213c2e64
ML		 1667 int i;
1668
e94390aa
VS		 1669 /* Component supports everything so we can keep the current mode */
1670 if (intel_tv->type == DRM_MODE_CONNECTOR_Component)
213c2e64
ML		 1671 return;
1672
e94390aa
VS		 1673 /* If the current mode is fine don't change it */
1674 if (!tv_mode->component_only)
1675 return;
213c2e64 1676
53abb679 1677 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
e94390aa 1678 tv_mode = &tv_modes[i];
213c2e64 1679
e94390aa 1680 if (!tv_mode->component_only)
213c2e64
ML		 1681 break;
1682 }
1683
0e891b3f 1684 connector->state->tv.mode = i;
213c2e64
ML		 1685}
1686
6c5ed5ae
ML		 1687static int
1688intel_tv_detect(struct drm_connector *connector,
1689 struct drm_modeset_acquire_ctx *ctx,
1690 bool force)
79e53945 1691{
df0e9248 1692 struct intel_tv *intel_tv = intel_attached_tv(connector);
bbfb44e8 1693 enum drm_connector_status status;
ea5b213a 1694 int type;
79e53945 1695
164c8598 1696 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
c23cc417 1697 connector->base.id, connector->name,
164c8598
CW		 1698 force);
1699
38de45c5 1700 if (force) {
8261b191 1701 struct intel_load_detect_pipe tmp;
6c5ed5ae 1702 int ret;
ea5b213a 1703
528132a3 1704 ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
6c5ed5ae
ML		 1705 if (ret < 0)
1706 return ret;
208bf9fd 1707
6c5ed5ae 1708 if (ret > 0) {
8102e126 1709 type = intel_tv_detect_type(intel_tv, connector);
6c5ed5ae 1710 intel_release_load_detect_pipe(connector, &tmp, ctx);
bbfb44e8
VS		 1711 status = type < 0 ?
1712 connector_status_disconnected :
1713 connector_status_connected;
79e53945 1714 } else
bbfb44e8 1715 status = connector_status_unknown;
bf5a269a 1716
0e891b3f
ML		 1717 if (status == connector_status_connected) {
1718 intel_tv->type = type;
1719 intel_tv_find_better_format(connector);
1720 }
d5627663 1721
0e891b3f
ML		 1722 return status;
1723 } else
1724 return connector->status;
79e53945
JB		 1725}
1726
763a4a01 1727static const struct input_res {
5023520f 1728 u16 w, h;
763a4a01 1729} input_res_table[] = {
5023520f
VS		 1730 { 640, 480 },
1731 { 800, 600 },
1732 { 1024, 768 },
1733 { 1280, 1024 },
1734 { 848, 480 },
1735 { 1280, 720 },
1736 { 1920, 1080 },
79e53945
JB		 1737};
1738
65ddf7f9
VS		 1739/* Choose preferred mode according to line number of TV format */
1740static bool
1741intel_tv_is_preferred_mode(const struct drm_display_mode *mode,
1742 const struct tv_mode *tv_mode)
1743{
1744 int vdisplay = intel_tv_mode_vdisplay(tv_mode);
1745
1746 /* prefer 480 line modes for all SD TV modes */
1747 if (vdisplay <= 576)
1748 vdisplay = 480;
1749
1750 return vdisplay == mode->vdisplay;
1751}
1752
bcae2ca8 1753static void
65ddf7f9
VS		 1754intel_tv_set_mode_type(struct drm_display_mode *mode,
1755 const struct tv_mode *tv_mode)
bcae2ca8 1756{
65ddf7f9
VS		 1757 mode->type = DRM_MODE_TYPE_DRIVER;
1758
1759 if (intel_tv_is_preferred_mode(mode, tv_mode))
1760 mode->type |= DRM_MODE_TYPE_PREFERRED;
bcae2ca8 1761}
1762
79e53945
JB		 1763static int
1764intel_tv_get_modes(struct drm_connector *connector)
1765{
0bb1ffe4 1766 struct drm_i915_private *dev_priv = to_i915(connector->dev);
0e891b3f 1767 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
e3bb355c 1768 int i, count = 0;
79e53945 1769
e3bb355c
VS		 1770 for (i = 0; i < ARRAY_SIZE(input_res_table); i++) {
1771 const struct input_res *input = &input_res_table[i];
1772 struct drm_display_mode *mode;
79e53945 1773
e3bb355c
VS		 1774 if (input->w > 1024 &&
1775 !tv_mode->progressive &&
1776 !tv_mode->component_only)
79e53945
JB		 1777 continue;
1778
0bb1ffe4
VS		 1779 /* no vertical scaling with wide sources on gen3 */
1780 if (IS_GEN(dev_priv, 3) && input->w > 1024 &&
1781 input->h > intel_tv_mode_vdisplay(tv_mode))
1782 continue;
1783
e3bb355c
VS		 1784 mode = drm_mode_create(connector->dev);
1785 if (!mode)
02c5dd98 1786 continue;
79e53945 1787
e3bb355c
VS		 1788 /*
1789 * We take the TV mode and scale it to look
1790 * like it had the expected h/vdisplay. This
1791 * provides the most information to userspace
1792 * about the actual timings of the mode. We
1793 * do ignore the margins though.
1794 */
1795 intel_tv_mode_to_mode(mode, tv_mode);
1796 if (count == 0) {
1797 DRM_DEBUG_KMS("TV mode:\n");
1798 drm_mode_debug_printmodeline(mode);
1799 }
1800 intel_tv_scale_mode_horiz(mode, input->w, 0, 0);
1801 intel_tv_scale_mode_vert(mode, input->h, 0, 0);
1802 intel_tv_set_mode_type(mode, tv_mode);
5023520f 1803
e3bb355c 1804 drm_mode_set_name(mode);
5023520f 1805
e3bb355c 1806 drm_mode_probed_add(connector, mode);
02c5dd98 1807 count++;
79e53945
JB		 1808 }
1809
02c5dd98 1810 return count;
79e53945
JB		 1811}
1812
79e53945 1813static const struct drm_connector_funcs intel_tv_connector_funcs = {
1ebaa0b9 1814 .late_register = intel_connector_register,
c191eca1 1815 .early_unregister = intel_connector_unregister,
d4b26e4f 1816 .destroy = intel_connector_destroy,
79e53945 1817 .fill_modes = drm_helper_probe_single_connector_modes,
c6f95f27 1818 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
690157f0 1819 .atomic_duplicate_state = intel_tv_connector_duplicate_state,
79e53945
JB		 1820};
1821
0e891b3f 1822static int intel_tv_atomic_check(struct drm_connector *connector,
6f3b6278 1823 struct drm_atomic_state *state)
0e891b3f 1824{
6f3b6278 1825 struct drm_connector_state *new_state;
0e891b3f
ML		 1826 struct drm_crtc_state *new_crtc_state;
1827 struct drm_connector_state *old_state;
1828
6f3b6278 1829 new_state = drm_atomic_get_new_connector_state(state, connector);
0e891b3f
ML		 1830 if (!new_state->crtc)
1831 return 0;
1832
6f3b6278
SP		 1833 old_state = drm_atomic_get_old_connector_state(state, connector);
1834 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
0e891b3f
ML		 1835
1836 if (old_state->tv.mode != new_state->tv.mode ||
1837 old_state->tv.margins.left != new_state->tv.margins.left ||
1838 old_state->tv.margins.right != new_state->tv.margins.right ||
1839 old_state->tv.margins.top != new_state->tv.margins.top ||
1840 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
1841 /* Force a modeset. */
1842
1843 new_crtc_state->connectors_changed = true;
1844 }
1845
1846 return 0;
1847}
1848
79e53945 1849static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
6c5ed5ae 1850 .detect_ctx = intel_tv_detect,
79e53945
JB		 1851 .mode_valid = intel_tv_mode_valid,
1852 .get_modes = intel_tv_get_modes,
0e891b3f 1853 .atomic_check = intel_tv_atomic_check,
79e53945
JB		 1854};
1855
79e53945 1856static const struct drm_encoder_funcs intel_tv_enc_funcs = {
ea5b213a 1857 .destroy = intel_encoder_destroy,
79e53945
JB		 1858};
1859
79e53945 1860void
c39055b0 1861intel_tv_init(struct drm_i915_private *dev_priv)
79e53945 1862{
c39055b0 1863 struct drm_device *dev = &dev_priv->drm;
79e53945 1864 struct drm_connector *connector;
ea5b213a 1865 struct intel_tv *intel_tv;
21d40d37 1866 struct intel_encoder *intel_encoder;
0c41ee2b 1867 struct intel_connector *intel_connector;
79e53945 1868 u32 tv_dac_on, tv_dac_off, save_tv_dac;
b7c914b3 1869 const char *tv_format_names[ARRAY_SIZE(tv_modes)];
79e53945 1870 int i, initial_mode = 0;
0e891b3f 1871 struct drm_connector_state *state;
79e53945
JB		 1872
1873 if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
1874 return;
1875
3bdd14d5 1876 if (!intel_bios_is_tv_present(dev_priv)) {
c3561438
ZY		 1877 DRM_DEBUG_KMS("Integrated TV is not present.\n");
1878 return;
1879 }
79e53945
JB		 1880
1881 /*
1882 * Sanity check the TV output by checking to see if the
1883 * DAC register holds a value
1884 */
1885 save_tv_dac = I915_READ(TV_DAC);
1886
1887 I915_WRITE(TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
1888 tv_dac_on = I915_READ(TV_DAC);
1889
1890 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1891 tv_dac_off = I915_READ(TV_DAC);
1892
1893 I915_WRITE(TV_DAC, save_tv_dac);
1894
1895 /*
1896 * If the register does not hold the state change enable
1897 * bit, (either as a 0 or a 1), assume it doesn't really
1898 * exist
1899 */
1900 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
1901 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1902 return;
1903
b14c5679 1904 intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL);
ea5b213a 1905 if (!intel_tv) {
79e53945
JB		 1906 return;
1907 }
f8aed700 1908
08d9bc92 1909 intel_connector = intel_connector_alloc();
0c41ee2b 1910 if (!intel_connector) {
ea5b213a 1911 kfree(intel_tv);
0c41ee2b
ZW		 1912 return;
1913 }
1914
ea5b213a 1915 intel_encoder = &intel_tv->base;
0c41ee2b 1916 connector = &intel_connector->base;
0e891b3f 1917 state = connector->state;
79e53945 1918
3930f18a
CW		 1919 /*
1920 * The documentation, for the older chipsets at least, recommend
8102e126
CW		 1921 * using a polling method rather than hotplug detection for TVs.
1922 * This is because in order to perform the hotplug detection, the PLLs
1923 * for the TV must be kept alive increasing power drain and starving
1924 * bandwidth from other encoders. Notably for instance, it causes
1925 * pipe underruns on Crestline when this encoder is supposedly idle.
1926 *
1927 * More recent chipsets favour HDMI rather than integrated S-Video.
1928 */
821450c6 1929 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
8102e126 1930
79e53945
JB		 1931 drm_connector_init(dev, connector, &intel_tv_connector_funcs,
1932 DRM_MODE_CONNECTOR_SVIDEO);
1933
4ef69c7a 1934 drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs,
580d8ed5 1935 DRM_MODE_ENCODER_TVDAC, "TV");
79e53945 1936
5d2d38dd 1937 intel_encoder->compute_config = intel_tv_compute_config;
7a495cfd 1938 intel_encoder->get_config = intel_tv_get_config;
809a2a8b 1939 intel_encoder->pre_enable = intel_tv_pre_enable;
6b5756a0
DV		 1940 intel_encoder->enable = intel_enable_tv;
1941 intel_encoder->disable = intel_disable_tv;
9a8ee983
DV		 1942 intel_encoder->get_hw_state = intel_tv_get_hw_state;
1943 intel_connector->get_hw_state = intel_connector_get_hw_state;
6b5756a0 1944
df0e9248 1945 intel_connector_attach_encoder(intel_connector, intel_encoder);
03cdc1d4 1946
21d40d37 1947 intel_encoder->type = INTEL_OUTPUT_TVOUT;
79f255a0 1948 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4 1949 intel_encoder->port = PORT_NONE;
0fbae9d2 1950 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B);
bc079e8b 1951 intel_encoder->cloneable = 0;
ea5b213a 1952 intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
79e53945
JB		 1953
1954 /* BIOS margin values */
0e891b3f
ML		 1955 state->tv.margins.left = 54;
1956 state->tv.margins.top = 36;
1957 state->tv.margins.right = 46;
1958 state->tv.margins.bottom = 37;
79e53945 1959
0e891b3f 1960 state->tv.mode = initial_mode;
79e53945 1961
79e53945
JB		 1962 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
1963 connector->interlace_allowed = false;
1964 connector->doublescan_allowed = false;
1965
1966 /* Create TV properties then attach current values */
a0ff6779
VS		 1967 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
1968 /* 1080p50/1080p60 not supported on gen3 */
1969 if (IS_GEN(dev_priv, 3) &&
1970 tv_modes[i].oversample == 1)
1971 break;
1972
b7c914b3 1973 tv_format_names[i] = tv_modes[i].name;
a0ff6779
VS		 1974 }
1975 drm_mode_create_tv_properties(dev, i, tv_format_names);
79e53945 1976
662595df 1977 drm_object_attach_property(&connector->base, dev->mode_config.tv_mode_property,
0e891b3f 1978 state->tv.mode);
662595df 1979 drm_object_attach_property(&connector->base,
79e53945 1980 dev->mode_config.tv_left_margin_property,
0e891b3f 1981 state->tv.margins.left);
662595df 1982 drm_object_attach_property(&connector->base,
79e53945 1983 dev->mode_config.tv_top_margin_property,
0e891b3f 1984 state->tv.margins.top);
662595df 1985 drm_object_attach_property(&connector->base,
79e53945 1986 dev->mode_config.tv_right_margin_property,
0e891b3f 1987 state->tv.margins.right);
662595df 1988 drm_object_attach_property(&connector->base,
79e53945 1989 dev->mode_config.tv_bottom_margin_property,
0e891b3f 1990 state->tv.margins.bottom);
79e53945 1991}
Linux 6.x block layer and io_uring tree(s)