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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
7d57382e | 29 | #include <linux/delay.h> |
178f736a | 30 | #include <linux/hdmi.h> |
331c201a JN |
31 | #include <linux/i2c.h> |
32 | #include <linux/slab.h> | |
33 | ||
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
2320175f | 37 | #include <drm/drm_hdcp.h> |
15953637 | 38 | #include <drm/drm_scdc_helper.h> |
760285e7 | 39 | #include <drm/i915_drm.h> |
46d196ec | 40 | #include <drm/intel_lpe_audio.h> |
331c201a | 41 | |
2126d3e9 | 42 | #include "i915_debugfs.h" |
7d57382e | 43 | #include "i915_drv.h" |
12392a74 | 44 | #include "intel_atomic.h" |
331c201a | 45 | #include "intel_audio.h" |
ec7f29ff | 46 | #include "intel_connector.h" |
fdc24cf3 | 47 | #include "intel_ddi.h" |
1d455f8d | 48 | #include "intel_display_types.h" |
27fec1f9 | 49 | #include "intel_dp.h" |
b1ad4c39 | 50 | #include "intel_dpio_phy.h" |
8834e365 | 51 | #include "intel_fifo_underrun.h" |
3ce2ea65 | 52 | #include "intel_gmbus.h" |
408bd917 | 53 | #include "intel_hdcp.h" |
0550691d | 54 | #include "intel_hdmi.h" |
dbeb38d9 | 55 | #include "intel_hotplug.h" |
f3e18947 | 56 | #include "intel_lspcon.h" |
44c1220a | 57 | #include "intel_panel.h" |
1d455f8d | 58 | #include "intel_sdvo.h" |
56c5098f | 59 | #include "intel_sideband.h" |
7d57382e | 60 | |
30add22d PZ |
61 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
62 | { | |
da63a9f2 | 63 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
64 | } |
65 | ||
afba0188 DV |
66 | static void |
67 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
68 | { | |
30add22d | 69 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
fac5e23e | 70 | struct drm_i915_private *dev_priv = to_i915(dev); |
faa087c4 | 71 | u32 enabled_bits; |
afba0188 | 72 | |
4f8036a2 | 73 | enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 74 | |
b242b7f7 | 75 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
76 | "HDMI port enabled, expecting disabled\n"); |
77 | } | |
78 | ||
8fc0aa6e ID |
79 | static void |
80 | assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, | |
81 | enum transcoder cpu_transcoder) | |
82 | { | |
83 | WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & | |
84 | TRANS_DDI_FUNC_ENABLE, | |
85 | "HDMI transcoder function enabled, expecting disabled\n"); | |
86 | } | |
87 | ||
f5bbfca3 | 88 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 89 | { |
da63a9f2 PZ |
90 | struct intel_digital_port *intel_dig_port = |
91 | container_of(encoder, struct intel_digital_port, base.base); | |
92 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
93 | } |
94 | ||
df0e9248 CW |
95 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
96 | { | |
da63a9f2 | 97 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
98 | } |
99 | ||
1d776538 | 100 | static u32 g4x_infoframe_index(unsigned int type) |
3c17fe4b | 101 | { |
178f736a | 102 | switch (type) { |
5cb3c1a1 VS |
103 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
104 | return VIDEO_DIP_SELECT_GAMUT; | |
178f736a | 105 | case HDMI_INFOFRAME_TYPE_AVI: |
ed517fbb | 106 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 107 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 108 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
109 | case HDMI_INFOFRAME_TYPE_VENDOR: |
110 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 111 | default: |
ffc85dab | 112 | MISSING_CASE(type); |
ed517fbb | 113 | return 0; |
45187ace | 114 | } |
45187ace JB |
115 | } |
116 | ||
1d776538 | 117 | static u32 g4x_infoframe_enable(unsigned int type) |
45187ace | 118 | { |
178f736a | 119 | switch (type) { |
5cb3c1a1 VS |
120 | case HDMI_PACKET_TYPE_GENERAL_CONTROL: |
121 | return VIDEO_DIP_ENABLE_GCP; | |
122 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
123 | return VIDEO_DIP_ENABLE_GAMUT; | |
509efa2b VS |
124 | case DP_SDP_VSC: |
125 | return 0; | |
178f736a | 126 | case HDMI_INFOFRAME_TYPE_AVI: |
ed517fbb | 127 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 128 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 129 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
130 | case HDMI_INFOFRAME_TYPE_VENDOR: |
131 | return VIDEO_DIP_ENABLE_VENDOR; | |
c0560fab US |
132 | case HDMI_INFOFRAME_TYPE_DRM: |
133 | return 0; | |
fa193ff7 | 134 | default: |
ffc85dab | 135 | MISSING_CASE(type); |
ed517fbb | 136 | return 0; |
fa193ff7 | 137 | } |
fa193ff7 PZ |
138 | } |
139 | ||
1d776538 | 140 | static u32 hsw_infoframe_enable(unsigned int type) |
2da8af54 | 141 | { |
178f736a | 142 | switch (type) { |
5cb3c1a1 VS |
143 | case HDMI_PACKET_TYPE_GENERAL_CONTROL: |
144 | return VIDEO_DIP_ENABLE_GCP_HSW; | |
145 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
146 | return VIDEO_DIP_ENABLE_GMP_HSW; | |
1d776538 VS |
147 | case DP_SDP_VSC: |
148 | return VIDEO_DIP_ENABLE_VSC_HSW; | |
4c614831 MN |
149 | case DP_SDP_PPS: |
150 | return VDIP_ENABLE_PPS; | |
178f736a | 151 | case HDMI_INFOFRAME_TYPE_AVI: |
2da8af54 | 152 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 153 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 154 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
155 | case HDMI_INFOFRAME_TYPE_VENDOR: |
156 | return VIDEO_DIP_ENABLE_VS_HSW; | |
44b42ebf VS |
157 | case HDMI_INFOFRAME_TYPE_DRM: |
158 | return VIDEO_DIP_ENABLE_DRM_GLK; | |
2da8af54 | 159 | default: |
ffc85dab | 160 | MISSING_CASE(type); |
2da8af54 PZ |
161 | return 0; |
162 | } | |
163 | } | |
164 | ||
f0f59a00 VS |
165 | static i915_reg_t |
166 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
167 | enum transcoder cpu_transcoder, | |
1d776538 | 168 | unsigned int type, |
f0f59a00 | 169 | int i) |
2da8af54 | 170 | { |
178f736a | 171 | switch (type) { |
5cb3c1a1 VS |
172 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
173 | return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); | |
1d776538 VS |
174 | case DP_SDP_VSC: |
175 | return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); | |
4c614831 MN |
176 | case DP_SDP_PPS: |
177 | return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); | |
178f736a | 178 | case HDMI_INFOFRAME_TYPE_AVI: |
436c6d4a | 179 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 180 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 181 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 182 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 183 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
44b42ebf VS |
184 | case HDMI_INFOFRAME_TYPE_DRM: |
185 | return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); | |
2da8af54 | 186 | default: |
ffc85dab | 187 | MISSING_CASE(type); |
f0f59a00 | 188 | return INVALID_MMIO_REG; |
2da8af54 PZ |
189 | } |
190 | } | |
191 | ||
922430dd GM |
192 | static int hsw_dip_data_size(struct drm_i915_private *dev_priv, |
193 | unsigned int type) | |
4c614831 MN |
194 | { |
195 | switch (type) { | |
196 | case DP_SDP_VSC: | |
197 | return VIDEO_DIP_VSC_DATA_SIZE; | |
198 | case DP_SDP_PPS: | |
199 | return VIDEO_DIP_PPS_DATA_SIZE; | |
922430dd GM |
200 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
201 | if (INTEL_GEN(dev_priv) >= 11) | |
202 | return VIDEO_DIP_GMP_DATA_SIZE; | |
203 | else | |
204 | return VIDEO_DIP_DATA_SIZE; | |
4c614831 MN |
205 | default: |
206 | return VIDEO_DIP_DATA_SIZE; | |
207 | } | |
208 | } | |
209 | ||
790ea70c | 210 | static void g4x_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 211 | const struct intel_crtc_state *crtc_state, |
1d776538 | 212 | unsigned int type, |
fff63867 | 213 | const void *frame, ssize_t len) |
45187ace | 214 | { |
faa087c4 | 215 | const u32 *data = frame; |
790ea70c | 216 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
22509ec8 | 217 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 218 | int i; |
3c17fe4b | 219 | |
822974ae PZ |
220 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
221 | ||
1d4f85ac | 222 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 223 | val |= g4x_infoframe_index(type); |
22509ec8 | 224 | |
178f736a | 225 | val &= ~g4x_infoframe_enable(type); |
45187ace | 226 | |
22509ec8 | 227 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 228 | |
45187ace | 229 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
230 | I915_WRITE(VIDEO_DIP_DATA, *data); |
231 | data++; | |
232 | } | |
adf00b26 PZ |
233 | /* Write every possible data byte to force correct ECC calculation. */ |
234 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
235 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
3c17fe4b | 236 | |
178f736a | 237 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 238 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 239 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 240 | |
22509ec8 | 241 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 242 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
243 | } |
244 | ||
f2a10d61 VS |
245 | static void g4x_read_infoframe(struct intel_encoder *encoder, |
246 | const struct intel_crtc_state *crtc_state, | |
247 | unsigned int type, | |
248 | void *frame, ssize_t len) | |
249 | { | |
250 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
251 | u32 val, *data = frame; | |
252 | int i; | |
253 | ||
254 | val = I915_READ(VIDEO_DIP_CTL); | |
255 | ||
256 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
257 | val |= g4x_infoframe_index(type); | |
258 | ||
259 | I915_WRITE(VIDEO_DIP_CTL, val); | |
260 | ||
261 | for (i = 0; i < len; i += 4) | |
262 | *data++ = I915_READ(VIDEO_DIP_DATA); | |
263 | } | |
264 | ||
509efa2b | 265 | static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 266 | const struct intel_crtc_state *pipe_config) |
e43823ec | 267 | { |
790ea70c | 268 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e43823ec JB |
269 | u32 val = I915_READ(VIDEO_DIP_CTL); |
270 | ||
ec1dc603 | 271 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 272 | return 0; |
89a35ecd | 273 | |
790ea70c | 274 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 275 | return 0; |
ec1dc603 VS |
276 | |
277 | return val & (VIDEO_DIP_ENABLE_AVI | | |
278 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
279 | } |
280 | ||
790ea70c | 281 | static void ibx_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 282 | const struct intel_crtc_state *crtc_state, |
1d776538 | 283 | unsigned int type, |
fff63867 | 284 | const void *frame, ssize_t len) |
fdf1250a | 285 | { |
faa087c4 | 286 | const u32 *data = frame; |
790ea70c | 287 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 288 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 289 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a | 290 | u32 val = I915_READ(reg); |
f0f59a00 | 291 | int i; |
fdf1250a | 292 | |
822974ae PZ |
293 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
294 | ||
fdf1250a | 295 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 296 | val |= g4x_infoframe_index(type); |
fdf1250a | 297 | |
178f736a | 298 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
299 | |
300 | I915_WRITE(reg, val); | |
301 | ||
302 | for (i = 0; i < len; i += 4) { | |
303 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
304 | data++; | |
305 | } | |
adf00b26 PZ |
306 | /* Write every possible data byte to force correct ECC calculation. */ |
307 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
308 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
fdf1250a | 309 | |
178f736a | 310 | val |= g4x_infoframe_enable(type); |
fdf1250a | 311 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 312 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
313 | |
314 | I915_WRITE(reg, val); | |
9d9740f0 | 315 | POSTING_READ(reg); |
fdf1250a PZ |
316 | } |
317 | ||
f2a10d61 VS |
318 | static void ibx_read_infoframe(struct intel_encoder *encoder, |
319 | const struct intel_crtc_state *crtc_state, | |
320 | unsigned int type, | |
321 | void *frame, ssize_t len) | |
322 | { | |
323 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
324 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
325 | u32 val, *data = frame; | |
326 | int i; | |
327 | ||
328 | val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); | |
329 | ||
330 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
331 | val |= g4x_infoframe_index(type); | |
332 | ||
333 | I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); | |
334 | ||
335 | for (i = 0; i < len; i += 4) | |
336 | *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); | |
337 | } | |
338 | ||
509efa2b | 339 | static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 340 | const struct intel_crtc_state *pipe_config) |
e43823ec | 341 | { |
790ea70c | 342 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
343 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
344 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); | |
e43823ec JB |
345 | u32 val = I915_READ(reg); |
346 | ||
ec1dc603 | 347 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 348 | return 0; |
ec1dc603 | 349 | |
790ea70c | 350 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 351 | return 0; |
052f62f7 | 352 | |
ec1dc603 VS |
353 | return val & (VIDEO_DIP_ENABLE_AVI | |
354 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
355 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
356 | } |
357 | ||
790ea70c | 358 | static void cpt_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 359 | const struct intel_crtc_state *crtc_state, |
1d776538 | 360 | unsigned int type, |
fff63867 | 361 | const void *frame, ssize_t len) |
b055c8f3 | 362 | { |
faa087c4 | 363 | const u32 *data = frame; |
790ea70c | 364 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 365 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 366 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 367 | u32 val = I915_READ(reg); |
f0f59a00 | 368 | int i; |
b055c8f3 | 369 | |
822974ae PZ |
370 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
371 | ||
64a8fc01 | 372 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 373 | val |= g4x_infoframe_index(type); |
45187ace | 374 | |
ecb97851 PZ |
375 | /* The DIP control register spec says that we need to update the AVI |
376 | * infoframe without clearing its enable bit */ | |
178f736a DL |
377 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
378 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 379 | |
22509ec8 | 380 | I915_WRITE(reg, val); |
45187ace JB |
381 | |
382 | for (i = 0; i < len; i += 4) { | |
b055c8f3 JB |
383 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
384 | data++; | |
385 | } | |
adf00b26 PZ |
386 | /* Write every possible data byte to force correct ECC calculation. */ |
387 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
388 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
b055c8f3 | 389 | |
178f736a | 390 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 391 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 392 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 393 | |
22509ec8 | 394 | I915_WRITE(reg, val); |
9d9740f0 | 395 | POSTING_READ(reg); |
45187ace | 396 | } |
90b107c8 | 397 | |
f2a10d61 VS |
398 | static void cpt_read_infoframe(struct intel_encoder *encoder, |
399 | const struct intel_crtc_state *crtc_state, | |
400 | unsigned int type, | |
401 | void *frame, ssize_t len) | |
402 | { | |
403 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
404 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
405 | u32 val, *data = frame; | |
406 | int i; | |
407 | ||
408 | val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); | |
409 | ||
410 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
411 | val |= g4x_infoframe_index(type); | |
412 | ||
413 | I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); | |
414 | ||
415 | for (i = 0; i < len; i += 4) | |
416 | *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); | |
417 | } | |
418 | ||
509efa2b | 419 | static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 420 | const struct intel_crtc_state *pipe_config) |
e43823ec | 421 | { |
790ea70c | 422 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
423 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
424 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 425 | |
ec1dc603 | 426 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 427 | return 0; |
ec1dc603 VS |
428 | |
429 | return val & (VIDEO_DIP_ENABLE_AVI | | |
430 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
431 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
432 | } |
433 | ||
790ea70c | 434 | static void vlv_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 435 | const struct intel_crtc_state *crtc_state, |
1d776538 | 436 | unsigned int type, |
fff63867 | 437 | const void *frame, ssize_t len) |
90b107c8 | 438 | { |
faa087c4 | 439 | const u32 *data = frame; |
790ea70c | 440 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 441 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 442 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 443 | u32 val = I915_READ(reg); |
f0f59a00 | 444 | int i; |
90b107c8 | 445 | |
822974ae PZ |
446 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
447 | ||
90b107c8 | 448 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 449 | val |= g4x_infoframe_index(type); |
22509ec8 | 450 | |
178f736a | 451 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 452 | |
22509ec8 | 453 | I915_WRITE(reg, val); |
90b107c8 SK |
454 | |
455 | for (i = 0; i < len; i += 4) { | |
456 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
457 | data++; | |
458 | } | |
adf00b26 PZ |
459 | /* Write every possible data byte to force correct ECC calculation. */ |
460 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
461 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
90b107c8 | 462 | |
178f736a | 463 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 464 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 465 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 466 | |
22509ec8 | 467 | I915_WRITE(reg, val); |
9d9740f0 | 468 | POSTING_READ(reg); |
90b107c8 SK |
469 | } |
470 | ||
f2a10d61 VS |
471 | static void vlv_read_infoframe(struct intel_encoder *encoder, |
472 | const struct intel_crtc_state *crtc_state, | |
473 | unsigned int type, | |
474 | void *frame, ssize_t len) | |
475 | { | |
476 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
477 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
478 | u32 val, *data = frame; | |
479 | int i; | |
480 | ||
481 | val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe)); | |
482 | ||
483 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
484 | val |= g4x_infoframe_index(type); | |
485 | ||
486 | I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val); | |
487 | ||
488 | for (i = 0; i < len; i += 4) | |
489 | *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe)); | |
490 | } | |
491 | ||
509efa2b | 492 | static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 493 | const struct intel_crtc_state *pipe_config) |
e43823ec | 494 | { |
790ea70c | 495 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
496 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
497 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 498 | |
ec1dc603 | 499 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 500 | return 0; |
ec1dc603 | 501 | |
790ea70c | 502 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 503 | return 0; |
535afa2e | 504 | |
ec1dc603 VS |
505 | return val & (VIDEO_DIP_ENABLE_AVI | |
506 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
507 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
508 | } |
509 | ||
790ea70c | 510 | static void hsw_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 511 | const struct intel_crtc_state *crtc_state, |
1d776538 | 512 | unsigned int type, |
fff63867 | 513 | const void *frame, ssize_t len) |
8c5f5f7c | 514 | { |
faa087c4 | 515 | const u32 *data = frame; |
790ea70c | 516 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 517 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
f0f59a00 | 518 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
4c614831 | 519 | int data_size; |
178f736a | 520 | int i; |
2da8af54 | 521 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 522 | |
922430dd GM |
523 | data_size = hsw_dip_data_size(dev_priv, type); |
524 | ||
525 | WARN_ON(len > data_size); | |
4c614831 | 526 | |
178f736a | 527 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
528 | I915_WRITE(ctl_reg, val); |
529 | ||
530 | for (i = 0; i < len; i += 4) { | |
436c6d4a VS |
531 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
532 | type, i >> 2), *data); | |
2da8af54 PZ |
533 | data++; |
534 | } | |
adf00b26 | 535 | /* Write every possible data byte to force correct ECC calculation. */ |
1d776538 | 536 | for (; i < data_size; i += 4) |
436c6d4a VS |
537 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
538 | type, i >> 2), 0); | |
8c5f5f7c | 539 | |
178f736a | 540 | val |= hsw_infoframe_enable(type); |
2da8af54 | 541 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 542 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
543 | } |
544 | ||
f2a10d61 VS |
545 | static void hsw_read_infoframe(struct intel_encoder *encoder, |
546 | const struct intel_crtc_state *crtc_state, | |
547 | unsigned int type, | |
548 | void *frame, ssize_t len) | |
549 | { | |
550 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
551 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
552 | u32 val, *data = frame; | |
553 | int i; | |
554 | ||
555 | val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder)); | |
556 | ||
557 | for (i = 0; i < len; i += 4) | |
558 | *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder, | |
559 | type, i >> 2)); | |
560 | } | |
561 | ||
509efa2b | 562 | static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 563 | const struct intel_crtc_state *pipe_config) |
e43823ec | 564 | { |
790ea70c | 565 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf | 566 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); |
44b42ebf VS |
567 | u32 mask; |
568 | ||
569 | mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | | |
570 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
571 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
572 | ||
573 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) | |
574 | mask |= VIDEO_DIP_ENABLE_DRM_GLK; | |
e43823ec | 575 | |
44b42ebf | 576 | return val & mask; |
e43823ec JB |
577 | } |
578 | ||
509efa2b VS |
579 | static const u8 infoframe_type_to_idx[] = { |
580 | HDMI_PACKET_TYPE_GENERAL_CONTROL, | |
581 | HDMI_PACKET_TYPE_GAMUT_METADATA, | |
582 | DP_SDP_VSC, | |
583 | HDMI_INFOFRAME_TYPE_AVI, | |
584 | HDMI_INFOFRAME_TYPE_SPD, | |
585 | HDMI_INFOFRAME_TYPE_VENDOR, | |
5a0200f6 | 586 | HDMI_INFOFRAME_TYPE_DRM, |
509efa2b VS |
587 | }; |
588 | ||
fbf08556 VS |
589 | u32 intel_hdmi_infoframe_enable(unsigned int type) |
590 | { | |
591 | int i; | |
592 | ||
593 | for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { | |
594 | if (infoframe_type_to_idx[i] == type) | |
595 | return BIT(i); | |
596 | } | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
509efa2b VS |
601 | u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, |
602 | const struct intel_crtc_state *crtc_state) | |
603 | { | |
604 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
605 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
606 | u32 val, ret = 0; | |
607 | int i; | |
608 | ||
609 | val = dig_port->infoframes_enabled(encoder, crtc_state); | |
610 | ||
611 | /* map from hardware bits to dip idx */ | |
612 | for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { | |
613 | unsigned int type = infoframe_type_to_idx[i]; | |
614 | ||
615 | if (HAS_DDI(dev_priv)) { | |
616 | if (val & hsw_infoframe_enable(type)) | |
617 | ret |= BIT(i); | |
618 | } else { | |
619 | if (val & g4x_infoframe_enable(type)) | |
620 | ret |= BIT(i); | |
621 | } | |
622 | } | |
623 | ||
624 | return ret; | |
625 | } | |
626 | ||
5adaea79 DL |
627 | /* |
628 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
629 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
630 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
631 | * used for both technologies. | |
632 | * | |
633 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
634 | * DW1: DB3 | DB2 | DB1 | DB0 | |
635 | * DW2: DB7 | DB6 | DB5 | DB4 | |
636 | * DW3: ... | |
637 | * | |
638 | * (HB is Header Byte, DB is Data Byte) | |
639 | * | |
640 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
641 | * trick them by giving an offset into the buffer and moving back the header | |
642 | * bytes by one. | |
643 | */ | |
790ea70c | 644 | static void intel_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 645 | const struct intel_crtc_state *crtc_state, |
fbf08556 VS |
646 | enum hdmi_infoframe_type type, |
647 | const union hdmi_infoframe *frame) | |
45187ace | 648 | { |
790ea70c | 649 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
faa087c4 | 650 | u8 buffer[VIDEO_DIP_DATA_SIZE]; |
5adaea79 | 651 | ssize_t len; |
45187ace | 652 | |
fbf08556 VS |
653 | if ((crtc_state->infoframes.enable & |
654 | intel_hdmi_infoframe_enable(type)) == 0) | |
655 | return; | |
656 | ||
657 | if (WARN_ON(frame->any.type != type)) | |
658 | return; | |
659 | ||
5adaea79 | 660 | /* see comment above for the reason for this offset */ |
fbf08556 VS |
661 | len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); |
662 | if (WARN_ON(len < 0)) | |
5adaea79 DL |
663 | return; |
664 | ||
665 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
121f0ff5 | 666 | memmove(&buffer[0], &buffer[1], 3); |
5adaea79 DL |
667 | buffer[3] = 0; |
668 | len++; | |
45187ace | 669 | |
fbf08556 | 670 | intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); |
45187ace JB |
671 | } |
672 | ||
f2a10d61 VS |
673 | void intel_read_infoframe(struct intel_encoder *encoder, |
674 | const struct intel_crtc_state *crtc_state, | |
675 | enum hdmi_infoframe_type type, | |
676 | union hdmi_infoframe *frame) | |
677 | { | |
678 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
679 | u8 buffer[VIDEO_DIP_DATA_SIZE]; | |
680 | int ret; | |
681 | ||
682 | if ((crtc_state->infoframes.enable & | |
683 | intel_hdmi_infoframe_enable(type)) == 0) | |
684 | return; | |
685 | ||
686 | intel_dig_port->read_infoframe(encoder, crtc_state, | |
687 | type, buffer, sizeof(buffer)); | |
688 | ||
689 | /* Fill the 'hole' (see big comment above) at position 3 */ | |
690 | memmove(&buffer[1], &buffer[0], 3); | |
691 | ||
692 | /* see comment above for the reason for this offset */ | |
693 | ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); | |
694 | if (ret) { | |
695 | DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type); | |
696 | return; | |
697 | } | |
698 | ||
699 | if (frame->any.type != type) | |
700 | DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", | |
701 | frame->any.type, type); | |
702 | } | |
703 | ||
fbf08556 VS |
704 | static bool |
705 | intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, | |
706 | struct intel_crtc_state *crtc_state, | |
707 | struct drm_connector_state *conn_state) | |
45187ace | 708 | { |
fbf08556 | 709 | struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; |
779c4c28 VS |
710 | const struct drm_display_mode *adjusted_mode = |
711 | &crtc_state->base.adjusted_mode; | |
fbf08556 | 712 | struct drm_connector *connector = conn_state->connector; |
5adaea79 | 713 | int ret; |
45187ace | 714 | |
fbf08556 VS |
715 | if (!crtc_state->has_infoframe) |
716 | return true; | |
717 | ||
718 | crtc_state->infoframes.enable |= | |
719 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); | |
720 | ||
721 | ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, | |
13d0add3 | 722 | adjusted_mode); |
fbf08556 VS |
723 | if (ret) |
724 | return false; | |
c846b619 | 725 | |
33b7f3ee | 726 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
fbf08556 | 727 | frame->colorspace = HDMI_COLORSPACE_YUV420; |
8c79f844 | 728 | else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) |
fbf08556 | 729 | frame->colorspace = HDMI_COLORSPACE_YUV444; |
2d8bd2bf | 730 | else |
fbf08556 | 731 | frame->colorspace = HDMI_COLORSPACE_RGB; |
2d8bd2bf | 732 | |
0e2f54f8 | 733 | drm_hdmi_avi_infoframe_colorspace(frame, conn_state); |
2d8bd2bf | 734 | |
cae154fc VS |
735 | /* nonsense combination */ |
736 | WARN_ON(crtc_state->limited_color_range && | |
737 | crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); | |
738 | ||
791ad5f1 VS |
739 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { |
740 | drm_hdmi_avi_infoframe_quant_range(frame, connector, | |
741 | adjusted_mode, | |
742 | crtc_state->limited_color_range ? | |
743 | HDMI_QUANTIZATION_RANGE_LIMITED : | |
744 | HDMI_QUANTIZATION_RANGE_FULL); | |
745 | } else { | |
746 | frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; | |
747 | frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; | |
748 | } | |
abedc077 | 749 | |
fbf08556 | 750 | drm_hdmi_avi_infoframe_content_type(frame, conn_state); |
6553b123 | 751 | |
2d8bd2bf | 752 | /* TODO: handle pixel repetition for YCBCR420 outputs */ |
fbf08556 VS |
753 | |
754 | ret = hdmi_avi_infoframe_check(frame); | |
755 | if (WARN_ON(ret)) | |
756 | return false; | |
757 | ||
758 | return true; | |
b055c8f3 JB |
759 | } |
760 | ||
fbf08556 VS |
761 | static bool |
762 | intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, | |
763 | struct intel_crtc_state *crtc_state, | |
764 | struct drm_connector_state *conn_state) | |
c0864cb3 | 765 | { |
fbf08556 | 766 | struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; |
5adaea79 DL |
767 | int ret; |
768 | ||
fbf08556 VS |
769 | if (!crtc_state->has_infoframe) |
770 | return true; | |
c0864cb3 | 771 | |
fbf08556 VS |
772 | crtc_state->infoframes.enable |= |
773 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); | |
c0864cb3 | 774 | |
fbf08556 VS |
775 | ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); |
776 | if (WARN_ON(ret)) | |
777 | return false; | |
778 | ||
779 | frame->sdi = HDMI_SPD_SDI_PC; | |
780 | ||
781 | ret = hdmi_spd_infoframe_check(frame); | |
782 | if (WARN_ON(ret)) | |
783 | return false; | |
784 | ||
785 | return true; | |
c0864cb3 JB |
786 | } |
787 | ||
fbf08556 VS |
788 | static bool |
789 | intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, | |
790 | struct intel_crtc_state *crtc_state, | |
791 | struct drm_connector_state *conn_state) | |
792 | { | |
793 | struct hdmi_vendor_infoframe *frame = | |
794 | &crtc_state->infoframes.hdmi.vendor.hdmi; | |
795 | const struct drm_display_info *info = | |
796 | &conn_state->connector->display_info; | |
c8bb75af LD |
797 | int ret; |
798 | ||
fbf08556 VS |
799 | if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) |
800 | return true; | |
801 | ||
802 | crtc_state->infoframes.enable |= | |
803 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); | |
804 | ||
805 | ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, | |
f1781e9b | 806 | conn_state->connector, |
ac240288 | 807 | &crtc_state->base.adjusted_mode); |
fbf08556 VS |
808 | if (WARN_ON(ret)) |
809 | return false; | |
c8bb75af | 810 | |
fbf08556 VS |
811 | ret = hdmi_vendor_infoframe_check(frame); |
812 | if (WARN_ON(ret)) | |
813 | return false; | |
814 | ||
815 | return true; | |
c8bb75af LD |
816 | } |
817 | ||
5a0200f6 US |
818 | static bool |
819 | intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, | |
820 | struct intel_crtc_state *crtc_state, | |
821 | struct drm_connector_state *conn_state) | |
822 | { | |
823 | struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; | |
824 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
825 | int ret; | |
826 | ||
827 | if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))) | |
828 | return true; | |
829 | ||
830 | if (!crtc_state->has_infoframe) | |
831 | return true; | |
832 | ||
833 | if (!conn_state->hdr_output_metadata) | |
834 | return true; | |
835 | ||
836 | crtc_state->infoframes.enable |= | |
837 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); | |
838 | ||
839 | ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); | |
840 | if (ret < 0) { | |
841 | DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n"); | |
842 | return false; | |
843 | } | |
844 | ||
845 | ret = hdmi_drm_infoframe_check(frame); | |
846 | if (WARN_ON(ret)) | |
847 | return false; | |
848 | ||
849 | return true; | |
850 | } | |
851 | ||
790ea70c | 852 | static void g4x_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 853 | bool enable, |
ac240288 ML |
854 | const struct intel_crtc_state *crtc_state, |
855 | const struct drm_connector_state *conn_state) | |
687f4d06 | 856 | { |
790ea70c VS |
857 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
858 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
69fde0a6 | 859 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
f0f59a00 | 860 | i915_reg_t reg = VIDEO_DIP_CTL; |
0c14c7f9 | 861 | u32 val = I915_READ(reg); |
790ea70c | 862 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 863 | |
afba0188 DV |
864 | assert_hdmi_port_disabled(intel_hdmi); |
865 | ||
0c14c7f9 PZ |
866 | /* If the registers were not initialized yet, they might be zeroes, |
867 | * which means we're selecting the AVI DIP and we're setting its | |
868 | * frequency to once. This seems to really confuse the HW and make | |
869 | * things stop working (the register spec says the AVI always needs to | |
870 | * be sent every VSync). So here we avoid writing to the register more | |
871 | * than we need and also explicitly select the AVI DIP and explicitly | |
872 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
873 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
874 | * either. */ | |
875 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
876 | ||
6897b4b5 | 877 | if (!enable) { |
0c14c7f9 PZ |
878 | if (!(val & VIDEO_DIP_ENABLE)) |
879 | return; | |
0be6f0c8 VS |
880 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
881 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
882 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
883 | return; | |
884 | } | |
885 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
886 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 887 | I915_WRITE(reg, val); |
9d9740f0 | 888 | POSTING_READ(reg); |
0c14c7f9 PZ |
889 | return; |
890 | } | |
891 | ||
72b78c9d PZ |
892 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
893 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
894 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
895 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
896 | return; | |
72b78c9d PZ |
897 | } |
898 | val &= ~VIDEO_DIP_PORT_MASK; | |
899 | val |= port; | |
900 | } | |
901 | ||
822974ae | 902 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
903 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
904 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 905 | |
f278d972 | 906 | I915_WRITE(reg, val); |
9d9740f0 | 907 | POSTING_READ(reg); |
f278d972 | 908 | |
fbf08556 VS |
909 | intel_write_infoframe(encoder, crtc_state, |
910 | HDMI_INFOFRAME_TYPE_AVI, | |
911 | &crtc_state->infoframes.avi); | |
912 | intel_write_infoframe(encoder, crtc_state, | |
913 | HDMI_INFOFRAME_TYPE_SPD, | |
914 | &crtc_state->infoframes.spd); | |
915 | intel_write_infoframe(encoder, crtc_state, | |
916 | HDMI_INFOFRAME_TYPE_VENDOR, | |
917 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
918 | } |
919 | ||
12aa3290 VS |
920 | /* |
921 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
922 | * | |
923 | * From HDMI specification 1.4a: | |
924 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
925 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
926 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
927 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
928 | * phase of 0 | |
929 | */ | |
930 | static bool gcp_default_phase_possible(int pipe_bpp, | |
931 | const struct drm_display_mode *mode) | |
932 | { | |
933 | unsigned int pixels_per_group; | |
934 | ||
935 | switch (pipe_bpp) { | |
936 | case 30: | |
937 | /* 4 pixels in 5 clocks */ | |
938 | pixels_per_group = 4; | |
939 | break; | |
940 | case 36: | |
941 | /* 2 pixels in 3 clocks */ | |
942 | pixels_per_group = 2; | |
943 | break; | |
944 | case 48: | |
945 | /* 1 pixel in 2 clocks */ | |
946 | pixels_per_group = 1; | |
947 | break; | |
948 | default: | |
949 | /* phase information not relevant for 8bpc */ | |
950 | return false; | |
951 | } | |
952 | ||
953 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
954 | mode->crtc_htotal % pixels_per_group == 0 && | |
955 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
956 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
957 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
958 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
959 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
960 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
961 | } | |
962 | ||
790ea70c | 963 | static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, |
ac240288 ML |
964 | const struct intel_crtc_state *crtc_state, |
965 | const struct drm_connector_state *conn_state) | |
6d67415f | 966 | { |
790ea70c | 967 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 968 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 969 | i915_reg_t reg; |
fbf08556 VS |
970 | |
971 | if ((crtc_state->infoframes.enable & | |
972 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) | |
973 | return false; | |
6d67415f VS |
974 | |
975 | if (HAS_DDI(dev_priv)) | |
ac240288 | 976 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); |
666a4537 | 977 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f | 978 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
2d1fe073 | 979 | else if (HAS_PCH_SPLIT(dev_priv)) |
6d67415f VS |
980 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
981 | else | |
982 | return false; | |
983 | ||
fbf08556 VS |
984 | I915_WRITE(reg, crtc_state->infoframes.gcp); |
985 | ||
986 | return true; | |
987 | } | |
988 | ||
f2a10d61 VS |
989 | void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, |
990 | struct intel_crtc_state *crtc_state) | |
991 | { | |
992 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
993 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
994 | i915_reg_t reg; | |
995 | ||
996 | if ((crtc_state->infoframes.enable & | |
997 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) | |
998 | return; | |
999 | ||
1000 | if (HAS_DDI(dev_priv)) | |
1001 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); | |
1002 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
1003 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); | |
1004 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1005 | reg = TVIDEO_DIP_GCP(crtc->pipe); | |
1006 | else | |
1007 | return; | |
1008 | ||
1009 | crtc_state->infoframes.gcp = I915_READ(reg); | |
1010 | } | |
1011 | ||
fbf08556 VS |
1012 | static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, |
1013 | struct intel_crtc_state *crtc_state, | |
1014 | struct drm_connector_state *conn_state) | |
1015 | { | |
1016 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1017 | ||
1018 | if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) | |
1019 | return; | |
1020 | ||
1021 | crtc_state->infoframes.enable |= | |
1022 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); | |
1023 | ||
05d9c878 CT |
1024 | /* Indicate color indication for deep color mode */ |
1025 | if (crtc_state->pipe_bpp > 24) | |
fbf08556 | 1026 | crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; |
6d67415f | 1027 | |
12aa3290 | 1028 | /* Enable default_phase whenever the display mode is suitably aligned */ |
ac240288 ML |
1029 | if (gcp_default_phase_possible(crtc_state->pipe_bpp, |
1030 | &crtc_state->base.adjusted_mode)) | |
fbf08556 | 1031 | crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; |
6d67415f VS |
1032 | } |
1033 | ||
790ea70c | 1034 | static void ibx_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1035 | bool enable, |
ac240288 ML |
1036 | const struct intel_crtc_state *crtc_state, |
1037 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1038 | { |
790ea70c | 1039 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1040 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 1041 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
69fde0a6 | 1042 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
f0f59a00 | 1043 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 1044 | u32 val = I915_READ(reg); |
790ea70c | 1045 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 1046 | |
afba0188 DV |
1047 | assert_hdmi_port_disabled(intel_hdmi); |
1048 | ||
0c14c7f9 PZ |
1049 | /* See the big comment in g4x_set_infoframes() */ |
1050 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1051 | ||
6897b4b5 | 1052 | if (!enable) { |
0c14c7f9 PZ |
1053 | if (!(val & VIDEO_DIP_ENABLE)) |
1054 | return; | |
0be6f0c8 VS |
1055 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1056 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1057 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 1058 | I915_WRITE(reg, val); |
9d9740f0 | 1059 | POSTING_READ(reg); |
0c14c7f9 PZ |
1060 | return; |
1061 | } | |
1062 | ||
72b78c9d | 1063 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
1064 | WARN(val & VIDEO_DIP_ENABLE, |
1065 | "DIP already enabled on port %c\n", | |
1066 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
1067 | val &= ~VIDEO_DIP_PORT_MASK; |
1068 | val |= port; | |
1069 | } | |
1070 | ||
822974ae | 1071 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
1072 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
1073 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1074 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 1075 | |
ac240288 | 1076 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1077 | val |= VIDEO_DIP_ENABLE_GCP; |
1078 | ||
f278d972 | 1079 | I915_WRITE(reg, val); |
9d9740f0 | 1080 | POSTING_READ(reg); |
f278d972 | 1081 | |
fbf08556 VS |
1082 | intel_write_infoframe(encoder, crtc_state, |
1083 | HDMI_INFOFRAME_TYPE_AVI, | |
1084 | &crtc_state->infoframes.avi); | |
1085 | intel_write_infoframe(encoder, crtc_state, | |
1086 | HDMI_INFOFRAME_TYPE_SPD, | |
1087 | &crtc_state->infoframes.spd); | |
1088 | intel_write_infoframe(encoder, crtc_state, | |
1089 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1090 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1091 | } |
1092 | ||
790ea70c | 1093 | static void cpt_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1094 | bool enable, |
ac240288 ML |
1095 | const struct intel_crtc_state *crtc_state, |
1096 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1097 | { |
790ea70c | 1098 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1099 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 1100 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f0f59a00 | 1101 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 PZ |
1102 | u32 val = I915_READ(reg); |
1103 | ||
afba0188 DV |
1104 | assert_hdmi_port_disabled(intel_hdmi); |
1105 | ||
0c14c7f9 PZ |
1106 | /* See the big comment in g4x_set_infoframes() */ |
1107 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1108 | ||
6897b4b5 | 1109 | if (!enable) { |
0c14c7f9 PZ |
1110 | if (!(val & VIDEO_DIP_ENABLE)) |
1111 | return; | |
0be6f0c8 VS |
1112 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1113 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1114 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 1115 | I915_WRITE(reg, val); |
9d9740f0 | 1116 | POSTING_READ(reg); |
0c14c7f9 PZ |
1117 | return; |
1118 | } | |
1119 | ||
822974ae PZ |
1120 | /* Set both together, unset both together: see the spec. */ |
1121 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 1122 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 1123 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 1124 | |
ac240288 | 1125 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1126 | val |= VIDEO_DIP_ENABLE_GCP; |
1127 | ||
822974ae | 1128 | I915_WRITE(reg, val); |
9d9740f0 | 1129 | POSTING_READ(reg); |
822974ae | 1130 | |
fbf08556 VS |
1131 | intel_write_infoframe(encoder, crtc_state, |
1132 | HDMI_INFOFRAME_TYPE_AVI, | |
1133 | &crtc_state->infoframes.avi); | |
1134 | intel_write_infoframe(encoder, crtc_state, | |
1135 | HDMI_INFOFRAME_TYPE_SPD, | |
1136 | &crtc_state->infoframes.spd); | |
1137 | intel_write_infoframe(encoder, crtc_state, | |
1138 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1139 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1140 | } |
1141 | ||
790ea70c | 1142 | static void vlv_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1143 | bool enable, |
ac240288 ML |
1144 | const struct intel_crtc_state *crtc_state, |
1145 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1146 | { |
790ea70c | 1147 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1148 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 1149 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f0f59a00 | 1150 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 1151 | u32 val = I915_READ(reg); |
790ea70c | 1152 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 1153 | |
afba0188 DV |
1154 | assert_hdmi_port_disabled(intel_hdmi); |
1155 | ||
0c14c7f9 PZ |
1156 | /* See the big comment in g4x_set_infoframes() */ |
1157 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1158 | ||
6897b4b5 | 1159 | if (!enable) { |
0c14c7f9 PZ |
1160 | if (!(val & VIDEO_DIP_ENABLE)) |
1161 | return; | |
0be6f0c8 VS |
1162 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1163 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1164 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 1165 | I915_WRITE(reg, val); |
9d9740f0 | 1166 | POSTING_READ(reg); |
0c14c7f9 PZ |
1167 | return; |
1168 | } | |
1169 | ||
6a2b8021 | 1170 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
1171 | WARN(val & VIDEO_DIP_ENABLE, |
1172 | "DIP already enabled on port %c\n", | |
1173 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
1174 | val &= ~VIDEO_DIP_PORT_MASK; |
1175 | val |= port; | |
1176 | } | |
1177 | ||
822974ae | 1178 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
1179 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
1180 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1181 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 1182 | |
ac240288 | 1183 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1184 | val |= VIDEO_DIP_ENABLE_GCP; |
1185 | ||
822974ae | 1186 | I915_WRITE(reg, val); |
9d9740f0 | 1187 | POSTING_READ(reg); |
822974ae | 1188 | |
fbf08556 VS |
1189 | intel_write_infoframe(encoder, crtc_state, |
1190 | HDMI_INFOFRAME_TYPE_AVI, | |
1191 | &crtc_state->infoframes.avi); | |
1192 | intel_write_infoframe(encoder, crtc_state, | |
1193 | HDMI_INFOFRAME_TYPE_SPD, | |
1194 | &crtc_state->infoframes.spd); | |
1195 | intel_write_infoframe(encoder, crtc_state, | |
1196 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1197 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1198 | } |
1199 | ||
790ea70c | 1200 | static void hsw_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1201 | bool enable, |
ac240288 ML |
1202 | const struct intel_crtc_state *crtc_state, |
1203 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1204 | { |
790ea70c | 1205 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1206 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); |
0dd87d20 | 1207 | u32 val = I915_READ(reg); |
0c14c7f9 | 1208 | |
8fc0aa6e ID |
1209 | assert_hdmi_transcoder_func_disabled(dev_priv, |
1210 | crtc_state->cpu_transcoder); | |
afba0188 | 1211 | |
0be6f0c8 VS |
1212 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
1213 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
44b42ebf VS |
1214 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | |
1215 | VIDEO_DIP_ENABLE_DRM_GLK); | |
0be6f0c8 | 1216 | |
6897b4b5 | 1217 | if (!enable) { |
0be6f0c8 | 1218 | I915_WRITE(reg, val); |
9d9740f0 | 1219 | POSTING_READ(reg); |
0c14c7f9 PZ |
1220 | return; |
1221 | } | |
1222 | ||
ac240288 | 1223 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1224 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
1225 | ||
0dd87d20 | 1226 | I915_WRITE(reg, val); |
9d9740f0 | 1227 | POSTING_READ(reg); |
0dd87d20 | 1228 | |
fbf08556 VS |
1229 | intel_write_infoframe(encoder, crtc_state, |
1230 | HDMI_INFOFRAME_TYPE_AVI, | |
1231 | &crtc_state->infoframes.avi); | |
1232 | intel_write_infoframe(encoder, crtc_state, | |
1233 | HDMI_INFOFRAME_TYPE_SPD, | |
1234 | &crtc_state->infoframes.spd); | |
1235 | intel_write_infoframe(encoder, crtc_state, | |
1236 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1237 | &crtc_state->infoframes.hdmi); | |
5a0200f6 US |
1238 | intel_write_infoframe(encoder, crtc_state, |
1239 | HDMI_INFOFRAME_TYPE_DRM, | |
1240 | &crtc_state->infoframes.drm); | |
687f4d06 PZ |
1241 | } |
1242 | ||
b2ccb822 VS |
1243 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) |
1244 | { | |
1245 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); | |
1246 | struct i2c_adapter *adapter = | |
1247 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
1248 | ||
1249 | if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) | |
1250 | return; | |
1251 | ||
1252 | DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", | |
1253 | enable ? "Enabling" : "Disabling"); | |
1254 | ||
1255 | drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, | |
1256 | adapter, enable); | |
1257 | } | |
1258 | ||
2320175f SP |
1259 | static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, |
1260 | unsigned int offset, void *buffer, size_t size) | |
1261 | { | |
1262 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1263 | struct drm_i915_private *dev_priv = | |
1264 | intel_dig_port->base.base.dev->dev_private; | |
1265 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
1266 | hdmi->ddc_bus); | |
1267 | int ret; | |
1268 | u8 start = offset & 0xff; | |
1269 | struct i2c_msg msgs[] = { | |
1270 | { | |
1271 | .addr = DRM_HDCP_DDC_ADDR, | |
1272 | .flags = 0, | |
1273 | .len = 1, | |
1274 | .buf = &start, | |
1275 | }, | |
1276 | { | |
1277 | .addr = DRM_HDCP_DDC_ADDR, | |
1278 | .flags = I2C_M_RD, | |
1279 | .len = size, | |
1280 | .buf = buffer | |
1281 | } | |
1282 | }; | |
1283 | ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); | |
1284 | if (ret == ARRAY_SIZE(msgs)) | |
1285 | return 0; | |
1286 | return ret >= 0 ? -EIO : ret; | |
1287 | } | |
1288 | ||
1289 | static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, | |
1290 | unsigned int offset, void *buffer, size_t size) | |
1291 | { | |
1292 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1293 | struct drm_i915_private *dev_priv = | |
1294 | intel_dig_port->base.base.dev->dev_private; | |
1295 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
1296 | hdmi->ddc_bus); | |
1297 | int ret; | |
1298 | u8 *write_buf; | |
1299 | struct i2c_msg msg; | |
1300 | ||
1301 | write_buf = kzalloc(size + 1, GFP_KERNEL); | |
1302 | if (!write_buf) | |
1303 | return -ENOMEM; | |
1304 | ||
1305 | write_buf[0] = offset & 0xff; | |
1306 | memcpy(&write_buf[1], buffer, size); | |
1307 | ||
1308 | msg.addr = DRM_HDCP_DDC_ADDR; | |
1309 | msg.flags = 0, | |
1310 | msg.len = size + 1, | |
1311 | msg.buf = write_buf; | |
1312 | ||
1313 | ret = i2c_transfer(adapter, &msg, 1); | |
1314 | if (ret == 1) | |
1b1b1162 RV |
1315 | ret = 0; |
1316 | else if (ret >= 0) | |
1317 | ret = -EIO; | |
1318 | ||
1319 | kfree(write_buf); | |
1320 | return ret; | |
2320175f SP |
1321 | } |
1322 | ||
1323 | static | |
1324 | int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, | |
1325 | u8 *an) | |
1326 | { | |
1327 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1328 | struct drm_i915_private *dev_priv = | |
1329 | intel_dig_port->base.base.dev->dev_private; | |
1330 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
1331 | hdmi->ddc_bus); | |
1332 | int ret; | |
1333 | ||
1334 | ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, | |
1335 | DRM_HDCP_AN_LEN); | |
1336 | if (ret) { | |
3aae21fc | 1337 | DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret); |
2320175f SP |
1338 | return ret; |
1339 | } | |
1340 | ||
1341 | ret = intel_gmbus_output_aksv(adapter); | |
1342 | if (ret < 0) { | |
3aae21fc | 1343 | DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret); |
2320175f SP |
1344 | return ret; |
1345 | } | |
1346 | return 0; | |
1347 | } | |
1348 | ||
1349 | static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, | |
1350 | u8 *bksv) | |
1351 | { | |
1352 | int ret; | |
1353 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, | |
1354 | DRM_HDCP_KSV_LEN); | |
1355 | if (ret) | |
3aae21fc | 1356 | DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret); |
2320175f SP |
1357 | return ret; |
1358 | } | |
1359 | ||
1360 | static | |
1361 | int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, | |
1362 | u8 *bstatus) | |
1363 | { | |
1364 | int ret; | |
1365 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, | |
1366 | bstatus, DRM_HDCP_BSTATUS_LEN); | |
1367 | if (ret) | |
3aae21fc | 1368 | DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret); |
2320175f SP |
1369 | return ret; |
1370 | } | |
1371 | ||
1372 | static | |
1373 | int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, | |
1374 | bool *repeater_present) | |
1375 | { | |
1376 | int ret; | |
1377 | u8 val; | |
1378 | ||
1379 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1380 | if (ret) { | |
3aae21fc | 1381 | DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); |
2320175f SP |
1382 | return ret; |
1383 | } | |
1384 | *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; | |
1385 | return 0; | |
1386 | } | |
1387 | ||
1388 | static | |
1389 | int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, | |
1390 | u8 *ri_prime) | |
1391 | { | |
1392 | int ret; | |
1393 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, | |
1394 | ri_prime, DRM_HDCP_RI_LEN); | |
1395 | if (ret) | |
3aae21fc | 1396 | DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret); |
2320175f SP |
1397 | return ret; |
1398 | } | |
1399 | ||
1400 | static | |
1401 | int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, | |
1402 | bool *ksv_ready) | |
1403 | { | |
1404 | int ret; | |
1405 | u8 val; | |
1406 | ||
1407 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1408 | if (ret) { | |
3aae21fc | 1409 | DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); |
2320175f SP |
1410 | return ret; |
1411 | } | |
1412 | *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; | |
1413 | return 0; | |
1414 | } | |
1415 | ||
1416 | static | |
1417 | int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, | |
1418 | int num_downstream, u8 *ksv_fifo) | |
1419 | { | |
1420 | int ret; | |
1421 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, | |
1422 | ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); | |
1423 | if (ret) { | |
3aae21fc | 1424 | DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret); |
2320175f SP |
1425 | return ret; |
1426 | } | |
1427 | return 0; | |
1428 | } | |
1429 | ||
1430 | static | |
1431 | int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, | |
1432 | int i, u32 *part) | |
1433 | { | |
1434 | int ret; | |
1435 | ||
1436 | if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) | |
1437 | return -EINVAL; | |
1438 | ||
1439 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), | |
1440 | part, DRM_HDCP_V_PRIME_PART_LEN); | |
1441 | if (ret) | |
3aae21fc | 1442 | DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret); |
2320175f SP |
1443 | return ret; |
1444 | } | |
1445 | ||
7412826c R |
1446 | static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) |
1447 | { | |
1448 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
1449 | struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); | |
1450 | struct drm_crtc *crtc = connector->base.state->crtc; | |
1451 | struct intel_crtc *intel_crtc = container_of(crtc, | |
1452 | struct intel_crtc, base); | |
1453 | u32 scanline; | |
1454 | int ret; | |
1455 | ||
1456 | for (;;) { | |
1457 | scanline = I915_READ(PIPEDSL(intel_crtc->pipe)); | |
1458 | if (scanline > 100 && scanline < 200) | |
1459 | break; | |
1460 | usleep_range(25, 50); | |
1461 | } | |
1462 | ||
1463 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); | |
1464 | if (ret) { | |
1465 | DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret); | |
1466 | return ret; | |
1467 | } | |
1468 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); | |
1469 | if (ret) { | |
1470 | DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret); | |
1471 | return ret; | |
1472 | } | |
1473 | ||
1474 | return 0; | |
1475 | } | |
1476 | ||
2320175f SP |
1477 | static |
1478 | int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, | |
1479 | bool enable) | |
1480 | { | |
7412826c R |
1481 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; |
1482 | struct intel_connector *connector = hdmi->attached_connector; | |
1483 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
2320175f SP |
1484 | int ret; |
1485 | ||
1486 | if (!enable) | |
1487 | usleep_range(6, 60); /* Bspec says >= 6us */ | |
1488 | ||
1489 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); | |
1490 | if (ret) { | |
1491 | DRM_ERROR("%s HDCP signalling failed (%d)\n", | |
1492 | enable ? "Enable" : "Disable", ret); | |
1493 | return ret; | |
1494 | } | |
7412826c R |
1495 | |
1496 | /* | |
1497 | * WA: To fix incorrect positioning of the window of | |
1498 | * opportunity and enc_en signalling in KABYLAKE. | |
1499 | */ | |
1500 | if (IS_KABYLAKE(dev_priv) && enable) | |
1501 | return kbl_repositioning_enc_en_signal(connector); | |
1502 | ||
2320175f SP |
1503 | return 0; |
1504 | } | |
1505 | ||
1506 | static | |
1507 | bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) | |
1508 | { | |
1509 | struct drm_i915_private *dev_priv = | |
1510 | intel_dig_port->base.base.dev->dev_private; | |
69205931 R |
1511 | struct intel_connector *connector = |
1512 | intel_dig_port->hdmi.attached_connector; | |
2320175f | 1513 | enum port port = intel_dig_port->base.port; |
69205931 | 1514 | enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; |
2320175f SP |
1515 | int ret; |
1516 | union { | |
1517 | u32 reg; | |
1518 | u8 shim[DRM_HDCP_RI_LEN]; | |
1519 | } ri; | |
1520 | ||
1521 | ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); | |
1522 | if (ret) | |
1523 | return false; | |
1524 | ||
69205931 | 1525 | I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg); |
2320175f SP |
1526 | |
1527 | /* Wait for Ri prime match */ | |
69205931 | 1528 | if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) & |
2320175f SP |
1529 | (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { |
1530 | DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", | |
69205931 R |
1531 | I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, |
1532 | port))); | |
2320175f SP |
1533 | return false; |
1534 | } | |
1535 | return true; | |
1536 | } | |
1537 | ||
67fdd8ea | 1538 | struct hdcp2_hdmi_msg_timeout { |
2d4254e5 R |
1539 | u8 msg_id; |
1540 | u32 timeout; | |
032048db JN |
1541 | }; |
1542 | ||
67fdd8ea | 1543 | static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { |
eac03efd VS |
1544 | { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, |
1545 | { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, | |
1546 | { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, | |
1547 | { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, | |
1548 | { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, | |
032048db | 1549 | }; |
2d4254e5 R |
1550 | |
1551 | static | |
1552 | int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, | |
126d0a94 | 1553 | u8 *rx_status) |
2d4254e5 R |
1554 | { |
1555 | return intel_hdmi_hdcp_read(intel_dig_port, | |
1556 | HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, | |
1557 | rx_status, | |
1558 | HDCP_2_2_HDMI_RXSTATUS_LEN); | |
1559 | } | |
1560 | ||
1561 | static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) | |
1562 | { | |
1563 | int i; | |
1564 | ||
eac03efd VS |
1565 | if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { |
1566 | if (is_paired) | |
1567 | return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; | |
1568 | else | |
1569 | return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; | |
1570 | } | |
1571 | ||
1572 | for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { | |
1573 | if (hdcp2_msg_timeout[i].msg_id == msg_id) | |
67fdd8ea | 1574 | return hdcp2_msg_timeout[i].timeout; |
eac03efd | 1575 | } |
2d4254e5 R |
1576 | |
1577 | return -EINVAL; | |
1578 | } | |
1579 | ||
1580 | static inline | |
1581 | int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port, | |
1582 | u8 msg_id, bool *msg_ready, | |
1583 | ssize_t *msg_sz) | |
1584 | { | |
1585 | u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; | |
1586 | int ret; | |
1587 | ||
1588 | ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status); | |
1589 | if (ret < 0) { | |
1590 | DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret); | |
1591 | return ret; | |
1592 | } | |
1593 | ||
1594 | *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | | |
1595 | rx_status[0]); | |
1596 | ||
1597 | if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) | |
1598 | *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && | |
1599 | *msg_sz); | |
1600 | else | |
1601 | *msg_ready = *msg_sz; | |
1602 | ||
1603 | return 0; | |
1604 | } | |
1605 | ||
1606 | static ssize_t | |
1607 | intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, | |
1608 | u8 msg_id, bool paired) | |
1609 | { | |
1610 | bool msg_ready = false; | |
1611 | int timeout, ret; | |
1612 | ssize_t msg_sz = 0; | |
1613 | ||
1614 | timeout = get_hdcp2_msg_timeout(msg_id, paired); | |
1615 | if (timeout < 0) | |
1616 | return timeout; | |
1617 | ||
1618 | ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port, | |
1619 | msg_id, &msg_ready, | |
1620 | &msg_sz), | |
1621 | !ret && msg_ready && msg_sz, timeout * 1000, | |
1622 | 1000, 5 * 1000); | |
1623 | if (ret) | |
1624 | DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n", | |
1625 | msg_id, ret, timeout); | |
1626 | ||
1627 | return ret ? ret : msg_sz; | |
1628 | } | |
1629 | ||
1630 | static | |
1631 | int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, | |
1632 | void *buf, size_t size) | |
1633 | { | |
1634 | unsigned int offset; | |
1635 | ||
1636 | offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; | |
1637 | return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size); | |
1638 | } | |
1639 | ||
1640 | static | |
1641 | int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, | |
1642 | u8 msg_id, void *buf, size_t size) | |
1643 | { | |
1644 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1645 | struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; | |
1646 | unsigned int offset; | |
1647 | ssize_t ret; | |
1648 | ||
1649 | ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id, | |
1650 | hdcp->is_paired); | |
1651 | if (ret < 0) | |
1652 | return ret; | |
1653 | ||
1654 | /* | |
1655 | * Available msg size should be equal to or lesser than the | |
1656 | * available buffer. | |
1657 | */ | |
1658 | if (ret > size) { | |
1659 | DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n", | |
1660 | ret, size); | |
1661 | return -1; | |
1662 | } | |
1663 | ||
1664 | offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; | |
1665 | ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret); | |
1666 | if (ret) | |
1667 | DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret); | |
1668 | ||
1669 | return ret; | |
1670 | } | |
1671 | ||
1672 | static | |
1673 | int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) | |
1674 | { | |
1675 | u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; | |
1676 | int ret; | |
1677 | ||
1678 | ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); | |
1679 | if (ret) | |
1680 | return ret; | |
1681 | ||
1682 | /* | |
1683 | * Re-auth request and Link Integrity Failures are represented by | |
1684 | * same bit. i.e reauth_req. | |
1685 | */ | |
1686 | if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) | |
1687 | ret = HDCP_REAUTH_REQUEST; | |
1688 | else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) | |
1689 | ret = HDCP_TOPOLOGY_CHANGE; | |
1690 | ||
1691 | return ret; | |
1692 | } | |
1693 | ||
1694 | static | |
1695 | int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port, | |
1696 | bool *capable) | |
1697 | { | |
1698 | u8 hdcp2_version; | |
1699 | int ret; | |
1700 | ||
1701 | *capable = false; | |
1702 | ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, | |
1703 | &hdcp2_version, sizeof(hdcp2_version)); | |
1704 | if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) | |
1705 | *capable = true; | |
1706 | ||
1707 | return ret; | |
1708 | } | |
1709 | ||
1710 | static inline | |
1711 | enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void) | |
1712 | { | |
1713 | return HDCP_PROTOCOL_HDMI; | |
1714 | } | |
1715 | ||
2320175f SP |
1716 | static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { |
1717 | .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, | |
1718 | .read_bksv = intel_hdmi_hdcp_read_bksv, | |
1719 | .read_bstatus = intel_hdmi_hdcp_read_bstatus, | |
1720 | .repeater_present = intel_hdmi_hdcp_repeater_present, | |
1721 | .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, | |
1722 | .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, | |
1723 | .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, | |
1724 | .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, | |
1725 | .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, | |
1726 | .check_link = intel_hdmi_hdcp_check_link, | |
2d4254e5 R |
1727 | .write_2_2_msg = intel_hdmi_hdcp2_write_msg, |
1728 | .read_2_2_msg = intel_hdmi_hdcp2_read_msg, | |
1729 | .check_2_2_link = intel_hdmi_hdcp2_check_link, | |
1730 | .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, | |
1731 | .protocol = HDCP_PROTOCOL_HDMI, | |
2320175f SP |
1732 | }; |
1733 | ||
ac240288 ML |
1734 | static void intel_hdmi_prepare(struct intel_encoder *encoder, |
1735 | const struct intel_crtc_state *crtc_state) | |
7d57382e | 1736 | { |
c59423a3 | 1737 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1738 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1739 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
c59423a3 | 1740 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
ac240288 | 1741 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; |
b242b7f7 | 1742 | u32 hdmi_val; |
7d57382e | 1743 | |
b2ccb822 VS |
1744 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
1745 | ||
b242b7f7 | 1746 | hdmi_val = SDVO_ENCODING_HDMI; |
ac240288 | 1747 | if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) |
0f2a2a75 | 1748 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
b599c0bc | 1749 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 1750 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 1751 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 1752 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 1753 | |
ac240288 | 1754 | if (crtc_state->pipe_bpp > 24) |
4f3a8bc7 | 1755 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 1756 | else |
4f3a8bc7 | 1757 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 1758 | |
ac240288 | 1759 | if (crtc_state->has_hdmi_sink) |
dc0fa718 | 1760 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 1761 | |
6e266956 | 1762 | if (HAS_PCH_CPT(dev_priv)) |
c59423a3 | 1763 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
920a14b2 | 1764 | else if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1765 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
dc0fa718 | 1766 | else |
c59423a3 | 1767 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 1768 | |
b242b7f7 PZ |
1769 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
1770 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
1771 | } |
1772 | ||
85234cdc DV |
1773 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
1774 | enum pipe *pipe) | |
7d57382e | 1775 | { |
76203467 | 1776 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
85234cdc | 1777 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
0e6e0be4 | 1778 | intel_wakeref_t wakeref; |
5b092174 | 1779 | bool ret; |
85234cdc | 1780 | |
0e6e0be4 CW |
1781 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
1782 | encoder->power_domain); | |
1783 | if (!wakeref) | |
6d129bea ID |
1784 | return false; |
1785 | ||
76203467 | 1786 | ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); |
5b092174 | 1787 | |
0e6e0be4 | 1788 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
5b092174 ID |
1789 | |
1790 | return ret; | |
85234cdc DV |
1791 | } |
1792 | ||
045ac3b5 | 1793 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 1794 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
1795 | { |
1796 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca | 1797 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1798 | struct drm_i915_private *dev_priv = to_i915(dev); |
045ac3b5 | 1799 | u32 tmp, flags = 0; |
18442d08 | 1800 | int dotclock; |
045ac3b5 | 1801 | |
e1214b95 VS |
1802 | pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); |
1803 | ||
045ac3b5 JB |
1804 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
1805 | ||
1806 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
1807 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1808 | else | |
1809 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1810 | ||
1811 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
1812 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1813 | else | |
1814 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1815 | ||
6897b4b5 DV |
1816 | if (tmp & HDMI_MODE_SELECT_HDMI) |
1817 | pipe_config->has_hdmi_sink = true; | |
1818 | ||
e5e70d4a VS |
1819 | pipe_config->infoframes.enable |= |
1820 | intel_hdmi_infoframes_enabled(encoder, pipe_config); | |
1821 | ||
1822 | if (pipe_config->infoframes.enable) | |
e43823ec JB |
1823 | pipe_config->has_infoframe = true; |
1824 | ||
dd6090f8 | 1825 | if (tmp & HDMI_AUDIO_ENABLE) |
9ed109a7 DV |
1826 | pipe_config->has_audio = true; |
1827 | ||
6e266956 | 1828 | if (!HAS_PCH_SPLIT(dev_priv) && |
8c875fca VS |
1829 | tmp & HDMI_COLOR_RANGE_16_235) |
1830 | pipe_config->limited_color_range = true; | |
1831 | ||
2d112de7 | 1832 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
1833 | |
1834 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
1835 | dotclock = pipe_config->port_clock * 2 / 3; | |
1836 | else | |
1837 | dotclock = pipe_config->port_clock; | |
1838 | ||
be69a133 VS |
1839 | if (pipe_config->pixel_multiplier) |
1840 | dotclock /= pipe_config->pixel_multiplier; | |
1841 | ||
2d112de7 | 1842 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
d4d6279a ACO |
1843 | |
1844 | pipe_config->lane_count = 4; | |
f2a10d61 VS |
1845 | |
1846 | intel_hdmi_read_gcp_infoframe(encoder, pipe_config); | |
1847 | ||
1848 | intel_read_infoframe(encoder, pipe_config, | |
1849 | HDMI_INFOFRAME_TYPE_AVI, | |
1850 | &pipe_config->infoframes.avi); | |
1851 | intel_read_infoframe(encoder, pipe_config, | |
1852 | HDMI_INFOFRAME_TYPE_SPD, | |
1853 | &pipe_config->infoframes.spd); | |
1854 | intel_read_infoframe(encoder, pipe_config, | |
1855 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1856 | &pipe_config->infoframes.hdmi); | |
045ac3b5 JB |
1857 | } |
1858 | ||
df18e721 | 1859 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder, |
5f88a9c6 VS |
1860 | const struct intel_crtc_state *pipe_config, |
1861 | const struct drm_connector_state *conn_state) | |
d1b1589c | 1862 | { |
ac240288 | 1863 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c | 1864 | |
ac240288 | 1865 | WARN_ON(!pipe_config->has_hdmi_sink); |
d1b1589c VS |
1866 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
1867 | pipe_name(crtc->pipe)); | |
bbf35e9d | 1868 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
d1b1589c VS |
1869 | } |
1870 | ||
fd6bbda9 | 1871 | static void g4x_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1872 | const struct intel_crtc_state *pipe_config, |
1873 | const struct drm_connector_state *conn_state) | |
7d57382e | 1874 | { |
5ab432ef | 1875 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1876 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1877 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
1878 | u32 temp; |
1879 | ||
b242b7f7 | 1880 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 1881 | |
bf868c7d | 1882 | temp |= SDVO_ENABLE; |
df18e721 | 1883 | if (pipe_config->has_audio) |
dd6090f8 | 1884 | temp |= HDMI_AUDIO_ENABLE; |
7a87c289 | 1885 | |
bf868c7d VS |
1886 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1887 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1888 | ||
df18e721 ML |
1889 | if (pipe_config->has_audio) |
1890 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
bf868c7d VS |
1891 | } |
1892 | ||
fd6bbda9 | 1893 | static void ibx_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1894 | const struct intel_crtc_state *pipe_config, |
1895 | const struct drm_connector_state *conn_state) | |
bf868c7d VS |
1896 | { |
1897 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1898 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf868c7d VS |
1899 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1900 | u32 temp; | |
1901 | ||
1902 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 1903 | |
bf868c7d | 1904 | temp |= SDVO_ENABLE; |
ac240288 | 1905 | if (pipe_config->has_audio) |
dd6090f8 | 1906 | temp |= HDMI_AUDIO_ENABLE; |
5ab432ef | 1907 | |
bf868c7d VS |
1908 | /* |
1909 | * HW workaround, need to write this twice for issue | |
1910 | * that may result in first write getting masked. | |
1911 | */ | |
1912 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1913 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1914 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1915 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1916 | |
bf868c7d VS |
1917 | /* |
1918 | * HW workaround, need to toggle enable bit off and on | |
1919 | * for 12bpc with pixel repeat. | |
1920 | * | |
1921 | * FIXME: BSpec says this should be done at the end of | |
1922 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1923 | */ |
df18e721 ML |
1924 | if (pipe_config->pipe_bpp > 24 && |
1925 | pipe_config->pixel_multiplier > 1) { | |
bf868c7d VS |
1926 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1927 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1928 | ||
1929 | /* | |
1930 | * HW workaround, need to write this twice for issue | |
1931 | * that may result in first write getting masked. | |
1932 | */ | |
1933 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1934 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1935 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1936 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1937 | } |
c1dec79a | 1938 | |
df18e721 ML |
1939 | if (pipe_config->has_audio) |
1940 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
d1b1589c VS |
1941 | } |
1942 | ||
fd6bbda9 | 1943 | static void cpt_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1944 | const struct intel_crtc_state *pipe_config, |
1945 | const struct drm_connector_state *conn_state) | |
d1b1589c VS |
1946 | { |
1947 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1948 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1949 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c VS |
1950 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1951 | enum pipe pipe = crtc->pipe; | |
1952 | u32 temp; | |
1953 | ||
1954 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1955 | ||
1956 | temp |= SDVO_ENABLE; | |
df18e721 | 1957 | if (pipe_config->has_audio) |
dd6090f8 | 1958 | temp |= HDMI_AUDIO_ENABLE; |
d1b1589c VS |
1959 | |
1960 | /* | |
1961 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1962 | * | |
1963 | * The procedure for 12bpc is as follows: | |
1964 | * 1. disable HDMI clock gating | |
1965 | * 2. enable HDMI with 8bpc | |
1966 | * 3. enable HDMI with 12bpc | |
1967 | * 4. enable HDMI clock gating | |
1968 | */ | |
1969 | ||
df18e721 | 1970 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1971 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1972 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1973 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1974 | ||
1975 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1976 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1977 | } |
d1b1589c VS |
1978 | |
1979 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1980 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1981 | ||
df18e721 | 1982 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1983 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1984 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1985 | ||
1986 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1987 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1988 | ||
1989 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1990 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1991 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1992 | } | |
1993 | ||
df18e721 ML |
1994 | if (pipe_config->has_audio) |
1995 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
b76cf76b | 1996 | } |
89b667f8 | 1997 | |
fd6bbda9 | 1998 | static void vlv_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1999 | const struct intel_crtc_state *pipe_config, |
2000 | const struct drm_connector_state *conn_state) | |
b76cf76b | 2001 | { |
5ab432ef DV |
2002 | } |
2003 | ||
fd6bbda9 | 2004 | static void intel_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2005 | const struct intel_crtc_state *old_crtc_state, |
2006 | const struct drm_connector_state *old_conn_state) | |
5ab432ef DV |
2007 | { |
2008 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2009 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 2010 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f99be1b3 VS |
2011 | struct intel_digital_port *intel_dig_port = |
2012 | hdmi_to_dig_port(intel_hdmi); | |
ac240288 | 2013 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
5ab432ef | 2014 | u32 temp; |
5ab432ef | 2015 | |
b242b7f7 | 2016 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 2017 | |
dd6090f8 | 2018 | temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); |
b242b7f7 PZ |
2019 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
2020 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
2021 | |
2022 | /* | |
2023 | * HW workaround for IBX, we need to move the port | |
2024 | * to transcoder A after disabling it to allow the | |
2025 | * matching DP port to be enabled on transcoder A. | |
2026 | */ | |
6e266956 | 2027 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { |
0c241d5b VS |
2028 | /* |
2029 | * We get CPU/PCH FIFO underruns on the other pipe when | |
2030 | * doing the workaround. Sweep them under the rug. | |
2031 | */ | |
2032 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
2033 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
2034 | ||
76203467 VS |
2035 | temp &= ~SDVO_PIPE_SEL_MASK; |
2036 | temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); | |
1612c8bd VS |
2037 | /* |
2038 | * HW workaround, need to write this twice for issue | |
2039 | * that may result in first write getting masked. | |
2040 | */ | |
2041 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
2042 | POSTING_READ(intel_hdmi->hdmi_reg); | |
2043 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
2044 | POSTING_READ(intel_hdmi->hdmi_reg); | |
2045 | ||
2046 | temp &= ~SDVO_ENABLE; | |
2047 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
2048 | POSTING_READ(intel_hdmi->hdmi_reg); | |
0c241d5b | 2049 | |
0f0f74bc | 2050 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
2051 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
2052 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 2053 | } |
6d67415f | 2054 | |
790ea70c VS |
2055 | intel_dig_port->set_infoframes(encoder, |
2056 | false, | |
f99be1b3 | 2057 | old_crtc_state, old_conn_state); |
b2ccb822 VS |
2058 | |
2059 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
7d57382e EA |
2060 | } |
2061 | ||
fd6bbda9 | 2062 | static void g4x_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2063 | const struct intel_crtc_state *old_crtc_state, |
2064 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2065 | { |
df18e721 | 2066 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
2067 | intel_audio_codec_disable(encoder, |
2068 | old_crtc_state, old_conn_state); | |
a4790cec | 2069 | |
fd6bbda9 | 2070 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
2071 | } |
2072 | ||
fd6bbda9 | 2073 | static void pch_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2074 | const struct intel_crtc_state *old_crtc_state, |
2075 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2076 | { |
df18e721 | 2077 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
2078 | intel_audio_codec_disable(encoder, |
2079 | old_crtc_state, old_conn_state); | |
a4790cec VS |
2080 | } |
2081 | ||
fd6bbda9 | 2082 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2083 | const struct intel_crtc_state *old_crtc_state, |
2084 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2085 | { |
fd6bbda9 | 2086 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
2087 | } |
2088 | ||
d6038611 | 2089 | static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) |
7d148ef5 | 2090 | { |
d6038611 VS |
2091 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2092 | const struct ddi_vbt_port_info *info = | |
2093 | &dev_priv->vbt.ddi_port_info[encoder->port]; | |
2094 | int max_tmds_clock; | |
2095 | ||
9672a69c | 2096 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
d6038611 VS |
2097 | max_tmds_clock = 594000; |
2098 | else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) | |
2099 | max_tmds_clock = 300000; | |
2100 | else if (INTEL_GEN(dev_priv) >= 5) | |
2101 | max_tmds_clock = 225000; | |
7d148ef5 | 2102 | else |
d6038611 VS |
2103 | max_tmds_clock = 165000; |
2104 | ||
2105 | if (info->max_tmds_clock) | |
2106 | max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); | |
2107 | ||
2108 | return max_tmds_clock; | |
7d148ef5 DV |
2109 | } |
2110 | ||
b1ba124d | 2111 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
7a5ca19f ML |
2112 | bool respect_downstream_limits, |
2113 | bool force_dvi) | |
b1ba124d | 2114 | { |
d6038611 VS |
2115 | struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; |
2116 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); | |
b1ba124d VS |
2117 | |
2118 | if (respect_downstream_limits) { | |
8cadab0a VS |
2119 | struct intel_connector *connector = hdmi->attached_connector; |
2120 | const struct drm_display_info *info = &connector->base.display_info; | |
2121 | ||
b1ba124d VS |
2122 | if (hdmi->dp_dual_mode.max_tmds_clock) |
2123 | max_tmds_clock = min(max_tmds_clock, | |
2124 | hdmi->dp_dual_mode.max_tmds_clock); | |
8cadab0a VS |
2125 | |
2126 | if (info->max_tmds_clock) | |
2127 | max_tmds_clock = min(max_tmds_clock, | |
2128 | info->max_tmds_clock); | |
7a5ca19f | 2129 | else if (!hdmi->has_hdmi_sink || force_dvi) |
b1ba124d VS |
2130 | max_tmds_clock = min(max_tmds_clock, 165000); |
2131 | } | |
2132 | ||
2133 | return max_tmds_clock; | |
2134 | } | |
2135 | ||
e64e739e VS |
2136 | static enum drm_mode_status |
2137 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
7a5ca19f ML |
2138 | int clock, bool respect_downstream_limits, |
2139 | bool force_dvi) | |
e64e739e | 2140 | { |
e2d214ae | 2141 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); |
e64e739e VS |
2142 | |
2143 | if (clock < 25000) | |
2144 | return MODE_CLOCK_LOW; | |
7a5ca19f | 2145 | if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) |
e64e739e VS |
2146 | return MODE_CLOCK_HIGH; |
2147 | ||
5e6ccc0b | 2148 | /* BXT DPLL can't generate 223-240 MHz */ |
cc3f90f0 | 2149 | if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) |
5e6ccc0b VS |
2150 | return MODE_CLOCK_RANGE; |
2151 | ||
2152 | /* CHV DPLL can't generate 216-240 MHz */ | |
e2d214ae | 2153 | if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) |
e64e739e VS |
2154 | return MODE_CLOCK_RANGE; |
2155 | ||
2156 | return MODE_OK; | |
2157 | } | |
2158 | ||
c19de8eb DL |
2159 | static enum drm_mode_status |
2160 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
2161 | struct drm_display_mode *mode) | |
7d57382e | 2162 | { |
e64e739e VS |
2163 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
2164 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
49cff963 | 2165 | struct drm_i915_private *dev_priv = to_i915(dev); |
e64e739e VS |
2166 | enum drm_mode_status status; |
2167 | int clock; | |
587bf496 | 2168 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
7a5ca19f ML |
2169 | bool force_dvi = |
2170 | READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; | |
e64e739e | 2171 | |
e4dd27aa VS |
2172 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
2173 | return MODE_NO_DBLESCAN; | |
2174 | ||
e64e739e | 2175 | clock = mode->clock; |
587bf496 MK |
2176 | |
2177 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
2178 | clock *= 2; | |
2179 | ||
2180 | if (clock > max_dotclk) | |
2181 | return MODE_CLOCK_HIGH; | |
2182 | ||
697c4078 CT |
2183 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
2184 | clock *= 2; | |
2185 | ||
b22ca995 SS |
2186 | if (drm_mode_is_420_only(&connector->display_info, mode)) |
2187 | clock /= 2; | |
2188 | ||
e64e739e | 2189 | /* check if we can do 8bpc */ |
7a5ca19f | 2190 | status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); |
7d57382e | 2191 | |
cd9e11a8 RS |
2192 | if (hdmi->has_hdmi_sink && !force_dvi) { |
2193 | /* if we can't do 8bpc we may still be able to do 12bpc */ | |
b2ae318a | 2194 | if (status != MODE_OK && !HAS_GMCH(dev_priv)) |
cd9e11a8 RS |
2195 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, |
2196 | true, force_dvi); | |
2197 | ||
2198 | /* if we can't do 8,12bpc we may still be able to do 10bpc */ | |
2199 | if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) | |
2200 | status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, | |
2201 | true, force_dvi); | |
2202 | } | |
2d20411e VS |
2203 | if (status != MODE_OK) |
2204 | return status; | |
7d57382e | 2205 | |
2d20411e | 2206 | return intel_mode_valid_max_plane_size(dev_priv, mode); |
7d57382e EA |
2207 | } |
2208 | ||
cd9e11a8 RS |
2209 | static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, |
2210 | int bpc) | |
71800632 | 2211 | { |
c750bdd3 VS |
2212 | struct drm_i915_private *dev_priv = |
2213 | to_i915(crtc_state->base.crtc->dev); | |
2214 | struct drm_atomic_state *state = crtc_state->base.state; | |
2215 | struct drm_connector_state *connector_state; | |
2216 | struct drm_connector *connector; | |
22dae8a0 RS |
2217 | const struct drm_display_mode *adjusted_mode = |
2218 | &crtc_state->base.adjusted_mode; | |
c750bdd3 | 2219 | int i; |
71800632 | 2220 | |
b2ae318a | 2221 | if (HAS_GMCH(dev_priv)) |
71800632 VS |
2222 | return false; |
2223 | ||
cd9e11a8 RS |
2224 | if (bpc == 10 && INTEL_GEN(dev_priv) < 11) |
2225 | return false; | |
2226 | ||
3fad10db | 2227 | if (crtc_state->pipe_bpp < bpc * 3) |
be33be5d VS |
2228 | return false; |
2229 | ||
2230 | if (!crtc_state->has_hdmi_sink) | |
2231 | return false; | |
2232 | ||
71800632 | 2233 | /* |
cd9e11a8 | 2234 | * HDMI deep color affects the clocks, so it's only possible |
71800632 VS |
2235 | * when not cloning with other encoder types. |
2236 | */ | |
c750bdd3 VS |
2237 | if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) |
2238 | return false; | |
2239 | ||
fe5f6b1f | 2240 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
c750bdd3 VS |
2241 | const struct drm_display_info *info = &connector->display_info; |
2242 | ||
2243 | if (connector_state->crtc != crtc_state->base.crtc) | |
2244 | continue; | |
2245 | ||
33b7f3ee | 2246 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { |
60436fd4 SS |
2247 | const struct drm_hdmi_info *hdmi = &info->hdmi; |
2248 | ||
cd9e11a8 RS |
2249 | if (bpc == 12 && !(hdmi->y420_dc_modes & |
2250 | DRM_EDID_YCBCR420_DC_36)) | |
2251 | return false; | |
2252 | else if (bpc == 10 && !(hdmi->y420_dc_modes & | |
2253 | DRM_EDID_YCBCR420_DC_30)) | |
60436fd4 SS |
2254 | return false; |
2255 | } else { | |
cd9e11a8 RS |
2256 | if (bpc == 12 && !(info->edid_hdmi_dc_modes & |
2257 | DRM_EDID_HDMI_DC_36)) | |
2258 | return false; | |
2259 | else if (bpc == 10 && !(info->edid_hdmi_dc_modes & | |
2260 | DRM_EDID_HDMI_DC_30)) | |
60436fd4 SS |
2261 | return false; |
2262 | } | |
c750bdd3 VS |
2263 | } |
2264 | ||
2abf3c0d | 2265 | /* Display WA #1139: glk */ |
cd9e11a8 | 2266 | if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && |
22dae8a0 RS |
2267 | adjusted_mode->htotal > 5460) |
2268 | return false; | |
2269 | ||
2270 | /* Display Wa_1405510057:icl */ | |
2271 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && | |
2dd24a9c | 2272 | bpc == 10 && INTEL_GEN(dev_priv) >= 11 && |
22dae8a0 RS |
2273 | (adjusted_mode->crtc_hblank_end - |
2274 | adjusted_mode->crtc_hblank_start) % 8 == 2) | |
46649d8b ACO |
2275 | return false; |
2276 | ||
c750bdd3 | 2277 | return true; |
71800632 VS |
2278 | } |
2279 | ||
60436fd4 SS |
2280 | static bool |
2281 | intel_hdmi_ycbcr420_config(struct drm_connector *connector, | |
9e362992 | 2282 | struct intel_crtc_state *config) |
60436fd4 | 2283 | { |
e5c05931 SS |
2284 | struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); |
2285 | ||
60436fd4 SS |
2286 | if (!connector->ycbcr_420_allowed) { |
2287 | DRM_ERROR("Platform doesn't support YCBCR420 output\n"); | |
2288 | return false; | |
2289 | } | |
2290 | ||
33b7f3ee | 2291 | config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; |
e5c05931 SS |
2292 | |
2293 | /* YCBCR 420 output conversion needs a scaler */ | |
2294 | if (skl_update_scaler_crtc(config)) { | |
2295 | DRM_DEBUG_KMS("Scaler allocation for output failed\n"); | |
2296 | return false; | |
2297 | } | |
2298 | ||
2299 | intel_pch_panel_fitting(intel_crtc, config, | |
2300 | DRM_MODE_SCALE_FULLSCREEN); | |
2301 | ||
60436fd4 SS |
2302 | return true; |
2303 | } | |
2304 | ||
9e362992 VS |
2305 | static int intel_hdmi_port_clock(int clock, int bpc) |
2306 | { | |
2307 | /* | |
2308 | * Need to adjust the port link by: | |
2309 | * 1.5x for 12bpc | |
2310 | * 1.25x for 10bpc | |
2311 | */ | |
2312 | return clock * bpc / 8; | |
2313 | } | |
2314 | ||
2315 | static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, | |
2316 | struct intel_crtc_state *crtc_state, | |
2317 | int clock, bool force_dvi) | |
2318 | { | |
2319 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
2320 | int bpc; | |
2321 | ||
2322 | for (bpc = 12; bpc >= 10; bpc -= 2) { | |
2323 | if (hdmi_deep_color_possible(crtc_state, bpc) && | |
2324 | hdmi_port_clock_valid(intel_hdmi, | |
2325 | intel_hdmi_port_clock(clock, bpc), | |
2326 | true, force_dvi) == MODE_OK) | |
2327 | return bpc; | |
2328 | } | |
2329 | ||
2330 | return 8; | |
2331 | } | |
2332 | ||
2333 | static int intel_hdmi_compute_clock(struct intel_encoder *encoder, | |
2334 | struct intel_crtc_state *crtc_state, | |
2335 | bool force_dvi) | |
2336 | { | |
2337 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
2338 | const struct drm_display_mode *adjusted_mode = | |
2339 | &crtc_state->base.adjusted_mode; | |
2340 | int bpc, clock = adjusted_mode->crtc_clock; | |
2341 | ||
2342 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) | |
2343 | clock *= 2; | |
2344 | ||
2345 | /* YCBCR420 TMDS rate requirement is half the pixel clock */ | |
2346 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
2347 | clock /= 2; | |
2348 | ||
2349 | bpc = intel_hdmi_compute_bpc(encoder, crtc_state, | |
2350 | clock, force_dvi); | |
2351 | ||
2352 | crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); | |
2353 | ||
2354 | /* | |
2355 | * pipe_bpp could already be below 8bpc due to | |
2356 | * FDI bandwidth constraints. We shouldn't bump it | |
2357 | * back up to 8bpc in that case. | |
2358 | */ | |
2359 | if (crtc_state->pipe_bpp > bpc * 3) | |
2360 | crtc_state->pipe_bpp = bpc * 3; | |
2361 | ||
2362 | DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n", | |
2363 | bpc, crtc_state->pipe_bpp); | |
2364 | ||
2365 | if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, | |
2366 | false, force_dvi) != MODE_OK) { | |
2367 | DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n", | |
2368 | crtc_state->port_clock); | |
2369 | return -EINVAL; | |
2370 | } | |
2371 | ||
2372 | return 0; | |
2373 | } | |
2374 | ||
ba2d08c2 VS |
2375 | static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, |
2376 | const struct drm_connector_state *conn_state) | |
2377 | { | |
2378 | const struct intel_digital_connector_state *intel_conn_state = | |
2379 | to_intel_digital_connector_state(conn_state); | |
2380 | const struct drm_display_mode *adjusted_mode = | |
2381 | &crtc_state->base.adjusted_mode; | |
2382 | ||
cae154fc VS |
2383 | /* |
2384 | * Our YCbCr output is always limited range. | |
2385 | * crtc_state->limited_color_range only applies to RGB, | |
2386 | * and it must never be set for YCbCr or we risk setting | |
2387 | * some conflicting bits in PIPECONF which will mess up | |
2388 | * the colors on the monitor. | |
2389 | */ | |
2390 | if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) | |
2391 | return false; | |
2392 | ||
ba2d08c2 VS |
2393 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
2394 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
2395 | return crtc_state->has_hdmi_sink && | |
2396 | drm_default_rgb_quant_range(adjusted_mode) == | |
2397 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
2398 | } else { | |
2399 | return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; | |
2400 | } | |
2401 | } | |
2402 | ||
204474a6 LP |
2403 | int intel_hdmi_compute_config(struct intel_encoder *encoder, |
2404 | struct intel_crtc_state *pipe_config, | |
2405 | struct drm_connector_state *conn_state) | |
7d57382e | 2406 | { |
5bfe2ac0 | 2407 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
4f8036a2 | 2408 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 2409 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
60436fd4 SS |
2410 | struct drm_connector *connector = conn_state->connector; |
2411 | struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; | |
7a5ca19f ML |
2412 | struct intel_digital_connector_state *intel_conn_state = |
2413 | to_intel_digital_connector_state(conn_state); | |
7a5ca19f | 2414 | bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; |
9e362992 | 2415 | int ret; |
3685a8f3 | 2416 | |
e4dd27aa | 2417 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
204474a6 | 2418 | return -EINVAL; |
e4dd27aa | 2419 | |
d9facae6 | 2420 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
7a5ca19f | 2421 | pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; |
6897b4b5 | 2422 | |
e43823ec JB |
2423 | if (pipe_config->has_hdmi_sink) |
2424 | pipe_config->has_infoframe = true; | |
2425 | ||
9e362992 | 2426 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
697c4078 | 2427 | pipe_config->pixel_multiplier = 2; |
697c4078 | 2428 | |
60436fd4 | 2429 | if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { |
9e362992 | 2430 | if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) { |
60436fd4 | 2431 | DRM_ERROR("Can't support YCBCR420 output\n"); |
204474a6 | 2432 | return -EINVAL; |
60436fd4 SS |
2433 | } |
2434 | } | |
2435 | ||
cae154fc VS |
2436 | pipe_config->limited_color_range = |
2437 | intel_hdmi_limited_color_range(pipe_config, conn_state); | |
2438 | ||
4f8036a2 | 2439 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) |
5bfe2ac0 DV |
2440 | pipe_config->has_pch_encoder = true; |
2441 | ||
7a5ca19f ML |
2442 | if (pipe_config->has_hdmi_sink) { |
2443 | if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
2444 | pipe_config->has_audio = intel_hdmi->has_audio; | |
2445 | else | |
2446 | pipe_config->has_audio = | |
2447 | intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
2448 | } | |
9ed109a7 | 2449 | |
9e362992 VS |
2450 | ret = intel_hdmi_compute_clock(encoder, pipe_config, force_dvi); |
2451 | if (ret) | |
2452 | return ret; | |
325b9d04 | 2453 | |
28b468a0 | 2454 | /* Set user selected PAR to incoming mode's member */ |
0e9f25d0 | 2455 | adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; |
28b468a0 | 2456 | |
d4d6279a ACO |
2457 | pipe_config->lane_count = 4; |
2458 | ||
9672a69c RV |
2459 | if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || |
2460 | IS_GEMINILAKE(dev_priv))) { | |
15953637 SS |
2461 | if (scdc->scrambling.low_rates) |
2462 | pipe_config->hdmi_scrambling = true; | |
2463 | ||
2464 | if (pipe_config->port_clock > 340000) { | |
2465 | pipe_config->hdmi_scrambling = true; | |
2466 | pipe_config->hdmi_high_tmds_clock_ratio = true; | |
2467 | } | |
2468 | } | |
2469 | ||
fbf08556 VS |
2470 | intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); |
2471 | ||
2472 | if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { | |
2473 | DRM_DEBUG_KMS("bad AVI infoframe\n"); | |
2474 | return -EINVAL; | |
2475 | } | |
2476 | ||
2477 | if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { | |
2478 | DRM_DEBUG_KMS("bad SPD infoframe\n"); | |
2479 | return -EINVAL; | |
2480 | } | |
2481 | ||
2482 | if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { | |
2483 | DRM_DEBUG_KMS("bad HDMI infoframe\n"); | |
2484 | return -EINVAL; | |
2485 | } | |
2486 | ||
5a0200f6 US |
2487 | if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { |
2488 | DRM_DEBUG_KMS("bad DRM infoframe\n"); | |
2489 | return -EINVAL; | |
2490 | } | |
2491 | ||
39e2df09 R |
2492 | intel_hdcp_transcoder_config(intel_hdmi->attached_connector, |
2493 | pipe_config->cpu_transcoder); | |
2494 | ||
204474a6 | 2495 | return 0; |
7d57382e EA |
2496 | } |
2497 | ||
953ece69 CW |
2498 | static void |
2499 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 2500 | { |
df0e9248 | 2501 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 2502 | |
953ece69 CW |
2503 | intel_hdmi->has_hdmi_sink = false; |
2504 | intel_hdmi->has_audio = false; | |
953ece69 | 2505 | |
b1ba124d VS |
2506 | intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; |
2507 | intel_hdmi->dp_dual_mode.max_tmds_clock = 0; | |
2508 | ||
953ece69 CW |
2509 | kfree(to_intel_connector(connector)->detect_edid); |
2510 | to_intel_connector(connector)->detect_edid = NULL; | |
2511 | } | |
2512 | ||
b1ba124d | 2513 | static void |
d6199256 | 2514 | intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) |
b1ba124d VS |
2515 | { |
2516 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
2517 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); | |
8f4f2797 | 2518 | enum port port = hdmi_to_dig_port(hdmi)->base.port; |
b1ba124d VS |
2519 | struct i2c_adapter *adapter = |
2520 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
2521 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | |
2522 | ||
d6199256 VS |
2523 | /* |
2524 | * Type 1 DVI adaptors are not required to implement any | |
2525 | * registers, so we can't always detect their presence. | |
2526 | * Ideally we should be able to check the state of the | |
2527 | * CONFIG1 pin, but no such luck on our hardware. | |
2528 | * | |
2529 | * The only method left to us is to check the VBT to see | |
2530 | * if the port is a dual mode capable DP port. But let's | |
2531 | * only do that when we sucesfully read the EDID, to avoid | |
2532 | * confusing log messages about DP dual mode adaptors when | |
2533 | * there's nothing connected to the port. | |
2534 | */ | |
2535 | if (type == DRM_DP_DUAL_MODE_UNKNOWN) { | |
30190629 AJ |
2536 | /* An overridden EDID imply that we want this port for testing. |
2537 | * Make sure not to set limits for that port. | |
2538 | */ | |
2539 | if (has_edid && !connector->override_edid && | |
d6199256 VS |
2540 | intel_bios_is_port_dp_dual_mode(dev_priv, port)) { |
2541 | DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); | |
2542 | type = DRM_DP_DUAL_MODE_TYPE1_DVI; | |
2543 | } else { | |
2544 | type = DRM_DP_DUAL_MODE_NONE; | |
2545 | } | |
2546 | } | |
2547 | ||
2548 | if (type == DRM_DP_DUAL_MODE_NONE) | |
b1ba124d VS |
2549 | return; |
2550 | ||
2551 | hdmi->dp_dual_mode.type = type; | |
2552 | hdmi->dp_dual_mode.max_tmds_clock = | |
2553 | drm_dp_dual_mode_max_tmds_clock(type, adapter); | |
2554 | ||
2555 | DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", | |
2556 | drm_dp_get_dual_mode_type_name(type), | |
2557 | hdmi->dp_dual_mode.max_tmds_clock); | |
2558 | } | |
2559 | ||
953ece69 | 2560 | static bool |
23f889bd | 2561 | intel_hdmi_set_edid(struct drm_connector *connector) |
953ece69 CW |
2562 | { |
2563 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
2564 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
0e6e0be4 | 2565 | intel_wakeref_t wakeref; |
23f889bd | 2566 | struct edid *edid; |
953ece69 | 2567 | bool connected = false; |
cfb926e1 | 2568 | struct i2c_adapter *i2c; |
164c8598 | 2569 | |
0e6e0be4 | 2570 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
671dedd2 | 2571 | |
cfb926e1 SB |
2572 | i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); |
2573 | ||
2574 | edid = drm_get_edid(connector, i2c); | |
2575 | ||
2576 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
2577 | DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
2578 | intel_gmbus_force_bit(i2c, true); | |
2579 | edid = drm_get_edid(connector, i2c); | |
2580 | intel_gmbus_force_bit(i2c, false); | |
2581 | } | |
2ded9e27 | 2582 | |
23f889bd | 2583 | intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); |
b1ba124d | 2584 | |
0e6e0be4 | 2585 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); |
30ad48b7 | 2586 | |
953ece69 CW |
2587 | to_intel_connector(connector)->detect_edid = edid; |
2588 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
953ece69 | 2589 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
7a5ca19f | 2590 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
953ece69 CW |
2591 | |
2592 | connected = true; | |
55b7d6e8 CW |
2593 | } |
2594 | ||
9c229127 NA |
2595 | cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); |
2596 | ||
953ece69 CW |
2597 | return connected; |
2598 | } | |
2599 | ||
8166fcea DV |
2600 | static enum drm_connector_status |
2601 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 2602 | { |
39d1e234 | 2603 | enum drm_connector_status status = connector_status_disconnected; |
8166fcea | 2604 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
9c229127 | 2605 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
39d1e234 | 2606 | struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; |
0e6e0be4 | 2607 | intel_wakeref_t wakeref; |
953ece69 | 2608 | |
8166fcea DV |
2609 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
2610 | connector->base.id, connector->name); | |
2611 | ||
0e6e0be4 | 2612 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
29bb94bb | 2613 | |
2dd24a9c | 2614 | if (INTEL_GEN(dev_priv) >= 11 && |
39d1e234 PZ |
2615 | !intel_digital_port_connected(encoder)) |
2616 | goto out; | |
2617 | ||
8166fcea | 2618 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 2619 | |
7e732cac | 2620 | if (intel_hdmi_set_edid(connector)) |
953ece69 | 2621 | status = connector_status_connected; |
671dedd2 | 2622 | |
39d1e234 | 2623 | out: |
0e6e0be4 | 2624 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); |
29bb94bb | 2625 | |
9c229127 NA |
2626 | if (status != connector_status_connected) |
2627 | cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); | |
2628 | ||
2ded9e27 | 2629 | return status; |
7d57382e EA |
2630 | } |
2631 | ||
953ece69 CW |
2632 | static void |
2633 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 2634 | { |
953ece69 CW |
2635 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
2636 | connector->base.id, connector->name); | |
7d57382e | 2637 | |
953ece69 | 2638 | intel_hdmi_unset_edid(connector); |
671dedd2 | 2639 | |
953ece69 CW |
2640 | if (connector->status != connector_status_connected) |
2641 | return; | |
671dedd2 | 2642 | |
23f889bd | 2643 | intel_hdmi_set_edid(connector); |
953ece69 | 2644 | } |
671dedd2 | 2645 | |
953ece69 CW |
2646 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
2647 | { | |
2648 | struct edid *edid; | |
2649 | ||
2650 | edid = to_intel_connector(connector)->detect_edid; | |
2651 | if (edid == NULL) | |
2652 | return 0; | |
671dedd2 | 2653 | |
953ece69 | 2654 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
2655 | } |
2656 | ||
fd6bbda9 | 2657 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2658 | const struct intel_crtc_state *pipe_config, |
2659 | const struct drm_connector_state *conn_state) | |
13732ba7 | 2660 | { |
f99be1b3 VS |
2661 | struct intel_digital_port *intel_dig_port = |
2662 | enc_to_dig_port(&encoder->base); | |
13732ba7 | 2663 | |
ac240288 | 2664 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 2665 | |
790ea70c | 2666 | intel_dig_port->set_infoframes(encoder, |
f99be1b3 VS |
2667 | pipe_config->has_infoframe, |
2668 | pipe_config, conn_state); | |
13732ba7 JB |
2669 | } |
2670 | ||
fd6bbda9 | 2671 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2672 | const struct intel_crtc_state *pipe_config, |
2673 | const struct drm_connector_state *conn_state) | |
89b667f8 JB |
2674 | { |
2675 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2e1029c6 | 2676 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5f68c275 | 2677 | |
2e1029c6 | 2678 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
b76cf76b | 2679 | |
53d98725 ACO |
2680 | /* HDMI 1.0V-2dB */ |
2681 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | |
2682 | 0x2b247878); | |
2683 | ||
790ea70c | 2684 | dport->set_infoframes(encoder, |
f99be1b3 VS |
2685 | pipe_config->has_infoframe, |
2686 | pipe_config, conn_state); | |
13732ba7 | 2687 | |
fd6bbda9 | 2688 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
b76cf76b | 2689 | |
9b6de0a1 | 2690 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
2691 | } |
2692 | ||
fd6bbda9 | 2693 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2694 | const struct intel_crtc_state *pipe_config, |
2695 | const struct drm_connector_state *conn_state) | |
89b667f8 | 2696 | { |
ac240288 | 2697 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 2698 | |
2e1029c6 | 2699 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
89b667f8 JB |
2700 | } |
2701 | ||
fd6bbda9 | 2702 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2703 | const struct intel_crtc_state *pipe_config, |
2704 | const struct drm_connector_state *conn_state) | |
9197c88b | 2705 | { |
ac240288 | 2706 | intel_hdmi_prepare(encoder, pipe_config); |
625695f8 | 2707 | |
2e1029c6 | 2708 | chv_phy_pre_pll_enable(encoder, pipe_config); |
9197c88b VS |
2709 | } |
2710 | ||
fd6bbda9 | 2711 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2712 | const struct intel_crtc_state *old_crtc_state, |
2713 | const struct drm_connector_state *old_conn_state) | |
d6db995f | 2714 | { |
2e1029c6 | 2715 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
d6db995f VS |
2716 | } |
2717 | ||
fd6bbda9 | 2718 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2719 | const struct intel_crtc_state *old_crtc_state, |
2720 | const struct drm_connector_state *old_conn_state) | |
89b667f8 | 2721 | { |
89b667f8 | 2722 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
2e1029c6 | 2723 | vlv_phy_reset_lanes(encoder, old_crtc_state); |
89b667f8 JB |
2724 | } |
2725 | ||
fd6bbda9 | 2726 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2727 | const struct intel_crtc_state *old_crtc_state, |
2728 | const struct drm_connector_state *old_conn_state) | |
580d3811 | 2729 | { |
580d3811 | 2730 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2731 | struct drm_i915_private *dev_priv = to_i915(dev); |
580d3811 | 2732 | |
221c7862 | 2733 | vlv_dpio_get(dev_priv); |
580d3811 | 2734 | |
a8f327fb | 2735 | /* Assert data lane reset */ |
2e1029c6 | 2736 | chv_data_lane_soft_reset(encoder, old_crtc_state, true); |
580d3811 | 2737 | |
221c7862 | 2738 | vlv_dpio_put(dev_priv); |
580d3811 VS |
2739 | } |
2740 | ||
fd6bbda9 | 2741 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2742 | const struct intel_crtc_state *pipe_config, |
2743 | const struct drm_connector_state *conn_state) | |
e4a1d846 CML |
2744 | { |
2745 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2746 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2747 | struct drm_i915_private *dev_priv = to_i915(dev); |
2e523e98 | 2748 | |
2e1029c6 | 2749 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
a02ef3c7 | 2750 | |
e4a1d846 CML |
2751 | /* FIXME: Program the support xxx V-dB */ |
2752 | /* Use 800mV-0dB */ | |
b7fa22d8 | 2753 | chv_set_phy_signal_level(encoder, 128, 102, false); |
e4a1d846 | 2754 | |
790ea70c | 2755 | dport->set_infoframes(encoder, |
f99be1b3 VS |
2756 | pipe_config->has_infoframe, |
2757 | pipe_config, conn_state); | |
b4eb1564 | 2758 | |
fd6bbda9 | 2759 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
e4a1d846 | 2760 | |
9b6de0a1 | 2761 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
2762 | |
2763 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2764 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2765 | } |
2766 | ||
7d09888e OV |
2767 | static struct i2c_adapter * |
2768 | intel_hdmi_get_i2c_adapter(struct drm_connector *connector) | |
2769 | { | |
2770 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
2771 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
2772 | ||
2773 | return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); | |
2774 | } | |
2775 | ||
2776 | static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) | |
2777 | { | |
2778 | struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); | |
2779 | struct kobject *i2c_kobj = &adapter->dev.kobj; | |
2780 | struct kobject *connector_kobj = &connector->kdev->kobj; | |
2781 | int ret; | |
2782 | ||
2783 | ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); | |
2784 | if (ret) | |
2785 | DRM_ERROR("Failed to create i2c symlink (%d)\n", ret); | |
2786 | } | |
2787 | ||
2788 | static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) | |
2789 | { | |
2790 | struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); | |
2791 | struct kobject *i2c_kobj = &adapter->dev.kobj; | |
2792 | struct kobject *connector_kobj = &connector->kdev->kobj; | |
2793 | ||
2794 | sysfs_remove_link(connector_kobj, i2c_kobj->name); | |
2795 | } | |
2796 | ||
bdc93fe0 R |
2797 | static int |
2798 | intel_hdmi_connector_register(struct drm_connector *connector) | |
2799 | { | |
2800 | int ret; | |
2801 | ||
2802 | ret = intel_connector_register(connector); | |
2803 | if (ret) | |
2804 | return ret; | |
2805 | ||
2806 | i915_debugfs_connector_add(connector); | |
2807 | ||
7d09888e OV |
2808 | intel_hdmi_create_i2c_symlink(connector); |
2809 | ||
bdc93fe0 R |
2810 | return ret; |
2811 | } | |
2812 | ||
7d57382e EA |
2813 | static void intel_hdmi_destroy(struct drm_connector *connector) |
2814 | { | |
5558f3d5 DM |
2815 | struct cec_notifier *n = intel_attached_hdmi(connector)->cec_notifier; |
2816 | ||
2817 | cec_notifier_conn_unregister(n); | |
d4b26e4f JN |
2818 | |
2819 | intel_connector_destroy(connector); | |
7d57382e EA |
2820 | } |
2821 | ||
7d09888e OV |
2822 | static void intel_hdmi_connector_unregister(struct drm_connector *connector) |
2823 | { | |
2824 | intel_hdmi_remove_i2c_symlink(connector); | |
2825 | ||
2826 | intel_connector_unregister(connector); | |
2827 | } | |
2828 | ||
7d57382e | 2829 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
7d57382e | 2830 | .detect = intel_hdmi_detect, |
953ece69 | 2831 | .force = intel_hdmi_force, |
7d57382e | 2832 | .fill_modes = drm_helper_probe_single_connector_modes, |
7a5ca19f ML |
2833 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
2834 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
bdc93fe0 | 2835 | .late_register = intel_hdmi_connector_register, |
7d09888e | 2836 | .early_unregister = intel_hdmi_connector_unregister, |
7d57382e | 2837 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 2838 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
7a5ca19f | 2839 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
7d57382e EA |
2840 | }; |
2841 | ||
2842 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
2843 | .get_modes = intel_hdmi_get_modes, | |
2844 | .mode_valid = intel_hdmi_mode_valid, | |
7a5ca19f | 2845 | .atomic_check = intel_digital_connector_atomic_check, |
7d57382e EA |
2846 | }; |
2847 | ||
7d57382e | 2848 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 2849 | .destroy = intel_encoder_destroy, |
7d57382e EA |
2850 | }; |
2851 | ||
55b7d6e8 CW |
2852 | static void |
2853 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
2854 | { | |
f1a12172 | 2855 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
2f146b78 US |
2856 | struct intel_digital_port *intel_dig_port = |
2857 | hdmi_to_dig_port(intel_hdmi); | |
f1a12172 | 2858 | |
3f43c48d | 2859 | intel_attach_force_audio_property(connector); |
e953fd7b | 2860 | intel_attach_broadcast_rgb_property(connector); |
94a11ddc | 2861 | intel_attach_aspect_ratio_property(connector); |
2f146b78 US |
2862 | |
2863 | /* | |
2864 | * Attach Colorspace property for Non LSPCON based device | |
2865 | * ToDo: This needs to be extended for LSPCON implementation | |
2866 | * as well. Will be implemented separately. | |
2867 | */ | |
2868 | if (!intel_dig_port->lspcon.active) | |
2869 | intel_attach_colorspace_property(connector); | |
2870 | ||
6553b123 | 2871 | drm_connector_attach_content_type_property(connector); |
0e9f25d0 | 2872 | connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
f1a12172 | 2873 | |
b7bedf31 US |
2874 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
2875 | drm_object_attach_property(&connector->base, | |
2876 | connector->dev->mode_config.hdr_output_metadata_property, 0); | |
2877 | ||
b2ae318a | 2878 | if (!HAS_GMCH(dev_priv)) |
f1a12172 | 2879 | drm_connector_attach_max_bpc_property(connector, 8, 12); |
55b7d6e8 CW |
2880 | } |
2881 | ||
15953637 SS |
2882 | /* |
2883 | * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup | |
2884 | * @encoder: intel_encoder | |
2885 | * @connector: drm_connector | |
2886 | * @high_tmds_clock_ratio = bool to indicate if the function needs to set | |
2887 | * or reset the high tmds clock ratio for scrambling | |
2888 | * @scrambling: bool to Indicate if the function needs to set or reset | |
2889 | * sink scrambling | |
2890 | * | |
2891 | * This function handles scrambling on HDMI 2.0 capable sinks. | |
2892 | * If required clock rate is > 340 Mhz && scrambling is supported by sink | |
2893 | * it enables scrambling. This should be called before enabling the HDMI | |
2894 | * 2.0 port, as the sink can choose to disable the scrambling if it doesn't | |
2895 | * detect a scrambled clock within 100 ms. | |
277ab5ab VS |
2896 | * |
2897 | * Returns: | |
2898 | * True on success, false on failure. | |
15953637 | 2899 | */ |
277ab5ab | 2900 | bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, |
15953637 SS |
2901 | struct drm_connector *connector, |
2902 | bool high_tmds_clock_ratio, | |
2903 | bool scrambling) | |
2904 | { | |
277ab5ab | 2905 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
15953637 | 2906 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
15953637 | 2907 | struct drm_scrambling *sink_scrambling = |
277ab5ab VS |
2908 | &connector->display_info.hdmi.scdc.scrambling; |
2909 | struct i2c_adapter *adapter = | |
2910 | intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); | |
15953637 SS |
2911 | |
2912 | if (!sink_scrambling->supported) | |
277ab5ab | 2913 | return true; |
15953637 | 2914 | |
277ab5ab VS |
2915 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", |
2916 | connector->base.id, connector->name, | |
2917 | yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); | |
15953637 | 2918 | |
277ab5ab VS |
2919 | /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ |
2920 | return drm_scdc_set_high_tmds_clock_ratio(adapter, | |
2921 | high_tmds_clock_ratio) && | |
2922 | drm_scdc_set_scrambling(adapter, scrambling); | |
15953637 SS |
2923 | } |
2924 | ||
cec3bb01 | 2925 | static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
e4ab73a1 | 2926 | { |
e4ab73a1 VS |
2927 | u8 ddc_pin; |
2928 | ||
cec3bb01 AS |
2929 | switch (port) { |
2930 | case PORT_B: | |
2931 | ddc_pin = GMBUS_PIN_DPB; | |
2932 | break; | |
2933 | case PORT_C: | |
2934 | ddc_pin = GMBUS_PIN_DPC; | |
2935 | break; | |
2936 | case PORT_D: | |
2937 | ddc_pin = GMBUS_PIN_DPD_CHV; | |
2938 | break; | |
2939 | default: | |
2940 | MISSING_CASE(port); | |
2941 | ddc_pin = GMBUS_PIN_DPB; | |
2942 | break; | |
e4ab73a1 | 2943 | } |
cec3bb01 AS |
2944 | return ddc_pin; |
2945 | } | |
2946 | ||
2947 | static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) | |
2948 | { | |
2949 | u8 ddc_pin; | |
e4ab73a1 VS |
2950 | |
2951 | switch (port) { | |
2952 | case PORT_B: | |
cec3bb01 | 2953 | ddc_pin = GMBUS_PIN_1_BXT; |
e4ab73a1 VS |
2954 | break; |
2955 | case PORT_C: | |
cec3bb01 AS |
2956 | ddc_pin = GMBUS_PIN_2_BXT; |
2957 | break; | |
2958 | default: | |
2959 | MISSING_CASE(port); | |
2960 | ddc_pin = GMBUS_PIN_1_BXT; | |
2961 | break; | |
2962 | } | |
2963 | return ddc_pin; | |
2964 | } | |
2965 | ||
2966 | static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, | |
2967 | enum port port) | |
2968 | { | |
2969 | u8 ddc_pin; | |
2970 | ||
2971 | switch (port) { | |
2972 | case PORT_B: | |
2973 | ddc_pin = GMBUS_PIN_1_BXT; | |
2974 | break; | |
2975 | case PORT_C: | |
2976 | ddc_pin = GMBUS_PIN_2_BXT; | |
e4ab73a1 VS |
2977 | break; |
2978 | case PORT_D: | |
cec3bb01 AS |
2979 | ddc_pin = GMBUS_PIN_4_CNP; |
2980 | break; | |
3a2a59cc RV |
2981 | case PORT_F: |
2982 | ddc_pin = GMBUS_PIN_3_BXT; | |
2983 | break; | |
cec3bb01 AS |
2984 | default: |
2985 | MISSING_CASE(port); | |
2986 | ddc_pin = GMBUS_PIN_1_BXT; | |
2987 | break; | |
2988 | } | |
2989 | return ddc_pin; | |
2990 | } | |
2991 | ||
5c749c52 AS |
2992 | static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
2993 | { | |
fb81cbe4 | 2994 | enum phy phy = intel_port_to_phy(dev_priv, port); |
5c749c52 | 2995 | |
fb81cbe4 LDM |
2996 | if (intel_phy_is_combo(dev_priv, phy)) |
2997 | return GMBUS_PIN_1_BXT + port; | |
2998 | else if (intel_phy_is_tc(dev_priv, phy)) | |
2999 | return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); | |
3000 | ||
3001 | WARN(1, "Unknown port:%c\n", port_name(port)); | |
3002 | return GMBUS_PIN_2_BXT; | |
5c749c52 AS |
3003 | } |
3004 | ||
c6f7acb8 MR |
3005 | static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
3006 | { | |
48cf0a1e | 3007 | enum phy phy = intel_port_to_phy(dev_priv, port); |
c6f7acb8 MR |
3008 | u8 ddc_pin; |
3009 | ||
48cf0a1e MR |
3010 | switch (phy) { |
3011 | case PHY_A: | |
c6f7acb8 MR |
3012 | ddc_pin = GMBUS_PIN_1_BXT; |
3013 | break; | |
48cf0a1e | 3014 | case PHY_B: |
c6f7acb8 MR |
3015 | ddc_pin = GMBUS_PIN_2_BXT; |
3016 | break; | |
48cf0a1e | 3017 | case PHY_C: |
c6f7acb8 MR |
3018 | ddc_pin = GMBUS_PIN_9_TC1_ICP; |
3019 | break; | |
3020 | default: | |
48cf0a1e | 3021 | MISSING_CASE(phy); |
c6f7acb8 MR |
3022 | ddc_pin = GMBUS_PIN_1_BXT; |
3023 | break; | |
3024 | } | |
3025 | return ddc_pin; | |
3026 | } | |
3027 | ||
cec3bb01 AS |
3028 | static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, |
3029 | enum port port) | |
3030 | { | |
3031 | u8 ddc_pin; | |
3032 | ||
3033 | switch (port) { | |
3034 | case PORT_B: | |
3035 | ddc_pin = GMBUS_PIN_DPB; | |
3036 | break; | |
3037 | case PORT_C: | |
3038 | ddc_pin = GMBUS_PIN_DPC; | |
3039 | break; | |
3040 | case PORT_D: | |
3041 | ddc_pin = GMBUS_PIN_DPD; | |
e4ab73a1 VS |
3042 | break; |
3043 | default: | |
3044 | MISSING_CASE(port); | |
3045 | ddc_pin = GMBUS_PIN_DPB; | |
3046 | break; | |
3047 | } | |
cec3bb01 AS |
3048 | return ddc_pin; |
3049 | } | |
3050 | ||
3051 | static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, | |
3052 | enum port port) | |
3053 | { | |
3054 | const struct ddi_vbt_port_info *info = | |
3055 | &dev_priv->vbt.ddi_port_info[port]; | |
3056 | u8 ddc_pin; | |
3057 | ||
3058 | if (info->alternate_ddc_pin) { | |
3059 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", | |
3060 | info->alternate_ddc_pin, port_name(port)); | |
3061 | return info->alternate_ddc_pin; | |
3062 | } | |
3063 | ||
c6f7acb8 MR |
3064 | if (HAS_PCH_MCC(dev_priv)) |
3065 | ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); | |
b01a3ef3 | 3066 | else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) |
e0f83eb5 | 3067 | ddc_pin = icl_port_to_ddc_pin(dev_priv, port); |
cec3bb01 AS |
3068 | else if (HAS_PCH_CNP(dev_priv)) |
3069 | ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); | |
e0f83eb5 RV |
3070 | else if (IS_GEN9_LP(dev_priv)) |
3071 | ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); | |
3072 | else if (IS_CHERRYVIEW(dev_priv)) | |
3073 | ddc_pin = chv_port_to_ddc_pin(dev_priv, port); | |
cec3bb01 AS |
3074 | else |
3075 | ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); | |
e4ab73a1 VS |
3076 | |
3077 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", | |
3078 | ddc_pin, port_name(port)); | |
3079 | ||
3080 | return ddc_pin; | |
3081 | } | |
3082 | ||
385e4de0 VS |
3083 | void intel_infoframe_init(struct intel_digital_port *intel_dig_port) |
3084 | { | |
3085 | struct drm_i915_private *dev_priv = | |
3086 | to_i915(intel_dig_port->base.base.dev); | |
3087 | ||
3088 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
3089 | intel_dig_port->write_infoframe = vlv_write_infoframe; | |
f2a10d61 | 3090 | intel_dig_port->read_infoframe = vlv_read_infoframe; |
385e4de0 | 3091 | intel_dig_port->set_infoframes = vlv_set_infoframes; |
509efa2b | 3092 | intel_dig_port->infoframes_enabled = vlv_infoframes_enabled; |
385e4de0 VS |
3093 | } else if (IS_G4X(dev_priv)) { |
3094 | intel_dig_port->write_infoframe = g4x_write_infoframe; | |
f2a10d61 | 3095 | intel_dig_port->read_infoframe = g4x_read_infoframe; |
385e4de0 | 3096 | intel_dig_port->set_infoframes = g4x_set_infoframes; |
509efa2b | 3097 | intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; |
385e4de0 | 3098 | } else if (HAS_DDI(dev_priv)) { |
06c812d7 | 3099 | if (intel_dig_port->lspcon.active) { |
509efa2b | 3100 | intel_dig_port->write_infoframe = lspcon_write_infoframe; |
f2a10d61 | 3101 | intel_dig_port->read_infoframe = lspcon_read_infoframe; |
06c812d7 | 3102 | intel_dig_port->set_infoframes = lspcon_set_infoframes; |
509efa2b | 3103 | intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled; |
06c812d7 | 3104 | } else { |
06c812d7 | 3105 | intel_dig_port->write_infoframe = hsw_write_infoframe; |
f2a10d61 | 3106 | intel_dig_port->read_infoframe = hsw_read_infoframe; |
509efa2b VS |
3107 | intel_dig_port->set_infoframes = hsw_set_infoframes; |
3108 | intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; | |
06c812d7 | 3109 | } |
385e4de0 VS |
3110 | } else if (HAS_PCH_IBX(dev_priv)) { |
3111 | intel_dig_port->write_infoframe = ibx_write_infoframe; | |
f2a10d61 | 3112 | intel_dig_port->read_infoframe = ibx_read_infoframe; |
385e4de0 | 3113 | intel_dig_port->set_infoframes = ibx_set_infoframes; |
509efa2b | 3114 | intel_dig_port->infoframes_enabled = ibx_infoframes_enabled; |
385e4de0 VS |
3115 | } else { |
3116 | intel_dig_port->write_infoframe = cpt_write_infoframe; | |
f2a10d61 | 3117 | intel_dig_port->read_infoframe = cpt_read_infoframe; |
385e4de0 | 3118 | intel_dig_port->set_infoframes = cpt_set_infoframes; |
509efa2b | 3119 | intel_dig_port->infoframes_enabled = cpt_infoframes_enabled; |
385e4de0 VS |
3120 | } |
3121 | } | |
3122 | ||
00c09d70 PZ |
3123 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
3124 | struct intel_connector *intel_connector) | |
7d57382e | 3125 | { |
b9cb234c PZ |
3126 | struct drm_connector *connector = &intel_connector->base; |
3127 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
3128 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
3129 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 3130 | struct drm_i915_private *dev_priv = to_i915(dev); |
8f4f2797 | 3131 | enum port port = intel_encoder->port; |
5558f3d5 | 3132 | struct cec_connector_info conn_info; |
373a3cf7 | 3133 | |
66a990dd VS |
3134 | DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n", |
3135 | intel_encoder->base.base.id, intel_encoder->base.name); | |
22f35042 | 3136 | |
ccb1a831 | 3137 | if (WARN(intel_dig_port->max_lanes < 4, |
66a990dd VS |
3138 | "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", |
3139 | intel_dig_port->max_lanes, intel_encoder->base.base.id, | |
3140 | intel_encoder->base.name)) | |
ccb1a831 VS |
3141 | return; |
3142 | ||
7d57382e | 3143 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 3144 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
3145 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
3146 | ||
c3febcc4 | 3147 | connector->interlace_allowed = 1; |
7d57382e | 3148 | connector->doublescan_allowed = 0; |
573e74ad | 3149 | connector->stereo_allowed = 1; |
66a9278e | 3150 | |
9672a69c | 3151 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
eadc2e51 SS |
3152 | connector->ycbcr_420_allowed = true; |
3153 | ||
e4ab73a1 VS |
3154 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
3155 | ||
f761bef2 | 3156 | if (WARN_ON(port == PORT_A)) |
e4ab73a1 | 3157 | return; |
cf53902f | 3158 | intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); |
7d57382e | 3159 | |
4f8036a2 | 3160 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
3161 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
3162 | else | |
3163 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
3164 | |
3165 | intel_hdmi_add_properties(intel_hdmi, connector); | |
3166 | ||
04707f97 R |
3167 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
3168 | intel_hdmi->attached_connector = intel_connector; | |
3169 | ||
fdddd08c | 3170 | if (is_hdcp_supported(dev_priv, port)) { |
2320175f SP |
3171 | int ret = intel_hdcp_init(intel_connector, |
3172 | &intel_hdmi_hdcp_shim); | |
3173 | if (ret) | |
3174 | DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); | |
3175 | } | |
3176 | ||
b9cb234c PZ |
3177 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
3178 | * 0xd. Failure to do so will result in spurious interrupts being | |
3179 | * generated on the port when a cable is not attached. | |
3180 | */ | |
1c0f1b3d | 3181 | if (IS_G45(dev_priv)) { |
b9cb234c PZ |
3182 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
3183 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
3184 | } | |
9c229127 | 3185 | |
5558f3d5 DM |
3186 | cec_fill_conn_info_from_drm(&conn_info, connector); |
3187 | ||
3188 | intel_hdmi->cec_notifier = | |
3189 | cec_notifier_conn_register(dev->dev, port_identifier(port), | |
3190 | &conn_info); | |
9c229127 NA |
3191 | if (!intel_hdmi->cec_notifier) |
3192 | DRM_DEBUG_KMS("CEC notifier get failed\n"); | |
b9cb234c PZ |
3193 | } |
3194 | ||
bb80c925 JRS |
3195 | static enum intel_hotplug_state |
3196 | intel_hdmi_hotplug(struct intel_encoder *encoder, | |
3197 | struct intel_connector *connector, bool irq_received) | |
3198 | { | |
3199 | enum intel_hotplug_state state; | |
3200 | ||
3201 | state = intel_encoder_hotplug(encoder, connector, irq_received); | |
3202 | ||
3203 | /* | |
3204 | * On many platforms the HDMI live state signal is known to be | |
3205 | * unreliable, so we can't use it to detect if a sink is connected or | |
3206 | * not. Instead we detect if it's connected based on whether we can | |
3207 | * read the EDID or not. That in turn has a problem during disconnect, | |
3208 | * since the HPD interrupt may be raised before the DDC lines get | |
3209 | * disconnected (due to how the required length of DDC vs. HPD | |
3210 | * connector pins are specified) and so we'll still be able to get a | |
3211 | * valid EDID. To solve this schedule another detection cycle if this | |
3212 | * time around we didn't detect any change in the sink's connection | |
3213 | * status. | |
3214 | */ | |
3215 | if (state == INTEL_HOTPLUG_UNCHANGED && irq_received) | |
3216 | state = INTEL_HOTPLUG_RETRY; | |
3217 | ||
3218 | return state; | |
3219 | } | |
3220 | ||
c39055b0 | 3221 | void intel_hdmi_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 3222 | i915_reg_t hdmi_reg, enum port port) |
b9cb234c PZ |
3223 | { |
3224 | struct intel_digital_port *intel_dig_port; | |
3225 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
3226 | struct intel_connector *intel_connector; |
3227 | ||
b14c5679 | 3228 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
3229 | if (!intel_dig_port) |
3230 | return; | |
3231 | ||
08d9bc92 | 3232 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
3233 | if (!intel_connector) { |
3234 | kfree(intel_dig_port); | |
3235 | return; | |
3236 | } | |
3237 | ||
3238 | intel_encoder = &intel_dig_port->base; | |
b9cb234c | 3239 | |
c39055b0 ACO |
3240 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
3241 | &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
3242 | "HDMI %c", port_name(port)); | |
00c09d70 | 3243 | |
bb80c925 | 3244 | intel_encoder->hotplug = intel_hdmi_hotplug; |
5bfe2ac0 | 3245 | intel_encoder->compute_config = intel_hdmi_compute_config; |
6e266956 | 3246 | if (HAS_PCH_SPLIT(dev_priv)) { |
a4790cec VS |
3247 | intel_encoder->disable = pch_disable_hdmi; |
3248 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
3249 | } else { | |
3250 | intel_encoder->disable = g4x_disable_hdmi; | |
3251 | } | |
00c09d70 | 3252 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 3253 | intel_encoder->get_config = intel_hdmi_get_config; |
920a14b2 | 3254 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 3255 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
3256 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
3257 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 3258 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 3259 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
11a914c2 | 3260 | } else if (IS_VALLEYVIEW(dev_priv)) { |
9514ac6e CML |
3261 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
3262 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 3263 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 3264 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 3265 | } else { |
13732ba7 | 3266 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
6e266956 | 3267 | if (HAS_PCH_CPT(dev_priv)) |
d1b1589c | 3268 | intel_encoder->enable = cpt_enable_hdmi; |
6e266956 | 3269 | else if (HAS_PCH_IBX(dev_priv)) |
bf868c7d | 3270 | intel_encoder->enable = ibx_enable_hdmi; |
d1b1589c | 3271 | else |
bf868c7d | 3272 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 3273 | } |
5ab432ef | 3274 | |
b9cb234c | 3275 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
79f255a0 | 3276 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
03cdc1d4 | 3277 | intel_encoder->port = port; |
920a14b2 | 3278 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 | 3279 | if (port == PORT_D) |
0fbae9d2 | 3280 | intel_encoder->crtc_mask = BIT(PIPE_C); |
882ec384 | 3281 | else |
0fbae9d2 | 3282 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B); |
882ec384 | 3283 | } else { |
0fbae9d2 | 3284 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); |
882ec384 | 3285 | } |
301ea74a | 3286 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
3287 | /* |
3288 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
3289 | * to work on real hardware. And since g4x can send infoframes to | |
3290 | * only one port anyway, nothing is lost by allowing it. | |
3291 | */ | |
9beb5fea | 3292 | if (IS_G4X(dev_priv)) |
c6f1495d | 3293 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
7d57382e | 3294 | |
b242b7f7 | 3295 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 3296 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 3297 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 3298 | |
385e4de0 VS |
3299 | intel_infoframe_init(intel_dig_port); |
3300 | ||
39053089 | 3301 | intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); |
b9cb234c | 3302 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 3303 | } |