[linux-2.6-block.git] / drivers / gpu / drm / i915 / display / intel_dvo.c

/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

#include <linux/i2c.h>
#include <linux/slab.h>

#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/i915_drm.h>

#include "i915_drv.h"
#include "intel_connector.h"
#include "intel_display_types.h"
#include "intel_dvo.h"
#include "intel_dvo_dev.h"
#include "intel_gmbus.h"
#include "intel_panel.h"

#define INTEL_DVO_CHIP_NONE	0
#define INTEL_DVO_CHIP_LVDS	1
#define INTEL_DVO_CHIP_TMDS	2
#define INTEL_DVO_CHIP_TVOUT	4

#define SIL164_ADDR	0x38
#define CH7xxx_ADDR	0x76
#define TFP410_ADDR	0x38
#define NS2501_ADDR     0x38

static const struct intel_dvo_device intel_dvo_devices[] = {
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "sil164",
		.dvo_reg = DVOC,
		.dvo_srcdim_reg = DVOC_SRCDIM,
		.slave_addr = SIL164_ADDR,
		.dev_ops = &sil164_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "ch7xxx",
		.dvo_reg = DVOC,
		.dvo_srcdim_reg = DVOC_SRCDIM,
		.slave_addr = CH7xxx_ADDR,
		.dev_ops = &ch7xxx_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "ch7xxx",
		.dvo_reg = DVOC,
		.dvo_srcdim_reg = DVOC_SRCDIM,
		.slave_addr = 0x75, /* For some ch7010 */
		.dev_ops = &ch7xxx_ops,
	},
	{
		.type = INTEL_DVO_CHIP_LVDS,
		.name = "ivch",
		.dvo_reg = DVOA,
		.dvo_srcdim_reg = DVOA_SRCDIM,
		.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
		.dev_ops = &ivch_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "tfp410",
		.dvo_reg = DVOC,
		.dvo_srcdim_reg = DVOC_SRCDIM,
		.slave_addr = TFP410_ADDR,
		.dev_ops = &tfp410_ops,
	},
	{
		.type = INTEL_DVO_CHIP_LVDS,
		.name = "ch7017",
		.dvo_reg = DVOC,
		.dvo_srcdim_reg = DVOC_SRCDIM,
		.slave_addr = 0x75,
		.gpio = GMBUS_PIN_DPB,
		.dev_ops = &ch7017_ops,
	},
	{
	        .type = INTEL_DVO_CHIP_TMDS,
		.name = "ns2501",
		.dvo_reg = DVOB,
		.dvo_srcdim_reg = DVOB_SRCDIM,
		.slave_addr = NS2501_ADDR,
		.dev_ops = &ns2501_ops,
       }
};

struct intel_dvo {
	struct intel_encoder base;

	struct intel_dvo_device dev;

	struct intel_connector *attached_connector;

	bool panel_wants_dither;
};

static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder)
{
	return container_of(encoder, struct intel_dvo, base);
}

static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector)
{
	return enc_to_dvo(intel_attached_encoder(connector));
}

static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
{
	struct drm_device *dev = connector->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
	u32 tmp;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);

	if (!(tmp & DVO_ENABLE))
		return false;

	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
}

static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
				   enum pipe *pipe)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 tmp;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);

	*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;

	return tmp & DVO_ENABLE;
}

static void intel_dvo_get_config(struct intel_encoder *encoder,
				 struct intel_crtc_state *pipe_config)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 tmp, flags = 0;

	pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);

	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;
	if (tmp & DVO_VSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

	pipe_config->base.adjusted_mode.flags |= flags;

	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
}

static void intel_disable_dvo(struct intel_encoder *encoder,
			      const struct intel_crtc_state *old_crtc_state,
			      const struct drm_connector_state *old_conn_state)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
	u32 temp = I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
	I915_READ(dvo_reg);
}

static void intel_enable_dvo(struct intel_encoder *encoder,
			     const struct intel_crtc_state *pipe_config,
			     const struct drm_connector_state *conn_state)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
	u32 temp = I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
					 &pipe_config->base.mode,
					 &pipe_config->base.adjusted_mode);

	I915_WRITE(dvo_reg, temp | DVO_ENABLE);
	I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
}

static enum drm_mode_status
intel_dvo_mode_valid(struct drm_connector *connector,
		     struct drm_display_mode *mode)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	const struct drm_display_mode *fixed_mode =
		to_intel_connector(connector)->panel.fixed_mode;
	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
	int target_clock = mode->clock;

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	/* XXX: Validate clock range */

	if (fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
			return MODE_PANEL;
		if (mode->vdisplay > fixed_mode->vdisplay)
			return MODE_PANEL;

		target_clock = fixed_mode->clock;
	}

	if (target_clock > max_dotclk)
		return MODE_CLOCK_HIGH;

	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
}

static int intel_dvo_compute_config(struct intel_encoder *encoder,
				    struct intel_crtc_state *pipe_config,
				    struct drm_connector_state *conn_state)
{
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	const struct drm_display_mode *fixed_mode =
		intel_dvo->attached_connector->panel.fixed_mode;
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;

	/*
	 * If we have timings from the BIOS for the panel, put them in
	 * to the adjusted mode.  The CRTC will be set up for this mode,
	 * with the panel scaling set up to source from the H/VDisplay
	 * of the original mode.
	 */
	if (fixed_mode)
		intel_fixed_panel_mode(fixed_mode, adjusted_mode);

	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return -EINVAL;

	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;

	return 0;
}

static void intel_dvo_pre_enable(struct intel_encoder *encoder,
				 const struct intel_crtc_state *pipe_config,
				 const struct drm_connector_state *conn_state)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	enum pipe pipe = crtc->pipe;
	u32 dvo_val;
	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
	i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;

	/* Save the data order, since I don't know what it should be set to. */
	dvo_val = I915_READ(dvo_reg) &
		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
		   DVO_BLANK_ACTIVE_HIGH;

	dvo_val |= DVO_PIPE_SEL(pipe);
	dvo_val |= DVO_PIPE_STALL;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		dvo_val |= DVO_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;

	/*I915_WRITE(DVOB_SRCDIM,
	  (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
	  (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
	I915_WRITE(dvo_srcdim_reg,
		   (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
		   (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
	/*I915_WRITE(DVOB, dvo_val);*/
	I915_WRITE(dvo_reg, dvo_val);
}

static enum drm_connector_status
intel_dvo_detect(struct drm_connector *connector, bool force)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
}

static int intel_dvo_get_modes(struct drm_connector *connector)
{
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
	const struct drm_display_mode *fixed_mode =
		to_intel_connector(connector)->panel.fixed_mode;

	/*
	 * We should probably have an i2c driver get_modes function for those
	 * devices which will have a fixed set of modes determined by the chip
	 * (TV-out, for example), but for now with just TMDS and LVDS,
	 * that's not the case.
	 */
	intel_ddc_get_modes(connector,
			    intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC));
	if (!list_empty(&connector->probed_modes))
		return 1;

	if (fixed_mode) {
		struct drm_display_mode *mode;
		mode = drm_mode_duplicate(connector->dev, fixed_mode);
		if (mode) {
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}

	return 0;
}

static const struct drm_connector_funcs intel_dvo_connector_funcs = {
	.detect = intel_dvo_detect,
	.late_register = intel_connector_register,
	.early_unregister = intel_connector_unregister,
	.destroy = intel_connector_destroy,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
};

static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
	.mode_valid = intel_dvo_mode_valid,
	.get_modes = intel_dvo_get_modes,
};

static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
{
	struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));

	if (intel_dvo->dev.dev_ops->destroy)
		intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);

	intel_encoder_destroy(encoder);
}

static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
	.destroy = intel_dvo_enc_destroy,
};

/*
 * Attempts to get a fixed panel timing for LVDS (currently only the i830).
 *
 * Other chips with DVO LVDS will need to extend this to deal with the LVDS
 * chip being on DVOB/C and having multiple pipes.
 */
static struct drm_display_mode *
intel_dvo_get_current_mode(struct intel_encoder *encoder)
{
	struct drm_display_mode *mode;

	mode = intel_encoder_current_mode(encoder);
	if (mode) {
		DRM_DEBUG_KMS("using current (BIOS) mode: ");
		drm_mode_debug_printmodeline(mode);
		mode->type |= DRM_MODE_TYPE_PREFERRED;
	}

	return mode;
}

static enum port intel_dvo_port(i915_reg_t dvo_reg)
{
	if (i915_mmio_reg_equal(dvo_reg, DVOA))
		return PORT_A;
	else if (i915_mmio_reg_equal(dvo_reg, DVOB))
		return PORT_B;
	else
		return PORT_C;
}

void intel_dvo_init(struct drm_i915_private *dev_priv)
{
	struct intel_encoder *intel_encoder;
	struct intel_dvo *intel_dvo;
	struct intel_connector *intel_connector;
	int i;
	int encoder_type = DRM_MODE_ENCODER_NONE;

	intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
	if (!intel_dvo)
		return;

	intel_connector = intel_connector_alloc();
	if (!intel_connector) {
		kfree(intel_dvo);
		return;
	}

	intel_dvo->attached_connector = intel_connector;

	intel_encoder = &intel_dvo->base;

	intel_encoder->disable = intel_disable_dvo;
	intel_encoder->enable = intel_enable_dvo;
	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
	intel_encoder->get_config = intel_dvo_get_config;
	intel_encoder->compute_config = intel_dvo_compute_config;
	intel_encoder->pre_enable = intel_dvo_pre_enable;
	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;

	/* Now, try to find a controller */
	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
		struct drm_connector *connector = &intel_connector->base;
		const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
		struct i2c_adapter *i2c;
		int gpio;
		bool dvoinit;
		enum pipe pipe;
		u32 dpll[I915_MAX_PIPES];
		enum port port;

		/*
		 * Allow the I2C driver info to specify the GPIO to be used in
		 * special cases, but otherwise default to what's defined
		 * in the spec.
		 */
		if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
			gpio = dvo->gpio;
		else if (dvo->type == INTEL_DVO_CHIP_LVDS)
			gpio = GMBUS_PIN_SSC;
		else
			gpio = GMBUS_PIN_DPB;

		/*
		 * Set up the I2C bus necessary for the chip we're probing.
		 * It appears that everything is on GPIOE except for panels
		 * on i830 laptops, which are on GPIOB (DVOA).
		 */
		i2c = intel_gmbus_get_adapter(dev_priv, gpio);

		intel_dvo->dev = *dvo;

		/*
		 * GMBUS NAK handling seems to be unstable, hence let the
		 * transmitter detection run in bit banging mode for now.
		 */
		intel_gmbus_force_bit(i2c, true);

		/*
		 * ns2501 requires the DVO 2x clock before it will
		 * respond to i2c accesses, so make sure we have
		 * have the clock enabled before we attempt to
		 * initialize the device.
		 */
		for_each_pipe(dev_priv, pipe) {
			dpll[pipe] = I915_READ(DPLL(pipe));
			I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);
		}

		dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);

		/* restore the DVO 2x clock state to original */
		for_each_pipe(dev_priv, pipe) {
			I915_WRITE(DPLL(pipe), dpll[pipe]);
		}

		intel_gmbus_force_bit(i2c, false);

		if (!dvoinit)
			continue;

		port = intel_dvo_port(dvo->dvo_reg);
		drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
				 &intel_dvo_enc_funcs, encoder_type,
				 "DVO %c", port_name(port));

		intel_encoder->type = INTEL_OUTPUT_DVO;
		intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
		intel_encoder->port = port;
		intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B);

		switch (dvo->type) {
		case INTEL_DVO_CHIP_TMDS:
			intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) |
				(1 << INTEL_OUTPUT_DVO);
			drm_connector_init(&dev_priv->drm, connector,
					   &intel_dvo_connector_funcs,
					   DRM_MODE_CONNECTOR_DVII);
			encoder_type = DRM_MODE_ENCODER_TMDS;
			break;
		case INTEL_DVO_CHIP_LVDS:
			intel_encoder->cloneable = 0;
			drm_connector_init(&dev_priv->drm, connector,
					   &intel_dvo_connector_funcs,
					   DRM_MODE_CONNECTOR_LVDS);
			encoder_type = DRM_MODE_ENCODER_LVDS;
			break;
		}

		drm_connector_helper_add(connector,
					 &intel_dvo_connector_helper_funcs);
		connector->display_info.subpixel_order = SubPixelHorizontalRGB;
		connector->interlace_allowed = false;
		connector->doublescan_allowed = false;

		intel_connector_attach_encoder(intel_connector, intel_encoder);
		if (dvo->type == INTEL_DVO_CHIP_LVDS) {
			/*
			 * For our LVDS chipsets, we should hopefully be able
			 * to dig the fixed panel mode out of the BIOS data.
			 * However, it's in a different format from the BIOS
			 * data on chipsets with integrated LVDS (stored in AIM
			 * headers, likely), so for now, just get the current
			 * mode being output through DVO.
			 */
			intel_panel_init(&intel_connector->panel,
					 intel_dvo_get_current_mode(intel_encoder),
					 NULL);
			intel_dvo->panel_wants_dither = true;
		}

		return;
	}

	kfree(intel_dvo);
	kfree(intel_connector);
}
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright © 2006-2007 Intel Corporation
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Eric Anholt <eric@anholt.net>
	26	*/
ec7f29ff	27
79e53945	28	#include <linux/i2c.h>
5a0e3ad6	29	#include <linux/slab.h>
ec7f29ff	30
c6f95f27	31	#include <drm/drm_atomic_helper.h>
760285e7	32	#include <drm/drm_crtc.h>
760285e7	33	#include <drm/i915_drm.h>
ec7f29ff	34
ec7f29ff JN	35	#include "i915_drv.h"
ec7f29ff JN	36	#include "intel_connector.h"
1d455f8d	37	#include "intel_display_types.h"
75a4639a	38	#include "intel_dvo.h"
531747b8	39	#include "intel_dvo_dev.h"
3ce2ea65	40	#include "intel_gmbus.h"
44c1220a	41	#include "intel_panel.h"
79e53945	42
5ece881d JN	43	#define INTEL_DVO_CHIP_NONE 0
	44	#define INTEL_DVO_CHIP_LVDS 1
	45	#define INTEL_DVO_CHIP_TMDS 2
	46	#define INTEL_DVO_CHIP_TVOUT 4
	47
79e53945 JB	48	#define SIL164_ADDR 0x38
	49	#define CH7xxx_ADDR 0x76
	50	#define TFP410_ADDR 0x38
7434a255	51	#define NS2501_ADDR 0x38
79e53945	52
ea5b213a	53	static const struct intel_dvo_device intel_dvo_devices[] = {
79e53945 JB	54	{
	55	.type = INTEL_DVO_CHIP_TMDS,
	56	.name = "sil164",
	57	.dvo_reg = DVOC,
78e0d2e3	58	.dvo_srcdim_reg = DVOC_SRCDIM,
79e53945 JB	59	.slave_addr = SIL164_ADDR,
	60	.dev_ops = &sil164_ops,
	61	},
	62	{
	63	.type = INTEL_DVO_CHIP_TMDS,
	64	.name = "ch7xxx",
	65	.dvo_reg = DVOC,
78e0d2e3	66	.dvo_srcdim_reg = DVOC_SRCDIM,
79e53945 JB	67	.slave_addr = CH7xxx_ADDR,
	68	.dev_ops = &ch7xxx_ops,
	69	},
98304ad1	70	{
	71	.type = INTEL_DVO_CHIP_TMDS,
	72	.name = "ch7xxx",
	73	.dvo_reg = DVOC,
78e0d2e3	74	.dvo_srcdim_reg = DVOC_SRCDIM,
98304ad1	75	.slave_addr = 0x75, /* For some ch7010 */
	76	.dev_ops = &ch7xxx_ops,
	77	},
79e53945 JB	78	{
	79	.type = INTEL_DVO_CHIP_LVDS,
	80	.name = "ivch",
	81	.dvo_reg = DVOA,
78e0d2e3	82	.dvo_srcdim_reg = DVOA_SRCDIM,
79e53945 JB	83	.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
	84	.dev_ops = &ivch_ops,
	85	},
	86	{
	87	.type = INTEL_DVO_CHIP_TMDS,
	88	.name = "tfp410",
	89	.dvo_reg = DVOC,
78e0d2e3	90	.dvo_srcdim_reg = DVOC_SRCDIM,
79e53945 JB	91	.slave_addr = TFP410_ADDR,
	92	.dev_ops = &tfp410_ops,
	93	},
	94	{
	95	.type = INTEL_DVO_CHIP_LVDS,
	96	.name = "ch7017",
	97	.dvo_reg = DVOC,
78e0d2e3	98	.dvo_srcdim_reg = DVOC_SRCDIM,
79e53945	99	.slave_addr = 0x75,
988c7015	100	.gpio = GMBUS_PIN_DPB,
79e53945	101	.dev_ops = &ch7017_ops,
7434a255 TR	102	},
	103	{
	104	.type = INTEL_DVO_CHIP_TMDS,
	105	.name = "ns2501",
316e0157	106	.dvo_reg = DVOB,
78e0d2e3	107	.dvo_srcdim_reg = DVOB_SRCDIM,
7434a255 TR	108	.slave_addr = NS2501_ADDR,
	109	.dev_ops = &ns2501_ops,
	110	}
79e53945 JB	111	};
79e53945 JB	112
ea5b213a CW	113	struct intel_dvo {
	114	struct intel_encoder base;
	115
	116	struct intel_dvo_device dev;
	117
28694070 VS	118	struct intel_connector *attached_connector;
28694070 VS	119
ea5b213a CW	120	bool panel_wants_dither;
	121	};
	122
69438e64	123	static struct intel_dvo enc_to_dvo(struct intel_encoder encoder)
ea5b213a	124	{
69438e64	125	return container_of(encoder, struct intel_dvo, base);
ea5b213a CW	126	}
ea5b213a CW	127
df0e9248 CW	128	static struct intel_dvo intel_attached_dvo(struct drm_connector connector)
df0e9248 CW	129	{
79fde301	130	return enc_to_dvo(intel_attached_encoder(connector));
df0e9248 CW	131	}
df0e9248 CW	132
732ce74f	133	static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
79e53945	134	{
f417c11b	135	struct drm_device *dev = connector->base.dev;
fac5e23e	136	struct drm_i915_private *dev_priv = to_i915(dev);
732ce74f	137	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
f417c11b VS	138	u32 tmp;
	139
	140	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	141
	142	if (!(tmp & DVO_ENABLE))
	143	return false;
732ce74f DV	144
	145	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
	146	}
	147
	148	static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
	149	enum pipe *pipe)
	150	{
b45a2588	151	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
69438e64	152	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
732ce74f DV	153	u32 tmp;
	154
	155	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	156
b45a2588	157	*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
732ce74f	158
b45a2588	159	return tmp & DVO_ENABLE;
732ce74f DV	160	}
732ce74f DV	161
045ac3b5	162	static void intel_dvo_get_config(struct intel_encoder *encoder,
5cec258b	163	struct intel_crtc_state *pipe_config)
045ac3b5	164	{
fac5e23e	165	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
69438e64	166	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
045ac3b5 JB	167	u32 tmp, flags = 0;
045ac3b5 JB	168
e1214b95 VS	169	pipe_config->output_types \|= BIT(INTEL_OUTPUT_DVO);
e1214b95 VS	170
045ac3b5 JB	171	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	172	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
	173	flags \|= DRM_MODE_FLAG_PHSYNC;
	174	else
	175	flags \|= DRM_MODE_FLAG_NHSYNC;
	176	if (tmp & DVO_VSYNC_ACTIVE_HIGH)
	177	flags \|= DRM_MODE_FLAG_PVSYNC;
	178	else
	179	flags \|= DRM_MODE_FLAG_NVSYNC;
	180
2d112de7	181	pipe_config->base.adjusted_mode.flags \|= flags;
18442d08	182
2d112de7	183	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
045ac3b5 JB	184	}
045ac3b5 JB	185
fd6bbda9	186	static void intel_disable_dvo(struct intel_encoder *encoder,
5f88a9c6 VS	187	const struct intel_crtc_state *old_crtc_state,
5f88a9c6 VS	188	const struct drm_connector_state *old_conn_state)
19c63fa8	189	{
fac5e23e	190	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
69438e64	191	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
f0f59a00	192	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
19c63fa8 DV	193	u32 temp = I915_READ(dvo_reg);
	194
	195	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
	196	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
	197	I915_READ(dvo_reg);
	198	}
	199
fd6bbda9	200	static void intel_enable_dvo(struct intel_encoder *encoder,
5f88a9c6 VS	201	const struct intel_crtc_state *pipe_config,
5f88a9c6 VS	202	const struct drm_connector_state *conn_state)
19c63fa8	203	{
fac5e23e	204	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
69438e64	205	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
f0f59a00	206	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
79e53945 JB	207	u32 temp = I915_READ(dvo_reg);
79e53945 JB	208
48f34e10	209	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
ae9a911b ML	210	&pipe_config->base.mode,
ae9a911b ML	211	&pipe_config->base.adjusted_mode);
48f34e10	212
c9c054c2 VS	213	I915_WRITE(dvo_reg, temp \| DVO_ENABLE);
	214	I915_READ(dvo_reg);
	215
19c63fa8 DV	216	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
	217	}
	218
c19de8eb DL	219	static enum drm_mode_status
	220	intel_dvo_mode_valid(struct drm_connector *connector,
	221	struct drm_display_mode *mode)
79e53945	222	{
df0e9248	223	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
28694070 VS	224	const struct drm_display_mode *fixed_mode =
28694070 VS	225	to_intel_connector(connector)->panel.fixed_mode;
26a91555 MK	226	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
26a91555 MK	227	int target_clock = mode->clock;
79e53945	228
e4dd27aa VS	229	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	230	return MODE_NO_DBLESCAN;
	231
79e53945 JB	232	/* XXX: Validate clock range */
79e53945 JB	233
28694070 VS	234	if (fixed_mode) {
28694070 VS	235	if (mode->hdisplay > fixed_mode->hdisplay)
79e53945	236	return MODE_PANEL;
28694070	237	if (mode->vdisplay > fixed_mode->vdisplay)
79e53945	238	return MODE_PANEL;
26a91555	239
28694070	240	target_clock = fixed_mode->clock;
79e53945 JB	241	}
79e53945 JB	242
26a91555 MK	243	if (target_clock > max_dotclk)
	244	return MODE_CLOCK_HIGH;
	245
ea5b213a	246	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
79e53945 JB	247	}
79e53945 JB	248
204474a6 LP	249	static int intel_dvo_compute_config(struct intel_encoder *encoder,
	250	struct intel_crtc_state *pipe_config,
	251	struct drm_connector_state *conn_state)
79e53945	252	{
a3470375	253	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
28694070 VS	254	const struct drm_display_mode *fixed_mode =
28694070 VS	255	intel_dvo->attached_connector->panel.fixed_mode;
2d112de7	256	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
79e53945	257
d5fdd43f CW	258	/*
d5fdd43f CW	259	* If we have timings from the BIOS for the panel, put them in
79e53945 JB	260	* to the adjusted mode. The CRTC will be set up for this mode,
	261	* with the panel scaling set up to source from the H/VDisplay
	262	* of the original mode.
	263	*/
28694070 VS	264	if (fixed_mode)
28694070 VS	265	intel_fixed_panel_mode(fixed_mode, adjusted_mode);
79e53945	266
e4dd27aa	267	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
204474a6	268	return -EINVAL;
e4dd27aa	269
d9facae6	270	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
204474a6 LP	271
204474a6 LP	272	return 0;
79e53945 JB	273	}
79e53945 JB	274
fd6bbda9	275	static void intel_dvo_pre_enable(struct intel_encoder *encoder,
5f88a9c6 VS	276	const struct intel_crtc_state *pipe_config,
5f88a9c6 VS	277	const struct drm_connector_state *conn_state)
79e53945	278	{
ae9a911b ML	279	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	280	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
	281	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
79fde301	282	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
d048a268	283	enum pipe pipe = crtc->pipe;
79e53945	284	u32 dvo_val;
f0f59a00 VS	285	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
f0f59a00 VS	286	i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;
79e53945	287
79e53945 JB	288	/* Save the data order, since I don't know what it should be set to. */
	289	dvo_val = I915_READ(dvo_reg) &
	290	(DVO_PRESERVE_MASK \| DVO_DATA_ORDER_GBRG);
	291	dvo_val \|= DVO_DATA_ORDER_FP \| DVO_BORDER_ENABLE \|
	292	DVO_BLANK_ACTIVE_HIGH;
	293
b45a2588	294	dvo_val \|= DVO_PIPE_SEL(pipe);
79e53945 JB	295	dvo_val \|= DVO_PIPE_STALL;
	296	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	297	dvo_val \|= DVO_HSYNC_ACTIVE_HIGH;
	298	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	299	dvo_val \|= DVO_VSYNC_ACTIVE_HIGH;
	300
79e53945	301	/*I915_WRITE(DVOB_SRCDIM,
aad941d5 VS	302	(adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) \|
aad941d5 VS	303	(adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
79e53945	304	I915_WRITE(dvo_srcdim_reg,
aad941d5 VS	305	(adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) \|
aad941d5 VS	306	(adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
79e53945 JB	307	/I915_WRITE(DVOB, dvo_val);/
	308	I915_WRITE(dvo_reg, dvo_val);
	309	}
	310
7b334fcb	311	static enum drm_connector_status
930a9e28	312	intel_dvo_detect(struct drm_connector *connector, bool force)
79e53945	313	{
df0e9248	314	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
164c8598	315	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417	316	connector->base.id, connector->name);
ea5b213a	317	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
79e53945 JB	318	}
	319
	320	static int intel_dvo_get_modes(struct drm_connector *connector)
	321	{
fac5e23e	322	struct drm_i915_private *dev_priv = to_i915(connector->dev);
28694070 VS	323	const struct drm_display_mode *fixed_mode =
28694070 VS	324	to_intel_connector(connector)->panel.fixed_mode;
79e53945	325
d5fdd43f CW	326	/*
d5fdd43f CW	327	* We should probably have an i2c driver get_modes function for those
79e53945 JB	328	* devices which will have a fixed set of modes determined by the chip
	329	* (TV-out, for example), but for now with just TMDS and LVDS,
	330	* that's not the case.
	331	*/
f899fc64	332	intel_ddc_get_modes(connector,
988c7015	333	intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC));
79e53945 JB	334	if (!list_empty(&connector->probed_modes))
	335	return 1;
	336
28694070	337	if (fixed_mode) {
79e53945	338	struct drm_display_mode *mode;
28694070	339	mode = drm_mode_duplicate(connector->dev, fixed_mode);
79e53945 JB	340	if (mode) {
	341	drm_mode_probed_add(connector, mode);
	342	return 1;
	343	}
	344	}
ea5b213a	345
79e53945 JB	346	return 0;
	347	}
	348
79e53945	349	static const struct drm_connector_funcs intel_dvo_connector_funcs = {
79e53945	350	.detect = intel_dvo_detect,
1ebaa0b9	351	.late_register = intel_connector_register,
c191eca1	352	.early_unregister = intel_connector_unregister,
d4b26e4f	353	.destroy = intel_connector_destroy,
79e53945	354	.fill_modes = drm_helper_probe_single_connector_modes,
c6f95f27	355	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725	356	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
79e53945 JB	357	};
	358
	359	static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
	360	.mode_valid = intel_dvo_mode_valid,
	361	.get_modes = intel_dvo_get_modes,
79e53945 JB	362	};
79e53945 JB	363
b358d0a6	364	static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
79e53945	365	{
69438e64	366	struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));
ea5b213a CW	367
	368	if (intel_dvo->dev.dev_ops->destroy)
	369	intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);
	370
ea5b213a	371	intel_encoder_destroy(encoder);
79e53945 JB	372	}
	373
	374	static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
	375	.destroy = intel_dvo_enc_destroy,
	376	};
	377
d5fdd43f	378	/*
79e53945 JB	379	* Attempts to get a fixed panel timing for LVDS (currently only the i830).
	380	*
	381	* Other chips with DVO LVDS will need to extend this to deal with the LVDS
	382	* chip being on DVOB/C and having multiple pipes.
	383	*/
	384	static struct drm_display_mode *
de330815	385	intel_dvo_get_current_mode(struct intel_encoder *encoder)
79e53945	386	{
de330815	387	struct drm_display_mode *mode;
79e53945	388
de330815 VS	389	mode = intel_encoder_current_mode(encoder);
	390	if (mode) {
	391	DRM_DEBUG_KMS("using current (BIOS) mode: ");
	392	drm_mode_debug_printmodeline(mode);
	393	mode->type \|= DRM_MODE_TYPE_PREFERRED;
79e53945	394	}
ea5b213a	395
79e53945 JB	396	return mode;
	397	}
	398
5748be60	399	static enum port intel_dvo_port(i915_reg_t dvo_reg)
580d8ed5 VS	400	{
580d8ed5 VS	401	if (i915_mmio_reg_equal(dvo_reg, DVOA))
5748be60	402	return PORT_A;
580d8ed5	403	else if (i915_mmio_reg_equal(dvo_reg, DVOB))
5748be60	404	return PORT_B;
580d8ed5	405	else
5748be60	406	return PORT_C;
580d8ed5 VS	407	}
580d8ed5 VS	408
c39055b0	409	void intel_dvo_init(struct drm_i915_private *dev_priv)
79e53945	410	{
21d40d37	411	struct intel_encoder *intel_encoder;
ea5b213a	412	struct intel_dvo *intel_dvo;
599be16c	413	struct intel_connector *intel_connector;
79e53945	414	int i;
79e53945	415	int encoder_type = DRM_MODE_ENCODER_NONE;
ea5b213a	416
b14c5679	417	intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
ea5b213a	418	if (!intel_dvo)
79e53945 JB	419	return;
79e53945 JB	420
9bdbd0b9	421	intel_connector = intel_connector_alloc();
599be16c	422	if (!intel_connector) {
ea5b213a	423	kfree(intel_dvo);
599be16c ZW	424	return;
	425	}
	426
28694070 VS	427	intel_dvo->attached_connector = intel_connector;
28694070 VS	428
ea5b213a CW	429	intel_encoder = &intel_dvo->base;
ea5b213a CW	430
19c63fa8 DV	431	intel_encoder->disable = intel_disable_dvo;
19c63fa8 DV	432	intel_encoder->enable = intel_enable_dvo;
732ce74f	433	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
045ac3b5	434	intel_encoder->get_config = intel_dvo_get_config;
a3470375	435	intel_encoder->compute_config = intel_dvo_compute_config;
912b0e2d	436	intel_encoder->pre_enable = intel_dvo_pre_enable;
732ce74f	437	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
19c63fa8	438
79e53945 JB	439	/* Now, try to find a controller */
79e53945 JB	440	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
599be16c	441	struct drm_connector *connector = &intel_connector->base;
ea5b213a	442	const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
f899fc64	443	struct i2c_adapter *i2c;
79e53945	444	int gpio;
e4bfff54	445	bool dvoinit;
46509475	446	enum pipe pipe;
accb1eb5	447	u32 dpll[I915_MAX_PIPES];
5748be60	448	enum port port;
79e53945	449
d5fdd43f CW	450	/*
d5fdd43f CW	451	* Allow the I2C driver info to specify the GPIO to be used in
79e53945 JB	452	* special cases, but otherwise default to what's defined
	453	* in the spec.
	454	*/
88ac7939	455	if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
79e53945 JB	456	gpio = dvo->gpio;
79e53945 JB	457	else if (dvo->type == INTEL_DVO_CHIP_LVDS)
988c7015	458	gpio = GMBUS_PIN_SSC;
79e53945	459	else
988c7015	460	gpio = GMBUS_PIN_DPB;
79e53945	461
d5fdd43f CW	462	/*
d5fdd43f CW	463	* Set up the I2C bus necessary for the chip we're probing.
79e53945 JB	464	* It appears that everything is on GPIOE except for panels
	465	* on i830 laptops, which are on GPIOB (DVOA).
	466	*/
3bd7d909	467	i2c = intel_gmbus_get_adapter(dev_priv, gpio);
79e53945	468
ea5b213a	469	intel_dvo->dev = *dvo;
e4bfff54	470
d5fdd43f CW	471	/*
d5fdd43f CW	472	* GMBUS NAK handling seems to be unstable, hence let the
e4bfff54 DMEA	473	* transmitter detection run in bit banging mode for now.
	474	*/
	475	intel_gmbus_force_bit(i2c, true);
	476
d5fdd43f CW	477	/*
d5fdd43f CW	478	* ns2501 requires the DVO 2x clock before it will
46509475 VS	479	* respond to i2c accesses, so make sure we have
	480	* have the clock enabled before we attempt to
	481	* initialize the device.
	482	*/
	483	for_each_pipe(dev_priv, pipe) {
	484	dpll[pipe] = I915_READ(DPLL(pipe));
	485	I915_WRITE(DPLL(pipe), dpll[pipe] \| DPLL_DVO_2X_MODE);
	486	}
	487
e4bfff54 DMEA	488	dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);
e4bfff54 DMEA	489
46509475 VS	490	/* restore the DVO 2x clock state to original */
	491	for_each_pipe(dev_priv, pipe) {
	492	I915_WRITE(DPLL(pipe), dpll[pipe]);
	493	}
	494
e4bfff54 DMEA	495	intel_gmbus_force_bit(i2c, false);
	496
	497	if (!dvoinit)
79e53945 JB	498	continue;
79e53945 JB	499
5748be60	500	port = intel_dvo_port(dvo->dvo_reg);
c39055b0	501	drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
580d8ed5	502	&intel_dvo_enc_funcs, encoder_type,
5748be60	503	"DVO %c", port_name(port));
580d8ed5	504
21d40d37	505	intel_encoder->type = INTEL_OUTPUT_DVO;
79f255a0	506	intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4	507	intel_encoder->port = port;
0fbae9d2	508	intel_encoder->crtc_mask = BIT(PIPE_A) \| BIT(PIPE_B);
03cdc1d4	509
79e53945 JB	510	switch (dvo->type) {
79e53945 JB	511	case INTEL_DVO_CHIP_TMDS:
bc079e8b VS	512	intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) \|
bc079e8b VS	513	(1 << INTEL_OUTPUT_DVO);
c39055b0	514	drm_connector_init(&dev_priv->drm, connector,
79e53945 JB	515	&intel_dvo_connector_funcs,
	516	DRM_MODE_CONNECTOR_DVII);
	517	encoder_type = DRM_MODE_ENCODER_TMDS;
	518	break;
	519	case INTEL_DVO_CHIP_LVDS:
bc079e8b	520	intel_encoder->cloneable = 0;
c39055b0	521	drm_connector_init(&dev_priv->drm, connector,
79e53945 JB	522	&intel_dvo_connector_funcs,
	523	DRM_MODE_CONNECTOR_LVDS);
	524	encoder_type = DRM_MODE_ENCODER_LVDS;
	525	break;
	526	}
	527
	528	drm_connector_helper_add(connector,
	529	&intel_dvo_connector_helper_funcs);
	530	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
	531	connector->interlace_allowed = false;
	532	connector->doublescan_allowed = false;
	533
df0e9248	534	intel_connector_attach_encoder(intel_connector, intel_encoder);
79e53945	535	if (dvo->type == INTEL_DVO_CHIP_LVDS) {
d5fdd43f CW	536	/*
d5fdd43f CW	537	* For our LVDS chipsets, we should hopefully be able
79e53945 JB	538	* to dig the fixed panel mode out of the BIOS data.
	539	* However, it's in a different format from the BIOS
	540	* data on chipsets with integrated LVDS (stored in AIM
	541	* headers, likely), so for now, just get the current
	542	* mode being output through DVO.
	543	*/
28694070	544	intel_panel_init(&intel_connector->panel,
de330815	545	intel_dvo_get_current_mode(intel_encoder),
d93fa1b4	546	NULL);
ea5b213a	547	intel_dvo->panel_wants_dither = true;
79e53945 JB	548	}
79e53945 JB	549
79e53945 JB	550	return;
	551	}
	552
ea5b213a	553	kfree(intel_dvo);
599be16c	554	kfree(intel_connector);
79e53945	555	}