Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
d2ee2e8a | 30 | |
c6f95f27 | 31 | #include <drm/drm_atomic_helper.h> |
760285e7 | 32 | #include <drm/drm_crtc.h> |
760285e7 | 33 | #include <drm/drm_edid.h> |
fcd70cd3 | 34 | #include <drm/drm_probe_helper.h> |
760285e7 | 35 | #include <drm/i915_drm.h> |
d2ee2e8a | 36 | |
79e53945 | 37 | #include "i915_drv.h" |
ec7f29ff | 38 | #include "intel_connector.h" |
d2ee2e8a | 39 | #include "intel_crt.h" |
fdc24cf3 | 40 | #include "intel_ddi.h" |
1d455f8d | 41 | #include "intel_display_types.h" |
8834e365 | 42 | #include "intel_fifo_underrun.h" |
3ce2ea65 | 43 | #include "intel_gmbus.h" |
dbeb38d9 | 44 | #include "intel_hotplug.h" |
79e53945 | 45 | |
e7dbb2f2 KP |
46 | /* Here's the desired hotplug mode */ |
47 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
48 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
49 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
50 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
51 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
52 | ADPA_CRT_HOTPLUG_ENABLE) | |
53 | ||
c9a1c4cd CW |
54 | struct intel_crt { |
55 | struct intel_encoder base; | |
637f44d2 AJ |
56 | /* DPMS state is stored in the connector, which we need in the |
57 | * encoder's enable/disable callbacks */ | |
58 | struct intel_connector *connector; | |
e7dbb2f2 | 59 | bool force_hotplug_required; |
f0f59a00 | 60 | i915_reg_t adpa_reg; |
c9a1c4cd CW |
61 | }; |
62 | ||
eebe6f0b | 63 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 64 | { |
eebe6f0b | 65 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
66 | } |
67 | ||
eebe6f0b | 68 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
79e53945 | 69 | { |
eebe6f0b | 70 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 DV |
71 | } |
72 | ||
6102a8ee VS |
73 | bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, |
74 | i915_reg_t adpa_reg, enum pipe *pipe) | |
75 | { | |
76 | u32 val; | |
77 | ||
78 | val = I915_READ(adpa_reg); | |
79 | ||
80 | /* asserts want to know the pipe even if the port is disabled */ | |
81 | if (HAS_PCH_CPT(dev_priv)) | |
82 | *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT; | |
83 | else | |
84 | *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT; | |
85 | ||
86 | return val & ADPA_DAC_ENABLE; | |
87 | } | |
88 | ||
e403fc94 DV |
89 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
90 | enum pipe *pipe) | |
79e53945 | 91 | { |
6102a8ee | 92 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e403fc94 | 93 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
0e6e0be4 | 94 | intel_wakeref_t wakeref; |
1c8fdda1 | 95 | bool ret; |
e403fc94 | 96 | |
0e6e0be4 CW |
97 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
98 | encoder->power_domain); | |
99 | if (!wakeref) | |
6d129bea ID |
100 | return false; |
101 | ||
6102a8ee | 102 | ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); |
e403fc94 | 103 | |
0e6e0be4 | 104 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
1c8fdda1 ID |
105 | |
106 | return ret; | |
e403fc94 DV |
107 | } |
108 | ||
6801c18c | 109 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
045ac3b5 | 110 | { |
fac5e23e | 111 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
045ac3b5 JB |
112 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
113 | u32 tmp, flags = 0; | |
114 | ||
115 | tmp = I915_READ(crt->adpa_reg); | |
116 | ||
117 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
118 | flags |= DRM_MODE_FLAG_PHSYNC; | |
119 | else | |
120 | flags |= DRM_MODE_FLAG_NHSYNC; | |
121 | ||
122 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
123 | flags |= DRM_MODE_FLAG_PVSYNC; | |
124 | else | |
125 | flags |= DRM_MODE_FLAG_NVSYNC; | |
126 | ||
6801c18c VS |
127 | return flags; |
128 | } | |
129 | ||
130 | static void intel_crt_get_config(struct intel_encoder *encoder, | |
5cec258b | 131 | struct intel_crtc_state *pipe_config) |
6801c18c | 132 | { |
e1214b95 VS |
133 | pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); |
134 | ||
2d112de7 | 135 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
18442d08 | 136 | |
e3b247da | 137 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
045ac3b5 JB |
138 | } |
139 | ||
6801c18c | 140 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
5cec258b | 141 | struct intel_crtc_state *pipe_config) |
6801c18c | 142 | { |
8802e5b6 VS |
143 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
144 | ||
6801c18c VS |
145 | intel_ddi_get_config(encoder, pipe_config); |
146 | ||
2d112de7 | 147 | pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
6801c18c VS |
148 | DRM_MODE_FLAG_NHSYNC | |
149 | DRM_MODE_FLAG_PVSYNC | | |
150 | DRM_MODE_FLAG_NVSYNC); | |
2d112de7 | 151 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
8802e5b6 VS |
152 | |
153 | pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); | |
6801c18c VS |
154 | } |
155 | ||
b2cabb0e DV |
156 | /* Note: The caller is required to filter out dpms modes not supported by the |
157 | * platform. */ | |
225cc348 | 158 | static void intel_crt_set_dpms(struct intel_encoder *encoder, |
5f88a9c6 | 159 | const struct intel_crtc_state *crtc_state, |
225cc348 | 160 | int mode) |
df0323c4 | 161 | { |
66478475 | 162 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b2cabb0e | 163 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
225cc348 ML |
164 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
165 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; | |
894ed1ec DV |
166 | u32 adpa; |
167 | ||
66478475 | 168 | if (INTEL_GEN(dev_priv) >= 5) |
894ed1ec DV |
169 | adpa = ADPA_HOTPLUG_BITS; |
170 | else | |
171 | adpa = 0; | |
df0323c4 | 172 | |
894ed1ec DV |
173 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
174 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
175 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
176 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
177 | ||
178 | /* For CPT allow 3 pipe config, for others just use A or B */ | |
6e266956 | 179 | if (HAS_PCH_LPT(dev_priv)) |
894ed1ec | 180 | ; /* Those bits don't exist here */ |
6e266956 | 181 | else if (HAS_PCH_CPT(dev_priv)) |
6102a8ee | 182 | adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); |
894ed1ec | 183 | else |
6102a8ee | 184 | adpa |= ADPA_PIPE_SEL(crtc->pipe); |
894ed1ec | 185 | |
6e266956 | 186 | if (!HAS_PCH_SPLIT(dev_priv)) |
894ed1ec | 187 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
79e53945 | 188 | |
0206e353 | 189 | switch (mode) { |
79e53945 | 190 | case DRM_MODE_DPMS_ON: |
894ed1ec | 191 | adpa |= ADPA_DAC_ENABLE; |
79e53945 JB |
192 | break; |
193 | case DRM_MODE_DPMS_STANDBY: | |
894ed1ec | 194 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
79e53945 JB |
195 | break; |
196 | case DRM_MODE_DPMS_SUSPEND: | |
894ed1ec | 197 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
198 | break; |
199 | case DRM_MODE_DPMS_OFF: | |
894ed1ec | 200 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
201 | break; |
202 | } | |
203 | ||
894ed1ec | 204 | I915_WRITE(crt->adpa_reg, adpa); |
df0323c4 | 205 | } |
2c07245f | 206 | |
fd6bbda9 | 207 | static void intel_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
208 | const struct intel_crtc_state *old_crtc_state, |
209 | const struct drm_connector_state *old_conn_state) | |
637f44d2 | 210 | { |
225cc348 | 211 | intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); |
637f44d2 AJ |
212 | } |
213 | ||
fd6bbda9 | 214 | static void pch_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
215 | const struct intel_crtc_state *old_crtc_state, |
216 | const struct drm_connector_state *old_conn_state) | |
1ea56e26 VS |
217 | { |
218 | } | |
219 | ||
fd6bbda9 | 220 | static void pch_post_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
221 | const struct intel_crtc_state *old_crtc_state, |
222 | const struct drm_connector_state *old_conn_state) | |
1ea56e26 | 223 | { |
fd6bbda9 | 224 | intel_disable_crt(encoder, old_crtc_state, old_conn_state); |
1ea56e26 | 225 | } |
abfdc1e3 | 226 | |
3daa3cee JN |
227 | static void hsw_disable_crt(struct intel_encoder *encoder, |
228 | const struct intel_crtc_state *old_crtc_state, | |
229 | const struct drm_connector_state *old_conn_state) | |
230 | { | |
c249f1f4 | 231 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3daa3cee | 232 | |
c249f1f4 | 233 | WARN_ON(!old_crtc_state->has_pch_encoder); |
3daa3cee JN |
234 | |
235 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
236 | } | |
237 | ||
b7076546 | 238 | static void hsw_post_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
239 | const struct intel_crtc_state *old_crtc_state, |
240 | const struct drm_connector_state *old_conn_state) | |
b7076546 ML |
241 | { |
242 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
243 | ||
afb2c443 ID |
244 | intel_ddi_disable_pipe_clock(old_crtc_state); |
245 | ||
b7076546 ML |
246 | pch_post_disable_crt(encoder, old_crtc_state, old_conn_state); |
247 | ||
248 | lpt_disable_pch_transcoder(dev_priv); | |
249 | lpt_disable_iclkip(dev_priv); | |
250 | ||
251 | intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state); | |
3daa3cee JN |
252 | |
253 | WARN_ON(!old_crtc_state->has_pch_encoder); | |
254 | ||
255 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
b7076546 ML |
256 | } |
257 | ||
51c4fa69 | 258 | static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder, |
c249f1f4 | 259 | const struct intel_crtc_state *crtc_state, |
51c4fa69 JN |
260 | const struct drm_connector_state *conn_state) |
261 | { | |
c249f1f4 | 262 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
51c4fa69 | 263 | |
c249f1f4 | 264 | WARN_ON(!crtc_state->has_pch_encoder); |
51c4fa69 JN |
265 | |
266 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
267 | } | |
268 | ||
269 | static void hsw_pre_enable_crt(struct intel_encoder *encoder, | |
c249f1f4 | 270 | const struct intel_crtc_state *crtc_state, |
51c4fa69 JN |
271 | const struct drm_connector_state *conn_state) |
272 | { | |
c249f1f4 VS |
273 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
274 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
275 | enum pipe pipe = crtc->pipe; | |
51c4fa69 | 276 | |
c249f1f4 | 277 | WARN_ON(!crtc_state->has_pch_encoder); |
51c4fa69 JN |
278 | |
279 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
27d81c28 | 280 | |
c249f1f4 | 281 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
afb2c443 ID |
282 | |
283 | intel_ddi_enable_pipe_clock(crtc_state); | |
51c4fa69 JN |
284 | } |
285 | ||
286 | static void hsw_enable_crt(struct intel_encoder *encoder, | |
c249f1f4 | 287 | const struct intel_crtc_state *crtc_state, |
51c4fa69 JN |
288 | const struct drm_connector_state *conn_state) |
289 | { | |
c249f1f4 VS |
290 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
291 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
292 | enum pipe pipe = crtc->pipe; | |
51c4fa69 | 293 | |
c249f1f4 | 294 | WARN_ON(!crtc_state->has_pch_encoder); |
51c4fa69 | 295 | |
c249f1f4 | 296 | intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); |
51c4fa69 JN |
297 | |
298 | intel_wait_for_vblank(dev_priv, pipe); | |
299 | intel_wait_for_vblank(dev_priv, pipe); | |
300 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
301 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
302 | } | |
303 | ||
fd6bbda9 | 304 | static void intel_enable_crt(struct intel_encoder *encoder, |
c249f1f4 | 305 | const struct intel_crtc_state *crtc_state, |
5f88a9c6 | 306 | const struct drm_connector_state *conn_state) |
637f44d2 | 307 | { |
c249f1f4 | 308 | intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); |
637f44d2 AJ |
309 | } |
310 | ||
c19de8eb DL |
311 | static enum drm_mode_status |
312 | intel_crt_mode_valid(struct drm_connector *connector, | |
313 | struct drm_display_mode *mode) | |
79e53945 | 314 | { |
6bcdcd9e | 315 | struct drm_device *dev = connector->dev; |
6e266956 TU |
316 | struct drm_i915_private *dev_priv = to_i915(dev); |
317 | int max_dotclk = dev_priv->max_dotclk_freq; | |
debded84 | 318 | int max_clock; |
6bcdcd9e | 319 | |
e4dd27aa VS |
320 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
321 | return MODE_NO_DBLESCAN; | |
322 | ||
6bcdcd9e ZY |
323 | if (mode->clock < 25000) |
324 | return MODE_CLOCK_LOW; | |
325 | ||
6e266956 | 326 | if (HAS_PCH_LPT(dev_priv)) |
debded84 | 327 | max_clock = 180000; |
11a914c2 | 328 | else if (IS_VALLEYVIEW(dev_priv)) |
debded84 VS |
329 | /* |
330 | * 270 MHz due to current DPLL limits, | |
331 | * DAC limit supposedly 355 MHz. | |
332 | */ | |
333 | max_clock = 270000; | |
f3ce44a0 | 334 | else if (IS_GEN_RANGE(dev_priv, 3, 4)) |
6bcdcd9e | 335 | max_clock = 400000; |
debded84 VS |
336 | else |
337 | max_clock = 350000; | |
6bcdcd9e ZY |
338 | if (mode->clock > max_clock) |
339 | return MODE_CLOCK_HIGH; | |
79e53945 | 340 | |
f8700b34 MK |
341 | if (mode->clock > max_dotclk) |
342 | return MODE_CLOCK_HIGH; | |
343 | ||
d4b1931c | 344 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
6e266956 | 345 | if (HAS_PCH_LPT(dev_priv) && |
d4b1931c PZ |
346 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
347 | return MODE_CLOCK_HIGH; | |
348 | ||
ad193bc6 VS |
349 | /* HSW/BDW FDI limited to 4k */ |
350 | if (mode->hdisplay > 4096) | |
351 | return MODE_H_ILLEGAL; | |
352 | ||
79e53945 JB |
353 | return MODE_OK; |
354 | } | |
355 | ||
204474a6 LP |
356 | static int intel_crt_compute_config(struct intel_encoder *encoder, |
357 | struct intel_crtc_state *pipe_config, | |
358 | struct drm_connector_state *conn_state) | |
2f26cdc0 | 359 | { |
e4dd27aa VS |
360 | struct drm_display_mode *adjusted_mode = |
361 | &pipe_config->base.adjusted_mode; | |
362 | ||
363 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
204474a6 | 364 | return -EINVAL; |
e4dd27aa | 365 | |
d9facae6 | 366 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
204474a6 LP |
367 | |
368 | return 0; | |
2f26cdc0 JN |
369 | } |
370 | ||
204474a6 LP |
371 | static int pch_crt_compute_config(struct intel_encoder *encoder, |
372 | struct intel_crtc_state *pipe_config, | |
373 | struct drm_connector_state *conn_state) | |
2f26cdc0 | 374 | { |
e4dd27aa VS |
375 | struct drm_display_mode *adjusted_mode = |
376 | &pipe_config->base.adjusted_mode; | |
377 | ||
378 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
204474a6 | 379 | return -EINVAL; |
e4dd27aa | 380 | |
2f26cdc0 | 381 | pipe_config->has_pch_encoder = true; |
d9facae6 | 382 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
2f26cdc0 | 383 | |
204474a6 | 384 | return 0; |
2f26cdc0 JN |
385 | } |
386 | ||
204474a6 LP |
387 | static int hsw_crt_compute_config(struct intel_encoder *encoder, |
388 | struct intel_crtc_state *pipe_config, | |
389 | struct drm_connector_state *conn_state) | |
79e53945 | 390 | { |
4f8036a2 | 391 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e4dd27aa VS |
392 | struct drm_display_mode *adjusted_mode = |
393 | &pipe_config->base.adjusted_mode; | |
394 | ||
395 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
204474a6 | 396 | return -EINVAL; |
5bfe2ac0 | 397 | |
ad193bc6 VS |
398 | /* HSW/BDW FDI limited to 4k */ |
399 | if (adjusted_mode->crtc_hdisplay > 4096 || | |
400 | adjusted_mode->crtc_hblank_start > 4096) | |
204474a6 | 401 | return -EINVAL; |
ad193bc6 | 402 | |
2f26cdc0 | 403 | pipe_config->has_pch_encoder = true; |
d9facae6 | 404 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
5bfe2ac0 | 405 | |
2a7aceec | 406 | /* LPT FDI RX only supports 8bpc. */ |
4f8036a2 | 407 | if (HAS_PCH_LPT(dev_priv)) { |
f58a1acc DV |
408 | if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { |
409 | DRM_DEBUG_KMS("LPT only supports 24bpp\n"); | |
204474a6 | 410 | return -EINVAL; |
f58a1acc DV |
411 | } |
412 | ||
2a7aceec | 413 | pipe_config->pipe_bpp = 24; |
f58a1acc | 414 | } |
2a7aceec | 415 | |
8f7abfd8 | 416 | /* FDI must always be 2.7 GHz */ |
2f26cdc0 | 417 | pipe_config->port_clock = 135000 * 2; |
00490c22 | 418 | |
204474a6 | 419 | return 0; |
79e53945 JB |
420 | } |
421 | ||
f2b115e6 | 422 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
423 | { |
424 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 425 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 426 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7dbb2f2 | 427 | u32 adpa; |
2c07245f ZW |
428 | bool ret; |
429 | ||
e7dbb2f2 KP |
430 | /* The first time through, trigger an explicit detection cycle */ |
431 | if (crt->force_hotplug_required) { | |
6e266956 | 432 | bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); |
e7dbb2f2 | 433 | u32 save_adpa; |
67941da2 | 434 | |
e7dbb2f2 KP |
435 | crt->force_hotplug_required = 0; |
436 | ||
ca54b810 | 437 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
438 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
439 | ||
440 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
441 | if (turn_off_dac) | |
442 | adpa &= ~ADPA_DAC_ENABLE; | |
443 | ||
ca54b810 | 444 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 445 | |
4cb3b44d | 446 | if (intel_de_wait_for_clear(dev_priv, |
e1672d1c | 447 | crt->adpa_reg, |
4cb3b44d | 448 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER, |
e1672d1c | 449 | 1000)) |
e7dbb2f2 KP |
450 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
451 | ||
452 | if (turn_off_dac) { | |
ca54b810 VS |
453 | I915_WRITE(crt->adpa_reg, save_adpa); |
454 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 455 | } |
a4a6b901 ZW |
456 | } |
457 | ||
2c07245f | 458 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 459 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 460 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
461 | ret = true; |
462 | else | |
463 | ret = false; | |
e7dbb2f2 | 464 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 465 | |
2c07245f | 466 | return ret; |
79e53945 JB |
467 | } |
468 | ||
7d2c24e8 JB |
469 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
470 | { | |
471 | struct drm_device *dev = connector->dev; | |
ca54b810 | 472 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 473 | struct drm_i915_private *dev_priv = to_i915(dev); |
b236d7c8 | 474 | bool reenable_hpd; |
7d2c24e8 JB |
475 | u32 adpa; |
476 | bool ret; | |
477 | u32 save_adpa; | |
478 | ||
b236d7c8 L |
479 | /* |
480 | * Doing a force trigger causes a hpd interrupt to get sent, which can | |
481 | * get us stuck in a loop if we're polling: | |
482 | * - We enable power wells and reset the ADPA | |
483 | * - output_poll_exec does force probe on VGA, triggering a hpd | |
484 | * - HPD handler waits for poll to unlock dev->mode_config.mutex | |
485 | * - output_poll_exec shuts off the ADPA, unlocks | |
486 | * dev->mode_config.mutex | |
487 | * - HPD handler runs, resets ADPA and brings us back to the start | |
488 | * | |
489 | * Just disable HPD interrupts here to prevent this | |
490 | */ | |
491 | reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); | |
492 | ||
ca54b810 | 493 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
494 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
495 | ||
496 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
497 | ||
ca54b810 | 498 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 499 | |
4cb3b44d DCS |
500 | if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, |
501 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) { | |
7d2c24e8 | 502 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
ca54b810 | 503 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
504 | } |
505 | ||
506 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 507 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
508 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
509 | ret = true; | |
510 | else | |
511 | ret = false; | |
512 | ||
513 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
514 | ||
b236d7c8 L |
515 | if (reenable_hpd) |
516 | intel_hpd_enable(dev_priv, crt->base.hpd_pin); | |
517 | ||
7d2c24e8 JB |
518 | return ret; |
519 | } | |
520 | ||
79e53945 JB |
521 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
522 | { | |
523 | struct drm_device *dev = connector->dev; | |
fac5e23e | 524 | struct drm_i915_private *dev_priv = to_i915(dev); |
0706f17c | 525 | u32 stat; |
7a772c49 | 526 | bool ret = false; |
771cb081 | 527 | int i, tries = 0; |
2c07245f | 528 | |
6e266956 | 529 | if (HAS_PCH_SPLIT(dev_priv)) |
f2b115e6 | 530 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 531 | |
11a914c2 | 532 | if (IS_VALLEYVIEW(dev_priv)) |
7d2c24e8 JB |
533 | return valleyview_crt_detect_hotplug(connector); |
534 | ||
771cb081 ZY |
535 | /* |
536 | * On 4 series desktop, CRT detect sequence need to be done twice | |
537 | * to get a reliable result. | |
538 | */ | |
79e53945 | 539 | |
1c0f1b3d | 540 | if (IS_G45(dev_priv)) |
771cb081 ZY |
541 | tries = 2; |
542 | else | |
543 | tries = 1; | |
771cb081 | 544 | |
771cb081 | 545 | for (i = 0; i < tries ; i++) { |
771cb081 | 546 | /* turn on the FORCE_DETECT */ |
0706f17c EE |
547 | i915_hotplug_interrupt_update(dev_priv, |
548 | CRT_HOTPLUG_FORCE_DETECT, | |
549 | CRT_HOTPLUG_FORCE_DETECT); | |
771cb081 | 550 | /* wait for FORCE_DETECT to go off */ |
4cb3b44d DCS |
551 | if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN, |
552 | CRT_HOTPLUG_FORCE_DETECT, 1000)) | |
79077319 | 553 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 554 | } |
79e53945 | 555 | |
7a772c49 AJ |
556 | stat = I915_READ(PORT_HOTPLUG_STAT); |
557 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
558 | ret = true; | |
559 | ||
560 | /* clear the interrupt we just generated, if any */ | |
561 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 562 | |
0706f17c | 563 | i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); |
7a772c49 AJ |
564 | |
565 | return ret; | |
79e53945 JB |
566 | } |
567 | ||
f1a2f5b7 JN |
568 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
569 | struct i2c_adapter *i2c) | |
570 | { | |
571 | struct edid *edid; | |
572 | ||
573 | edid = drm_get_edid(connector, i2c); | |
574 | ||
575 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
576 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
577 | intel_gmbus_force_bit(i2c, true); | |
578 | edid = drm_get_edid(connector, i2c); | |
579 | intel_gmbus_force_bit(i2c, false); | |
580 | } | |
581 | ||
582 | return edid; | |
583 | } | |
584 | ||
585 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
586 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
587 | struct i2c_adapter *adapter) | |
588 | { | |
589 | struct edid *edid; | |
ebda95a9 | 590 | int ret; |
f1a2f5b7 JN |
591 | |
592 | edid = intel_crt_get_edid(connector, adapter); | |
593 | if (!edid) | |
594 | return 0; | |
595 | ||
ebda95a9 JN |
596 | ret = intel_connector_update_modes(connector, edid); |
597 | kfree(edid); | |
598 | ||
599 | return ret; | |
f1a2f5b7 JN |
600 | } |
601 | ||
f5afcd3d | 602 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 603 | { |
f5afcd3d | 604 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 605 | struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); |
a2bd1f54 DV |
606 | struct edid *edid; |
607 | struct i2c_adapter *i2c; | |
c96b63a6 | 608 | bool ret = false; |
79e53945 | 609 | |
a2bd1f54 | 610 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 611 | |
41aa3448 | 612 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 613 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 DV |
614 | |
615 | if (edid) { | |
616 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 617 | |
f5afcd3d DM |
618 | /* |
619 | * This may be a DVI-I connector with a shared DDC | |
620 | * link between analog and digital outputs, so we | |
621 | * have to check the EDID input spec of the attached device. | |
622 | */ | |
f5afcd3d DM |
623 | if (!is_digital) { |
624 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
c96b63a6 ACO |
625 | ret = true; |
626 | } else { | |
627 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
f5afcd3d | 628 | } |
a2bd1f54 DV |
629 | } else { |
630 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
631 | } |
632 | ||
a2bd1f54 DV |
633 | kfree(edid); |
634 | ||
c96b63a6 | 635 | return ret; |
79e53945 JB |
636 | } |
637 | ||
e4a5d54f | 638 | static enum drm_connector_status |
c7cc5216 | 639 | intel_crt_load_detect(struct intel_crt *crt, u32 pipe) |
e4a5d54f | 640 | { |
7173188d | 641 | struct drm_device *dev = crt->base.base.dev; |
fac5e23e | 642 | struct drm_i915_private *dev_priv = to_i915(dev); |
c54f0bac | 643 | struct intel_uncore *uncore = &dev_priv->uncore; |
c7cc5216 JN |
644 | u32 save_bclrpat; |
645 | u32 save_vtotal; | |
646 | u32 vtotal, vactive; | |
647 | u32 vsample; | |
648 | u32 vblank, vblank_start, vblank_end; | |
649 | u32 dsl; | |
f0f59a00 VS |
650 | i915_reg_t bclrpat_reg, vtotal_reg, |
651 | vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; | |
c7cc5216 | 652 | u8 st00; |
e4a5d54f ML |
653 | enum drm_connector_status status; |
654 | ||
6ec3d0c0 CW |
655 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
656 | ||
9db4a9c7 JB |
657 | bclrpat_reg = BCLRPAT(pipe); |
658 | vtotal_reg = VTOTAL(pipe); | |
659 | vblank_reg = VBLANK(pipe); | |
660 | vsync_reg = VSYNC(pipe); | |
661 | pipeconf_reg = PIPECONF(pipe); | |
662 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f | 663 | |
c54f0bac TU |
664 | save_bclrpat = intel_uncore_read(uncore, bclrpat_reg); |
665 | save_vtotal = intel_uncore_read(uncore, vtotal_reg); | |
666 | vblank = intel_uncore_read(uncore, vblank_reg); | |
e4a5d54f ML |
667 | |
668 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
669 | vactive = (save_vtotal & 0x7ff) + 1; | |
670 | ||
671 | vblank_start = (vblank & 0xfff) + 1; | |
672 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
673 | ||
674 | /* Set the border color to purple. */ | |
c54f0bac | 675 | intel_uncore_write(uncore, bclrpat_reg, 0x500050); |
e4a5d54f | 676 | |
cf819eff | 677 | if (!IS_GEN(dev_priv, 2)) { |
c54f0bac TU |
678 | u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg); |
679 | intel_uncore_write(uncore, | |
680 | pipeconf_reg, | |
681 | pipeconf | PIPECONF_FORCE_BORDER); | |
682 | intel_uncore_posting_read(uncore, pipeconf_reg); | |
e4a5d54f ML |
683 | /* Wait for next Vblank to substitue |
684 | * border color for Color info */ | |
0f0f74bc | 685 | intel_wait_for_vblank(dev_priv, pipe); |
c54f0bac | 686 | st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE); |
e4a5d54f ML |
687 | status = ((st00 & (1 << 4)) != 0) ? |
688 | connector_status_connected : | |
689 | connector_status_disconnected; | |
690 | ||
c54f0bac | 691 | intel_uncore_write(uncore, pipeconf_reg, pipeconf); |
e4a5d54f ML |
692 | } else { |
693 | bool restore_vblank = false; | |
694 | int count, detect; | |
695 | ||
696 | /* | |
697 | * If there isn't any border, add some. | |
698 | * Yes, this will flicker | |
699 | */ | |
700 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
c7cc5216 JN |
701 | u32 vsync = I915_READ(vsync_reg); |
702 | u32 vsync_start = (vsync & 0xffff) + 1; | |
e4a5d54f ML |
703 | |
704 | vblank_start = vsync_start; | |
c54f0bac TU |
705 | intel_uncore_write(uncore, |
706 | vblank_reg, | |
707 | (vblank_start - 1) | | |
708 | ((vblank_end - 1) << 16)); | |
e4a5d54f ML |
709 | restore_vblank = true; |
710 | } | |
711 | /* sample in the vertical border, selecting the larger one */ | |
712 | if (vblank_start - vactive >= vtotal - vblank_end) | |
713 | vsample = (vblank_start + vactive) >> 1; | |
714 | else | |
715 | vsample = (vtotal + vblank_end) >> 1; | |
716 | ||
717 | /* | |
718 | * Wait for the border to be displayed | |
719 | */ | |
c54f0bac | 720 | while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive) |
e4a5d54f | 721 | ; |
c54f0bac TU |
722 | while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <= |
723 | vsample) | |
e4a5d54f ML |
724 | ; |
725 | /* | |
726 | * Watch ST00 for an entire scanline | |
727 | */ | |
728 | detect = 0; | |
729 | count = 0; | |
730 | do { | |
731 | count++; | |
732 | /* Read the ST00 VGA status register */ | |
c54f0bac | 733 | st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE); |
e4a5d54f ML |
734 | if (st00 & (1 << 4)) |
735 | detect++; | |
c54f0bac | 736 | } while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl)); |
e4a5d54f ML |
737 | |
738 | /* restore vblank if necessary */ | |
739 | if (restore_vblank) | |
c54f0bac | 740 | intel_uncore_write(uncore, vblank_reg, vblank); |
e4a5d54f ML |
741 | /* |
742 | * If more than 3/4 of the scanline detected a monitor, | |
743 | * then it is assumed to be present. This works even on i830, | |
744 | * where there isn't any way to force the border color across | |
745 | * the screen | |
746 | */ | |
747 | status = detect * 4 > count * 3 ? | |
748 | connector_status_connected : | |
749 | connector_status_disconnected; | |
750 | } | |
751 | ||
752 | /* Restore previous settings */ | |
c54f0bac | 753 | intel_uncore_write(uncore, bclrpat_reg, save_bclrpat); |
e4a5d54f ML |
754 | |
755 | return status; | |
756 | } | |
757 | ||
f0dfb1a8 VS |
758 | static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) |
759 | { | |
760 | DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); | |
761 | return 1; | |
762 | } | |
763 | ||
764 | static const struct dmi_system_id intel_spurious_crt_detect[] = { | |
765 | { | |
766 | .callback = intel_spurious_crt_detect_dmi_callback, | |
767 | .ident = "ACER ZGB", | |
768 | .matches = { | |
769 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
770 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
771 | }, | |
772 | }, | |
69a44b16 VS |
773 | { |
774 | .callback = intel_spurious_crt_detect_dmi_callback, | |
775 | .ident = "Intel DZ77BH-55K", | |
776 | .matches = { | |
777 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), | |
778 | DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), | |
779 | }, | |
780 | }, | |
f0dfb1a8 VS |
781 | { } |
782 | }; | |
783 | ||
6c5ed5ae ML |
784 | static int |
785 | intel_crt_detect(struct drm_connector *connector, | |
786 | struct drm_modeset_acquire_ctx *ctx, | |
787 | bool force) | |
79e53945 | 788 | { |
66478475 | 789 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
c9a1c4cd | 790 | struct intel_crt *crt = intel_attached_crt(connector); |
671dedd2 | 791 | struct intel_encoder *intel_encoder = &crt->base; |
0e6e0be4 | 792 | intel_wakeref_t wakeref; |
6c5ed5ae | 793 | int status, ret; |
e95c8438 | 794 | struct intel_load_detect_pipe tmp; |
79e53945 | 795 | |
164c8598 | 796 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
c23cc417 | 797 | connector->base.id, connector->name, |
164c8598 CW |
798 | force); |
799 | ||
4165791d | 800 | if (i915_modparams.load_detect_test) { |
0e6e0be4 CW |
801 | wakeref = intel_display_power_get(dev_priv, |
802 | intel_encoder->power_domain); | |
4165791d VS |
803 | goto load_detect; |
804 | } | |
805 | ||
f0dfb1a8 VS |
806 | /* Skip machines without VGA that falsely report hotplug events */ |
807 | if (dmi_check_system(intel_spurious_crt_detect)) | |
808 | return connector_status_disconnected; | |
809 | ||
0e6e0be4 CW |
810 | wakeref = intel_display_power_get(dev_priv, |
811 | intel_encoder->power_domain); | |
671dedd2 | 812 | |
56b857a5 | 813 | if (I915_HAS_HOTPLUG(dev_priv)) { |
aaa37730 DV |
814 | /* We can not rely on the HPD pin always being correctly wired |
815 | * up, for example many KVM do not pass it through, and so | |
816 | * only trust an assertion that the monitor is connected. | |
817 | */ | |
6ec3d0c0 CW |
818 | if (intel_crt_detect_hotplug(connector)) { |
819 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
c19a0df2 PZ |
820 | status = connector_status_connected; |
821 | goto out; | |
aaa37730 | 822 | } else |
e7dbb2f2 | 823 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
824 | } |
825 | ||
c19a0df2 PZ |
826 | if (intel_crt_detect_ddc(connector)) { |
827 | status = connector_status_connected; | |
828 | goto out; | |
829 | } | |
79e53945 | 830 | |
aaa37730 DV |
831 | /* Load detection is broken on HPD capable machines. Whoever wants a |
832 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
833 | * to have the right resistors for HP detection) needs to fix this up. | |
834 | * For now just bail out. */ | |
4165791d | 835 | if (I915_HAS_HOTPLUG(dev_priv)) { |
c19a0df2 PZ |
836 | status = connector_status_disconnected; |
837 | goto out; | |
838 | } | |
aaa37730 | 839 | |
4165791d | 840 | load_detect: |
c19a0df2 PZ |
841 | if (!force) { |
842 | status = connector->status; | |
843 | goto out; | |
844 | } | |
7b334fcb | 845 | |
e4a5d54f | 846 | /* for pre-945g platforms use load detect */ |
6c5ed5ae ML |
847 | ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx); |
848 | if (ret > 0) { | |
e95c8438 DV |
849 | if (intel_crt_detect_ddc(connector)) |
850 | status = connector_status_connected; | |
66478475 | 851 | else if (INTEL_GEN(dev_priv) < 4) |
c8ecb2f1 ML |
852 | status = intel_crt_load_detect(crt, |
853 | to_intel_crtc(connector->state->crtc)->pipe); | |
4f044a88 | 854 | else if (i915_modparams.load_detect_test) |
32fff610 | 855 | status = connector_status_disconnected; |
5bedeb2d DV |
856 | else |
857 | status = connector_status_unknown; | |
6c5ed5ae | 858 | intel_release_load_detect_pipe(connector, &tmp, ctx); |
2927e421 | 859 | } else if (ret == 0) { |
e95c8438 | 860 | status = connector_status_unknown; |
2927e421 | 861 | } else { |
6c5ed5ae | 862 | status = ret; |
2927e421 | 863 | } |
208bf9fd | 864 | |
c19a0df2 | 865 | out: |
0e6e0be4 | 866 | intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); |
e4a5d54f | 867 | return status; |
79e53945 JB |
868 | } |
869 | ||
79e53945 JB |
870 | static int intel_crt_get_modes(struct drm_connector *connector) |
871 | { | |
8e4d36b9 | 872 | struct drm_device *dev = connector->dev; |
fac5e23e | 873 | struct drm_i915_private *dev_priv = to_i915(dev); |
671dedd2 ID |
874 | struct intel_crt *crt = intel_attached_crt(connector); |
875 | struct intel_encoder *intel_encoder = &crt->base; | |
0e6e0be4 | 876 | intel_wakeref_t wakeref; |
3bd7d909 | 877 | struct i2c_adapter *i2c; |
0e6e0be4 | 878 | int ret; |
8e4d36b9 | 879 | |
0e6e0be4 CW |
880 | wakeref = intel_display_power_get(dev_priv, |
881 | intel_encoder->power_domain); | |
671dedd2 | 882 | |
41aa3448 | 883 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 884 | ret = intel_crt_ddc_get_modes(connector, i2c); |
9beb5fea | 885 | if (ret || !IS_G4X(dev_priv)) |
671dedd2 | 886 | goto out; |
8e4d36b9 | 887 | |
8e4d36b9 | 888 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
988c7015 | 889 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); |
671dedd2 ID |
890 | ret = intel_crt_ddc_get_modes(connector, i2c); |
891 | ||
892 | out: | |
0e6e0be4 | 893 | intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); |
671dedd2 ID |
894 | |
895 | return ret; | |
79e53945 JB |
896 | } |
897 | ||
9504a892 | 898 | void intel_crt_reset(struct drm_encoder *encoder) |
f3269058 | 899 | { |
66478475 | 900 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
28cf71ce | 901 | struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); |
f3269058 | 902 | |
66478475 | 903 | if (INTEL_GEN(dev_priv) >= 5) { |
2e938892 DV |
904 | u32 adpa; |
905 | ||
ca54b810 | 906 | adpa = I915_READ(crt->adpa_reg); |
2e938892 DV |
907 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
908 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
909 | I915_WRITE(crt->adpa_reg, adpa); |
910 | POSTING_READ(crt->adpa_reg); | |
2e938892 | 911 | |
0039a4b3 | 912 | DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); |
f3269058 | 913 | crt->force_hotplug_required = 1; |
2e938892 DV |
914 | } |
915 | ||
f3269058 CW |
916 | } |
917 | ||
79e53945 JB |
918 | /* |
919 | * Routines for controlling stuff on the analog port | |
920 | */ | |
921 | ||
79e53945 | 922 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
79e53945 | 923 | .fill_modes = drm_helper_probe_single_connector_modes, |
1ebaa0b9 | 924 | .late_register = intel_connector_register, |
c191eca1 | 925 | .early_unregister = intel_connector_unregister, |
d4b26e4f | 926 | .destroy = intel_connector_destroy, |
c6f95f27 | 927 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 928 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
929 | }; |
930 | ||
931 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
6c5ed5ae | 932 | .detect_ctx = intel_crt_detect, |
79e53945 JB |
933 | .mode_valid = intel_crt_mode_valid, |
934 | .get_modes = intel_crt_get_modes, | |
79e53945 JB |
935 | }; |
936 | ||
79e53945 | 937 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
28cf71ce | 938 | .reset = intel_crt_reset, |
ea5b213a | 939 | .destroy = intel_encoder_destroy, |
79e53945 JB |
940 | }; |
941 | ||
c39055b0 | 942 | void intel_crt_init(struct drm_i915_private *dev_priv) |
79e53945 JB |
943 | { |
944 | struct drm_connector *connector; | |
c9a1c4cd | 945 | struct intel_crt *crt; |
454c1ca8 | 946 | struct intel_connector *intel_connector; |
6c03a6bd VS |
947 | i915_reg_t adpa_reg; |
948 | u32 adpa; | |
79e53945 | 949 | |
6e266956 | 950 | if (HAS_PCH_SPLIT(dev_priv)) |
6c03a6bd | 951 | adpa_reg = PCH_ADPA; |
11a914c2 | 952 | else if (IS_VALLEYVIEW(dev_priv)) |
6c03a6bd VS |
953 | adpa_reg = VLV_ADPA; |
954 | else | |
955 | adpa_reg = ADPA; | |
956 | ||
957 | adpa = I915_READ(adpa_reg); | |
958 | if ((adpa & ADPA_DAC_ENABLE) == 0) { | |
959 | /* | |
960 | * On some machines (some IVB at least) CRT can be | |
961 | * fused off, but there's no known fuse bit to | |
962 | * indicate that. On these machine the ADPA register | |
963 | * works normally, except the DAC enable bit won't | |
964 | * take. So the only way to tell is attempt to enable | |
965 | * it and see what happens. | |
966 | */ | |
967 | I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | | |
968 | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); | |
969 | if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) | |
970 | return; | |
971 | I915_WRITE(adpa_reg, adpa); | |
972 | } | |
973 | ||
c9a1c4cd CW |
974 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
975 | if (!crt) | |
79e53945 JB |
976 | return; |
977 | ||
9bdbd0b9 | 978 | intel_connector = intel_connector_alloc(); |
454c1ca8 | 979 | if (!intel_connector) { |
c9a1c4cd | 980 | kfree(crt); |
454c1ca8 ZW |
981 | return; |
982 | } | |
983 | ||
984 | connector = &intel_connector->base; | |
637f44d2 | 985 | crt->connector = intel_connector; |
c39055b0 | 986 | drm_connector_init(&dev_priv->drm, &intel_connector->base, |
79e53945 JB |
987 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
988 | ||
c39055b0 | 989 | drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, |
580d8ed5 | 990 | DRM_MODE_ENCODER_DAC, "CRT"); |
79e53945 | 991 | |
c9a1c4cd | 992 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 993 | |
c9a1c4cd | 994 | crt->base.type = INTEL_OUTPUT_ANALOG; |
301ea74a | 995 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
50a0bc90 | 996 | if (IS_I830(dev_priv)) |
0fbae9d2 | 997 | crt->base.crtc_mask = BIT(PIPE_A); |
59c859d6 | 998 | else |
0fbae9d2 | 999 | crt->base.crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); |
59c859d6 | 1000 | |
cf819eff | 1001 | if (IS_GEN(dev_priv, 2)) |
dbb02575 DV |
1002 | connector->interlace_allowed = 0; |
1003 | else | |
1004 | connector->interlace_allowed = 1; | |
79e53945 JB |
1005 | connector->doublescan_allowed = 0; |
1006 | ||
6c03a6bd | 1007 | crt->adpa_reg = adpa_reg; |
540a8950 | 1008 | |
79f255a0 ACO |
1009 | crt->base.power_domain = POWER_DOMAIN_PORT_CRT; |
1010 | ||
56b857a5 | 1011 | if (I915_HAS_HOTPLUG(dev_priv) && |
dba14b27 | 1012 | !dmi_check_system(intel_spurious_crt_detect)) { |
1d843f9d | 1013 | crt->base.hpd_pin = HPD_CRT; |
dba14b27 VS |
1014 | crt->base.hotplug = intel_encoder_hotplug; |
1015 | } | |
c5ce4ef3 | 1016 | |
4f8036a2 | 1017 | if (HAS_DDI(dev_priv)) { |
03cdc1d4 | 1018 | crt->base.port = PORT_E; |
a2985791 | 1019 | crt->base.get_config = hsw_crt_get_config; |
4eda01b2 | 1020 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
2f26cdc0 | 1021 | crt->base.compute_config = hsw_crt_compute_config; |
51c4fa69 JN |
1022 | crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; |
1023 | crt->base.pre_enable = hsw_pre_enable_crt; | |
1024 | crt->base.enable = hsw_enable_crt; | |
3daa3cee | 1025 | crt->base.disable = hsw_disable_crt; |
b7076546 | 1026 | crt->base.post_disable = hsw_post_disable_crt; |
a2985791 | 1027 | } else { |
c5ce4ef3 | 1028 | if (HAS_PCH_SPLIT(dev_priv)) { |
2f26cdc0 | 1029 | crt->base.compute_config = pch_crt_compute_config; |
c5ce4ef3 JN |
1030 | crt->base.disable = pch_disable_crt; |
1031 | crt->base.post_disable = pch_post_disable_crt; | |
1032 | } else { | |
2f26cdc0 | 1033 | crt->base.compute_config = intel_crt_compute_config; |
c5ce4ef3 JN |
1034 | crt->base.disable = intel_disable_crt; |
1035 | } | |
03cdc1d4 | 1036 | crt->base.port = PORT_NONE; |
a2985791 | 1037 | crt->base.get_config = intel_crt_get_config; |
4eda01b2 | 1038 | crt->base.get_hw_state = intel_crt_get_hw_state; |
51c4fa69 | 1039 | crt->base.enable = intel_enable_crt; |
a2985791 | 1040 | } |
e403fc94 | 1041 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
df0323c4 | 1042 | |
79e53945 JB |
1043 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
1044 | ||
56b857a5 | 1045 | if (!I915_HAS_HOTPLUG(dev_priv)) |
821450c6 | 1046 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
eb1f8e4f | 1047 | |
e7dbb2f2 KP |
1048 | /* |
1049 | * Configure the automatic hotplug detection stuff | |
1050 | */ | |
1051 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 1052 | |
68d18ad7 | 1053 | /* |
3e68320e DL |
1054 | * TODO: find a proper way to discover whether we need to set the the |
1055 | * polarity and link reversal bits or not, instead of relying on the | |
1056 | * BIOS. | |
68d18ad7 | 1057 | */ |
6e266956 | 1058 | if (HAS_PCH_LPT(dev_priv)) { |
3e68320e DL |
1059 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
1060 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
1061 | ||
eede3b53 | 1062 | dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; |
3e68320e | 1063 | } |
754970ee | 1064 | |
28cf71ce | 1065 | intel_crt_reset(&crt->base.base); |
79e53945 | 1066 | } |