[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / mmhub_v2_0.c

/*
 * Copyright 2019 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "amdgpu.h"
#include "mmhub_v2_0.h"

#include "mmhub/mmhub_2_0_0_offset.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"
#include "mmhub/mmhub_2_0_0_default.h"
#include "navi10_enum.h"

#include "soc15_common.h"

void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
				uint64_t page_table_base)
{
	/* two registers distance between mmMMVM_CONTEXT0_* to mmMMVM_CONTEXT1_* */
	int offset = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
			- mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;

	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
			offset * vmid, lower_32_bits(page_table_base));

	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
			offset * vmid, upper_32_bits(page_table_base));
}

static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
{
	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);

	mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);

	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
		     (u32)(adev->gmc.gart_start >> 12));
	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
		     (u32)(adev->gmc.gart_start >> 44));

	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
		     (u32)(adev->gmc.gart_end >> 12));
	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
		     (u32)(adev->gmc.gart_end >> 44));
}

static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
{
	uint64_t value;
	uint32_t tmp;

	/* Disable AGP. */
	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0);
	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF);

	/* Program the system aperture low logical page number. */
	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
		     adev->gmc.vram_start >> 18);
	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
		     adev->gmc.vram_end >> 18);

	/* Set default page address. */
	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
		adev->vm_manager.vram_base_offset;
	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
		     (u32)(value >> 12));
	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
		     (u32)(value >> 44));

	/* Program "protection fault". */
	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
		     (u32)(adev->dummy_page_addr >> 12));
	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
		     (u32)((u64)adev->dummy_page_addr >> 44));

	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
}

static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
{
	uint32_t tmp;

	/* Setup TLB control */
	tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);

	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
			    MTYPE, MTYPE_UC); /* UC, uncached */

	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
}

static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
{
	uint32_t tmp;

	/* Setup L2 cache */
	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
			    ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
	/* XXX for emulation, Refer to closed source code.*/
	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
			    0);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);

	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);

	tmp = mmMMVM_L2_CNTL3_DEFAULT;
	if (adev->gmc.translate_further) {
		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
	} else {
		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
	}
	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);

	tmp = mmMMVM_L2_CNTL4_DEFAULT;
	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
}

static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
{
	uint32_t tmp;

	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
}

static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
{
	WREG32_SOC15(MMHUB, 0,
		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
		     0xFFFFFFFF);
	WREG32_SOC15(MMHUB, 0,
		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
		     0x0000000F);

	WREG32_SOC15(MMHUB, 0,
		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
	WREG32_SOC15(MMHUB, 0,
		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);

	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
		     0);
	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
		     0);
}

static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
{
	int i;
	uint32_t tmp;

	for (i = 0; i <= 14; i++) {
		tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
				    adev->vm_manager.num_level);
		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
				    1);
		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
				    READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
				    PAGE_TABLE_BLOCK_SIZE,
				    adev->vm_manager.block_size - 9);
		/* Send no-retry XNACK on fault to suppress VM fault storm. */
		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
				    !amdgpu_noretry);
		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp);
		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
			lower_32_bits(adev->vm_manager.max_pfn - 1));
		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
			upper_32_bits(adev->vm_manager.max_pfn - 1));
	}
}

static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
{
	unsigned i;

	for (i = 0; i < 18; ++i) {
		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
				    2 * i, 0xffffffff);
		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
				    2 * i, 0x1f);
	}
}

int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
{
	if (amdgpu_sriov_vf(adev)) {
		/*
		 * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
		 * VF copy registers so vbios post doesn't program them, for
		 * SRIOV driver need to program them
		 */
		WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE,
			     adev->gmc.vram_start >> 24);
		WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP,
			     adev->gmc.vram_end >> 24);
	}

	/* GART Enable. */
	mmhub_v2_0_init_gart_aperture_regs(adev);
	mmhub_v2_0_init_system_aperture_regs(adev);
	mmhub_v2_0_init_tlb_regs(adev);
	mmhub_v2_0_init_cache_regs(adev);

	mmhub_v2_0_enable_system_domain(adev);
	mmhub_v2_0_disable_identity_aperture(adev);
	mmhub_v2_0_setup_vmid_config(adev);
	mmhub_v2_0_program_invalidation(adev);

	return 0;
}

void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
{
	u32 tmp;
	u32 i;

	/* Disable all tables */
	for (i = 0; i < 16; i++)
		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, i, 0);

	/* Setup TLB control */
	tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
			    ENABLE_ADVANCED_DRIVER_MODEL, 0);
	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);

	/* Setup L2 cache */
	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
}

/**
 * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling
 *
 * @adev: amdgpu_device pointer
 * @value: true redirects VM faults to the default page
 */
void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
{
	u32 tmp;
	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
			    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
			    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
			    PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
			    PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
			    TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
			    value);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
			    NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
			    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
			    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
			    READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
			    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
			    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	if (!value) {
		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
				CRASH_ON_NO_RETRY_FAULT, 1);
		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
				CRASH_ON_RETRY_FAULT, 1);
	}
	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
}

void mmhub_v2_0_init(struct amdgpu_device *adev)
{
	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];

	hub->ctx0_ptb_addr_lo32 =
		SOC15_REG_OFFSET(MMHUB, 0,
				 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
	hub->ctx0_ptb_addr_hi32 =
		SOC15_REG_OFFSET(MMHUB, 0,
				 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
	hub->vm_inv_eng0_req =
		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
	hub->vm_inv_eng0_ack =
		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
	hub->vm_context0_cntl =
		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
	hub->vm_l2_pro_fault_status =
		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
	hub->vm_l2_pro_fault_cntl =
		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);

}

static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
							bool enable)
{
	uint32_t def, data, def1, data1;

	def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);

	def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
		data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;

		data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
		           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
		           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
		           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
		           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
		           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);

	} else {
		data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;

		data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
			  DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
			  DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
			  DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
			  DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
			  DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
	}

	if (def != data)
		WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);

	if (def1 != data1)
		WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
}

static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
						       bool enable)
{
	uint32_t def, data;

	def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
		data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
	else
		data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;

	if (def != data)
		WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
}

int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
			       enum amd_clockgating_state state)
{
	if (amdgpu_sriov_vf(adev))
		return 0;

	switch (adev->asic_type) {
	case CHIP_NAVI10:
	case CHIP_NAVI14:
	case CHIP_NAVI12:
		mmhub_v2_0_update_medium_grain_clock_gating(adev,
				state == AMD_CG_STATE_GATE ? true : false);
		mmhub_v2_0_update_medium_grain_light_sleep(adev,
				state == AMD_CG_STATE_GATE ? true : false);
		break;
	default:
		break;
	}

	return 0;
}

void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
{
	int data, data1;

	if (amdgpu_sriov_vf(adev))
		*flags = 0;

	data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);

	data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

	/* AMD_CG_SUPPORT_MC_MGCG */
	if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
	    !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
		       DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
		       DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
		       DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
		       DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
		       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
		*flags |= AMD_CG_SUPPORT_MC_MGCG;

	/* AMD_CG_SUPPORT_MC_LS */
	if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
		*flags |= AMD_CG_SUPPORT_MC_LS;
}
Commit	Line	Data
adc43c1b HZ	1	/*
	2	* Copyright 2019 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#include "amdgpu.h"
	25	#include "mmhub_v2_0.h"
	26
	27	#include "mmhub/mmhub_2_0_0_offset.h"
	28	#include "mmhub/mmhub_2_0_0_sh_mask.h"
	29	#include "mmhub/mmhub_2_0_0_default.h"
	30	#include "navi10_enum.h"
	31
	32	#include "soc15_common.h"
	33
e7956997 YZ	34	void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
e7956997 YZ	35	uint64_t page_table_base)
adc43c1b	36	{
e7956997 YZ	37	/* two registers distance between mmMMVM_CONTEXT0_* to mmMMVM_CONTEXT1_* */
	38	int offset = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
	39	- mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
adc43c1b	40
e7956997 YZ	41	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
e7956997 YZ	42	offset * vmid, lower_32_bits(page_table_base));
adc43c1b	43
e7956997 YZ	44	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
e7956997 YZ	45	offset * vmid, upper_32_bits(page_table_base));
adc43c1b HZ	46	}
	47
	48	static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
	49	{
e7956997 YZ	50	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
	51
	52	mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
adc43c1b HZ	53
	54	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
	55	(u32)(adev->gmc.gart_start >> 12));
	56	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
	57	(u32)(adev->gmc.gart_start >> 44));
	58
	59	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
	60	(u32)(adev->gmc.gart_end >> 12));
	61	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
	62	(u32)(adev->gmc.gart_end >> 44));
	63	}
	64
	65	static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
	66	{
	67	uint64_t value;
	68	uint32_t tmp;
	69
	70	/* Disable AGP. */
	71	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
	72	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0);
	73	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF);
	74
	75	/* Program the system aperture low logical page number. */
	76	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
	77	adev->gmc.vram_start >> 18);
	78	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
	79	adev->gmc.vram_end >> 18);
	80
	81	/* Set default page address. */
	82	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
	83	adev->vm_manager.vram_base_offset;
	84	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
	85	(u32)(value >> 12));
	86	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
	87	(u32)(value >> 44));
	88
	89	/* Program "protection fault". */
	90	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
	91	(u32)(adev->dummy_page_addr >> 12));
	92	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
	93	(u32)((u64)adev->dummy_page_addr >> 44));
	94
	95	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
	96	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
	97	ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
	98	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
	99	}
	100
	101	static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
	102	{
	103	uint32_t tmp;
	104
	105	/* Setup TLB control */
	106	tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
	107
	108	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
	109	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
	110	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
	111	ENABLE_ADVANCED_DRIVER_MODEL, 1);
	112	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
	113	SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
	114	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
	115	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
	116	MTYPE, MTYPE_UC); /* UC, uncached */
117
118	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
119	}
120
121	static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
122	{
123	uint32_t tmp;
124
125	/* Setup L2 cache */
126	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
127	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
128	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
3ebab625 JX	129	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
3ebab625 JX	130	ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
adc43c1b HZ	131	/* XXX for emulation, Refer to closed source code.*/
	132	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
	133	0);
8b7d6157	134	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
adc43c1b HZ	135	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
	136	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
	137	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
	138
	139	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
	140	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
	141	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
	142	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
	143
	144	tmp = mmMMVM_L2_CNTL3_DEFAULT;
46203a50 AD	145	if (adev->gmc.translate_further) {
	146	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
	147	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
	148	L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
	149	} else {
	150	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
	151	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
	152	L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
	153	}
adc43c1b HZ	154	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
	155
	156	tmp = mmMMVM_L2_CNTL4_DEFAULT;
	157	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
	158	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
	159	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
	160	}
	161
	162	static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
	163	{
	164	uint32_t tmp;
	165
	166	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
	167	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
	168	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
7cae7061 FK	169	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
7cae7061 FK	170	RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
adc43c1b HZ	171	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
	172	}
	173
	174	static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
	175	{
	176	WREG32_SOC15(MMHUB, 0,
	177	mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
	178	0xFFFFFFFF);
	179	WREG32_SOC15(MMHUB, 0,
	180	mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
	181	0x0000000F);
	182
	183	WREG32_SOC15(MMHUB, 0,
	184	mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
	185	WREG32_SOC15(MMHUB, 0,
	186	mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
	187
	188	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
	189	0);
	190	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
	191	0);
	192	}
	193
	194	static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
	195	{
	196	int i;
	197	uint32_t tmp;
	198
	199	for (i = 0; i <= 14; i++) {
	200	tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
	201	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
	202	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
	203	adev->vm_manager.num_level);
	204	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
	205	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	206	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
	207	DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
	208	1);
	209	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
	210	PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	211	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
	212	VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	213	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
	214	READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	215	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
	216	WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	217	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
	218	EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	219	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
	220	PAGE_TABLE_BLOCK_SIZE,
	221	adev->vm_manager.block_size - 9);
	222	/* Send no-retry XNACK on fault to suppress VM fault storm. */
	223	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
75ee6487 FK	224	RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
75ee6487 FK	225	!amdgpu_noretry);
adc43c1b HZ	226	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp);
	227	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
	228	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
	229	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
	230	lower_32_bits(adev->vm_manager.max_pfn - 1));
	231	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
	232	upper_32_bits(adev->vm_manager.max_pfn - 1));
	233	}
	234	}
	235
	236	static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
	237	{
	238	unsigned i;
	239
	240	for (i = 0; i < 18; ++i) {
	241	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
	242	2 * i, 0xffffffff);
	243	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
	244	2 * i, 0x1f);
	245	}
	246	}
	247
	248	int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
	249	{
	250	if (amdgpu_sriov_vf(adev)) {
	251	/*
	252	* MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
	253	* VF copy registers so vbios post doesn't program them, for
	254	* SRIOV driver need to program them
	255	*/
	256	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE,
	257	adev->gmc.vram_start >> 24);
	258	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP,
	259	adev->gmc.vram_end >> 24);
	260	}
	261
	262	/* GART Enable. */
	263	mmhub_v2_0_init_gart_aperture_regs(adev);
	264	mmhub_v2_0_init_system_aperture_regs(adev);
	265	mmhub_v2_0_init_tlb_regs(adev);
	266	mmhub_v2_0_init_cache_regs(adev);
	267
	268	mmhub_v2_0_enable_system_domain(adev);
	269	mmhub_v2_0_disable_identity_aperture(adev);
	270	mmhub_v2_0_setup_vmid_config(adev);
	271	mmhub_v2_0_program_invalidation(adev);
	272
	273	return 0;
	274	}
	275
	276	void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
	277	{
	278	u32 tmp;
	279	u32 i;
	280
	281	/* Disable all tables */
	282	for (i = 0; i < 16; i++)
	283	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, i, 0);
	284
	285	/* Setup TLB control */
	286	tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
	287	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
	288	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
	289	ENABLE_ADVANCED_DRIVER_MODEL, 0);
290	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
291
292	/* Setup L2 cache */
293	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
294	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
295	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
296	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
297	}
298
299	/**
300	* mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling
301	*
302	* @adev: amdgpu_device pointer
303	* @value: true redirects VM faults to the default page
304	*/
305	void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
306	{
307	u32 tmp;
308	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
309	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
310	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
311	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
312	PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
313	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
314	PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
315	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
316	PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
317	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
318	TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
319	value);
320	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
321	NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
322	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
323	DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
324	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
325	VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
326	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
327	READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
328	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
329	WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
330	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
331	EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
332	if (!value) {
333	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
334	CRASH_ON_NO_RETRY_FAULT, 1);
335	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
336	CRASH_ON_RETRY_FAULT, 1);
337	}
338	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
339	}
340
341	void mmhub_v2_0_init(struct amdgpu_device *adev)
342	{
a2d15ed7	343	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
adc43c1b HZ	344
	345	hub->ctx0_ptb_addr_lo32 =
	346	SOC15_REG_OFFSET(MMHUB, 0,
	347	mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
	348	hub->ctx0_ptb_addr_hi32 =
	349	SOC15_REG_OFFSET(MMHUB, 0,
	350	mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
	351	hub->vm_inv_eng0_req =
	352	SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
	353	hub->vm_inv_eng0_ack =
	354	SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
	355	hub->vm_context0_cntl =
	356	SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
	357	hub->vm_l2_pro_fault_status =
	358	SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
	359	hub->vm_l2_pro_fault_cntl =
	360	SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
	361
	362	}
	363
	364	static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
	365	bool enable)
	366	{
	367	uint32_t def, data, def1, data1;
	368
	369	def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
	370
	371	def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
	372
	373	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
	374	data \|= MM_ATC_L2_MISC_CG__ENABLE_MASK;
	375
	376	data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK \|
	377	DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK \|
	378	DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK \|
	379	DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK \|
	380	DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK \|
	381	DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
	382
	383	} else {
	384	data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
	385
	386	data1 \|= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK \|
	387	DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK \|
	388	DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK \|
	389	DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK \|
	390	DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK \|
	391	DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
	392	}
	393
	394	if (def != data)
	395	WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
	396
	397	if (def1 != data1)
	398	WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
	399	}
	400
	401	static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
	402	bool enable)
	403	{
	404	uint32_t def, data;
	405
	406	def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
	407
408	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
409	data \|= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
410	else
411	data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
412
413	if (def != data)
414	WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
415	}
416
417	int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
418	enum amd_clockgating_state state)
419	{
420	if (amdgpu_sriov_vf(adev))
421	return 0;
422
423	switch (adev->asic_type) {
424	case CHIP_NAVI10:
408c49de	425	case CHIP_NAVI14:
cf5a95e5	426	case CHIP_NAVI12:
adc43c1b HZ	427	mmhub_v2_0_update_medium_grain_clock_gating(adev,
	428	state == AMD_CG_STATE_GATE ? true : false);
	429	mmhub_v2_0_update_medium_grain_light_sleep(adev,
	430	state == AMD_CG_STATE_GATE ? true : false);
	431	break;
	432	default:
	433	break;
	434	}
	435
	436	return 0;
	437	}
	438
	439	void mmhub_v2_0_get_clockgating(struct amdgpu_device adev, u32 flags)
	440	{
	441	int data, data1;
	442
	443	if (amdgpu_sriov_vf(adev))
	444	*flags = 0;
	445
	446	data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
	447
	448	data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
	449
	450	/* AMD_CG_SUPPORT_MC_MGCG */
	451	if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
	452	!(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK \|
	453	DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK \|
	454	DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK \|
	455	DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK \|
	456	DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK \|
	457	DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
	458	*flags \|= AMD_CG_SUPPORT_MC_MGCG;
	459
	460	/* AMD_CG_SUPPORT_MC_LS */
	461	if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
	462	*flags \|= AMD_CG_SUPPORT_MC_LS;
	463	}