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073440d2 CK |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Christian König | |
23 | */ | |
24 | #ifndef __AMDGPU_VM_H__ | |
25 | #define __AMDGPU_VM_H__ | |
26 | ||
02208441 | 27 | #include <linux/idr.h> |
1b1f42d8 LS |
28 | #include <linux/kfifo.h> |
29 | #include <linux/rbtree.h> | |
30 | #include <drm/gpu_scheduler.h> | |
61b100e9 | 31 | #include <drm/drm_file.h> |
f921661b | 32 | #include <drm/ttm/ttm_bo_driver.h> |
073440d2 | 33 | |
073440d2 CK |
34 | #include "amdgpu_sync.h" |
35 | #include "amdgpu_ring.h" | |
620f774f | 36 | #include "amdgpu_ids.h" |
073440d2 CK |
37 | |
38 | struct amdgpu_bo_va; | |
39 | struct amdgpu_job; | |
40 | struct amdgpu_bo_list_entry; | |
41 | ||
42 | /* | |
43 | * GPUVM handling | |
44 | */ | |
45 | ||
073440d2 CK |
46 | /* Maximum number of PTEs the hardware can write with one command */ |
47 | #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF | |
48 | ||
49 | /* number of entries in page table */ | |
36b32a68 | 50 | #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) |
073440d2 | 51 | |
35ba15f0 CK |
52 | #define AMDGPU_PTE_VALID (1ULL << 0) |
53 | #define AMDGPU_PTE_SYSTEM (1ULL << 1) | |
54 | #define AMDGPU_PTE_SNOOPED (1ULL << 2) | |
073440d2 CK |
55 | |
56 | /* VI only */ | |
35ba15f0 | 57 | #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) |
073440d2 | 58 | |
35ba15f0 CK |
59 | #define AMDGPU_PTE_READABLE (1ULL << 5) |
60 | #define AMDGPU_PTE_WRITEABLE (1ULL << 6) | |
073440d2 | 61 | |
982a1348 | 62 | #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) |
073440d2 | 63 | |
d0766e98 ZJ |
64 | /* TILED for VEGA10, reserved for older ASICs */ |
65 | #define AMDGPU_PTE_PRT (1ULL << 51) | |
284710fa | 66 | |
cf2f0a37 AD |
67 | /* PDE is handled as PTE for VEGA10 */ |
68 | #define AMDGPU_PDE_PTE (1ULL << 54) | |
69 | ||
6a42fd6f CK |
70 | /* PTE is handled as PDE for VEGA10 (Translate Further) */ |
71 | #define AMDGPU_PTE_TF (1ULL << 56) | |
72 | ||
73 | /* PDE Block Fragment Size for VEGA10 */ | |
74 | #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) | |
75 | ||
959a2091 YZ |
76 | |
77 | /* For GFX9 */ | |
ca02061c AD |
78 | #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57) |
79 | #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL) | |
80 | ||
959a2091 | 81 | #define AMDGPU_MTYPE_NC 0 |
6d16dac8 YZ |
82 | #define AMDGPU_MTYPE_CC 2 |
83 | ||
84 | #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ | |
85 | | AMDGPU_PTE_SNOOPED \ | |
86 | | AMDGPU_PTE_EXECUTABLE \ | |
87 | | AMDGPU_PTE_READABLE \ | |
88 | | AMDGPU_PTE_WRITEABLE \ | |
89 | | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC)) | |
90 | ||
073440d2 CK |
91 | /* How to programm VM fault handling */ |
92 | #define AMDGPU_VM_FAULT_STOP_NEVER 0 | |
93 | #define AMDGPU_VM_FAULT_STOP_FIRST 1 | |
94 | #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 | |
95 | ||
eb60ef2b CK |
96 | /* max number of VMHUB */ |
97 | #define AMDGPU_MAX_VMHUBS 2 | |
98 | #define AMDGPU_GFXHUB 0 | |
99 | #define AMDGPU_MMHUB 1 | |
100 | ||
101 | /* hardcode that limit for now */ | |
18d09e63 | 102 | #define AMDGPU_VA_RESERVED_SIZE (1ULL << 20) |
ff4cd389 | 103 | |
c3505770 CZ |
104 | /* max vmids dedicated for process */ |
105 | #define AMDGPU_VM_MAX_RESERVED_VMID 1 | |
eb60ef2b | 106 | |
9a4b7d4c HK |
107 | #define AMDGPU_VM_CONTEXT_GFX 0 |
108 | #define AMDGPU_VM_CONTEXT_COMPUTE 1 | |
109 | ||
110 | /* See vm_update_mode */ | |
111 | #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) | |
112 | #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) | |
113 | ||
196f7489 CZ |
114 | /* VMPT level enumerate, and the hiberachy is: |
115 | * PDB2->PDB1->PDB0->PTB | |
116 | */ | |
117 | enum amdgpu_vm_level { | |
118 | AMDGPU_VM_PDB2, | |
119 | AMDGPU_VM_PDB1, | |
120 | AMDGPU_VM_PDB0, | |
121 | AMDGPU_VM_PTB | |
122 | }; | |
123 | ||
ec681545 CK |
124 | /* base structure for tracking BO usage in a VM */ |
125 | struct amdgpu_vm_bo_base { | |
126 | /* constant after initialization */ | |
127 | struct amdgpu_vm *vm; | |
128 | struct amdgpu_bo *bo; | |
129 | ||
130 | /* protected by bo being reserved */ | |
646b9025 | 131 | struct amdgpu_vm_bo_base *next; |
ec681545 CK |
132 | |
133 | /* protected by spinlock */ | |
134 | struct list_head vm_status; | |
3d7d4d3a CK |
135 | |
136 | /* protected by the BO being reserved */ | |
137 | bool moved; | |
ec681545 | 138 | }; |
9a4b7d4c | 139 | |
073440d2 | 140 | struct amdgpu_vm_pt { |
3f3333f8 | 141 | struct amdgpu_vm_bo_base base; |
67003a15 CK |
142 | |
143 | /* array of page tables, one for each directory entry */ | |
3f3333f8 | 144 | struct amdgpu_vm_pt *entries; |
073440d2 CK |
145 | }; |
146 | ||
4473e1db HR |
147 | /* provided by hw blocks that can write ptes, e.g., sdma */ |
148 | struct amdgpu_vm_pte_funcs { | |
149 | /* number of dw to reserve per operation */ | |
150 | unsigned copy_pte_num_dw; | |
151 | ||
152 | /* copy pte entries from GART */ | |
153 | void (*copy_pte)(struct amdgpu_ib *ib, | |
154 | uint64_t pe, uint64_t src, | |
155 | unsigned count); | |
156 | ||
157 | /* write pte one entry at a time with addr mapping */ | |
158 | void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, | |
159 | uint64_t value, unsigned count, | |
160 | uint32_t incr); | |
161 | /* for linear pte/pde updates without addr mapping */ | |
162 | void (*set_pte_pde)(struct amdgpu_ib *ib, | |
163 | uint64_t pe, | |
164 | uint64_t addr, unsigned count, | |
165 | uint32_t incr, uint64_t flags); | |
166 | }; | |
167 | ||
2aa37bf5 AG |
168 | struct amdgpu_task_info { |
169 | char process_name[TASK_COMM_LEN]; | |
170 | char task_name[TASK_COMM_LEN]; | |
171 | pid_t pid; | |
172 | pid_t tgid; | |
173 | }; | |
174 | ||
d1e29462 CK |
175 | /** |
176 | * struct amdgpu_vm_update_params | |
177 | * | |
178 | * Encapsulate some VM table update parameters to reduce | |
179 | * the number of function parameters | |
180 | * | |
181 | */ | |
182 | struct amdgpu_vm_update_params { | |
183 | ||
184 | /** | |
185 | * @adev: amdgpu device we do this update for | |
186 | */ | |
187 | struct amdgpu_device *adev; | |
188 | ||
189 | /** | |
190 | * @vm: optional amdgpu_vm we do this update for | |
191 | */ | |
192 | struct amdgpu_vm *vm; | |
193 | ||
194 | /** | |
195 | * @pages_addr: | |
196 | * | |
197 | * DMA addresses to use for mapping | |
198 | */ | |
199 | dma_addr_t *pages_addr; | |
200 | ||
6dd09027 CK |
201 | /** |
202 | * @job: job to used for hw submission | |
203 | */ | |
204 | struct amdgpu_job *job; | |
205 | ||
d1e29462 CK |
206 | /** |
207 | * @ib: indirect buffer to fill with commands | |
208 | */ | |
209 | struct amdgpu_ib *ib; | |
210 | ||
6dd09027 CK |
211 | /** |
212 | * @num_dw_left: number of dw left for the IB | |
213 | */ | |
214 | unsigned int num_dw_left; | |
d1e29462 CK |
215 | }; |
216 | ||
6dd09027 CK |
217 | struct amdgpu_vm_update_funcs { |
218 | ||
219 | int (*prepare)(struct amdgpu_vm_update_params *p, void * owner, | |
220 | struct dma_fence *exclusive); | |
221 | int (*update)(struct amdgpu_vm_update_params *p, | |
222 | struct amdgpu_bo *bo, uint64_t pe, uint64_t addr, | |
223 | unsigned count, uint32_t incr, uint64_t flags); | |
224 | int (*commit)(struct amdgpu_vm_update_params *p, | |
225 | struct dma_fence **fence); | |
226 | }; | |
227 | ||
073440d2 CK |
228 | struct amdgpu_vm { |
229 | /* tree of virtual addresses mapped */ | |
f808c13f | 230 | struct rb_root_cached va; |
073440d2 | 231 | |
3f3333f8 CK |
232 | /* BOs who needs a validation */ |
233 | struct list_head evicted; | |
234 | ||
ea09729c CK |
235 | /* PT BOs which relocated and their parent need an update */ |
236 | struct list_head relocated; | |
237 | ||
c12a2ee5 | 238 | /* per VM BOs moved, but not yet updated in the PT */ |
27c7b9ae | 239 | struct list_head moved; |
073440d2 | 240 | |
806f043f CK |
241 | /* All BOs of this VM not currently in the state machine */ |
242 | struct list_head idle; | |
243 | ||
c12a2ee5 CK |
244 | /* regular invalidated BOs, but not yet updated in the PT */ |
245 | struct list_head invalidated; | |
246 | spinlock_t invalidated_lock; | |
247 | ||
073440d2 CK |
248 | /* BO mappings freed, but not yet updated in the PT */ |
249 | struct list_head freed; | |
250 | ||
251 | /* contains the page directory */ | |
67003a15 | 252 | struct amdgpu_vm_pt root; |
d5884513 | 253 | struct dma_fence *last_update; |
073440d2 | 254 | |
073440d2 | 255 | /* Scheduler entity for page table updates */ |
1b1f42d8 | 256 | struct drm_sched_entity entity; |
073440d2 | 257 | |
02208441 | 258 | unsigned int pasid; |
36bbf3bf | 259 | /* dedicated to vm */ |
620f774f | 260 | struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS]; |
9a4b7d4c HK |
261 | |
262 | /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ | |
6dd09027 CK |
263 | bool use_cpu_for_update; |
264 | ||
265 | /* Functions to use for VM table updates */ | |
266 | const struct amdgpu_vm_update_funcs *update_funcs; | |
51ac7eec YZ |
267 | |
268 | /* Flag to indicate ATS support from PTE for GFX9 */ | |
269 | bool pte_support_ats; | |
a2f14820 | 270 | |
c98171cc | 271 | /* Up to 128 pending retry page faults */ |
a2f14820 | 272 | DECLARE_KFIFO(faults, u64, 128); |
c98171cc | 273 | |
5b21d3e5 FK |
274 | /* Points to the KFD process VM info */ |
275 | struct amdkfd_process_info *process_info; | |
276 | ||
277 | /* List node in amdkfd_process_info.vm_list_head */ | |
278 | struct list_head vm_list_node; | |
279 | ||
280 | /* Valid while the PD is reserved or fenced */ | |
281 | uint64_t pd_phys_addr; | |
2aa37bf5 AG |
282 | |
283 | /* Some basic info about the task */ | |
284 | struct amdgpu_task_info task_info; | |
f921661b HR |
285 | |
286 | /* Store positions of group of BOs */ | |
287 | struct ttm_lru_bulk_move lru_bulk_move; | |
288 | /* mark whether can do the bulk move */ | |
289 | bool bulk_moveable; | |
073440d2 CK |
290 | }; |
291 | ||
073440d2 CK |
292 | struct amdgpu_vm_manager { |
293 | /* Handling of VMIDs */ | |
620f774f | 294 | struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; |
073440d2 CK |
295 | |
296 | /* Handling of VM fences */ | |
297 | u64 fence_context; | |
298 | unsigned seqno[AMDGPU_MAX_RINGS]; | |
299 | ||
22770e5a | 300 | uint64_t max_pfn; |
8437a097 | 301 | uint32_t num_level; |
36b32a68 | 302 | uint32_t block_size; |
e618d306 | 303 | uint32_t fragment_size; |
196f7489 | 304 | enum amdgpu_vm_level root_level; |
073440d2 CK |
305 | /* vram base address for page table entry */ |
306 | u64 vram_base_offset; | |
073440d2 | 307 | /* vm pte handling */ |
3798e9a6 CK |
308 | const struct amdgpu_vm_pte_funcs *vm_pte_funcs; |
309 | struct drm_sched_rq *vm_pte_rqs[AMDGPU_MAX_RINGS]; | |
310 | unsigned vm_pte_num_rqs; | |
284710fa CK |
311 | |
312 | /* partial resident texture handling */ | |
313 | spinlock_t prt_lock; | |
451bc8eb | 314 | atomic_t num_prt_users; |
9a4b7d4c HK |
315 | |
316 | /* controls how VM page tables are updated for Graphics and Compute. | |
317 | * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU | |
318 | * BIT1[= 0] Compute updated by SDMA [= 1] by CPU | |
319 | */ | |
320 | int vm_update_mode; | |
02208441 FK |
321 | |
322 | /* PASID to VM mapping, will be used in interrupt context to | |
323 | * look up VM of a page fault | |
324 | */ | |
325 | struct idr pasid_idr; | |
326 | spinlock_t pasid_lock; | |
073440d2 CK |
327 | }; |
328 | ||
4473e1db HR |
329 | #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) |
330 | #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) | |
331 | #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) | |
332 | ||
6dd09027 CK |
333 | extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; |
334 | extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; | |
335 | ||
073440d2 CK |
336 | void amdgpu_vm_manager_init(struct amdgpu_device *adev); |
337 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev); | |
56753e73 CK |
338 | |
339 | long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); | |
9a4b7d4c | 340 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
02208441 | 341 | int vm_context, unsigned int pasid); |
1685b01a | 342 | int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid); |
bf47afba | 343 | void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); |
073440d2 CK |
344 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); |
345 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, | |
346 | struct list_head *validated, | |
347 | struct amdgpu_bo_list_entry *entry); | |
3f3333f8 | 348 | bool amdgpu_vm_ready(struct amdgpu_vm *vm); |
073440d2 CK |
349 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
350 | int (*callback)(void *p, struct amdgpu_bo *bo), | |
351 | void *param); | |
8fdf074f | 352 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); |
194d2161 CK |
353 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, |
354 | struct amdgpu_vm *vm); | |
073440d2 | 355 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, |
f3467818 NH |
356 | struct amdgpu_vm *vm, |
357 | struct dma_fence **fence); | |
73fb16e7 | 358 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 359 | struct amdgpu_vm *vm); |
073440d2 CK |
360 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, |
361 | struct amdgpu_bo_va *bo_va, | |
362 | bool clear); | |
363 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 364 | struct amdgpu_bo *bo, bool evicted); |
6dd09027 | 365 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); |
073440d2 CK |
366 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, |
367 | struct amdgpu_bo *bo); | |
368 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
369 | struct amdgpu_vm *vm, | |
370 | struct amdgpu_bo *bo); | |
371 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
372 | struct amdgpu_bo_va *bo_va, | |
373 | uint64_t addr, uint64_t offset, | |
268c3001 | 374 | uint64_t size, uint64_t flags); |
80f95c57 CK |
375 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, |
376 | struct amdgpu_bo_va *bo_va, | |
377 | uint64_t addr, uint64_t offset, | |
378 | uint64_t size, uint64_t flags); | |
073440d2 CK |
379 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, |
380 | struct amdgpu_bo_va *bo_va, | |
381 | uint64_t addr); | |
dc54d3d1 CK |
382 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, |
383 | struct amdgpu_vm *vm, | |
384 | uint64_t saddr, uint64_t size); | |
aebc5e6f CK |
385 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, |
386 | uint64_t addr); | |
8ab19ea6 | 387 | void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); |
073440d2 CK |
388 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, |
389 | struct amdgpu_bo_va *bo_va); | |
43370c4c | 390 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, |
f3368128 CK |
391 | uint32_t fragment_size_default, unsigned max_level, |
392 | unsigned max_bits); | |
cfbcacf4 | 393 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
b9bf33d5 CZ |
394 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
395 | struct amdgpu_job *job); | |
e59c0205 | 396 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); |
073440d2 | 397 | |
2aa37bf5 | 398 | void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid, |
f921661b | 399 | struct amdgpu_task_info *task_info); |
2aa37bf5 AG |
400 | |
401 | void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); | |
402 | ||
f921661b HR |
403 | void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, |
404 | struct amdgpu_vm *vm); | |
b61857b5 CZ |
405 | void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo); |
406 | ||
073440d2 | 407 | #endif |