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mm: replace get_user_pages() write/force parameters with gup_flags
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ttm.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <ttm/ttm_bo_api.h>
33#include <ttm/ttm_bo_driver.h>
34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h>
36#include <ttm/ttm_page_alloc.h>
a693e050 37#include <ttm/ttm_memory.h>
d38ceaf9
AD		 38#include <drm/drmP.h>
39#include <drm/amdgpu_drm.h>
40#include <linux/seq_file.h>
41#include <linux/slab.h>
42#include <linux/swiotlb.h>
43#include <linux/swap.h>
44#include <linux/pagemap.h>
45#include <linux/debugfs.h>
46#include "amdgpu.h"
47#include "bif/bif_4_1_d.h"
48
49#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
50
51static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
52static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
53
54static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
55{
56 struct amdgpu_mman *mman;
57 struct amdgpu_device *adev;
58
59 mman = container_of(bdev, struct amdgpu_mman, bdev);
60 adev = container_of(mman, struct amdgpu_device, mman);
61 return adev;
62}
63
64
65/*
66 * Global memory.
67 */
68static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
69{
70 return ttm_mem_global_init(ref->object);
71}
72
73static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
74{
75 ttm_mem_global_release(ref->object);
76}
77
a693e050 78int amdgpu_ttm_global_init(struct amdgpu_device *adev)
d38ceaf9
AD		 79{
80 struct drm_global_reference *global_ref;
703297c1
CK		 81 struct amdgpu_ring *ring;
82 struct amd_sched_rq *rq;
d38ceaf9
AD		 83 int r;
84
85 adev->mman.mem_global_referenced = false;
86 global_ref = &adev->mman.mem_global_ref;
87 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
88 global_ref->size = sizeof(struct ttm_mem_global);
89 global_ref->init = &amdgpu_ttm_mem_global_init;
90 global_ref->release = &amdgpu_ttm_mem_global_release;
91 r = drm_global_item_ref(global_ref);
e9d035ec 92 if (r) {
d38ceaf9
AD		 93 DRM_ERROR("Failed setting up TTM memory accounting "
94 "subsystem.\n");
e9d035ec 95 goto error_mem;
d38ceaf9
AD		 96 }
97
98 adev->mman.bo_global_ref.mem_glob =
99 adev->mman.mem_global_ref.object;
100 global_ref = &adev->mman.bo_global_ref.ref;
101 global_ref->global_type = DRM_GLOBAL_TTM_BO;
102 global_ref->size = sizeof(struct ttm_bo_global);
103 global_ref->init = &ttm_bo_global_init;
104 global_ref->release = &ttm_bo_global_release;
105 r = drm_global_item_ref(global_ref);
e9d035ec 106 if (r) {
d38ceaf9 107 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
e9d035ec 108 goto error_bo;
d38ceaf9
AD		 109 }
110
703297c1
CK		 111 ring = adev->mman.buffer_funcs_ring;
112 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
113 r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
114 rq, amdgpu_sched_jobs);
e9d035ec 115 if (r) {
703297c1 116 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
e9d035ec 117 goto error_entity;
703297c1
CK		 118 }
119
d38ceaf9 120 adev->mman.mem_global_referenced = true;
703297c1 121
d38ceaf9 122 return 0;
e9d035ec
HR		 123
124error_entity:
125 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
126error_bo:
127 drm_global_item_unref(&adev->mman.mem_global_ref);
128error_mem:
129 return r;
d38ceaf9
AD		 130}
131
132static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
133{
134 if (adev->mman.mem_global_referenced) {
703297c1
CK		 135 amd_sched_entity_fini(adev->mman.entity.sched,
136 &adev->mman.entity);
d38ceaf9
AD		 137 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
138 drm_global_item_unref(&adev->mman.mem_global_ref);
139 adev->mman.mem_global_referenced = false;
140 }
141}
142
143static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
144{
145 return 0;
146}
147
148static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
149 struct ttm_mem_type_manager *man)
150{
151 struct amdgpu_device *adev;
152
153 adev = amdgpu_get_adev(bdev);
154
155 switch (type) {
156 case TTM_PL_SYSTEM:
157 /* System memory */
158 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
159 man->available_caching = TTM_PL_MASK_CACHING;
160 man->default_caching = TTM_PL_FLAG_CACHED;
161 break;
162 case TTM_PL_TT:
bb990bb0 163 man->func = &amdgpu_gtt_mgr_func;
d38ceaf9
AD		 164 man->gpu_offset = adev->mc.gtt_start;
165 man->available_caching = TTM_PL_MASK_CACHING;
166 man->default_caching = TTM_PL_FLAG_CACHED;
167 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
168 break;
169 case TTM_PL_VRAM:
170 /* "On-card" video ram */
171 man->func = &ttm_bo_manager_func;
172 man->gpu_offset = adev->mc.vram_start;
173 man->flags = TTM_MEMTYPE_FLAG_FIXED |
174 TTM_MEMTYPE_FLAG_MAPPABLE;
175 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
176 man->default_caching = TTM_PL_FLAG_WC;
177 break;
178 case AMDGPU_PL_GDS:
179 case AMDGPU_PL_GWS:
180 case AMDGPU_PL_OA:
181 /* On-chip GDS memory*/
182 man->func = &ttm_bo_manager_func;
183 man->gpu_offset = 0;
184 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
185 man->available_caching = TTM_PL_FLAG_UNCACHED;
186 man->default_caching = TTM_PL_FLAG_UNCACHED;
187 break;
188 default:
189 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
190 return -EINVAL;
191 }
192 return 0;
193}
194
195static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
196 struct ttm_placement *placement)
197{
765e7fbf 198 struct amdgpu_bo *abo;
d38ceaf9
AD		 199 static struct ttm_place placements = {
200 .fpfn = 0,
201 .lpfn = 0,
202 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
203 };
08291c5c 204 unsigned i;
d38ceaf9
AD		 205
206 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
207 placement->placement = &placements;
208 placement->busy_placement = &placements;
209 placement->num_placement = 1;
210 placement->num_busy_placement = 1;
211 return;
212 }
765e7fbf 213 abo = container_of(bo, struct amdgpu_bo, tbo);
d38ceaf9
AD		 214 switch (bo->mem.mem_type) {
215 case TTM_PL_VRAM:
765e7fbf
CK		 216 if (abo->adev->mman.buffer_funcs_ring->ready == false) {
217 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
08291c5c 218 } else {
765e7fbf
CK		 219 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
220 for (i = 0; i < abo->placement.num_placement; ++i) {
221 if (!(abo->placements[i].flags &
08291c5c
CK		 222 TTM_PL_FLAG_TT))
223 continue;
224
765e7fbf 225 if (abo->placements[i].lpfn)
08291c5c
CK		 226 continue;
227
228 /* set an upper limit to force directly
229 * allocating address space for the BO.
230 */
765e7fbf
CK		 231 abo->placements[i].lpfn =
232 abo->adev->mc.gtt_size >> PAGE_SHIFT;
08291c5c
CK		 233 }
234 }
d38ceaf9
AD		 235 break;
236 case TTM_PL_TT:
237 default:
765e7fbf 238 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
d38ceaf9 239 }
765e7fbf 240 *placement = abo->placement;
d38ceaf9
AD		 241}
242
243static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
244{
765e7fbf 245 struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
d38ceaf9 246
054892ed
JG		 247 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
248 return -EPERM;
28a39654 249 return drm_vma_node_verify_access(&abo->gem_base.vma_node,
d9a1f0b4 250 filp->private_data);
d38ceaf9
AD		 251}
252
253static void amdgpu_move_null(struct ttm_buffer_object *bo,
254 struct ttm_mem_reg *new_mem)
255{
256 struct ttm_mem_reg *old_mem = &bo->mem;
257
258 BUG_ON(old_mem->mm_node != NULL);
259 *old_mem = *new_mem;
260 new_mem->mm_node = NULL;
261}
262
263static int amdgpu_move_blit(struct ttm_buffer_object *bo,
264 bool evict, bool no_wait_gpu,
265 struct ttm_mem_reg *new_mem,
266 struct ttm_mem_reg *old_mem)
267{
268 struct amdgpu_device *adev;
269 struct amdgpu_ring *ring;
270 uint64_t old_start, new_start;
c7ae72c0 271 struct fence *fence;
d38ceaf9
AD		 272 int r;
273
274 adev = amdgpu_get_adev(bo->bdev);
275 ring = adev->mman.buffer_funcs_ring;
d38ceaf9
AD		 276
277 switch (old_mem->mem_type) {
d38ceaf9 278 case TTM_PL_TT:
bb990bb0 279 r = amdgpu_ttm_bind(bo, old_mem);
c855e250
CK		 280 if (r)
281 return r;
282
283 case TTM_PL_VRAM:
ad78069c 284 old_start = (u64)old_mem->start << PAGE_SHIFT;
27798e07 285 old_start += bo->bdev->man[old_mem->mem_type].gpu_offset;
d38ceaf9
AD		 286 break;
287 default:
288 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
289 return -EINVAL;
290 }
291 switch (new_mem->mem_type) {
d38ceaf9 292 case TTM_PL_TT:
bb990bb0 293 r = amdgpu_ttm_bind(bo, new_mem);
c855e250
CK		 294 if (r)
295 return r;
296
297 case TTM_PL_VRAM:
ad78069c 298 new_start = (u64)new_mem->start << PAGE_SHIFT;
27798e07 299 new_start += bo->bdev->man[new_mem->mem_type].gpu_offset;
d38ceaf9
AD		 300 break;
301 default:
302 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
303 return -EINVAL;
304 }
305 if (!ring->ready) {
306 DRM_ERROR("Trying to move memory with ring turned off.\n");
307 return -EINVAL;
308 }
309
310 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
311
312 r = amdgpu_copy_buffer(ring, old_start, new_start,
313 new_mem->num_pages * PAGE_SIZE, /* bytes */
e24db985 314 bo->resv, &fence, false);
ce64bc25
CK		 315 if (r)
316 return r;
317
318 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
c7ae72c0 319 fence_put(fence);
d38ceaf9
AD		 320 return r;
321}
322
323static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
324 bool evict, bool interruptible,
325 bool no_wait_gpu,
326 struct ttm_mem_reg *new_mem)
327{
328 struct amdgpu_device *adev;
329 struct ttm_mem_reg *old_mem = &bo->mem;
330 struct ttm_mem_reg tmp_mem;
331 struct ttm_place placements;
332 struct ttm_placement placement;
333 int r;
334
335 adev = amdgpu_get_adev(bo->bdev);
336 tmp_mem = *new_mem;
337 tmp_mem.mm_node = NULL;
338 placement.num_placement = 1;
339 placement.placement = &placements;
340 placement.num_busy_placement = 1;
341 placement.busy_placement = &placements;
342 placements.fpfn = 0;
056472f1 343 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
d38ceaf9
AD		 344 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
345 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
346 interruptible, no_wait_gpu);
347 if (unlikely(r)) {
348 return r;
349 }
350
351 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
352 if (unlikely(r)) {
353 goto out_cleanup;
354 }
355
356 r = ttm_tt_bind(bo->ttm, &tmp_mem);
357 if (unlikely(r)) {
358 goto out_cleanup;
359 }
360 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
361 if (unlikely(r)) {
362 goto out_cleanup;
363 }
4e2f0caa 364 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
d38ceaf9
AD		 365out_cleanup:
366 ttm_bo_mem_put(bo, &tmp_mem);
367 return r;
368}
369
370static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
371 bool evict, bool interruptible,
372 bool no_wait_gpu,
373 struct ttm_mem_reg *new_mem)
374{
375 struct amdgpu_device *adev;
376 struct ttm_mem_reg *old_mem = &bo->mem;
377 struct ttm_mem_reg tmp_mem;
378 struct ttm_placement placement;
379 struct ttm_place placements;
380 int r;
381
382 adev = amdgpu_get_adev(bo->bdev);
383 tmp_mem = *new_mem;
384 tmp_mem.mm_node = NULL;
385 placement.num_placement = 1;
386 placement.placement = &placements;
387 placement.num_busy_placement = 1;
388 placement.busy_placement = &placements;
389 placements.fpfn = 0;
056472f1 390 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
d38ceaf9
AD		 391 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
392 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
393 interruptible, no_wait_gpu);
394 if (unlikely(r)) {
395 return r;
396 }
4e2f0caa 397 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
d38ceaf9
AD		 398 if (unlikely(r)) {
399 goto out_cleanup;
400 }
401 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
402 if (unlikely(r)) {
403 goto out_cleanup;
404 }
405out_cleanup:
406 ttm_bo_mem_put(bo, &tmp_mem);
407 return r;
408}
409
410static int amdgpu_bo_move(struct ttm_buffer_object *bo,
411 bool evict, bool interruptible,
412 bool no_wait_gpu,
413 struct ttm_mem_reg *new_mem)
414{
415 struct amdgpu_device *adev;
104ece97 416 struct amdgpu_bo *abo;
d38ceaf9
AD		 417 struct ttm_mem_reg *old_mem = &bo->mem;
418 int r;
419
104ece97
MD		 420 /* Can't move a pinned BO */
421 abo = container_of(bo, struct amdgpu_bo, tbo);
422 if (WARN_ON_ONCE(abo->pin_count > 0))
423 return -EINVAL;
424
d38ceaf9 425 adev = amdgpu_get_adev(bo->bdev);
dbd5ed60
CK		 426
427 /* remember the eviction */
428 if (evict)
429 atomic64_inc(&adev->num_evictions);
430
d38ceaf9
AD		 431 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
432 amdgpu_move_null(bo, new_mem);
433 return 0;
434 }
435 if ((old_mem->mem_type == TTM_PL_TT &&
436 new_mem->mem_type == TTM_PL_SYSTEM) ||
437 (old_mem->mem_type == TTM_PL_SYSTEM &&
438 new_mem->mem_type == TTM_PL_TT)) {
439 /* bind is enough */
440 amdgpu_move_null(bo, new_mem);
441 return 0;
442 }
443 if (adev->mman.buffer_funcs == NULL ||
444 adev->mman.buffer_funcs_ring == NULL ||
445 !adev->mman.buffer_funcs_ring->ready) {
446 /* use memcpy */
447 goto memcpy;
448 }
449
450 if (old_mem->mem_type == TTM_PL_VRAM &&
451 new_mem->mem_type == TTM_PL_SYSTEM) {
452 r = amdgpu_move_vram_ram(bo, evict, interruptible,
453 no_wait_gpu, new_mem);
454 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
455 new_mem->mem_type == TTM_PL_VRAM) {
456 r = amdgpu_move_ram_vram(bo, evict, interruptible,
457 no_wait_gpu, new_mem);
458 } else {
459 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
460 }
461
462 if (r) {
463memcpy:
4499f2ac 464 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
d38ceaf9
AD		 465 if (r) {
466 return r;
467 }
468 }
469
470 /* update statistics */
471 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
472 return 0;
473}
474
475static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
476{
477 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
478 struct amdgpu_device *adev = amdgpu_get_adev(bdev);
479
480 mem->bus.addr = NULL;
481 mem->bus.offset = 0;
482 mem->bus.size = mem->num_pages << PAGE_SHIFT;
483 mem->bus.base = 0;
484 mem->bus.is_iomem = false;
485 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
486 return -EINVAL;
487 switch (mem->mem_type) {
488 case TTM_PL_SYSTEM:
489 /* system memory */
490 return 0;
491 case TTM_PL_TT:
492 break;
493 case TTM_PL_VRAM:
494 mem->bus.offset = mem->start << PAGE_SHIFT;
495 /* check if it's visible */
496 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
497 return -EINVAL;
498 mem->bus.base = adev->mc.aper_base;
499 mem->bus.is_iomem = true;
500#ifdef __alpha__
501 /*
502 * Alpha: use bus.addr to hold the ioremap() return,
503 * so we can modify bus.base below.
504 */
505 if (mem->placement & TTM_PL_FLAG_WC)
506 mem->bus.addr =
507 ioremap_wc(mem->bus.base + mem->bus.offset,
508 mem->bus.size);
509 else
510 mem->bus.addr =
511 ioremap_nocache(mem->bus.base + mem->bus.offset,
512 mem->bus.size);
513
514 /*
515 * Alpha: Use just the bus offset plus
516 * the hose/domain memory base for bus.base.
517 * It then can be used to build PTEs for VRAM
518 * access, as done in ttm_bo_vm_fault().
519 */
520 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
521 adev->ddev->hose->dense_mem_base;
522#endif
523 break;
524 default:
525 return -EINVAL;
526 }
527 return 0;
528}
529
530static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
531{
532}
533
534/*
535 * TTM backend functions.
536 */
637dd3b5
CK		 537struct amdgpu_ttm_gup_task_list {
538 struct list_head list;
539 struct task_struct *task;
540};
541
d38ceaf9 542struct amdgpu_ttm_tt {
637dd3b5
CK		 543 struct ttm_dma_tt ttm;
544 struct amdgpu_device *adev;
545 u64 offset;
546 uint64_t userptr;
547 struct mm_struct *usermm;
548 uint32_t userflags;
549 spinlock_t guptasklock;
550 struct list_head guptasks;
2f568dbd 551 atomic_t mmu_invalidations;
5c1354bd 552 struct list_head list;
d38ceaf9
AD		 553};
554
2f568dbd 555int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
d38ceaf9 556{
d38ceaf9 557 struct amdgpu_ttm_tt *gtt = (void *)ttm;
768ae309 558 unsigned int flags = 0;
2f568dbd
CK		 559 unsigned pinned = 0;
560 int r;
d38ceaf9 561
768ae309
LS		 562 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
563 flags |= FOLL_WRITE;
564
d38ceaf9 565 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
2f568dbd 566 /* check that we only use anonymous memory
d38ceaf9
AD		 567 to prevent problems with writeback */
568 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
569 struct vm_area_struct *vma;
570
571 vma = find_vma(gtt->usermm, gtt->userptr);
572 if (!vma || vma->vm_file || vma->vm_end < end)
573 return -EPERM;
574 }
575
576 do {
577 unsigned num_pages = ttm->num_pages - pinned;
578 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
2f568dbd 579 struct page **p = pages + pinned;
637dd3b5
CK		 580 struct amdgpu_ttm_gup_task_list guptask;
581
582 guptask.task = current;
583 spin_lock(&gtt->guptasklock);
584 list_add(&guptask.list, &gtt->guptasks);
585 spin_unlock(&gtt->guptasklock);
d38ceaf9 586
768ae309 587 r = get_user_pages(userptr, num_pages, flags, p, NULL);
637dd3b5
CK		 588
589 spin_lock(&gtt->guptasklock);
590 list_del(&guptask.list);
591 spin_unlock(&gtt->guptasklock);
d38ceaf9 592
d38ceaf9
AD		 593 if (r < 0)
594 goto release_pages;
595
596 pinned += r;
597
598 } while (pinned < ttm->num_pages);
599
2f568dbd
CK		 600 return 0;
601
602release_pages:
603 release_pages(pages, pinned, 0);
604 return r;
605}
606
607/* prepare the sg table with the user pages */
608static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
609{
610 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
611 struct amdgpu_ttm_tt *gtt = (void *)ttm;
612 unsigned nents;
613 int r;
614
615 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
616 enum dma_data_direction direction = write ?
617 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
618
d38ceaf9
AD		 619 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
620 ttm->num_pages << PAGE_SHIFT,
621 GFP_KERNEL);
622 if (r)
623 goto release_sg;
624
625 r = -ENOMEM;
626 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
627 if (nents != ttm->sg->nents)
628 goto release_sg;
629
630 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
631 gtt->ttm.dma_address, ttm->num_pages);
632
633 return 0;
634
635release_sg:
636 kfree(ttm->sg);
d38ceaf9
AD		 637 return r;
638}
639
640static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
641{
642 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
643 struct amdgpu_ttm_tt *gtt = (void *)ttm;
dd08fae1 644 struct sg_page_iter sg_iter;
d38ceaf9
AD		 645
646 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
647 enum dma_data_direction direction = write ?
648 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
649
650 /* double check that we don't free the table twice */
651 if (!ttm->sg->sgl)
652 return;
653
654 /* free the sg table and pages again */
655 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
656
dd08fae1 657 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
658 struct page *page = sg_page_iter_page(&sg_iter);
d38ceaf9
AD		 659 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
660 set_page_dirty(page);
661
662 mark_page_accessed(page);
09cbfeaf 663 put_page(page);
d38ceaf9
AD		 664 }
665
666 sg_free_table(ttm->sg);
667}
668
669static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
670 struct ttm_mem_reg *bo_mem)
671{
672 struct amdgpu_ttm_tt *gtt = (void*)ttm;
d38ceaf9
AD		 673 int r;
674
e2f784fa
CZ		 675 if (gtt->userptr) {
676 r = amdgpu_ttm_tt_pin_userptr(ttm);
677 if (r) {
678 DRM_ERROR("failed to pin userptr\n");
679 return r;
680 }
681 }
d38ceaf9
AD		 682 if (!ttm->num_pages) {
683 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
684 ttm->num_pages, bo_mem, ttm);
685 }
686
687 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
688 bo_mem->mem_type == AMDGPU_PL_GWS ||
689 bo_mem->mem_type == AMDGPU_PL_OA)
690 return -EINVAL;
691
c855e250
CK		 692 return 0;
693}
694
695bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
696{
697 struct amdgpu_ttm_tt *gtt = (void *)ttm;
698
699 return gtt && !list_empty(&gtt->list);
700}
701
bb990bb0 702int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
c855e250 703{
bb990bb0
CK		 704 struct ttm_tt *ttm = bo->ttm;
705 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
c855e250
CK		 706 uint32_t flags;
707 int r;
708
709 if (!ttm || amdgpu_ttm_is_bound(ttm))
710 return 0;
711
bb990bb0
CK		 712 r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo,
713 NULL, bo_mem);
714 if (r) {
715 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r);
716 return r;
717 }
718
c855e250 719 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
bb990bb0 720 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
d38ceaf9
AD		 721 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
722 ttm->pages, gtt->ttm.dma_address, flags);
723
724 if (r) {
71c76a08
CK		 725 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
726 ttm->num_pages, gtt->offset);
d38ceaf9
AD		 727 return r;
728 }
5c1354bd
CZ		 729 spin_lock(&gtt->adev->gtt_list_lock);
730 list_add_tail(&gtt->list, &gtt->adev->gtt_list);
731 spin_unlock(&gtt->adev->gtt_list_lock);
d38ceaf9
AD		 732 return 0;
733}
734
2c0d7318
CZ		 735int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
736{
737 struct amdgpu_ttm_tt *gtt, *tmp;
738 struct ttm_mem_reg bo_mem;
739 uint32_t flags;
740 int r;
741
742 bo_mem.mem_type = TTM_PL_TT;
743 spin_lock(&adev->gtt_list_lock);
744 list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
745 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
746 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
747 gtt->ttm.ttm.pages, gtt->ttm.dma_address,
748 flags);
749 if (r) {
750 spin_unlock(&adev->gtt_list_lock);
71c76a08
CK		 751 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
752 gtt->ttm.ttm.num_pages, gtt->offset);
2c0d7318
CZ		 753 return r;
754 }
755 }
756 spin_unlock(&adev->gtt_list_lock);
757 return 0;
758}
759
d38ceaf9
AD		 760static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
761{
762 struct amdgpu_ttm_tt *gtt = (void *)ttm;
763
85a4b579
CK		 764 if (gtt->userptr)
765 amdgpu_ttm_tt_unpin_userptr(ttm);
766
78ab0a38
CK		 767 if (!amdgpu_ttm_is_bound(ttm))
768 return 0;
769
d38ceaf9
AD		 770 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
771 if (gtt->adev->gart.ready)
772 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
773
5c1354bd
CZ		 774 spin_lock(&gtt->adev->gtt_list_lock);
775 list_del_init(&gtt->list);
776 spin_unlock(&gtt->adev->gtt_list_lock);
777
d38ceaf9
AD		 778 return 0;
779}
780
781static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
782{
783 struct amdgpu_ttm_tt *gtt = (void *)ttm;
784
785 ttm_dma_tt_fini(&gtt->ttm);
786 kfree(gtt);
787}
788
789static struct ttm_backend_func amdgpu_backend_func = {
790 .bind = &amdgpu_ttm_backend_bind,
791 .unbind = &amdgpu_ttm_backend_unbind,
792 .destroy = &amdgpu_ttm_backend_destroy,
793};
794
795static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
796 unsigned long size, uint32_t page_flags,
797 struct page *dummy_read_page)
798{
799 struct amdgpu_device *adev;
800 struct amdgpu_ttm_tt *gtt;
801
802 adev = amdgpu_get_adev(bdev);
803
804 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
805 if (gtt == NULL) {
806 return NULL;
807 }
808 gtt->ttm.ttm.func = &amdgpu_backend_func;
809 gtt->adev = adev;
810 if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
811 kfree(gtt);
812 return NULL;
813 }
5c1354bd 814 INIT_LIST_HEAD(&gtt->list);
d38ceaf9
AD		 815 return &gtt->ttm.ttm;
816}
817
818static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
819{
820 struct amdgpu_device *adev;
821 struct amdgpu_ttm_tt *gtt = (void *)ttm;
822 unsigned i;
823 int r;
824 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
825
826 if (ttm->state != tt_unpopulated)
827 return 0;
828
829 if (gtt && gtt->userptr) {
5f0b34cc 830 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
d38ceaf9
AD		 831 if (!ttm->sg)
832 return -ENOMEM;
833
834 ttm->page_flags |= TTM_PAGE_FLAG_SG;
835 ttm->state = tt_unbound;
836 return 0;
837 }
838
839 if (slave && ttm->sg) {
840 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
841 gtt->ttm.dma_address, ttm->num_pages);
842 ttm->state = tt_unbound;
843 return 0;
844 }
845
846 adev = amdgpu_get_adev(ttm->bdev);
847
848#ifdef CONFIG_SWIOTLB
849 if (swiotlb_nr_tbl()) {
850 return ttm_dma_populate(&gtt->ttm, adev->dev);
851 }
852#endif
853
854 r = ttm_pool_populate(ttm);
855 if (r) {
856 return r;
857 }
858
859 for (i = 0; i < ttm->num_pages; i++) {
860 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
861 0, PAGE_SIZE,
862 PCI_DMA_BIDIRECTIONAL);
863 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
09ccbb74 864 while (i--) {
d38ceaf9
AD		 865 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
866 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
867 gtt->ttm.dma_address[i] = 0;
868 }
869 ttm_pool_unpopulate(ttm);
870 return -EFAULT;
871 }
872 }
873 return 0;
874}
875
876static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
877{
878 struct amdgpu_device *adev;
879 struct amdgpu_ttm_tt *gtt = (void *)ttm;
880 unsigned i;
881 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
882
883 if (gtt && gtt->userptr) {
884 kfree(ttm->sg);
885 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
886 return;
887 }
888
889 if (slave)
890 return;
891
892 adev = amdgpu_get_adev(ttm->bdev);
893
894#ifdef CONFIG_SWIOTLB
895 if (swiotlb_nr_tbl()) {
896 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
897 return;
898 }
899#endif
900
901 for (i = 0; i < ttm->num_pages; i++) {
902 if (gtt->ttm.dma_address[i]) {
903 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
904 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
905 }
906 }
907
908 ttm_pool_unpopulate(ttm);
909}
910
911int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
912 uint32_t flags)
913{
914 struct amdgpu_ttm_tt *gtt = (void *)ttm;
915
916 if (gtt == NULL)
917 return -EINVAL;
918
919 gtt->userptr = addr;
920 gtt->usermm = current->mm;
921 gtt->userflags = flags;
637dd3b5
CK		 922 spin_lock_init(&gtt->guptasklock);
923 INIT_LIST_HEAD(&gtt->guptasks);
2f568dbd 924 atomic_set(&gtt->mmu_invalidations, 0);
637dd3b5 925
d38ceaf9
AD		 926 return 0;
927}
928
cc325d19 929struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
d38ceaf9
AD		 930{
931 struct amdgpu_ttm_tt *gtt = (void *)ttm;
932
933 if (gtt == NULL)
cc325d19 934 return NULL;
d38ceaf9 935
cc325d19 936 return gtt->usermm;
d38ceaf9
AD		 937}
938
cc1de6e8
CK		 939bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
940 unsigned long end)
941{
942 struct amdgpu_ttm_tt *gtt = (void *)ttm;
637dd3b5 943 struct amdgpu_ttm_gup_task_list *entry;
cc1de6e8
CK		 944 unsigned long size;
945
637dd3b5 946 if (gtt == NULL || !gtt->userptr)
cc1de6e8
CK		 947 return false;
948
949 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
950 if (gtt->userptr > end || gtt->userptr + size <= start)
951 return false;
952
637dd3b5
CK		 953 spin_lock(&gtt->guptasklock);
954 list_for_each_entry(entry, &gtt->guptasks, list) {
955 if (entry->task == current) {
956 spin_unlock(&gtt->guptasklock);
957 return false;
958 }
959 }
960 spin_unlock(&gtt->guptasklock);
961
2f568dbd
CK		 962 atomic_inc(&gtt->mmu_invalidations);
963
cc1de6e8
CK		 964 return true;
965}
966
2f568dbd
CK		 967bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
968 int *last_invalidated)
969{
970 struct amdgpu_ttm_tt *gtt = (void *)ttm;
971 int prev_invalidated = *last_invalidated;
972
973 *last_invalidated = atomic_read(&gtt->mmu_invalidations);
974 return prev_invalidated != *last_invalidated;
975}
976
d38ceaf9
AD		 977bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
978{
979 struct amdgpu_ttm_tt *gtt = (void *)ttm;
980
981 if (gtt == NULL)
982 return false;
983
984 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
985}
986
987uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
988 struct ttm_mem_reg *mem)
989{
990 uint32_t flags = 0;
991
992 if (mem && mem->mem_type != TTM_PL_SYSTEM)
993 flags |= AMDGPU_PTE_VALID;
994
6d99905a 995 if (mem && mem->mem_type == TTM_PL_TT) {
d38ceaf9
AD		 996 flags |= AMDGPU_PTE_SYSTEM;
997
6d99905a
CK		 998 if (ttm->caching_state == tt_cached)
999 flags |= AMDGPU_PTE_SNOOPED;
1000 }
d38ceaf9 1001
8f3c1629 1002 if (adev->asic_type >= CHIP_TONGA)
d38ceaf9
AD		 1003 flags |= AMDGPU_PTE_EXECUTABLE;
1004
1005 flags |= AMDGPU_PTE_READABLE;
1006
1007 if (!amdgpu_ttm_tt_is_readonly(ttm))
1008 flags |= AMDGPU_PTE_WRITEABLE;
1009
1010 return flags;
1011}
1012
29b3259a
CK		 1013static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
1014{
1015 struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
1016 unsigned i, j;
1017
1018 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1019 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1020
1021 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1022 if (&tbo->lru == lru->lru[j])
1023 lru->lru[j] = tbo->lru.prev;
1024
1025 if (&tbo->swap == lru->swap_lru)
1026 lru->swap_lru = tbo->swap.prev;
1027 }
1028}
1029
1030static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
1031{
1032 struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
1033 unsigned log2_size = min(ilog2(tbo->num_pages),
1034 AMDGPU_TTM_LRU_SIZE - 1);
1035
1036 return &adev->mman.log2_size[log2_size];
1037}
1038
1039static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
1040{
1041 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1042 struct list_head *res = lru->lru[tbo->mem.mem_type];
1043
1044 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1fdc0b76
CK		 1045 while ((++lru)->lru[tbo->mem.mem_type] == res)
1046 lru->lru[tbo->mem.mem_type] = &tbo->lru;
29b3259a
CK		 1047
1048 return res;
1049}
1050
1051static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
1052{
1053 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1054 struct list_head *res = lru->swap_lru;
1055
1056 lru->swap_lru = &tbo->swap;
1fdc0b76
CK		 1057 while ((++lru)->swap_lru == res)
1058 lru->swap_lru = &tbo->swap;
29b3259a
CK		 1059
1060 return res;
1061}
1062
d38ceaf9
AD		 1063static struct ttm_bo_driver amdgpu_bo_driver = {
1064 .ttm_tt_create = &amdgpu_ttm_tt_create,
1065 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1066 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1067 .invalidate_caches = &amdgpu_invalidate_caches,
1068 .init_mem_type = &amdgpu_init_mem_type,
1069 .evict_flags = &amdgpu_evict_flags,
1070 .move = &amdgpu_bo_move,
1071 .verify_access = &amdgpu_verify_access,
1072 .move_notify = &amdgpu_bo_move_notify,
1073 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1074 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1075 .io_mem_free = &amdgpu_ttm_io_mem_free,
29b3259a
CK		 1076 .lru_removal = &amdgpu_ttm_lru_removal,
1077 .lru_tail = &amdgpu_ttm_lru_tail,
1078 .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
d38ceaf9
AD		 1079};
1080
1081int amdgpu_ttm_init(struct amdgpu_device *adev)
1082{
29b3259a 1083 unsigned i, j;
d38ceaf9
AD		 1084 int r;
1085
d38ceaf9
AD		 1086 /* No others user of address space so set it to 0 */
1087 r = ttm_bo_device_init(&adev->mman.bdev,
1088 adev->mman.bo_global_ref.ref.object,
1089 &amdgpu_bo_driver,
1090 adev->ddev->anon_inode->i_mapping,
1091 DRM_FILE_PAGE_OFFSET,
1092 adev->need_dma32);
1093 if (r) {
1094 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1095 return r;
1096 }
29b3259a
CK		 1097
1098 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1099 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1100
1101 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1102 lru->lru[j] = &adev->mman.bdev.man[j].lru;
1103 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1104 }
1105
1fdc0b76
CK		 1106 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1107 adev->mman.guard.lru[j] = NULL;
1108 adev->mman.guard.swap_lru = NULL;
1109
d38ceaf9
AD		 1110 adev->mman.initialized = true;
1111 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1112 adev->mc.real_vram_size >> PAGE_SHIFT);
1113 if (r) {
1114 DRM_ERROR("Failed initializing VRAM heap.\n");
1115 return r;
1116 }
1117 /* Change the size here instead of the init above so only lpfn is affected */
1118 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1119
1120 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
857d913d
AD		 1121 AMDGPU_GEM_DOMAIN_VRAM,
1122 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b 1123 NULL, NULL, &adev->stollen_vga_memory);
d38ceaf9
AD		 1124 if (r) {
1125 return r;
1126 }
1127 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1128 if (r)
1129 return r;
1130 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1131 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1132 if (r) {
1133 amdgpu_bo_unref(&adev->stollen_vga_memory);
1134 return r;
1135 }
1136 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1137 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1138 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1139 adev->mc.gtt_size >> PAGE_SHIFT);
1140 if (r) {
1141 DRM_ERROR("Failed initializing GTT heap.\n");
1142 return r;
1143 }
1144 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1145 (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1146
1147 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1148 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1149 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1150 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1151 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1152 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1153 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1154 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1155 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1156 /* GDS Memory */
1157 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1158 adev->gds.mem.total_size >> PAGE_SHIFT);
1159 if (r) {
1160 DRM_ERROR("Failed initializing GDS heap.\n");
1161 return r;
1162 }
1163
1164 /* GWS */
1165 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1166 adev->gds.gws.total_size >> PAGE_SHIFT);
1167 if (r) {
1168 DRM_ERROR("Failed initializing gws heap.\n");
1169 return r;
1170 }
1171
1172 /* OA */
1173 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1174 adev->gds.oa.total_size >> PAGE_SHIFT);
1175 if (r) {
1176 DRM_ERROR("Failed initializing oa heap.\n");
1177 return r;
1178 }
1179
1180 r = amdgpu_ttm_debugfs_init(adev);
1181 if (r) {
1182 DRM_ERROR("Failed to init debugfs\n");
1183 return r;
1184 }
1185 return 0;
1186}
1187
1188void amdgpu_ttm_fini(struct amdgpu_device *adev)
1189{
1190 int r;
1191
1192 if (!adev->mman.initialized)
1193 return;
1194 amdgpu_ttm_debugfs_fini(adev);
1195 if (adev->stollen_vga_memory) {
1196 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1197 if (r == 0) {
1198 amdgpu_bo_unpin(adev->stollen_vga_memory);
1199 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1200 }
1201 amdgpu_bo_unref(&adev->stollen_vga_memory);
1202 }
1203 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1204 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1205 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1206 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1207 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1208 ttm_bo_device_release(&adev->mman.bdev);
1209 amdgpu_gart_fini(adev);
1210 amdgpu_ttm_global_fini(adev);
1211 adev->mman.initialized = false;
1212 DRM_INFO("amdgpu: ttm finalized\n");
1213}
1214
1215/* this should only be called at bootup or when userspace
1216 * isn't running */
1217void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1218{
1219 struct ttm_mem_type_manager *man;
1220
1221 if (!adev->mman.initialized)
1222 return;
1223
1224 man = &adev->mman.bdev.man[TTM_PL_VRAM];
1225 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1226 man->size = size >> PAGE_SHIFT;
1227}
1228
d38ceaf9
AD		 1229int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1230{
1231 struct drm_file *file_priv;
1232 struct amdgpu_device *adev;
d38ceaf9 1233
e176fe17 1234 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
d38ceaf9 1235 return -EINVAL;
d38ceaf9
AD		 1236
1237 file_priv = filp->private_data;
1238 adev = file_priv->minor->dev->dev_private;
e176fe17 1239 if (adev == NULL)
d38ceaf9 1240 return -EINVAL;
e176fe17
CK		 1241
1242 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
d38ceaf9
AD		 1243}
1244
1245int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1246 uint64_t src_offset,
1247 uint64_t dst_offset,
1248 uint32_t byte_count,
1249 struct reservation_object *resv,
e24db985 1250 struct fence **fence, bool direct_submit)
d38ceaf9
AD		 1251{
1252 struct amdgpu_device *adev = ring->adev;
d71518b5
CK		 1253 struct amdgpu_job *job;
1254
d38ceaf9
AD		 1255 uint32_t max_bytes;
1256 unsigned num_loops, num_dw;
1257 unsigned i;
1258 int r;
1259
d38ceaf9
AD		 1260 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1261 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1262 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1263
c7ae72c0
CZ		 1264 /* for IB padding */
1265 while (num_dw & 0x7)
1266 num_dw++;
1267
d71518b5
CK		 1268 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1269 if (r)
9066b0c3 1270 return r;
c7ae72c0
CZ		 1271
1272 if (resv) {
e86f9cee 1273 r = amdgpu_sync_resv(adev, &job->sync, resv,
c7ae72c0
CZ		 1274 AMDGPU_FENCE_OWNER_UNDEFINED);
1275 if (r) {
1276 DRM_ERROR("sync failed (%d).\n", r);
1277 goto error_free;
1278 }
d38ceaf9 1279 }
d38ceaf9
AD		 1280
1281 for (i = 0; i < num_loops; i++) {
1282 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1283
d71518b5
CK		 1284 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1285 dst_offset, cur_size_in_bytes);
d38ceaf9
AD		 1286
1287 src_offset += cur_size_in_bytes;
1288 dst_offset += cur_size_in_bytes;
1289 byte_count -= cur_size_in_bytes;
1290 }
1291
d71518b5
CK		 1292 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1293 WARN_ON(job->ibs[0].length_dw > num_dw);
e24db985
CZ		 1294 if (direct_submit) {
1295 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1296 NULL, NULL, fence);
1297 job->fence = fence_get(*fence);
1298 if (r)
1299 DRM_ERROR("Error scheduling IBs (%d)\n", r);
1300 amdgpu_job_free(job);
1301 } else {
1302 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1303 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1304 if (r)
1305 goto error_free;
1306 }
d38ceaf9 1307
e24db985 1308 return r;
d71518b5 1309
c7ae72c0 1310error_free:
d71518b5 1311 amdgpu_job_free(job);
c7ae72c0 1312 return r;
d38ceaf9
AD		 1313}
1314
59b4a977
FC		 1315int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1316 uint32_t src_data,
1317 struct reservation_object *resv,
1318 struct fence **fence)
1319{
1320 struct amdgpu_device *adev = bo->adev;
1321 struct amdgpu_job *job;
1322 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1323
1324 uint32_t max_bytes, byte_count;
1325 uint64_t dst_offset;
1326 unsigned int num_loops, num_dw;
1327 unsigned int i;
1328 int r;
1329
1330 byte_count = bo->tbo.num_pages << PAGE_SHIFT;
1331 max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1332 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1333 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1334
1335 /* for IB padding */
1336 while (num_dw & 0x7)
1337 num_dw++;
1338
1339 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1340 if (r)
1341 return r;
1342
1343 if (resv) {
1344 r = amdgpu_sync_resv(adev, &job->sync, resv,
1345 AMDGPU_FENCE_OWNER_UNDEFINED);
1346 if (r) {
1347 DRM_ERROR("sync failed (%d).\n", r);
1348 goto error_free;
1349 }
1350 }
1351
1352 dst_offset = bo->tbo.mem.start << PAGE_SHIFT;
1353 for (i = 0; i < num_loops; i++) {
1354 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1355
1356 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1357 dst_offset, cur_size_in_bytes);
1358
1359 dst_offset += cur_size_in_bytes;
1360 byte_count -= cur_size_in_bytes;
1361 }
1362
1363 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1364 WARN_ON(job->ibs[0].length_dw > num_dw);
1365 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1366 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1367 if (r)
1368 goto error_free;
1369
1370 return 0;
1371
1372error_free:
1373 amdgpu_job_free(job);
1374 return r;
1375}
1376
d38ceaf9
AD		 1377#if defined(CONFIG_DEBUG_FS)
1378
1379static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1380{
1381 struct drm_info_node *node = (struct drm_info_node *)m->private;
1382 unsigned ttm_pl = *(int *)node->info_ent->data;
1383 struct drm_device *dev = node->minor->dev;
1384 struct amdgpu_device *adev = dev->dev_private;
1385 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1386 int ret;
1387 struct ttm_bo_global *glob = adev->mman.bdev.glob;
1388
1389 spin_lock(&glob->lru_lock);
1390 ret = drm_mm_dump_table(m, mm);
1391 spin_unlock(&glob->lru_lock);
a2ef8a97 1392 if (ttm_pl == TTM_PL_VRAM)
e1b35f61 1393 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
a2ef8a97 1394 adev->mman.bdev.man[ttm_pl].size,
e1b35f61
AB		 1395 (u64)atomic64_read(&adev->vram_usage) >> 20,
1396 (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
d38ceaf9
AD		 1397 return ret;
1398}
1399
1400static int ttm_pl_vram = TTM_PL_VRAM;
1401static int ttm_pl_tt = TTM_PL_TT;
1402
06ab6832 1403static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
d38ceaf9
AD		 1404 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1405 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1406 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1407#ifdef CONFIG_SWIOTLB
1408 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1409#endif
1410};
1411
1412static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1413 size_t size, loff_t *pos)
1414{
1415 struct amdgpu_device *adev = f->f_inode->i_private;
1416 ssize_t result = 0;
1417 int r;
1418
1419 if (size & 0x3 || *pos & 0x3)
1420 return -EINVAL;
1421
1422 while (size) {
1423 unsigned long flags;
1424 uint32_t value;
1425
1426 if (*pos >= adev->mc.mc_vram_size)
1427 return result;
1428
1429 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1430 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1431 WREG32(mmMM_INDEX_HI, *pos >> 31);
1432 value = RREG32(mmMM_DATA);
1433 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1434
1435 r = put_user(value, (uint32_t *)buf);
1436 if (r)
1437 return r;
1438
1439 result += 4;
1440 buf += 4;
1441 *pos += 4;
1442 size -= 4;
1443 }
1444
1445 return result;
1446}
1447
1448static const struct file_operations amdgpu_ttm_vram_fops = {
1449 .owner = THIS_MODULE,
1450 .read = amdgpu_ttm_vram_read,
1451 .llseek = default_llseek
1452};
1453
a1d29476
CK		 1454#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1455
d38ceaf9
AD		 1456static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1457 size_t size, loff_t *pos)
1458{
1459 struct amdgpu_device *adev = f->f_inode->i_private;
1460 ssize_t result = 0;
1461 int r;
1462
1463 while (size) {
1464 loff_t p = *pos / PAGE_SIZE;
1465 unsigned off = *pos & ~PAGE_MASK;
1466 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1467 struct page *page;
1468 void *ptr;
1469
1470 if (p >= adev->gart.num_cpu_pages)
1471 return result;
1472
1473 page = adev->gart.pages[p];
1474 if (page) {
1475 ptr = kmap(page);
1476 ptr += off;
1477
1478 r = copy_to_user(buf, ptr, cur_size);
1479 kunmap(adev->gart.pages[p]);
1480 } else
1481 r = clear_user(buf, cur_size);
1482
1483 if (r)
1484 return -EFAULT;
1485
1486 result += cur_size;
1487 buf += cur_size;
1488 *pos += cur_size;
1489 size -= cur_size;
1490 }
1491
1492 return result;
1493}
1494
1495static const struct file_operations amdgpu_ttm_gtt_fops = {
1496 .owner = THIS_MODULE,
1497 .read = amdgpu_ttm_gtt_read,
1498 .llseek = default_llseek
1499};
1500
1501#endif
1502
a1d29476
CK		 1503#endif
1504
d38ceaf9
AD		 1505static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1506{
1507#if defined(CONFIG_DEBUG_FS)
1508 unsigned count;
1509
1510 struct drm_minor *minor = adev->ddev->primary;
1511 struct dentry *ent, *root = minor->debugfs_root;
1512
1513 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1514 adev, &amdgpu_ttm_vram_fops);
1515 if (IS_ERR(ent))
1516 return PTR_ERR(ent);
1517 i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1518 adev->mman.vram = ent;
1519
a1d29476 1520#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9
AD		 1521 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1522 adev, &amdgpu_ttm_gtt_fops);
1523 if (IS_ERR(ent))
1524 return PTR_ERR(ent);
1525 i_size_write(ent->d_inode, adev->mc.gtt_size);
1526 adev->mman.gtt = ent;
1527
a1d29476 1528#endif
d38ceaf9
AD		 1529 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1530
1531#ifdef CONFIG_SWIOTLB
1532 if (!swiotlb_nr_tbl())
1533 --count;
1534#endif
1535
1536 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1537#else
1538
1539 return 0;
1540#endif
1541}
1542
1543static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1544{
1545#if defined(CONFIG_DEBUG_FS)
1546
1547 debugfs_remove(adev->mman.vram);
1548 adev->mman.vram = NULL;
1549
a1d29476 1550#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9
AD		 1551 debugfs_remove(adev->mman.gtt);
1552 adev->mman.gtt = NULL;
1553#endif
a1d29476
CK		 1554
1555#endif
d38ceaf9 1556}
a693e050
KW		 1557
1558u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev)
1559{
1560 return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object);
1561}
Linux 6.x block layer and io_uring tree(s)