[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_object.h

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#ifndef __AMDGPU_OBJECT_H__
#define __AMDGPU_OBJECT_H__

#include <drm/amdgpu_drm.h>
#include "amdgpu.h"

#define AMDGPU_BO_INVALID_OFFSET	LONG_MAX
#define AMDGPU_BO_MAX_PLACEMENTS	3

struct amdgpu_bo_param {
	unsigned long			size;
	int				byte_align;
	u32				domain;
	u32				preferred_domain;
	u64				flags;
	enum ttm_bo_type		type;
	bool				no_wait_gpu;
	struct dma_resv	*resv;
};

/* bo virtual addresses in a vm */
struct amdgpu_bo_va_mapping {
	struct amdgpu_bo_va		*bo_va;
	struct list_head		list;
	struct rb_node			rb;
	uint64_t			start;
	uint64_t			last;
	uint64_t			__subtree_last;
	uint64_t			offset;
	uint64_t			flags;
};

/* User space allocated BO in a VM */
struct amdgpu_bo_va {
	struct amdgpu_vm_bo_base	base;

	/* protected by bo being reserved */
	unsigned			ref_count;

	/* all other members protected by the VM PD being reserved */
	struct dma_fence	        *last_pt_update;

	/* mappings for this bo_va */
	struct list_head		invalids;
	struct list_head		valids;

	/* If the mappings are cleared or filled */
	bool				cleared;

	bool				is_xgmi;
};

struct amdgpu_bo {
	/* Protected by tbo.reserved */
	u32				preferred_domains;
	u32				allowed_domains;
	struct ttm_place		placements[AMDGPU_BO_MAX_PLACEMENTS];
	struct ttm_placement		placement;
	struct ttm_buffer_object	tbo;
	struct ttm_bo_kmap_obj		kmap;
	u64				flags;
	unsigned			pin_count;
	u64				tiling_flags;
	u64				metadata_flags;
	void				*metadata;
	u32				metadata_size;
	unsigned			prime_shared_count;
	/* per VM structure for page tables and with virtual addresses */
	struct amdgpu_vm_bo_base	*vm_bo;
	/* Constant after initialization */
	struct amdgpu_bo		*parent;
	struct amdgpu_bo		*shadow;

	struct ttm_bo_kmap_obj		dma_buf_vmap;
	struct amdgpu_mn		*mn;

	union {
		struct list_head	mn_list;
		struct list_head	shadow_list;
	};

	struct kgd_mem                  *kfd_bo;
};

static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
{
	return container_of(tbo, struct amdgpu_bo, tbo);
}

/**
 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
 * @mem_type:	ttm memory type
 *
 * Returns corresponding domain of the ttm mem_type
 */
static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
{
	switch (mem_type) {
	case TTM_PL_VRAM:
		return AMDGPU_GEM_DOMAIN_VRAM;
	case TTM_PL_TT:
		return AMDGPU_GEM_DOMAIN_GTT;
	case TTM_PL_SYSTEM:
		return AMDGPU_GEM_DOMAIN_CPU;
	case AMDGPU_PL_GDS:
		return AMDGPU_GEM_DOMAIN_GDS;
	case AMDGPU_PL_GWS:
		return AMDGPU_GEM_DOMAIN_GWS;
	case AMDGPU_PL_OA:
		return AMDGPU_GEM_DOMAIN_OA;
	default:
		break;
	}
	return 0;
}

/**
 * amdgpu_bo_reserve - reserve bo
 * @bo:		bo structure
 * @no_intr:	don't return -ERESTARTSYS on pending signal
 *
 * Returns:
 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
 * a signal. Release all buffer reservations and return to user-space.
 */
static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
{
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
	int r;

	r = __ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
	if (unlikely(r != 0)) {
		if (r != -ERESTARTSYS)
			dev_err(adev->dev, "%p reserve failed\n", bo);
		return r;
	}
	return 0;
}

static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
{
	ttm_bo_unreserve(&bo->tbo);
}

static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
{
	return bo->tbo.num_pages << PAGE_SHIFT;
}

static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
{
	return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
}

static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
{
	return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
}

/**
 * amdgpu_bo_mmap_offset - return mmap offset of bo
 * @bo:	amdgpu object for which we query the offset
 *
 * Returns mmap offset of the object.
 */
static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
{
	return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
}

/**
 * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM
 */
static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
{
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
	unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
	struct drm_mm_node *node = bo->tbo.mem.mm_node;
	unsigned long pages_left;

	if (bo->tbo.mem.mem_type != TTM_PL_VRAM)
		return false;

	for (pages_left = bo->tbo.mem.num_pages; pages_left;
	     pages_left -= node->size, node++)
		if (node->start < fpfn)
			return true;

	return false;
}

/**
 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
 */
static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
{
	return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
}

bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);

int amdgpu_bo_create(struct amdgpu_device *adev,
		     struct amdgpu_bo_param *bp,
		     struct amdgpu_bo **bo_ptr);
int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
			      unsigned long size, int align,
			      u32 domain, struct amdgpu_bo **bo_ptr,
			      u64 *gpu_addr, void **cpu_addr);
int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
			    unsigned long size, int align,
			    u32 domain, struct amdgpu_bo **bo_ptr,
			    u64 *gpu_addr, void **cpu_addr);
void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
			   void **cpu_addr);
int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
void amdgpu_bo_unref(struct amdgpu_bo **bo);
int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
			     u64 min_offset, u64 max_offset);
int amdgpu_bo_unpin(struct amdgpu_bo *bo);
int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
int amdgpu_bo_init(struct amdgpu_device *adev);
int amdgpu_bo_late_init(struct amdgpu_device *adev);
void amdgpu_bo_fini(struct amdgpu_device *adev);
int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
				struct vm_area_struct *vma);
int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
			    uint32_t metadata_size, uint64_t flags);
int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
			   size_t buffer_size, uint32_t *metadata_size,
			   uint64_t *flags);
void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
			   bool evict,
			   struct ttm_mem_reg *new_mem);
void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
		     bool shared);
int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
int amdgpu_bo_validate(struct amdgpu_bo *bo);
int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
			     struct dma_fence **fence);
uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
					    uint32_t domain);

/*
 * sub allocation
 */

static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
{
	return sa_bo->manager->gpu_addr + sa_bo->soffset;
}

static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
{
	return sa_bo->manager->cpu_ptr + sa_bo->soffset;
}

int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
				     struct amdgpu_sa_manager *sa_manager,
				     unsigned size, u32 align, u32 domain);
void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
				      struct amdgpu_sa_manager *sa_manager);
int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
				      struct amdgpu_sa_manager *sa_manager);
int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
		     struct amdgpu_sa_bo **sa_bo,
		     unsigned size, unsigned align);
void amdgpu_sa_bo_free(struct amdgpu_device *adev,
			      struct amdgpu_sa_bo **sa_bo,
			      struct dma_fence *fence);
#if defined(CONFIG_DEBUG_FS)
void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
					 struct seq_file *m);
#endif

bool amdgpu_bo_support_uswc(u64 bo_flags);


#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#ifndef __AMDGPU_OBJECT_H__
	29	#define __AMDGPU_OBJECT_H__
	30
	31	#include <drm/amdgpu_drm.h>
	32	#include "amdgpu.h"
	33
9702d40d	34	#define AMDGPU_BO_INVALID_OFFSET LONG_MAX
bf314ca3	35	#define AMDGPU_BO_MAX_PLACEMENTS 3
9702d40d	36
a906dbb1 CZ	37	struct amdgpu_bo_param {
	38	unsigned long size;
	39	int byte_align;
	40	u32 domain;
aa2b2e28	41	u32 preferred_domain;
a906dbb1 CZ	42	u64 flags;
a906dbb1 CZ	43	enum ttm_bo_type type;
061468c4	44	bool no_wait_gpu;
52791eee	45	struct dma_resv *resv;
a906dbb1 CZ	46	};
a906dbb1 CZ	47
ec681545	48	/* bo virtual addresses in a vm */
9124a398	49	struct amdgpu_bo_va_mapping {
aebc5e6f	50	struct amdgpu_bo_va *bo_va;
9124a398 CK	51	struct list_head list;
	52	struct rb_node rb;
	53	uint64_t start;
	54	uint64_t last;
	55	uint64_t __subtree_last;
	56	uint64_t offset;
	57	uint64_t flags;
	58	};
	59
ec681545	60	/* User space allocated BO in a VM */
9124a398	61	struct amdgpu_bo_va {
ec681545 CK	62	struct amdgpu_vm_bo_base base;
ec681545 CK	63
9124a398	64	/* protected by bo being reserved */
9124a398 CK	65	unsigned ref_count;
9124a398 CK	66
00b5cc83 CK	67	/* all other members protected by the VM PD being reserved */
	68	struct dma_fence *last_pt_update;
	69
9124a398 CK	70	/* mappings for this bo_va */
	71	struct list_head invalids;
	72	struct list_head valids;
cb7b6ec2 CK	73
	74	/* If the mappings are cleared or filled */
	75	bool cleared;
df399b06	76
df399b06	77	bool is_xgmi;
9124a398 CK	78	};
9124a398 CK	79
9124a398 CK	80	struct amdgpu_bo {
9124a398 CK	81	/* Protected by tbo.reserved */
6d7d9c5a	82	u32 preferred_domains;
9124a398	83	u32 allowed_domains;
bf314ca3	84	struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS];
9124a398 CK	85	struct ttm_placement placement;
	86	struct ttm_buffer_object tbo;
	87	struct ttm_bo_kmap_obj kmap;
	88	u64 flags;
	89	unsigned pin_count;
	90	u64 tiling_flags;
	91	u64 metadata_flags;
	92	void *metadata;
	93	u32 metadata_size;
	94	unsigned prime_shared_count;
646b9025 CK	95	/* per VM structure for page tables and with virtual addresses */
646b9025 CK	96	struct amdgpu_vm_bo_base *vm_bo;
9124a398	97	/* Constant after initialization */
9124a398 CK	98	struct amdgpu_bo *parent;
	99	struct amdgpu_bo *shadow;
	100
	101	struct ttm_bo_kmap_obj dma_buf_vmap;
	102	struct amdgpu_mn *mn;
ed5b89c6 CK	103
	104	union {
	105	struct list_head mn_list;
	106	struct list_head shadow_list;
	107	};
a46a2cd1 FK	108
a46a2cd1 FK	109	struct kgd_mem *kfd_bo;
9124a398 CK	110	};
9124a398 CK	111
b82485fd AR	112	static inline struct amdgpu_bo ttm_to_amdgpu_bo(struct ttm_buffer_object tbo)
	113	{
	114	return container_of(tbo, struct amdgpu_bo, tbo);
	115	}
	116
d38ceaf9 AD	117	/**
	118	* amdgpu_mem_type_to_domain - return domain corresponding to mem_type
	119	* @mem_type: ttm memory type
	120	*
	121	* Returns corresponding domain of the ttm mem_type
	122	*/
	123	static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
	124	{
	125	switch (mem_type) {
	126	case TTM_PL_VRAM:
	127	return AMDGPU_GEM_DOMAIN_VRAM;
	128	case TTM_PL_TT:
	129	return AMDGPU_GEM_DOMAIN_GTT;
	130	case TTM_PL_SYSTEM:
	131	return AMDGPU_GEM_DOMAIN_CPU;
	132	case AMDGPU_PL_GDS:
	133	return AMDGPU_GEM_DOMAIN_GDS;
	134	case AMDGPU_PL_GWS:
	135	return AMDGPU_GEM_DOMAIN_GWS;
	136	case AMDGPU_PL_OA:
	137	return AMDGPU_GEM_DOMAIN_OA;
	138	default:
	139	break;
	140	}
	141	return 0;
	142	}
	143
	144	/**
	145	* amdgpu_bo_reserve - reserve bo
	146	* @bo: bo structure
	147	* @no_intr: don't return -ERESTARTSYS on pending signal
	148	*
	149	* Returns:
	150	* -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
	151	* a signal. Release all buffer reservations and return to user-space.
	152	*/
	153	static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
	154	{
a7d64de6	155	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
d38ceaf9 AD	156	int r;
d38ceaf9 AD	157
55c2e5a1	158	r = __ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
d38ceaf9 AD	159	if (unlikely(r != 0)) {
d38ceaf9 AD	160	if (r != -ERESTARTSYS)
a7d64de6	161	dev_err(adev->dev, "%p reserve failed\n", bo);
d38ceaf9 AD	162	return r;
	163	}
	164	return 0;
	165	}
	166
	167	static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
	168	{
	169	ttm_bo_unreserve(&bo->tbo);
	170	}
	171
d38ceaf9 AD	172	static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
	173	{
	174	return bo->tbo.num_pages << PAGE_SHIFT;
	175	}
	176
	177	static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
	178	{
	179	return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
	180	}
	181
	182	static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
	183	{
	184	return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
	185	}
	186
	187	/**
	188	* amdgpu_bo_mmap_offset - return mmap offset of bo
	189	* @bo: amdgpu object for which we query the offset
	190	*
	191	* Returns mmap offset of the object.
	192	*/
	193	static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
	194	{
b96f3e7c	195	return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
d38ceaf9 AD	196	}
d38ceaf9 AD	197
5422a28f CK	198	/**
	199	* amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM
	200	*/
	201	static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
	202	{
	203	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
	204	unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
	205	struct drm_mm_node *node = bo->tbo.mem.mm_node;
	206	unsigned long pages_left;
	207
	208	if (bo->tbo.mem.mem_type != TTM_PL_VRAM)
	209	return false;
	210
	211	for (pages_left = bo->tbo.mem.num_pages; pages_left;
	212	pages_left -= node->size, node++)
	213	if (node->start < fpfn)
	214	return true;
	215
	216	return false;
	217	}
	218
177ae09b AR	219	/**
	220	* amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
	221	*/
	222	static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
	223	{
	224	return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
	225	}
	226
c704ab18 CK	227	bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
	228	void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
	229
3216c6b7 CZ	230	int amdgpu_bo_create(struct amdgpu_device *adev,
3216c6b7 CZ	231	struct amdgpu_bo_param *bp,
eab3de23	232	struct amdgpu_bo **bo_ptr);
9d903cbd CK	233	int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
	234	unsigned long size, int align,
	235	u32 domain, struct amdgpu_bo **bo_ptr,
	236	u64 gpu_addr, void *cpu_addr);
7c204889 CK	237	int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
	238	unsigned long size, int align,
	239	u32 domain, struct amdgpu_bo **bo_ptr,
	240	u64 gpu_addr, void *cpu_addr);
aa1d562e JZ	241	void amdgpu_bo_free_kernel(struct amdgpu_bo *bo, u64 gpu_addr,
aa1d562e JZ	242	void **cpu_addr);
d38ceaf9	243	int amdgpu_bo_kmap(struct amdgpu_bo bo, void *ptr);
f5e1c740	244	void amdgpu_bo_kptr(struct amdgpu_bo bo);
d38ceaf9 AD	245	void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
	246	struct amdgpu_bo amdgpu_bo_ref(struct amdgpu_bo bo);
	247	void amdgpu_bo_unref(struct amdgpu_bo **bo);
7b7c6c81	248	int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
d38ceaf9	249	int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
7b7c6c81	250	u64 min_offset, u64 max_offset);
d38ceaf9 AD	251	int amdgpu_bo_unpin(struct amdgpu_bo *bo);
d38ceaf9 AD	252	int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
d38ceaf9	253	int amdgpu_bo_init(struct amdgpu_device *adev);
6f752ec2	254	int amdgpu_bo_late_init(struct amdgpu_device *adev);
d38ceaf9 AD	255	void amdgpu_bo_fini(struct amdgpu_device *adev);
	256	int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
	257	struct vm_area_struct *vma);
	258	int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
	259	void amdgpu_bo_get_tiling_flags(struct amdgpu_bo bo, u64 tiling_flags);
	260	int amdgpu_bo_set_metadata (struct amdgpu_bo bo, void metadata,
	261	uint32_t metadata_size, uint64_t flags);
	262	int amdgpu_bo_get_metadata(struct amdgpu_bo bo, void buffer,
	263	size_t buffer_size, uint32_t *metadata_size,
	264	uint64_t *flags);
	265	void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
66257db7 NH	266	bool evict,
66257db7 NH	267	struct ttm_mem_reg *new_mem);
ab2f7a5c	268	void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
d38ceaf9	269	int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
f54d1867	270	void amdgpu_bo_fence(struct amdgpu_bo bo, struct dma_fence fence,
d38ceaf9	271	bool shared);
e8e32426	272	int amdgpu_bo_sync_wait(struct amdgpu_bo bo, void owner, bool intr);
cdb7e8f2	273	u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
82521316	274	int amdgpu_bo_validate(struct amdgpu_bo *bo);
403009bf CK	275	int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
403009bf CK	276	struct dma_fence **fence);
84b74608 DS	277	uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
84b74608 DS	278	uint32_t domain);
d38ceaf9 AD	279
	280	/*
	281	* sub allocation
	282	*/
	283
	284	static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
	285	{
	286	return sa_bo->manager->gpu_addr + sa_bo->soffset;
	287	}
	288
	289	static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
	290	{
	291	return sa_bo->manager->cpu_ptr + sa_bo->soffset;
	292	}
	293
	294	int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
	295	struct amdgpu_sa_manager *sa_manager,
	296	unsigned size, u32 align, u32 domain);
	297	void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
	298	struct amdgpu_sa_manager *sa_manager);
	299	int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
	300	struct amdgpu_sa_manager *sa_manager);
bbf0b345 JZ	301	int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
	302	struct amdgpu_sa_bo **sa_bo,
	303	unsigned size, unsigned align);
d38ceaf9 AD	304	void amdgpu_sa_bo_free(struct amdgpu_device *adev,
d38ceaf9 AD	305	struct amdgpu_sa_bo **sa_bo,
f54d1867	306	struct dma_fence *fence);
d38ceaf9 AD	307	#if defined(CONFIG_DEBUG_FS)
	308	void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
	309	struct seq_file *m);
	310	#endif
	311
3d1b8ec7 AG	312	bool amdgpu_bo_support_uswc(u64 bo_flags);
3d1b8ec7 AG	313
d38ceaf9 AD	314
d38ceaf9 AD	315	#endif