projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'sound-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
45#include <drm/drm_gem.h>
7e5a547f 46#include <drm/amdgpu_drm.h>
97b2e202 47
5fc3aeeb 48#include "amd_shared.h"
97b2e202
AD		 49#include "amdgpu_family.h"
50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
55
56/*
57 * Modules parameters.
58 */
59extern int amdgpu_modeset;
60extern int amdgpu_vram_limit;
61extern int amdgpu_gart_size;
62extern int amdgpu_benchmarking;
63extern int amdgpu_testing;
64extern int amdgpu_audio;
65extern int amdgpu_disp_priority;
66extern int amdgpu_hw_i2c;
67extern int amdgpu_pcie_gen2;
68extern int amdgpu_msi;
69extern int amdgpu_lockup_timeout;
70extern int amdgpu_dpm;
71extern int amdgpu_smc_load_fw;
72extern int amdgpu_aspm;
73extern int amdgpu_runtime_pm;
74extern int amdgpu_hard_reset;
75extern unsigned amdgpu_ip_block_mask;
76extern int amdgpu_bapm;
77extern int amdgpu_deep_color;
78extern int amdgpu_vm_size;
79extern int amdgpu_vm_block_size;
80
81#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
82#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
83/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
84#define AMDGPU_IB_POOL_SIZE 16
85#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
86#define AMDGPUFB_CONN_LIMIT 4
87#define AMDGPU_BIOS_NUM_SCRATCH 8
88
97b2e202
AD		 89/* max number of rings */
90#define AMDGPU_MAX_RINGS 16
91#define AMDGPU_MAX_GFX_RINGS 1
92#define AMDGPU_MAX_COMPUTE_RINGS 8
93#define AMDGPU_MAX_VCE_RINGS 2
94
95/* number of hw syncs before falling back on blocking */
96#define AMDGPU_NUM_SYNCS 4
97
98/* hardcode that limit for now */
99#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
100
101/* hard reset data */
102#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
103
104/* reset flags */
105#define AMDGPU_RESET_GFX (1 << 0)
106#define AMDGPU_RESET_COMPUTE (1 << 1)
107#define AMDGPU_RESET_DMA (1 << 2)
108#define AMDGPU_RESET_CP (1 << 3)
109#define AMDGPU_RESET_GRBM (1 << 4)
110#define AMDGPU_RESET_DMA1 (1 << 5)
111#define AMDGPU_RESET_RLC (1 << 6)
112#define AMDGPU_RESET_SEM (1 << 7)
113#define AMDGPU_RESET_IH (1 << 8)
114#define AMDGPU_RESET_VMC (1 << 9)
115#define AMDGPU_RESET_MC (1 << 10)
116#define AMDGPU_RESET_DISPLAY (1 << 11)
117#define AMDGPU_RESET_UVD (1 << 12)
118#define AMDGPU_RESET_VCE (1 << 13)
119#define AMDGPU_RESET_VCE1 (1 << 14)
120
121/* CG block flags */
122#define AMDGPU_CG_BLOCK_GFX (1 << 0)
123#define AMDGPU_CG_BLOCK_MC (1 << 1)
124#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
125#define AMDGPU_CG_BLOCK_UVD (1 << 3)
126#define AMDGPU_CG_BLOCK_VCE (1 << 4)
127#define AMDGPU_CG_BLOCK_HDP (1 << 5)
128#define AMDGPU_CG_BLOCK_BIF (1 << 6)
129
130/* CG flags */
131#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
132#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
133#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
134#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
135#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
136#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
137#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
138#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
139#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
140#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
141#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
142#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
143#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
144#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
145#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
146#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
147#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
148
149/* PG flags */
150#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
151#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
152#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
153#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
154#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
155#define AMDGPU_PG_SUPPORT_CP (1 << 5)
156#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
157#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
158#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
159#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
160#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
161
162/* GFX current status */
163#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
164#define AMDGPU_GFX_SAFE_MODE 0x00000001L
165#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
166#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
167#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
168
169/* max cursor sizes (in pixels) */
170#define CIK_CURSOR_WIDTH 128
171#define CIK_CURSOR_HEIGHT 128
172
173struct amdgpu_device;
174struct amdgpu_fence;
175struct amdgpu_ib;
176struct amdgpu_vm;
177struct amdgpu_ring;
178struct amdgpu_semaphore;
179struct amdgpu_cs_parser;
180struct amdgpu_irq_src;
181
182enum amdgpu_cp_irq {
183 AMDGPU_CP_IRQ_GFX_EOP = 0,
184 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
185 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
186 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
188 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
189 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
190 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
192
193 AMDGPU_CP_IRQ_LAST
194};
195
196enum amdgpu_sdma_irq {
197 AMDGPU_SDMA_IRQ_TRAP0 = 0,
198 AMDGPU_SDMA_IRQ_TRAP1,
199
200 AMDGPU_SDMA_IRQ_LAST
201};
202
203enum amdgpu_thermal_irq {
204 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
205 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
206
207 AMDGPU_THERMAL_IRQ_LAST
208};
209
97b2e202 210int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 211 enum amd_ip_block_type block_type,
212 enum amd_clockgating_state state);
97b2e202 213int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 214 enum amd_ip_block_type block_type,
215 enum amd_powergating_state state);
97b2e202
AD		 216
217struct amdgpu_ip_block_version {
5fc3aeeb 218 enum amd_ip_block_type type;
97b2e202
AD		 219 u32 major;
220 u32 minor;
221 u32 rev;
5fc3aeeb 222 const struct amd_ip_funcs *funcs;
97b2e202
AD		 223};
224
225int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 226 enum amd_ip_block_type type,
97b2e202
AD		 227 u32 major, u32 minor);
228
229const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
230 struct amdgpu_device *adev,
5fc3aeeb 231 enum amd_ip_block_type type);
97b2e202
AD		 232
233/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
234struct amdgpu_buffer_funcs {
235 /* maximum bytes in a single operation */
236 uint32_t copy_max_bytes;
237
238 /* number of dw to reserve per operation */
239 unsigned copy_num_dw;
240
241 /* used for buffer migration */
242 void (*emit_copy_buffer)(struct amdgpu_ring *ring,
243 /* src addr in bytes */
244 uint64_t src_offset,
245 /* dst addr in bytes */
246 uint64_t dst_offset,
247 /* number of byte to transfer */
248 uint32_t byte_count);
249
250 /* maximum bytes in a single operation */
251 uint32_t fill_max_bytes;
252
253 /* number of dw to reserve per operation */
254 unsigned fill_num_dw;
255
256 /* used for buffer clearing */
257 void (*emit_fill_buffer)(struct amdgpu_ring *ring,
258 /* value to write to memory */
259 uint32_t src_data,
260 /* dst addr in bytes */
261 uint64_t dst_offset,
262 /* number of byte to fill */
263 uint32_t byte_count);
264};
265
266/* provided by hw blocks that can write ptes, e.g., sdma */
267struct amdgpu_vm_pte_funcs {
268 /* copy pte entries from GART */
269 void (*copy_pte)(struct amdgpu_ib *ib,
270 uint64_t pe, uint64_t src,
271 unsigned count);
272 /* write pte one entry at a time with addr mapping */
273 void (*write_pte)(struct amdgpu_ib *ib,
274 uint64_t pe,
275 uint64_t addr, unsigned count,
276 uint32_t incr, uint32_t flags);
277 /* for linear pte/pde updates without addr mapping */
278 void (*set_pte_pde)(struct amdgpu_ib *ib,
279 uint64_t pe,
280 uint64_t addr, unsigned count,
281 uint32_t incr, uint32_t flags);
282 /* pad the indirect buffer to the necessary number of dw */
283 void (*pad_ib)(struct amdgpu_ib *ib);
284};
285
286/* provided by the gmc block */
287struct amdgpu_gart_funcs {
288 /* flush the vm tlb via mmio */
289 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
290 uint32_t vmid);
291 /* write pte/pde updates using the cpu */
292 int (*set_pte_pde)(struct amdgpu_device *adev,
293 void *cpu_pt_addr, /* cpu addr of page table */
294 uint32_t gpu_page_idx, /* pte/pde to update */
295 uint64_t addr, /* addr to write into pte/pde */
296 uint32_t flags); /* access flags */
297};
298
299/* provided by the ih block */
300struct amdgpu_ih_funcs {
301 /* ring read/write ptr handling, called from interrupt context */
302 u32 (*get_wptr)(struct amdgpu_device *adev);
303 void (*decode_iv)(struct amdgpu_device *adev,
304 struct amdgpu_iv_entry *entry);
305 void (*set_rptr)(struct amdgpu_device *adev);
306};
307
308/* provided by hw blocks that expose a ring buffer for commands */
309struct amdgpu_ring_funcs {
310 /* ring read/write ptr handling */
311 u32 (*get_rptr)(struct amdgpu_ring *ring);
312 u32 (*get_wptr)(struct amdgpu_ring *ring);
313 void (*set_wptr)(struct amdgpu_ring *ring);
314 /* validating and patching of IBs */
315 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
316 /* command emit functions */
317 void (*emit_ib)(struct amdgpu_ring *ring,
318 struct amdgpu_ib *ib);
319 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 320 uint64_t seq, unsigned flags);
97b2e202
AD		 321 bool (*emit_semaphore)(struct amdgpu_ring *ring,
322 struct amdgpu_semaphore *semaphore,
323 bool emit_wait);
324 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
325 uint64_t pd_addr);
d2edb07b 326 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 327 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
328 uint32_t gds_base, uint32_t gds_size,
329 uint32_t gws_base, uint32_t gws_size,
330 uint32_t oa_base, uint32_t oa_size);
331 /* testing functions */
332 int (*test_ring)(struct amdgpu_ring *ring);
333 int (*test_ib)(struct amdgpu_ring *ring);
334 bool (*is_lockup)(struct amdgpu_ring *ring);
335};
336
337/*
338 * BIOS.
339 */
340bool amdgpu_get_bios(struct amdgpu_device *adev);
341bool amdgpu_read_bios(struct amdgpu_device *adev);
342
343/*
344 * Dummy page
345 */
346struct amdgpu_dummy_page {
347 struct page *page;
348 dma_addr_t addr;
349};
350int amdgpu_dummy_page_init(struct amdgpu_device *adev);
351void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
352
353
354/*
355 * Clocks
356 */
357
358#define AMDGPU_MAX_PPLL 3
359
360struct amdgpu_clock {
361 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
362 struct amdgpu_pll spll;
363 struct amdgpu_pll mpll;
364 /* 10 Khz units */
365 uint32_t default_mclk;
366 uint32_t default_sclk;
367 uint32_t default_dispclk;
368 uint32_t current_dispclk;
369 uint32_t dp_extclk;
370 uint32_t max_pixel_clock;
371};
372
373/*
374 * Fences.
375 */
376struct amdgpu_fence_driver {
377 struct amdgpu_ring *ring;
378 uint64_t gpu_addr;
379 volatile uint32_t *cpu_addr;
380 /* sync_seq is protected by ring emission lock */
381 uint64_t sync_seq[AMDGPU_MAX_RINGS];
382 atomic64_t last_seq;
383 bool initialized;
384 bool delayed_irq;
385 struct amdgpu_irq_src *irq_src;
386 unsigned irq_type;
387 struct delayed_work lockup_work;
388};
389
390/* some special values for the owner field */
391#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
392#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
393#define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
394
890ee23f
CZ		 395#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
396#define AMDGPU_FENCE_FLAG_INT (1 << 1)
397
97b2e202
AD		 398struct amdgpu_fence {
399 struct fence base;
400
401 /* RB, DMA, etc. */
402 struct amdgpu_ring *ring;
403 uint64_t seq;
404
405 /* filp or special value for fence creator */
406 void *owner;
407
408 wait_queue_t fence_wake;
409};
410
411struct amdgpu_user_fence {
412 /* write-back bo */
413 struct amdgpu_bo *bo;
414 /* write-back address offset to bo start */
415 uint32_t offset;
416};
417
418int amdgpu_fence_driver_init(struct amdgpu_device *adev);
419void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
420void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
421
422void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
423int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
424 struct amdgpu_irq_src *irq_src,
425 unsigned irq_type);
426int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
427 struct amdgpu_fence **fence);
03507c4f
CK		 428int amdgpu_fence_recreate(struct amdgpu_ring *ring, void *owner,
429 uint64_t seq, struct amdgpu_fence **fence);
97b2e202
AD		 430void amdgpu_fence_process(struct amdgpu_ring *ring);
431int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
432int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
433unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
434
435bool amdgpu_fence_signaled(struct amdgpu_fence *fence);
436int amdgpu_fence_wait(struct amdgpu_fence *fence, bool interruptible);
437int amdgpu_fence_wait_any(struct amdgpu_device *adev,
438 struct amdgpu_fence **fences,
439 bool intr);
97b2e202
AD		 440struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
441void amdgpu_fence_unref(struct amdgpu_fence **fence);
442
443bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
444 struct amdgpu_ring *ring);
445void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
446 struct amdgpu_ring *ring);
447
448static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
449 struct amdgpu_fence *b)
450{
451 if (!a) {
452 return b;
453 }
454
455 if (!b) {
456 return a;
457 }
458
459 BUG_ON(a->ring != b->ring);
460
461 if (a->seq > b->seq) {
462 return a;
463 } else {
464 return b;
465 }
466}
467
468static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
469 struct amdgpu_fence *b)
470{
471 if (!a) {
472 return false;
473 }
474
475 if (!b) {
476 return true;
477 }
478
479 BUG_ON(a->ring != b->ring);
480
481 return a->seq < b->seq;
482}
483
484int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user,
485 void *owner, struct amdgpu_fence **fence);
486
487/*
488 * TTM.
489 */
490struct amdgpu_mman {
491 struct ttm_bo_global_ref bo_global_ref;
492 struct drm_global_reference mem_global_ref;
493 struct ttm_bo_device bdev;
494 bool mem_global_referenced;
495 bool initialized;
496
497#if defined(CONFIG_DEBUG_FS)
498 struct dentry *vram;
499 struct dentry *gtt;
500#endif
501
502 /* buffer handling */
503 const struct amdgpu_buffer_funcs *buffer_funcs;
504 struct amdgpu_ring *buffer_funcs_ring;
505};
506
507int amdgpu_copy_buffer(struct amdgpu_ring *ring,
508 uint64_t src_offset,
509 uint64_t dst_offset,
510 uint32_t byte_count,
511 struct reservation_object *resv,
512 struct amdgpu_fence **fence);
513int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
514
515struct amdgpu_bo_list_entry {
516 struct amdgpu_bo *robj;
517 struct ttm_validate_buffer tv;
518 struct amdgpu_bo_va *bo_va;
519 unsigned prefered_domains;
520 unsigned allowed_domains;
521 uint32_t priority;
522};
523
524struct amdgpu_bo_va_mapping {
525 struct list_head list;
526 struct interval_tree_node it;
527 uint64_t offset;
528 uint32_t flags;
529};
530
531/* bo virtual addresses in a specific vm */
532struct amdgpu_bo_va {
533 /* protected by bo being reserved */
534 struct list_head bo_list;
535 uint64_t addr;
536 struct amdgpu_fence *last_pt_update;
537 unsigned ref_count;
538
539 /* protected by vm mutex */
540 struct list_head mappings;
541 struct list_head vm_status;
542
543 /* constant after initialization */
544 struct amdgpu_vm *vm;
545 struct amdgpu_bo *bo;
546};
547
7e5a547f
CZ		 548#define AMDGPU_GEM_DOMAIN_MAX 0x3
549
97b2e202
AD		 550struct amdgpu_bo {
551 /* Protected by gem.mutex */
552 struct list_head list;
553 /* Protected by tbo.reserved */
554 u32 initial_domain;
7e5a547f 555 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 556 struct ttm_placement placement;
557 struct ttm_buffer_object tbo;
558 struct ttm_bo_kmap_obj kmap;
559 u64 flags;
560 unsigned pin_count;
561 void *kptr;
562 u64 tiling_flags;
563 u64 metadata_flags;
564 void *metadata;
565 u32 metadata_size;
566 /* list of all virtual address to which this bo
567 * is associated to
568 */
569 struct list_head va;
570 /* Constant after initialization */
571 struct amdgpu_device *adev;
572 struct drm_gem_object gem_base;
573
574 struct ttm_bo_kmap_obj dma_buf_vmap;
575 pid_t pid;
576 struct amdgpu_mn *mn;
577 struct list_head mn_list;
578};
579#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
580
581void amdgpu_gem_object_free(struct drm_gem_object *obj);
582int amdgpu_gem_object_open(struct drm_gem_object *obj,
583 struct drm_file *file_priv);
584void amdgpu_gem_object_close(struct drm_gem_object *obj,
585 struct drm_file *file_priv);
586unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
587struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
588struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
589 struct dma_buf_attachment *attach,
590 struct sg_table *sg);
591struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
592 struct drm_gem_object *gobj,
593 int flags);
594int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
595void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
596struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
597void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
598void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
599int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
600
601/* sub-allocation manager, it has to be protected by another lock.
602 * By conception this is an helper for other part of the driver
603 * like the indirect buffer or semaphore, which both have their
604 * locking.
605 *
606 * Principe is simple, we keep a list of sub allocation in offset
607 * order (first entry has offset == 0, last entry has the highest
608 * offset).
609 *
610 * When allocating new object we first check if there is room at
611 * the end total_size - (last_object_offset + last_object_size) >=
612 * alloc_size. If so we allocate new object there.
613 *
614 * When there is not enough room at the end, we start waiting for
615 * each sub object until we reach object_offset+object_size >=
616 * alloc_size, this object then become the sub object we return.
617 *
618 * Alignment can't be bigger than page size.
619 *
620 * Hole are not considered for allocation to keep things simple.
621 * Assumption is that there won't be hole (all object on same
622 * alignment).
623 */
624struct amdgpu_sa_manager {
625 wait_queue_head_t wq;
626 struct amdgpu_bo *bo;
627 struct list_head *hole;
628 struct list_head flist[AMDGPU_MAX_RINGS];
629 struct list_head olist;
630 unsigned size;
631 uint64_t gpu_addr;
632 void *cpu_ptr;
633 uint32_t domain;
634 uint32_t align;
635};
636
637struct amdgpu_sa_bo;
638
639/* sub-allocation buffer */
640struct amdgpu_sa_bo {
641 struct list_head olist;
642 struct list_head flist;
643 struct amdgpu_sa_manager *manager;
644 unsigned soffset;
645 unsigned eoffset;
646 struct amdgpu_fence *fence;
647};
648
649/*
650 * GEM objects.
651 */
652struct amdgpu_gem {
653 struct mutex mutex;
654 struct list_head objects;
655};
656
657int amdgpu_gem_init(struct amdgpu_device *adev);
658void amdgpu_gem_fini(struct amdgpu_device *adev);
659int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
660 int alignment, u32 initial_domain,
661 u64 flags, bool kernel,
662 struct drm_gem_object **obj);
663
664int amdgpu_mode_dumb_create(struct drm_file *file_priv,
665 struct drm_device *dev,
666 struct drm_mode_create_dumb *args);
667int amdgpu_mode_dumb_mmap(struct drm_file *filp,
668 struct drm_device *dev,
669 uint32_t handle, uint64_t *offset_p);
670
671/*
672 * Semaphores.
673 */
674struct amdgpu_semaphore {
675 struct amdgpu_sa_bo *sa_bo;
676 signed waiters;
677 uint64_t gpu_addr;
678};
679
680int amdgpu_semaphore_create(struct amdgpu_device *adev,
681 struct amdgpu_semaphore **semaphore);
682bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
683 struct amdgpu_semaphore *semaphore);
684bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
685 struct amdgpu_semaphore *semaphore);
686void amdgpu_semaphore_free(struct amdgpu_device *adev,
687 struct amdgpu_semaphore **semaphore,
688 struct amdgpu_fence *fence);
689
690/*
691 * Synchronization
692 */
693struct amdgpu_sync {
694 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
695 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS];
696 struct amdgpu_fence *last_vm_update;
697};
698
699void amdgpu_sync_create(struct amdgpu_sync *sync);
700void amdgpu_sync_fence(struct amdgpu_sync *sync,
701 struct amdgpu_fence *fence);
702int amdgpu_sync_resv(struct amdgpu_device *adev,
703 struct amdgpu_sync *sync,
704 struct reservation_object *resv,
705 void *owner);
706int amdgpu_sync_rings(struct amdgpu_sync *sync,
707 struct amdgpu_ring *ring);
708void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
709 struct amdgpu_fence *fence);
710
711/*
712 * GART structures, functions & helpers
713 */
714struct amdgpu_mc;
715
716#define AMDGPU_GPU_PAGE_SIZE 4096
717#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
718#define AMDGPU_GPU_PAGE_SHIFT 12
719#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
720
721struct amdgpu_gart {
722 dma_addr_t table_addr;
723 struct amdgpu_bo *robj;
724 void *ptr;
725 unsigned num_gpu_pages;
726 unsigned num_cpu_pages;
727 unsigned table_size;
728 struct page **pages;
729 dma_addr_t *pages_addr;
730 bool ready;
731 const struct amdgpu_gart_funcs *gart_funcs;
732};
733
734int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
735void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
736int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
737void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
738int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
739void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
740int amdgpu_gart_init(struct amdgpu_device *adev);
741void amdgpu_gart_fini(struct amdgpu_device *adev);
742void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
743 int pages);
744int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
745 int pages, struct page **pagelist,
746 dma_addr_t *dma_addr, uint32_t flags);
747
748/*
749 * GPU MC structures, functions & helpers
750 */
751struct amdgpu_mc {
752 resource_size_t aper_size;
753 resource_size_t aper_base;
754 resource_size_t agp_base;
755 /* for some chips with <= 32MB we need to lie
756 * about vram size near mc fb location */
757 u64 mc_vram_size;
758 u64 visible_vram_size;
759 u64 gtt_size;
760 u64 gtt_start;
761 u64 gtt_end;
762 u64 vram_start;
763 u64 vram_end;
764 unsigned vram_width;
765 u64 real_vram_size;
766 int vram_mtrr;
767 u64 gtt_base_align;
768 u64 mc_mask;
769 const struct firmware *fw; /* MC firmware */
770 uint32_t fw_version;
771 struct amdgpu_irq_src vm_fault;
81c59f54 772 uint32_t vram_type;
97b2e202
AD		 773};
774
775/*
776 * GPU doorbell structures, functions & helpers
777 */
778typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
779{
780 AMDGPU_DOORBELL_KIQ = 0x000,
781 AMDGPU_DOORBELL_HIQ = 0x001,
782 AMDGPU_DOORBELL_DIQ = 0x002,
783 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
784 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
785 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
786 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
787 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
788 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
789 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
790 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
791 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
792 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
793 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
794 AMDGPU_DOORBELL_IH = 0x1E8,
795 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
796 AMDGPU_DOORBELL_INVALID = 0xFFFF
797} AMDGPU_DOORBELL_ASSIGNMENT;
798
799struct amdgpu_doorbell {
800 /* doorbell mmio */
801 resource_size_t base;
802 resource_size_t size;
803 u32 __iomem *ptr;
804 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
805};
806
807void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
808 phys_addr_t *aperture_base,
809 size_t *aperture_size,
810 size_t *start_offset);
811
812/*
813 * IRQS.
814 */
815
816struct amdgpu_flip_work {
817 struct work_struct flip_work;
818 struct work_struct unpin_work;
819 struct amdgpu_device *adev;
820 int crtc_id;
821 uint64_t base;
822 struct drm_pending_vblank_event *event;
823 struct amdgpu_bo *old_rbo;
824 struct fence *fence;
825};
826
827
828/*
829 * CP & rings.
830 */
831
832struct amdgpu_ib {
833 struct amdgpu_sa_bo *sa_bo;
834 uint32_t length_dw;
835 uint64_t gpu_addr;
836 uint32_t *ptr;
837 struct amdgpu_ring *ring;
838 struct amdgpu_fence *fence;
839 struct amdgpu_user_fence *user;
840 struct amdgpu_vm *vm;
3cb485f3 841 struct amdgpu_ctx *ctx;
97b2e202 842 struct amdgpu_sync sync;
97b2e202
AD		 843 uint32_t gds_base, gds_size;
844 uint32_t gws_base, gws_size;
845 uint32_t oa_base, oa_size;
de807f81 846 uint32_t flags;
97b2e202
AD		 847};
848
849enum amdgpu_ring_type {
850 AMDGPU_RING_TYPE_GFX,
851 AMDGPU_RING_TYPE_COMPUTE,
852 AMDGPU_RING_TYPE_SDMA,
853 AMDGPU_RING_TYPE_UVD,
854 AMDGPU_RING_TYPE_VCE
855};
856
857struct amdgpu_ring {
858 struct amdgpu_device *adev;
859 const struct amdgpu_ring_funcs *funcs;
860 struct amdgpu_fence_driver fence_drv;
861
862 struct mutex *ring_lock;
863 struct amdgpu_bo *ring_obj;
864 volatile uint32_t *ring;
865 unsigned rptr_offs;
866 u64 next_rptr_gpu_addr;
867 volatile u32 *next_rptr_cpu_addr;
868 unsigned wptr;
869 unsigned wptr_old;
870 unsigned ring_size;
871 unsigned ring_free_dw;
872 int count_dw;
873 atomic_t last_rptr;
874 atomic64_t last_activity;
875 uint64_t gpu_addr;
876 uint32_t align_mask;
877 uint32_t ptr_mask;
878 bool ready;
879 u32 nop;
880 u32 idx;
881 u64 last_semaphore_signal_addr;
882 u64 last_semaphore_wait_addr;
883 u32 me;
884 u32 pipe;
885 u32 queue;
886 struct amdgpu_bo *mqd_obj;
887 u32 doorbell_index;
888 bool use_doorbell;
889 unsigned wptr_offs;
890 unsigned next_rptr_offs;
891 unsigned fence_offs;
3cb485f3 892 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 893 enum amdgpu_ring_type type;
894 char name[16];
895};
896
897/*
898 * VM
899 */
900
901/* maximum number of VMIDs */
902#define AMDGPU_NUM_VM 16
903
904/* number of entries in page table */
905#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
906
907/* PTBs (Page Table Blocks) need to be aligned to 32K */
908#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
909#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
910#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
911
912#define AMDGPU_PTE_VALID (1 << 0)
913#define AMDGPU_PTE_SYSTEM (1 << 1)
914#define AMDGPU_PTE_SNOOPED (1 << 2)
915
916/* VI only */
917#define AMDGPU_PTE_EXECUTABLE (1 << 4)
918
919#define AMDGPU_PTE_READABLE (1 << 5)
920#define AMDGPU_PTE_WRITEABLE (1 << 6)
921
922/* PTE (Page Table Entry) fragment field for different page sizes */
923#define AMDGPU_PTE_FRAG_4KB (0 << 7)
924#define AMDGPU_PTE_FRAG_64KB (4 << 7)
925#define AMDGPU_LOG2_PAGES_PER_FRAG 4
926
927struct amdgpu_vm_pt {
928 struct amdgpu_bo *bo;
929 uint64_t addr;
930};
931
932struct amdgpu_vm_id {
933 unsigned id;
934 uint64_t pd_gpu_addr;
935 /* last flushed PD/PT update */
936 struct amdgpu_fence *flushed_updates;
937 /* last use of vmid */
938 struct amdgpu_fence *last_id_use;
939};
940
941struct amdgpu_vm {
942 struct mutex mutex;
943
944 struct rb_root va;
945
946 /* protecting invalidated and freed */
947 spinlock_t status_lock;
948
949 /* BOs moved, but not yet updated in the PT */
950 struct list_head invalidated;
951
952 /* BOs freed, but not yet updated in the PT */
953 struct list_head freed;
954
955 /* contains the page directory */
956 struct amdgpu_bo *page_directory;
957 unsigned max_pde_used;
958
959 /* array of page tables, one for each page directory entry */
960 struct amdgpu_vm_pt *page_tables;
961
962 /* for id and flush management per ring */
963 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
964};
965
966struct amdgpu_vm_manager {
967 struct amdgpu_fence *active[AMDGPU_NUM_VM];
968 uint32_t max_pfn;
969 /* number of VMIDs */
970 unsigned nvm;
971 /* vram base address for page table entry */
972 u64 vram_base_offset;
973 /* is vm enabled? */
974 bool enabled;
975 /* for hw to save the PD addr on suspend/resume */
976 uint32_t saved_table_addr[AMDGPU_NUM_VM];
977 /* vm pte handling */
978 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
979 struct amdgpu_ring *vm_pte_funcs_ring;
980};
981
982/*
983 * context related structures
984 */
985
986struct amdgpu_ctx_state {
987 uint64_t flags;
d94aed5a 988 uint32_t hangs;
97b2e202
AD		 989};
990
991struct amdgpu_ctx {
992 /* call kref_get()before CS start and kref_put() after CS fence signaled */
993 struct kref refcount;
994 struct amdgpu_fpriv *fpriv;
995 struct amdgpu_ctx_state state;
996 uint32_t id;
d94aed5a 997 unsigned reset_counter;
97b2e202
AD		 998};
999
1000struct amdgpu_ctx_mgr {
1001 struct amdgpu_device *adev;
1002 struct idr ctx_handles;
1003 /* lock for IDR system */
0147ee0f 1004 struct mutex lock;
97b2e202
AD		 1005};
1006
1007/*
1008 * file private structure
1009 */
1010
1011struct amdgpu_fpriv {
1012 struct amdgpu_vm vm;
1013 struct mutex bo_list_lock;
1014 struct idr bo_list_handles;
1015 struct amdgpu_ctx_mgr ctx_mgr;
1016};
1017
1018/*
1019 * residency list
1020 */
1021
1022struct amdgpu_bo_list {
1023 struct mutex lock;
1024 struct amdgpu_bo *gds_obj;
1025 struct amdgpu_bo *gws_obj;
1026 struct amdgpu_bo *oa_obj;
1027 bool has_userptr;
1028 unsigned num_entries;
1029 struct amdgpu_bo_list_entry *array;
1030};
1031
1032struct amdgpu_bo_list *
1033amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1034void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1035void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1036
1037/*
1038 * GFX stuff
1039 */
1040#include "clearstate_defs.h"
1041
1042struct amdgpu_rlc {
1043 /* for power gating */
1044 struct amdgpu_bo *save_restore_obj;
1045 uint64_t save_restore_gpu_addr;
1046 volatile uint32_t *sr_ptr;
1047 const u32 *reg_list;
1048 u32 reg_list_size;
1049 /* for clear state */
1050 struct amdgpu_bo *clear_state_obj;
1051 uint64_t clear_state_gpu_addr;
1052 volatile uint32_t *cs_ptr;
1053 const struct cs_section_def *cs_data;
1054 u32 clear_state_size;
1055 /* for cp tables */
1056 struct amdgpu_bo *cp_table_obj;
1057 uint64_t cp_table_gpu_addr;
1058 volatile uint32_t *cp_table_ptr;
1059 u32 cp_table_size;
1060};
1061
1062struct amdgpu_mec {
1063 struct amdgpu_bo *hpd_eop_obj;
1064 u64 hpd_eop_gpu_addr;
1065 u32 num_pipe;
1066 u32 num_mec;
1067 u32 num_queue;
1068};
1069
1070/*
1071 * GPU scratch registers structures, functions & helpers
1072 */
1073struct amdgpu_scratch {
1074 unsigned num_reg;
1075 uint32_t reg_base;
1076 bool free[32];
1077 uint32_t reg[32];
1078};
1079
1080/*
1081 * GFX configurations
1082 */
1083struct amdgpu_gca_config {
1084 unsigned max_shader_engines;
1085 unsigned max_tile_pipes;
1086 unsigned max_cu_per_sh;
1087 unsigned max_sh_per_se;
1088 unsigned max_backends_per_se;
1089 unsigned max_texture_channel_caches;
1090 unsigned max_gprs;
1091 unsigned max_gs_threads;
1092 unsigned max_hw_contexts;
1093 unsigned sc_prim_fifo_size_frontend;
1094 unsigned sc_prim_fifo_size_backend;
1095 unsigned sc_hiz_tile_fifo_size;
1096 unsigned sc_earlyz_tile_fifo_size;
1097
1098 unsigned num_tile_pipes;
1099 unsigned backend_enable_mask;
1100 unsigned mem_max_burst_length_bytes;
1101 unsigned mem_row_size_in_kb;
1102 unsigned shader_engine_tile_size;
1103 unsigned num_gpus;
1104 unsigned multi_gpu_tile_size;
1105 unsigned mc_arb_ramcfg;
1106 unsigned gb_addr_config;
1107
1108 uint32_t tile_mode_array[32];
1109 uint32_t macrotile_mode_array[16];
1110};
1111
1112struct amdgpu_gfx {
1113 struct mutex gpu_clock_mutex;
1114 struct amdgpu_gca_config config;
1115 struct amdgpu_rlc rlc;
1116 struct amdgpu_mec mec;
1117 struct amdgpu_scratch scratch;
1118 const struct firmware *me_fw; /* ME firmware */
1119 uint32_t me_fw_version;
1120 const struct firmware *pfp_fw; /* PFP firmware */
1121 uint32_t pfp_fw_version;
1122 const struct firmware *ce_fw; /* CE firmware */
1123 uint32_t ce_fw_version;
1124 const struct firmware *rlc_fw; /* RLC firmware */
1125 uint32_t rlc_fw_version;
1126 const struct firmware *mec_fw; /* MEC firmware */
1127 uint32_t mec_fw_version;
1128 const struct firmware *mec2_fw; /* MEC2 firmware */
1129 uint32_t mec2_fw_version;
02558a00
KW		 1130 uint32_t me_feature_version;
1131 uint32_t ce_feature_version;
1132 uint32_t pfp_feature_version;
351643d7
JZ		 1133 uint32_t rlc_feature_version;
1134 uint32_t mec_feature_version;
1135 uint32_t mec2_feature_version;
97b2e202
AD		 1136 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1137 unsigned num_gfx_rings;
1138 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1139 unsigned num_compute_rings;
1140 struct amdgpu_irq_src eop_irq;
1141 struct amdgpu_irq_src priv_reg_irq;
1142 struct amdgpu_irq_src priv_inst_irq;
1143 /* gfx status */
1144 uint32_t gfx_current_status;
1145 /* sync signal for const engine */
1146 unsigned ce_sync_offs;
a101a899
KW		 1147 /* ce ram size*/
1148 unsigned ce_ram_size;
97b2e202
AD		 1149};
1150
1151int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1152 unsigned size, struct amdgpu_ib *ib);
1153void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1154int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1155 struct amdgpu_ib *ib, void *owner);
1156int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1157void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1158int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1159/* Ring access between begin & end cannot sleep */
1160void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1161int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1162int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1163void amdgpu_ring_commit(struct amdgpu_ring *ring);
1164void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1165void amdgpu_ring_undo(struct amdgpu_ring *ring);
1166void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1167void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
1168bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
1169unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1170 uint32_t **data);
1171int amdgpu_ring_restore(struct amdgpu_ring *ring,
1172 unsigned size, uint32_t *data);
1173int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1174 unsigned ring_size, u32 nop, u32 align_mask,
1175 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1176 enum amdgpu_ring_type ring_type);
1177void amdgpu_ring_fini(struct amdgpu_ring *ring);
1178
1179/*
1180 * CS.
1181 */
1182struct amdgpu_cs_chunk {
1183 uint32_t chunk_id;
1184 uint32_t length_dw;
1185 uint32_t *kdata;
1186 void __user *user_ptr;
1187};
1188
1189struct amdgpu_cs_parser {
1190 struct amdgpu_device *adev;
1191 struct drm_file *filp;
3cb485f3 1192 struct amdgpu_ctx *ctx;
97b2e202
AD		 1193 struct amdgpu_bo_list *bo_list;
1194 /* chunks */
1195 unsigned nchunks;
1196 struct amdgpu_cs_chunk *chunks;
1197 /* relocations */
1198 struct amdgpu_bo_list_entry *vm_bos;
97b2e202
AD		 1199 struct list_head validated;
1200
1201 struct amdgpu_ib *ibs;
1202 uint32_t num_ibs;
1203
1204 struct ww_acquire_ctx ticket;
1205
1206 /* user fence */
1207 struct amdgpu_user_fence uf;
1208};
1209
1210static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1211{
1212 return p->ibs[ib_idx].ptr[idx];
1213}
1214
1215/*
1216 * Writeback
1217 */
1218#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1219
1220struct amdgpu_wb {
1221 struct amdgpu_bo *wb_obj;
1222 volatile uint32_t *wb;
1223 uint64_t gpu_addr;
1224 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1225 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1226};
1227
1228int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1229void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1230
1231/**
1232 * struct amdgpu_pm - power management datas
1233 * It keeps track of various data needed to take powermanagement decision.
1234 */
1235
1236enum amdgpu_pm_state_type {
1237 /* not used for dpm */
1238 POWER_STATE_TYPE_DEFAULT,
1239 POWER_STATE_TYPE_POWERSAVE,
1240 /* user selectable states */
1241 POWER_STATE_TYPE_BATTERY,
1242 POWER_STATE_TYPE_BALANCED,
1243 POWER_STATE_TYPE_PERFORMANCE,
1244 /* internal states */
1245 POWER_STATE_TYPE_INTERNAL_UVD,
1246 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1247 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1248 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1249 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1250 POWER_STATE_TYPE_INTERNAL_BOOT,
1251 POWER_STATE_TYPE_INTERNAL_THERMAL,
1252 POWER_STATE_TYPE_INTERNAL_ACPI,
1253 POWER_STATE_TYPE_INTERNAL_ULV,
1254 POWER_STATE_TYPE_INTERNAL_3DPERF,
1255};
1256
1257enum amdgpu_int_thermal_type {
1258 THERMAL_TYPE_NONE,
1259 THERMAL_TYPE_EXTERNAL,
1260 THERMAL_TYPE_EXTERNAL_GPIO,
1261 THERMAL_TYPE_RV6XX,
1262 THERMAL_TYPE_RV770,
1263 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1264 THERMAL_TYPE_EVERGREEN,
1265 THERMAL_TYPE_SUMO,
1266 THERMAL_TYPE_NI,
1267 THERMAL_TYPE_SI,
1268 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1269 THERMAL_TYPE_CI,
1270 THERMAL_TYPE_KV,
1271};
1272
1273enum amdgpu_dpm_auto_throttle_src {
1274 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1275 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1276};
1277
1278enum amdgpu_dpm_event_src {
1279 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1280 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1281 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1282 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1283 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1284};
1285
1286#define AMDGPU_MAX_VCE_LEVELS 6
1287
1288enum amdgpu_vce_level {
1289 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1290 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1291 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1292 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1293 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1294 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1295};
1296
1297struct amdgpu_ps {
1298 u32 caps; /* vbios flags */
1299 u32 class; /* vbios flags */
1300 u32 class2; /* vbios flags */
1301 /* UVD clocks */
1302 u32 vclk;
1303 u32 dclk;
1304 /* VCE clocks */
1305 u32 evclk;
1306 u32 ecclk;
1307 bool vce_active;
1308 enum amdgpu_vce_level vce_level;
1309 /* asic priv */
1310 void *ps_priv;
1311};
1312
1313struct amdgpu_dpm_thermal {
1314 /* thermal interrupt work */
1315 struct work_struct work;
1316 /* low temperature threshold */
1317 int min_temp;
1318 /* high temperature threshold */
1319 int max_temp;
1320 /* was last interrupt low to high or high to low */
1321 bool high_to_low;
1322 /* interrupt source */
1323 struct amdgpu_irq_src irq;
1324};
1325
1326enum amdgpu_clk_action
1327{
1328 AMDGPU_SCLK_UP = 1,
1329 AMDGPU_SCLK_DOWN
1330};
1331
1332struct amdgpu_blacklist_clocks
1333{
1334 u32 sclk;
1335 u32 mclk;
1336 enum amdgpu_clk_action action;
1337};
1338
1339struct amdgpu_clock_and_voltage_limits {
1340 u32 sclk;
1341 u32 mclk;
1342 u16 vddc;
1343 u16 vddci;
1344};
1345
1346struct amdgpu_clock_array {
1347 u32 count;
1348 u32 *values;
1349};
1350
1351struct amdgpu_clock_voltage_dependency_entry {
1352 u32 clk;
1353 u16 v;
1354};
1355
1356struct amdgpu_clock_voltage_dependency_table {
1357 u32 count;
1358 struct amdgpu_clock_voltage_dependency_entry *entries;
1359};
1360
1361union amdgpu_cac_leakage_entry {
1362 struct {
1363 u16 vddc;
1364 u32 leakage;
1365 };
1366 struct {
1367 u16 vddc1;
1368 u16 vddc2;
1369 u16 vddc3;
1370 };
1371};
1372
1373struct amdgpu_cac_leakage_table {
1374 u32 count;
1375 union amdgpu_cac_leakage_entry *entries;
1376};
1377
1378struct amdgpu_phase_shedding_limits_entry {
1379 u16 voltage;
1380 u32 sclk;
1381 u32 mclk;
1382};
1383
1384struct amdgpu_phase_shedding_limits_table {
1385 u32 count;
1386 struct amdgpu_phase_shedding_limits_entry *entries;
1387};
1388
1389struct amdgpu_uvd_clock_voltage_dependency_entry {
1390 u32 vclk;
1391 u32 dclk;
1392 u16 v;
1393};
1394
1395struct amdgpu_uvd_clock_voltage_dependency_table {
1396 u8 count;
1397 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1398};
1399
1400struct amdgpu_vce_clock_voltage_dependency_entry {
1401 u32 ecclk;
1402 u32 evclk;
1403 u16 v;
1404};
1405
1406struct amdgpu_vce_clock_voltage_dependency_table {
1407 u8 count;
1408 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1409};
1410
1411struct amdgpu_ppm_table {
1412 u8 ppm_design;
1413 u16 cpu_core_number;
1414 u32 platform_tdp;
1415 u32 small_ac_platform_tdp;
1416 u32 platform_tdc;
1417 u32 small_ac_platform_tdc;
1418 u32 apu_tdp;
1419 u32 dgpu_tdp;
1420 u32 dgpu_ulv_power;
1421 u32 tj_max;
1422};
1423
1424struct amdgpu_cac_tdp_table {
1425 u16 tdp;
1426 u16 configurable_tdp;
1427 u16 tdc;
1428 u16 battery_power_limit;
1429 u16 small_power_limit;
1430 u16 low_cac_leakage;
1431 u16 high_cac_leakage;
1432 u16 maximum_power_delivery_limit;
1433};
1434
1435struct amdgpu_dpm_dynamic_state {
1436 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1437 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1438 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1439 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1440 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1441 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1442 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1443 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1444 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1445 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1446 struct amdgpu_clock_array valid_sclk_values;
1447 struct amdgpu_clock_array valid_mclk_values;
1448 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1449 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1450 u32 mclk_sclk_ratio;
1451 u32 sclk_mclk_delta;
1452 u16 vddc_vddci_delta;
1453 u16 min_vddc_for_pcie_gen2;
1454 struct amdgpu_cac_leakage_table cac_leakage_table;
1455 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1456 struct amdgpu_ppm_table *ppm_table;
1457 struct amdgpu_cac_tdp_table *cac_tdp_table;
1458};
1459
1460struct amdgpu_dpm_fan {
1461 u16 t_min;
1462 u16 t_med;
1463 u16 t_high;
1464 u16 pwm_min;
1465 u16 pwm_med;
1466 u16 pwm_high;
1467 u8 t_hyst;
1468 u32 cycle_delay;
1469 u16 t_max;
1470 u8 control_mode;
1471 u16 default_max_fan_pwm;
1472 u16 default_fan_output_sensitivity;
1473 u16 fan_output_sensitivity;
1474 bool ucode_fan_control;
1475};
1476
1477enum amdgpu_pcie_gen {
1478 AMDGPU_PCIE_GEN1 = 0,
1479 AMDGPU_PCIE_GEN2 = 1,
1480 AMDGPU_PCIE_GEN3 = 2,
1481 AMDGPU_PCIE_GEN_INVALID = 0xffff
1482};
1483
1484enum amdgpu_dpm_forced_level {
1485 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1486 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1487 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1488};
1489
1490struct amdgpu_vce_state {
1491 /* vce clocks */
1492 u32 evclk;
1493 u32 ecclk;
1494 /* gpu clocks */
1495 u32 sclk;
1496 u32 mclk;
1497 u8 clk_idx;
1498 u8 pstate;
1499};
1500
1501struct amdgpu_dpm_funcs {
1502 int (*get_temperature)(struct amdgpu_device *adev);
1503 int (*pre_set_power_state)(struct amdgpu_device *adev);
1504 int (*set_power_state)(struct amdgpu_device *adev);
1505 void (*post_set_power_state)(struct amdgpu_device *adev);
1506 void (*display_configuration_changed)(struct amdgpu_device *adev);
1507 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1508 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1509 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1510 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1511 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1512 bool (*vblank_too_short)(struct amdgpu_device *adev);
1513 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1514 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1515 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1516 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1517 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1518 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1519 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1520};
1521
1522struct amdgpu_dpm {
1523 struct amdgpu_ps *ps;
1524 /* number of valid power states */
1525 int num_ps;
1526 /* current power state that is active */
1527 struct amdgpu_ps *current_ps;
1528 /* requested power state */
1529 struct amdgpu_ps *requested_ps;
1530 /* boot up power state */
1531 struct amdgpu_ps *boot_ps;
1532 /* default uvd power state */
1533 struct amdgpu_ps *uvd_ps;
1534 /* vce requirements */
1535 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1536 enum amdgpu_vce_level vce_level;
1537 enum amdgpu_pm_state_type state;
1538 enum amdgpu_pm_state_type user_state;
1539 u32 platform_caps;
1540 u32 voltage_response_time;
1541 u32 backbias_response_time;
1542 void *priv;
1543 u32 new_active_crtcs;
1544 int new_active_crtc_count;
1545 u32 current_active_crtcs;
1546 int current_active_crtc_count;
1547 struct amdgpu_dpm_dynamic_state dyn_state;
1548 struct amdgpu_dpm_fan fan;
1549 u32 tdp_limit;
1550 u32 near_tdp_limit;
1551 u32 near_tdp_limit_adjusted;
1552 u32 sq_ramping_threshold;
1553 u32 cac_leakage;
1554 u16 tdp_od_limit;
1555 u32 tdp_adjustment;
1556 u16 load_line_slope;
1557 bool power_control;
1558 bool ac_power;
1559 /* special states active */
1560 bool thermal_active;
1561 bool uvd_active;
1562 bool vce_active;
1563 /* thermal handling */
1564 struct amdgpu_dpm_thermal thermal;
1565 /* forced levels */
1566 enum amdgpu_dpm_forced_level forced_level;
1567};
1568
1569struct amdgpu_pm {
1570 struct mutex mutex;
97b2e202
AD		 1571 u32 current_sclk;
1572 u32 current_mclk;
1573 u32 default_sclk;
1574 u32 default_mclk;
1575 struct amdgpu_i2c_chan *i2c_bus;
1576 /* internal thermal controller on rv6xx+ */
1577 enum amdgpu_int_thermal_type int_thermal_type;
1578 struct device *int_hwmon_dev;
1579 /* fan control parameters */
1580 bool no_fan;
1581 u8 fan_pulses_per_revolution;
1582 u8 fan_min_rpm;
1583 u8 fan_max_rpm;
1584 /* dpm */
1585 bool dpm_enabled;
1586 struct amdgpu_dpm dpm;
1587 const struct firmware *fw; /* SMC firmware */
1588 uint32_t fw_version;
1589 const struct amdgpu_dpm_funcs *funcs;
1590};
1591
1592/*
1593 * UVD
1594 */
1595#define AMDGPU_MAX_UVD_HANDLES 10
1596#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1597#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1598#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1599
1600struct amdgpu_uvd {
1601 struct amdgpu_bo *vcpu_bo;
1602 void *cpu_addr;
1603 uint64_t gpu_addr;
1604 void *saved_bo;
1605 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1606 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1607 struct delayed_work idle_work;
1608 const struct firmware *fw; /* UVD firmware */
1609 struct amdgpu_ring ring;
1610 struct amdgpu_irq_src irq;
1611 bool address_64_bit;
1612};
1613
1614/*
1615 * VCE
1616 */
1617#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1618#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1619
6a585777
AD		 1620#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1621#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1622
97b2e202
AD		 1623struct amdgpu_vce {
1624 struct amdgpu_bo *vcpu_bo;
1625 uint64_t gpu_addr;
1626 unsigned fw_version;
1627 unsigned fb_version;
1628 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1629 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1630 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1631 struct delayed_work idle_work;
1632 const struct firmware *fw; /* VCE firmware */
1633 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1634 struct amdgpu_irq_src irq;
6a585777 1635 unsigned harvest_config;
97b2e202
AD		 1636};
1637
1638/*
1639 * SDMA
1640 */
1641struct amdgpu_sdma {
1642 /* SDMA firmware */
1643 const struct firmware *fw;
1644 uint32_t fw_version;
cfa2104f 1645 uint32_t feature_version;
97b2e202
AD		 1646
1647 struct amdgpu_ring ring;
1648};
1649
1650/*
1651 * Firmware
1652 */
1653struct amdgpu_firmware {
1654 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1655 bool smu_load;
1656 struct amdgpu_bo *fw_buf;
1657 unsigned int fw_size;
1658};
1659
1660/*
1661 * Benchmarking
1662 */
1663void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1664
1665
1666/*
1667 * Testing
1668 */
1669void amdgpu_test_moves(struct amdgpu_device *adev);
1670void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1671 struct amdgpu_ring *cpA,
1672 struct amdgpu_ring *cpB);
1673void amdgpu_test_syncing(struct amdgpu_device *adev);
1674
1675/*
1676 * MMU Notifier
1677 */
1678#if defined(CONFIG_MMU_NOTIFIER)
1679int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1680void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1681#else
1682static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1683{
1684 return -ENODEV;
1685}
1686static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1687#endif
1688
1689/*
1690 * Debugfs
1691 */
1692struct amdgpu_debugfs {
1693 struct drm_info_list *files;
1694 unsigned num_files;
1695};
1696
1697int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1698 struct drm_info_list *files,
1699 unsigned nfiles);
1700int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1701
1702#if defined(CONFIG_DEBUG_FS)
1703int amdgpu_debugfs_init(struct drm_minor *minor);
1704void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1705#endif
1706
1707/*
1708 * amdgpu smumgr functions
1709 */
1710struct amdgpu_smumgr_funcs {
1711 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1712 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1713 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1714};
1715
1716/*
1717 * amdgpu smumgr
1718 */
1719struct amdgpu_smumgr {
1720 struct amdgpu_bo *toc_buf;
1721 struct amdgpu_bo *smu_buf;
1722 /* asic priv smu data */
1723 void *priv;
1724 spinlock_t smu_lock;
1725 /* smumgr functions */
1726 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1727 /* ucode loading complete flag */
1728 uint32_t fw_flags;
1729};
1730
1731/*
1732 * ASIC specific register table accessible by UMD
1733 */
1734struct amdgpu_allowed_register_entry {
1735 uint32_t reg_offset;
1736 bool untouched;
1737 bool grbm_indexed;
1738};
1739
1740struct amdgpu_cu_info {
1741 uint32_t number; /* total active CU number */
1742 uint32_t ao_cu_mask;
1743 uint32_t bitmap[4][4];
1744};
1745
1746
1747/*
1748 * ASIC specific functions.
1749 */
1750struct amdgpu_asic_funcs {
1751 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1752 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1753 u32 sh_num, u32 reg_offset, u32 *value);
1754 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1755 int (*reset)(struct amdgpu_device *adev);
1756 /* wait for mc_idle */
1757 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1758 /* get the reference clock */
1759 u32 (*get_xclk)(struct amdgpu_device *adev);
1760 /* get the gpu clock counter */
1761 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1762 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1763 /* MM block clocks */
1764 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1765 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1766};
1767
1768/*
1769 * IOCTL.
1770 */
1771int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1772 struct drm_file *filp);
1773int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1774 struct drm_file *filp);
1775
1776int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1777 struct drm_file *filp);
1778int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1779 struct drm_file *filp);
1780int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1781 struct drm_file *filp);
1782int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1783 struct drm_file *filp);
1784int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1785 struct drm_file *filp);
1786int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1787 struct drm_file *filp);
1788int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1789int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1790
1791int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1792 struct drm_file *filp);
1793
1794/* VRAM scratch page for HDP bug, default vram page */
1795struct amdgpu_vram_scratch {
1796 struct amdgpu_bo *robj;
1797 volatile uint32_t *ptr;
1798 u64 gpu_addr;
1799};
1800
1801/*
1802 * ACPI
1803 */
1804struct amdgpu_atif_notification_cfg {
1805 bool enabled;
1806 int command_code;
1807};
1808
1809struct amdgpu_atif_notifications {
1810 bool display_switch;
1811 bool expansion_mode_change;
1812 bool thermal_state;
1813 bool forced_power_state;
1814 bool system_power_state;
1815 bool display_conf_change;
1816 bool px_gfx_switch;
1817 bool brightness_change;
1818 bool dgpu_display_event;
1819};
1820
1821struct amdgpu_atif_functions {
1822 bool system_params;
1823 bool sbios_requests;
1824 bool select_active_disp;
1825 bool lid_state;
1826 bool get_tv_standard;
1827 bool set_tv_standard;
1828 bool get_panel_expansion_mode;
1829 bool set_panel_expansion_mode;
1830 bool temperature_change;
1831 bool graphics_device_types;
1832};
1833
1834struct amdgpu_atif {
1835 struct amdgpu_atif_notifications notifications;
1836 struct amdgpu_atif_functions functions;
1837 struct amdgpu_atif_notification_cfg notification_cfg;
1838 struct amdgpu_encoder *encoder_for_bl;
1839};
1840
1841struct amdgpu_atcs_functions {
1842 bool get_ext_state;
1843 bool pcie_perf_req;
1844 bool pcie_dev_rdy;
1845 bool pcie_bus_width;
1846};
1847
1848struct amdgpu_atcs {
1849 struct amdgpu_atcs_functions functions;
1850};
1851
1852int amdgpu_ctx_alloc(struct amdgpu_device *adev,struct amdgpu_fpriv *fpriv,
1853 uint32_t *id,uint32_t flags);
1854int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1855 uint32_t id);
97b2e202
AD		 1856
1857void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv);
66b3cf2a
JZ		 1858struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1859int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
97b2e202
AD		 1860
1861extern int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1862 struct drm_file *filp);
1863
1864/*
1865 * Core structure, functions and helpers.
1866 */
1867typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1868typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1869
1870typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1871typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1872
8faf0e08
AD		 1873struct amdgpu_ip_block_status {
1874 bool valid;
1875 bool sw;
1876 bool hw;
1877};
1878
97b2e202
AD		 1879struct amdgpu_device {
1880 struct device *dev;
1881 struct drm_device *ddev;
1882 struct pci_dev *pdev;
1883 struct rw_semaphore exclusive_lock;
1884
1885 /* ASIC */
1886 enum amdgpu_asic_type asic_type;
1887 uint32_t family;
1888 uint32_t rev_id;
1889 uint32_t external_rev_id;
1890 unsigned long flags;
1891 int usec_timeout;
1892 const struct amdgpu_asic_funcs *asic_funcs;
1893 bool shutdown;
1894 bool suspend;
1895 bool need_dma32;
1896 bool accel_working;
1897 bool needs_reset;
1898 struct work_struct reset_work;
1899 struct notifier_block acpi_nb;
1900 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1901 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1902 unsigned debugfs_count;
1903#if defined(CONFIG_DEBUG_FS)
1904 struct dentry *debugfs_regs;
1905#endif
1906 struct amdgpu_atif atif;
1907 struct amdgpu_atcs atcs;
1908 struct mutex srbm_mutex;
1909 /* GRBM index mutex. Protects concurrent access to GRBM index */
1910 struct mutex grbm_idx_mutex;
1911 struct dev_pm_domain vga_pm_domain;
1912 bool have_disp_power_ref;
1913
1914 /* BIOS */
1915 uint8_t *bios;
1916 bool is_atom_bios;
1917 uint16_t bios_header_start;
1918 struct amdgpu_bo *stollen_vga_memory;
1919 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1920
1921 /* Register/doorbell mmio */
1922 resource_size_t rmmio_base;
1923 resource_size_t rmmio_size;
1924 void __iomem *rmmio;
1925 /* protects concurrent MM_INDEX/DATA based register access */
1926 spinlock_t mmio_idx_lock;
1927 /* protects concurrent SMC based register access */
1928 spinlock_t smc_idx_lock;
1929 amdgpu_rreg_t smc_rreg;
1930 amdgpu_wreg_t smc_wreg;
1931 /* protects concurrent PCIE register access */
1932 spinlock_t pcie_idx_lock;
1933 amdgpu_rreg_t pcie_rreg;
1934 amdgpu_wreg_t pcie_wreg;
1935 /* protects concurrent UVD register access */
1936 spinlock_t uvd_ctx_idx_lock;
1937 amdgpu_rreg_t uvd_ctx_rreg;
1938 amdgpu_wreg_t uvd_ctx_wreg;
1939 /* protects concurrent DIDT register access */
1940 spinlock_t didt_idx_lock;
1941 amdgpu_rreg_t didt_rreg;
1942 amdgpu_wreg_t didt_wreg;
1943 /* protects concurrent ENDPOINT (audio) register access */
1944 spinlock_t audio_endpt_idx_lock;
1945 amdgpu_block_rreg_t audio_endpt_rreg;
1946 amdgpu_block_wreg_t audio_endpt_wreg;
1947 void __iomem *rio_mem;
1948 resource_size_t rio_mem_size;
1949 struct amdgpu_doorbell doorbell;
1950
1951 /* clock/pll info */
1952 struct amdgpu_clock clock;
1953
1954 /* MC */
1955 struct amdgpu_mc mc;
1956 struct amdgpu_gart gart;
1957 struct amdgpu_dummy_page dummy_page;
1958 struct amdgpu_vm_manager vm_manager;
1959
1960 /* memory management */
1961 struct amdgpu_mman mman;
1962 struct amdgpu_gem gem;
1963 struct amdgpu_vram_scratch vram_scratch;
1964 struct amdgpu_wb wb;
1965 atomic64_t vram_usage;
1966 atomic64_t vram_vis_usage;
1967 atomic64_t gtt_usage;
1968 atomic64_t num_bytes_moved;
d94aed5a 1969 atomic_t gpu_reset_counter;
97b2e202
AD		 1970
1971 /* display */
1972 struct amdgpu_mode_info mode_info;
1973 struct work_struct hotplug_work;
1974 struct amdgpu_irq_src crtc_irq;
1975 struct amdgpu_irq_src pageflip_irq;
1976 struct amdgpu_irq_src hpd_irq;
1977
1978 /* rings */
1979 wait_queue_head_t fence_queue;
1980 unsigned fence_context;
1981 struct mutex ring_lock;
1982 unsigned num_rings;
1983 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1984 bool ib_pool_ready;
1985 struct amdgpu_sa_manager ring_tmp_bo;
1986
1987 /* interrupts */
1988 struct amdgpu_irq irq;
1989
1990 /* dpm */
1991 struct amdgpu_pm pm;
1992 u32 cg_flags;
1993 u32 pg_flags;
1994
1995 /* amdgpu smumgr */
1996 struct amdgpu_smumgr smu;
1997
1998 /* gfx */
1999 struct amdgpu_gfx gfx;
2000
2001 /* sdma */
2002 struct amdgpu_sdma sdma[2];
2003 struct amdgpu_irq_src sdma_trap_irq;
2004 struct amdgpu_irq_src sdma_illegal_inst_irq;
2005
2006 /* uvd */
2007 bool has_uvd;
2008 struct amdgpu_uvd uvd;
2009
2010 /* vce */
2011 struct amdgpu_vce vce;
2012
2013 /* firmwares */
2014 struct amdgpu_firmware firmware;
2015
2016 /* GDS */
2017 struct amdgpu_gds gds;
2018
2019 const struct amdgpu_ip_block_version *ip_blocks;
2020 int num_ip_blocks;
8faf0e08 2021 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2022 struct mutex mn_lock;
2023 DECLARE_HASHTABLE(mn_hash, 7);
2024
2025 /* tracking pinned memory */
2026 u64 vram_pin_size;
2027 u64 gart_pin_size;
2028};
2029
2030bool amdgpu_device_is_px(struct drm_device *dev);
2031int amdgpu_device_init(struct amdgpu_device *adev,
2032 struct drm_device *ddev,
2033 struct pci_dev *pdev,
2034 uint32_t flags);
2035void amdgpu_device_fini(struct amdgpu_device *adev);
2036int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2037
2038uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2039 bool always_indirect);
2040void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2041 bool always_indirect);
2042u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2043void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2044
2045u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2046void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2047
2048/*
2049 * Cast helper
2050 */
2051extern const struct fence_ops amdgpu_fence_ops;
2052static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2053{
2054 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2055
2056 if (__f->base.ops == &amdgpu_fence_ops)
2057 return __f;
2058
2059 return NULL;
2060}
2061
2062/*
2063 * Registers read & write functions.
2064 */
2065#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2066#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2067#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2068#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2069#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2070#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2071#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2072#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2073#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2074#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2075#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2076#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2077#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2078#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2079#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2080#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2081#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2082#define WREG32_P(reg, val, mask) \
2083 do { \
2084 uint32_t tmp_ = RREG32(reg); \
2085 tmp_ &= (mask); \
2086 tmp_ |= ((val) & ~(mask)); \
2087 WREG32(reg, tmp_); \
2088 } while (0)
2089#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2090#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2091#define WREG32_PLL_P(reg, val, mask) \
2092 do { \
2093 uint32_t tmp_ = RREG32_PLL(reg); \
2094 tmp_ &= (mask); \
2095 tmp_ |= ((val) & ~(mask)); \
2096 WREG32_PLL(reg, tmp_); \
2097 } while (0)
2098#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2099#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2100#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2101
2102#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2103#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2104
2105#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2106#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2107
2108#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2109 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2110 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2111
2112#define REG_GET_FIELD(value, reg, field) \
2113 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2114
2115/*
2116 * BIOS helpers.
2117 */
2118#define RBIOS8(i) (adev->bios[i])
2119#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2120#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2121
2122/*
2123 * RING helpers.
2124 */
2125static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2126{
2127 if (ring->count_dw <= 0)
86c2b790 2128 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2129 ring->ring[ring->wptr++] = v;
2130 ring->wptr &= ring->ptr_mask;
2131 ring->count_dw--;
2132 ring->ring_free_dw--;
2133}
2134
2135/*
2136 * ASICs macro.
2137 */
2138#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2139#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2140#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2141#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2142#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2143#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2144#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2145#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2146#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2147#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2148#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2149#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2150#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2151#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2152#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2153#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2154#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2155#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2156#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2157#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2158#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2159#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2160#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2161#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2162#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2163#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202
AD		 2164#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2165#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2166#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
97b2e202
AD		 2167#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2168#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2169#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2170#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2171#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2172#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2173#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2174#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2175#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2176#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2177#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2178#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2179#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2180#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2181#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2182#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2183#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2184#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2185#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2186#define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b))
2187#define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b))
2188#define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2189#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2190#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2191#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2192#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2193#define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2194#define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2195#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2196#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2197#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2198#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2199#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
b7a07769 2200#define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
97b2e202
AD		 2201#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2202#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2203#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2204#define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2205#define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2206
2207#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2208
2209/* Common functions */
2210int amdgpu_gpu_reset(struct amdgpu_device *adev);
2211void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2212bool amdgpu_card_posted(struct amdgpu_device *adev);
2213void amdgpu_update_display_priority(struct amdgpu_device *adev);
2214bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2215int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2216int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2217 u32 ip_instance, u32 ring,
2218 struct amdgpu_ring **out_ring);
2219void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2220bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2221int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2222 uint32_t flags);
2223bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2224bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2225uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2226 struct ttm_mem_reg *mem);
2227void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2228void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2229void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2230void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2231 const u32 *registers,
2232 const u32 array_size);
2233
2234bool amdgpu_device_is_px(struct drm_device *dev);
2235/* atpx handler */
2236#if defined(CONFIG_VGA_SWITCHEROO)
2237void amdgpu_register_atpx_handler(void);
2238void amdgpu_unregister_atpx_handler(void);
2239#else
2240static inline void amdgpu_register_atpx_handler(void) {}
2241static inline void amdgpu_unregister_atpx_handler(void) {}
2242#endif
2243
2244/*
2245 * KMS
2246 */
2247extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2248extern int amdgpu_max_kms_ioctl;
2249
2250int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2251int amdgpu_driver_unload_kms(struct drm_device *dev);
2252void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2253int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2254void amdgpu_driver_postclose_kms(struct drm_device *dev,
2255 struct drm_file *file_priv);
2256void amdgpu_driver_preclose_kms(struct drm_device *dev,
2257 struct drm_file *file_priv);
2258int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2259int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2260u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
2261int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
2262void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
2263int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
2264 int *max_error,
2265 struct timeval *vblank_time,
2266 unsigned flags);
2267long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2268 unsigned long arg);
2269
2270/*
2271 * vm
2272 */
2273int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2274void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2275struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2276 struct amdgpu_vm *vm,
2277 struct list_head *head);
2278struct amdgpu_fence *amdgpu_vm_grab_id(struct amdgpu_ring *ring,
2279 struct amdgpu_vm *vm);
2280void amdgpu_vm_flush(struct amdgpu_ring *ring,
2281 struct amdgpu_vm *vm,
2282 struct amdgpu_fence *updates);
2283void amdgpu_vm_fence(struct amdgpu_device *adev,
2284 struct amdgpu_vm *vm,
2285 struct amdgpu_fence *fence);
2286uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2287int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2288 struct amdgpu_vm *vm);
2289int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2290 struct amdgpu_vm *vm);
2291int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
cfe2c978 2292 struct amdgpu_vm *vm, struct amdgpu_sync *sync);
97b2e202
AD		 2293int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2294 struct amdgpu_bo_va *bo_va,
2295 struct ttm_mem_reg *mem);
2296void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2297 struct amdgpu_bo *bo);
2298struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2299 struct amdgpu_bo *bo);
2300struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2301 struct amdgpu_vm *vm,
2302 struct amdgpu_bo *bo);
2303int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2304 struct amdgpu_bo_va *bo_va,
2305 uint64_t addr, uint64_t offset,
2306 uint64_t size, uint32_t flags);
2307int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2308 struct amdgpu_bo_va *bo_va,
2309 uint64_t addr);
2310void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2311 struct amdgpu_bo_va *bo_va);
2312
2313/*
2314 * functions used by amdgpu_encoder.c
2315 */
2316struct amdgpu_afmt_acr {
2317 u32 clock;
2318
2319 int n_32khz;
2320 int cts_32khz;
2321
2322 int n_44_1khz;
2323 int cts_44_1khz;
2324
2325 int n_48khz;
2326 int cts_48khz;
2327
2328};
2329
2330struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2331
2332/* amdgpu_acpi.c */
2333#if defined(CONFIG_ACPI)
2334int amdgpu_acpi_init(struct amdgpu_device *adev);
2335void amdgpu_acpi_fini(struct amdgpu_device *adev);
2336bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2337int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2338 u8 perf_req, bool advertise);
2339int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2340#else
2341static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2342static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2343#endif
2344
2345struct amdgpu_bo_va_mapping *
2346amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2347 uint64_t addr, struct amdgpu_bo **bo);
2348
2349#include "amdgpu_object.h"
2350
2351#endif
Linux 6.x block layer and io_uring tree(s)