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ba5625c3 BP |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright 2017-2018 NXP. | |
4 | */ | |
5 | ||
6 | #include <dt-bindings/clock/imx8mm-clock.h> | |
7 | #include <linux/clk.h> | |
8 | #include <linux/err.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of.h> | |
13 | #include <linux/of_address.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/types.h> | |
16 | ||
17 | #include "clk.h" | |
18 | ||
19 | static u32 share_count_sai1; | |
20 | static u32 share_count_sai2; | |
21 | static u32 share_count_sai3; | |
22 | static u32 share_count_sai4; | |
23 | static u32 share_count_sai5; | |
24 | static u32 share_count_sai6; | |
25 | static u32 share_count_dcss; | |
26 | static u32 share_count_pdm; | |
27 | static u32 share_count_nand; | |
28 | ||
29 | #define PLL_1416X_RATE(_rate, _m, _p, _s) \ | |
30 | { \ | |
31 | .rate = (_rate), \ | |
32 | .mdiv = (_m), \ | |
33 | .pdiv = (_p), \ | |
34 | .sdiv = (_s), \ | |
35 | } | |
36 | ||
37 | #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ | |
38 | { \ | |
39 | .rate = (_rate), \ | |
40 | .mdiv = (_m), \ | |
41 | .pdiv = (_p), \ | |
42 | .sdiv = (_s), \ | |
43 | .kdiv = (_k), \ | |
44 | } | |
45 | ||
46 | static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = { | |
47 | PLL_1416X_RATE(1800000000U, 225, 3, 0), | |
48 | PLL_1416X_RATE(1600000000U, 200, 3, 0), | |
49 | PLL_1416X_RATE(1200000000U, 300, 3, 1), | |
50 | PLL_1416X_RATE(1000000000U, 250, 3, 1), | |
51 | PLL_1416X_RATE(800000000U, 200, 3, 1), | |
52 | PLL_1416X_RATE(750000000U, 250, 2, 2), | |
53 | PLL_1416X_RATE(700000000U, 350, 3, 2), | |
54 | PLL_1416X_RATE(600000000U, 300, 3, 2), | |
55 | }; | |
56 | ||
57 | static const struct imx_pll14xx_rate_table imx8mm_audiopll_tbl[] = { | |
58 | PLL_1443X_RATE(786432000U, 655, 5, 2, 23593), | |
59 | PLL_1443X_RATE(722534400U, 301, 5, 1, 3670), | |
60 | }; | |
61 | ||
62 | static const struct imx_pll14xx_rate_table imx8mm_videopll_tbl[] = { | |
63 | PLL_1443X_RATE(650000000U, 325, 3, 2, 0), | |
64 | PLL_1443X_RATE(594000000U, 198, 2, 2, 0), | |
65 | }; | |
66 | ||
67 | static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = { | |
68 | PLL_1443X_RATE(650000000U, 325, 3, 2, 0), | |
69 | }; | |
70 | ||
71 | static struct imx_pll14xx_clk imx8mm_audio_pll __initdata = { | |
72 | .type = PLL_1443X, | |
73 | .rate_table = imx8mm_audiopll_tbl, | |
74 | .rate_count = ARRAY_SIZE(imx8mm_audiopll_tbl), | |
75 | }; | |
76 | ||
77 | static struct imx_pll14xx_clk imx8mm_video_pll __initdata = { | |
78 | .type = PLL_1443X, | |
79 | .rate_table = imx8mm_videopll_tbl, | |
80 | .rate_count = ARRAY_SIZE(imx8mm_videopll_tbl), | |
81 | }; | |
82 | ||
83 | static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = { | |
84 | .type = PLL_1443X, | |
85 | .rate_table = imx8mm_drampll_tbl, | |
86 | .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl), | |
87 | }; | |
88 | ||
89 | static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = { | |
90 | .type = PLL_1416X, | |
91 | .rate_table = imx8mm_pll1416x_tbl, | |
92 | .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl), | |
93 | }; | |
94 | ||
95 | static struct imx_pll14xx_clk imx8mm_gpu_pll __initdata = { | |
96 | .type = PLL_1416X, | |
97 | .rate_table = imx8mm_pll1416x_tbl, | |
98 | .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl), | |
99 | }; | |
100 | ||
101 | static struct imx_pll14xx_clk imx8mm_vpu_pll __initdata = { | |
102 | .type = PLL_1416X, | |
103 | .rate_table = imx8mm_pll1416x_tbl, | |
104 | .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl), | |
105 | }; | |
106 | ||
107 | static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = { | |
108 | .type = PLL_1416X, | |
109 | .rate_table = imx8mm_pll1416x_tbl, | |
110 | .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl), | |
111 | }; | |
112 | ||
113 | static const char *pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; | |
114 | static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; | |
115 | static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; | |
116 | static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; | |
117 | static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; | |
118 | static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; | |
119 | static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; | |
120 | static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; | |
121 | static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; | |
122 | static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; | |
123 | static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; | |
124 | ||
125 | /* CCM ROOT */ | |
126 | static const char *imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", | |
127 | "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; | |
128 | ||
129 | static const char *imx8mm_m4_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "sys_pll1_266m", | |
130 | "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; | |
131 | ||
132 | static const char *imx8mm_vpu_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", | |
133 | "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "vpu_pll_out", }; | |
134 | ||
135 | static const char *imx8mm_gpu3d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", | |
136 | "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; | |
137 | ||
138 | static const char *imx8mm_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", | |
139 | "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; | |
140 | ||
141 | static const char *imx8mm_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", "sys_pll2_250m", | |
142 | "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "sys_pll1_100m",}; | |
143 | ||
144 | static const char *imx8mm_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", | |
145 | "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; | |
146 | ||
147 | static const char *imx8mm_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", | |
148 | "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; | |
149 | ||
150 | static const char *imx8mm_vpu_bus_sels[] = {"osc_24m", "sys_pll1_800m", "vpu_pll_out", "audio_pll2_out", | |
151 | "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_200m", "sys_pll1_100m", }; | |
152 | ||
153 | static const char *imx8mm_disp_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll3_out", | |
154 | "sys_pll1_40m", "audio_pll2_out", "clk_ext1", "clk_ext4", }; | |
155 | ||
156 | static const char *imx8mm_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m", "sys_pll3_out", | |
157 | "sys_pll1_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", }; | |
158 | ||
159 | static const char *imx8mm_disp_rtrm_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll2_1000m", | |
160 | "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", }; | |
161 | ||
162 | static const char *imx8mm_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m", | |
163 | "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; | |
164 | ||
165 | static const char *imx8mm_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", | |
166 | "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; | |
167 | ||
168 | static const char *imx8mm_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", | |
169 | "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; | |
170 | ||
171 | static const char *imx8mm_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", | |
172 | "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; | |
173 | ||
174 | static const char *imx8mm_noc_apb_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out", "sys_pll2_333m", "sys_pll2_200m", | |
175 | "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", }; | |
176 | ||
177 | static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", | |
178 | "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; | |
179 | ||
180 | static const char *imx8mm_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_1000m", | |
181 | "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; | |
182 | ||
183 | static const char *imx8mm_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", "sys_pll2_500m", | |
184 | "sys_pll2_1000m", "sys_pll3_out", "audio_pll1_out", "sys_pll1_266m", }; | |
185 | ||
186 | static const char *imx8mm_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", | |
187 | "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; | |
188 | ||
189 | static const char *imx8mm_vpu_g1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m", | |
190 | "sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", }; | |
191 | ||
192 | static const char *imx8mm_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m", | |
193 | "sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", }; | |
194 | ||
195 | static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "video_pll2_out", "sys_pll1_800m", "sys_pll2_1000m", | |
196 | "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", }; | |
197 | ||
198 | static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "video_pll2_out", "sys_pll1_800m", "sys_pll2_1000m", | |
199 | "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", }; | |
200 | ||
201 | static const char *imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m", | |
202 | "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", }; | |
203 | ||
204 | static const char *imx8mm_pcie1_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2", | |
205 | "clk_ext3", "clk_ext4", "sys_pll1_400m", }; | |
206 | ||
207 | static const char *imx8mm_pcie1_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", | |
208 | "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; | |
209 | ||
210 | static const char *imx8mm_dc_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", | |
211 | "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; | |
212 | ||
213 | static const char *imx8mm_lcdif_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", | |
214 | "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; | |
215 | ||
216 | static const char *imx8mm_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", | |
217 | "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; | |
218 | ||
219 | static const char *imx8mm_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", | |
220 | "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; | |
221 | ||
222 | static const char *imx8mm_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", | |
223 | "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; | |
224 | ||
225 | static const char *imx8mm_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", | |
226 | "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; | |
227 | ||
228 | static const char *imx8mm_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", | |
229 | "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; | |
230 | ||
231 | static const char *imx8mm_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", | |
232 | "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; | |
233 | ||
234 | static const char *imx8mm_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", | |
235 | "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; | |
236 | ||
237 | static const char *imx8mm_spdif2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", | |
238 | "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; | |
239 | ||
240 | static const char *imx8mm_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", | |
241 | "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; | |
242 | ||
243 | static const char *imx8mm_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", | |
244 | "clk_ext3", "clk_ext4", "video_pll1_out", }; | |
245 | ||
246 | static const char *imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", | |
247 | "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", }; | |
248 | ||
249 | static const char *imx8mm_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m", | |
250 | "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out", }; | |
251 | ||
252 | static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", | |
253 | "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; | |
254 | ||
255 | static const char *imx8mm_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", | |
256 | "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; | |
257 | ||
258 | static const char *imx8mm_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", | |
259 | "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; | |
260 | ||
261 | static const char *imx8mm_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", | |
262 | "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; | |
263 | ||
264 | static const char *imx8mm_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", | |
265 | "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; | |
266 | ||
267 | static const char *imx8mm_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", | |
268 | "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; | |
269 | ||
270 | static const char *imx8mm_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", | |
271 | "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; | |
272 | ||
273 | static const char *imx8mm_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", | |
274 | "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; | |
275 | ||
276 | static const char *imx8mm_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", | |
277 | "sys_pll3_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; | |
278 | ||
279 | static const char *imx8mm_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", | |
280 | "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; | |
281 | ||
282 | static const char *imx8mm_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", | |
283 | "sys_pll3_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; | |
284 | ||
285 | static const char *imx8mm_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", | |
286 | "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; | |
287 | ||
288 | static const char *imx8mm_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", | |
289 | "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; | |
290 | ||
291 | static const char *imx8mm_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", | |
292 | "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; | |
293 | ||
294 | static const char *imx8mm_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", | |
295 | "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; | |
296 | ||
297 | static const char *imx8mm_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", | |
298 | "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; | |
299 | ||
300 | static const char *imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", | |
301 | "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; | |
302 | ||
303 | static const char *imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", | |
304 | "sys3_pll2_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; | |
305 | ||
306 | static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", | |
307 | "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; | |
308 | ||
309 | static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m", | |
310 | "video_pll1_out", "sys_pll1_800m", "audio_pll1_out", "clk_ext1" }; | |
311 | ||
312 | static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", | |
313 | "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; | |
314 | ||
315 | static const char *imx8mm_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out", "sys_pll3_out", "sys_pll2_200m", | |
316 | "sys_pll1_266m", "sys_pll2_500m", "sys_pll1_100m", }; | |
317 | ||
318 | static const char *imx8mm_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", | |
319 | "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", }; | |
320 | ||
321 | static const char *imx8mm_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m", "sys_pll1_800m", | |
322 | "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; | |
323 | ||
324 | static const char *imx8mm_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m", "sys_pll1_800m", | |
325 | "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", }; | |
326 | ||
327 | static const char *imx8mm_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", | |
328 | "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", }; | |
329 | ||
330 | static const char *imx8mm_csi1_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", | |
331 | "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", }; | |
332 | ||
333 | static const char *imx8mm_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", | |
334 | "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; | |
335 | ||
336 | static const char *imx8mm_csi1_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m", | |
337 | "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", }; | |
338 | ||
339 | static const char *imx8mm_csi2_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", | |
340 | "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", }; | |
341 | ||
342 | static const char *imx8mm_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", | |
343 | "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; | |
344 | ||
345 | static const char *imx8mm_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m", | |
346 | "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", }; | |
347 | ||
348 | static const char *imx8mm_pcie2_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m", | |
349 | "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", }; | |
350 | ||
351 | static const char *imx8mm_pcie2_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", | |
352 | "clk_ext2", "clk_ext3", "clk_ext4", "sys_pll1_400m", }; | |
353 | ||
354 | static const char *imx8mm_pcie2_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", | |
355 | "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; | |
356 | ||
357 | static const char *imx8mm_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", | |
358 | "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; | |
359 | ||
360 | static const char *imx8mm_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "sys_pll1_800m", | |
361 | "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", }; | |
362 | ||
363 | static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m", | |
364 | "audio_pll2_clk", "sys_pll2_125m", "sys_pll3_clk", "audio_pll1_out", }; | |
365 | ||
366 | static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; | |
367 | ||
368 | static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", "sys_pll1_200m", "audio_pll2_clk", | |
369 | "vpu_pll", "sys_pll1_80m", }; | |
370 | ||
371 | static struct clk *clks[IMX8MM_CLK_END]; | |
372 | static struct clk_onecell_data clk_data; | |
373 | ||
374 | static struct clk ** const uart_clks[] __initconst = { | |
375 | &clks[IMX8MM_CLK_UART1_ROOT], | |
376 | &clks[IMX8MM_CLK_UART2_ROOT], | |
377 | &clks[IMX8MM_CLK_UART3_ROOT], | |
378 | &clks[IMX8MM_CLK_UART4_ROOT], | |
379 | NULL | |
380 | }; | |
381 | ||
341fdf26 | 382 | static int __init imx8mm_clocks_init(struct device_node *ccm_node) |
ba5625c3 BP |
383 | { |
384 | struct device_node *np; | |
385 | void __iomem *base; | |
386 | int ret; | |
387 | ||
388 | clks[IMX8MM_CLK_DUMMY] = imx_clk_fixed("dummy", 0); | |
389 | clks[IMX8MM_CLK_24M] = of_clk_get_by_name(ccm_node, "osc_24m"); | |
390 | clks[IMX8MM_CLK_32K] = of_clk_get_by_name(ccm_node, "osc_32k"); | |
391 | clks[IMX8MM_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1"); | |
392 | clks[IMX8MM_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2"); | |
393 | clks[IMX8MM_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3"); | |
394 | clks[IMX8MM_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4"); | |
395 | ||
396 | np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); | |
397 | base = of_iomap(np, 0); | |
398 | if (WARN_ON(!base)) | |
399 | return -ENOMEM; | |
400 | ||
401 | clks[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); | |
402 | clks[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); | |
403 | clks[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); | |
404 | clks[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); | |
405 | clks[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); | |
406 | clks[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); | |
407 | clks[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); | |
408 | clks[IMX8MM_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); | |
409 | clks[IMX8MM_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); | |
410 | clks[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); | |
411 | ||
412 | clks[IMX8MM_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx8mm_audio_pll); | |
413 | clks[IMX8MM_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx8mm_audio_pll); | |
414 | clks[IMX8MM_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx8mm_video_pll); | |
415 | clks[IMX8MM_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mm_dram_pll); | |
416 | clks[IMX8MM_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mm_gpu_pll); | |
417 | clks[IMX8MM_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mm_vpu_pll); | |
418 | clks[IMX8MM_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mm_arm_pll); | |
419 | clks[IMX8MM_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mm_sys_pll); | |
420 | clks[IMX8MM_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mm_sys_pll); | |
421 | clks[IMX8MM_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mm_sys_pll); | |
422 | ||
423 | /* PLL bypass out */ | |
424 | clks[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); | |
425 | clks[IMX8MM_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); | |
426 | clks[IMX8MM_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); | |
427 | clks[IMX8MM_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); | |
428 | clks[IMX8MM_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); | |
429 | clks[IMX8MM_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); | |
430 | clks[IMX8MM_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); | |
431 | clks[IMX8MM_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT); | |
432 | clks[IMX8MM_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT); | |
433 | clks[IMX8MM_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); | |
434 | ||
435 | /* unbypass all the plls */ | |
436 | clk_set_parent(clks[IMX8MM_AUDIO_PLL1_BYPASS], clks[IMX8MM_AUDIO_PLL1]); | |
437 | clk_set_parent(clks[IMX8MM_AUDIO_PLL2_BYPASS], clks[IMX8MM_AUDIO_PLL2]); | |
438 | clk_set_parent(clks[IMX8MM_VIDEO_PLL1_BYPASS], clks[IMX8MM_VIDEO_PLL1]); | |
439 | clk_set_parent(clks[IMX8MM_DRAM_PLL_BYPASS], clks[IMX8MM_DRAM_PLL]); | |
440 | clk_set_parent(clks[IMX8MM_GPU_PLL_BYPASS], clks[IMX8MM_GPU_PLL]); | |
441 | clk_set_parent(clks[IMX8MM_VPU_PLL_BYPASS], clks[IMX8MM_VPU_PLL]); | |
442 | clk_set_parent(clks[IMX8MM_ARM_PLL_BYPASS], clks[IMX8MM_ARM_PLL]); | |
443 | clk_set_parent(clks[IMX8MM_SYS_PLL1_BYPASS], clks[IMX8MM_SYS_PLL1]); | |
444 | clk_set_parent(clks[IMX8MM_SYS_PLL2_BYPASS], clks[IMX8MM_SYS_PLL2]); | |
445 | clk_set_parent(clks[IMX8MM_SYS_PLL3_BYPASS], clks[IMX8MM_SYS_PLL3]); | |
446 | ||
447 | /* PLL out gate */ | |
448 | clks[IMX8MM_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); | |
449 | clks[IMX8MM_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); | |
450 | clks[IMX8MM_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13); | |
451 | clks[IMX8MM_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); | |
b3fddd5b PF |
452 | clks[IMX8MM_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); |
453 | clks[IMX8MM_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11); | |
454 | clks[IMX8MM_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11); | |
455 | clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11); | |
456 | clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11); | |
457 | clks[IMX8MM_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); | |
ba5625c3 BP |
458 | |
459 | /* SYS PLL fixed output */ | |
460 | clks[IMX8MM_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); | |
461 | clks[IMX8MM_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); | |
462 | clks[IMX8MM_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); | |
463 | clks[IMX8MM_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); | |
464 | clks[IMX8MM_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); | |
465 | clks[IMX8MM_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); | |
466 | clks[IMX8MM_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); | |
467 | clks[IMX8MM_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); | |
468 | clks[IMX8MM_SYS_PLL1_800M] = imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); | |
469 | ||
470 | clks[IMX8MM_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); | |
471 | clks[IMX8MM_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); | |
472 | clks[IMX8MM_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); | |
473 | clks[IMX8MM_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); | |
474 | clks[IMX8MM_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); | |
475 | clks[IMX8MM_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); | |
476 | clks[IMX8MM_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); | |
477 | clks[IMX8MM_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); | |
478 | clks[IMX8MM_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); | |
479 | ||
480 | np = ccm_node; | |
481 | base = of_iomap(np, 0); | |
482 | if (WARN_ON(!base)) | |
483 | return -ENOMEM; | |
484 | ||
485 | /* Core Slice */ | |
486 | clks[IMX8MM_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)); | |
487 | clks[IMX8MM_CLK_M4_SRC] = imx_clk_mux2("arm_m4_src", base + 0x8080, 24, 3, imx8mm_m4_sels, ARRAY_SIZE(imx8mm_m4_sels)); | |
488 | clks[IMX8MM_CLK_VPU_SRC] = imx_clk_mux2("vpu_src", base + 0x8100, 24, 3, imx8mm_vpu_sels, ARRAY_SIZE(imx8mm_vpu_sels)); | |
489 | clks[IMX8MM_CLK_GPU3D_SRC] = imx_clk_mux2("gpu3d_src", base + 0x8180, 24, 3, imx8mm_gpu3d_sels, ARRAY_SIZE(imx8mm_gpu3d_sels)); | |
490 | clks[IMX8MM_CLK_GPU2D_SRC] = imx_clk_mux2("gpu2d_src", base + 0x8200, 24, 3, imx8mm_gpu2d_sels, ARRAY_SIZE(imx8mm_gpu2d_sels)); | |
491 | clks[IMX8MM_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28); | |
492 | clks[IMX8MM_CLK_M4_CG] = imx_clk_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28); | |
493 | clks[IMX8MM_CLK_VPU_CG] = imx_clk_gate3("vpu_cg", "vpu_src", base + 0x8100, 28); | |
494 | clks[IMX8MM_CLK_GPU3D_CG] = imx_clk_gate3("gpu3d_cg", "gpu3d_src", base + 0x8180, 28); | |
495 | clks[IMX8MM_CLK_GPU2D_CG] = imx_clk_gate3("gpu2d_cg", "gpu2d_src", base + 0x8200, 28); | |
496 | clks[IMX8MM_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3); | |
497 | clks[IMX8MM_CLK_M4_DIV] = imx_clk_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3); | |
498 | clks[IMX8MM_CLK_VPU_DIV] = imx_clk_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3); | |
499 | clks[IMX8MM_CLK_GPU3D_DIV] = imx_clk_divider2("gpu3d_div", "gpu3d_cg", base + 0x8180, 0, 3); | |
500 | clks[IMX8MM_CLK_GPU2D_DIV] = imx_clk_divider2("gpu2d_div", "gpu2d_cg", base + 0x8200, 0, 3); | |
501 | ||
502 | /* BUS */ | |
503 | clks[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800); | |
504 | clks[IMX8MM_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels, base + 0x8880); | |
505 | clks[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_composite_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900); | |
506 | clks[IMX8MM_CLK_VPU_BUS] = imx8m_clk_composite("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980); | |
507 | clks[IMX8MM_CLK_DISP_AXI] = imx8m_clk_composite("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00); | |
508 | clks[IMX8MM_CLK_DISP_APB] = imx8m_clk_composite("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80); | |
509 | clks[IMX8MM_CLK_DISP_RTRM] = imx8m_clk_composite("disp_rtrm", imx8mm_disp_rtrm_sels, base + 0x8b00); | |
510 | clks[IMX8MM_CLK_USB_BUS] = imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80); | |
511 | clks[IMX8MM_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mm_gpu_axi_sels, base + 0x8c00); | |
512 | clks[IMX8MM_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mm_gpu_ahb_sels, base + 0x8c80); | |
513 | clks[IMX8MM_CLK_NOC] = imx8m_clk_composite_critical("noc", imx8mm_noc_sels, base + 0x8d00); | |
514 | clks[IMX8MM_CLK_NOC_APB] = imx8m_clk_composite_critical("noc_apb", imx8mm_noc_apb_sels, base + 0x8d80); | |
515 | ||
516 | /* AHB */ | |
517 | clks[IMX8MM_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels, base + 0x9000); | |
518 | clks[IMX8MM_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mm_audio_ahb_sels, base + 0x9100); | |
519 | ||
520 | /* IPG */ | |
521 | clks[IMX8MM_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); | |
522 | clks[IMX8MM_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1); | |
523 | ||
524 | /* IP */ | |
525 | clks[IMX8MM_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mm_dram_alt_sels, base + 0xa000); | |
526 | clks[IMX8MM_CLK_DRAM_APB] = imx8m_clk_composite("dram_apb", imx8mm_dram_apb_sels, base + 0xa080); | |
527 | clks[IMX8MM_CLK_VPU_G1] = imx8m_clk_composite("vpu_g1", imx8mm_vpu_g1_sels, base + 0xa100); | |
528 | clks[IMX8MM_CLK_VPU_G2] = imx8m_clk_composite("vpu_g2", imx8mm_vpu_g2_sels, base + 0xa180); | |
529 | clks[IMX8MM_CLK_DISP_DTRC] = imx8m_clk_composite("disp_dtrc", imx8mm_disp_dtrc_sels, base + 0xa200); | |
530 | clks[IMX8MM_CLK_DISP_DC8000] = imx8m_clk_composite("disp_dc8000", imx8mm_disp_dc8000_sels, base + 0xa280); | |
531 | clks[IMX8MM_CLK_PCIE1_CTRL] = imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels, base + 0xa300); | |
532 | clks[IMX8MM_CLK_PCIE1_PHY] = imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels, base + 0xa380); | |
533 | clks[IMX8MM_CLK_PCIE1_AUX] = imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels, base + 0xa400); | |
534 | clks[IMX8MM_CLK_DC_PIXEL] = imx8m_clk_composite("dc_pixel", imx8mm_dc_pixel_sels, base + 0xa480); | |
535 | clks[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_composite("lcdif_pixel", imx8mm_lcdif_pixel_sels, base + 0xa500); | |
536 | clks[IMX8MM_CLK_SAI1] = imx8m_clk_composite("sai1", imx8mm_sai1_sels, base + 0xa580); | |
537 | clks[IMX8MM_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mm_sai2_sels, base + 0xa600); | |
538 | clks[IMX8MM_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mm_sai3_sels, base + 0xa680); | |
539 | clks[IMX8MM_CLK_SAI4] = imx8m_clk_composite("sai4", imx8mm_sai4_sels, base + 0xa700); | |
540 | clks[IMX8MM_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mm_sai5_sels, base + 0xa780); | |
541 | clks[IMX8MM_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mm_sai6_sels, base + 0xa800); | |
542 | clks[IMX8MM_CLK_SPDIF1] = imx8m_clk_composite("spdif1", imx8mm_spdif1_sels, base + 0xa880); | |
543 | clks[IMX8MM_CLK_SPDIF2] = imx8m_clk_composite("spdif2", imx8mm_spdif2_sels, base + 0xa900); | |
544 | clks[IMX8MM_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels, base + 0xa980); | |
545 | clks[IMX8MM_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels, base + 0xaa00); | |
546 | clks[IMX8MM_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels, base + 0xaa80); | |
547 | clks[IMX8MM_CLK_NAND] = imx8m_clk_composite("nand", imx8mm_nand_sels, base + 0xab00); | |
548 | clks[IMX8MM_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80); | |
549 | clks[IMX8MM_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels, base + 0xac00); | |
550 | clks[IMX8MM_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels, base + 0xac80); | |
551 | clks[IMX8MM_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00); | |
552 | clks[IMX8MM_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80); | |
553 | clks[IMX8MM_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00); | |
554 | clks[IMX8MM_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80); | |
555 | clks[IMX8MM_CLK_UART1] = imx8m_clk_composite("uart1", imx8mm_uart1_sels, base + 0xaf00); | |
556 | clks[IMX8MM_CLK_UART2] = imx8m_clk_composite("uart2", imx8mm_uart2_sels, base + 0xaf80); | |
557 | clks[IMX8MM_CLK_UART3] = imx8m_clk_composite("uart3", imx8mm_uart3_sels, base + 0xb000); | |
558 | clks[IMX8MM_CLK_UART4] = imx8m_clk_composite("uart4", imx8mm_uart4_sels, base + 0xb080); | |
559 | clks[IMX8MM_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100); | |
560 | clks[IMX8MM_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180); | |
561 | clks[IMX8MM_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280); | |
562 | clks[IMX8MM_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300); | |
563 | clks[IMX8MM_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380); | |
564 | clks[IMX8MM_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400); | |
565 | clks[IMX8MM_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480); | |
566 | clks[IMX8MM_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500); | |
567 | clks[IMX8MM_CLK_GPT1] = imx8m_clk_composite("gpt1", imx8mm_gpt1_sels, base + 0xb580); | |
568 | clks[IMX8MM_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900); | |
569 | clks[IMX8MM_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mm_wrclk_sels, base + 0xb980); | |
570 | clks[IMX8MM_CLK_CLKO1] = imx8m_clk_composite("clko1", imx8mm_clko1_sels, base + 0xba00); | |
571 | clks[IMX8MM_CLK_DSI_CORE] = imx8m_clk_composite("dsi_core", imx8mm_dsi_core_sels, base + 0xbb00); | |
572 | clks[IMX8MM_CLK_DSI_PHY_REF] = imx8m_clk_composite("dsi_phy_ref", imx8mm_dsi_phy_sels, base + 0xbb80); | |
573 | clks[IMX8MM_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mm_dsi_dbi_sels, base + 0xbc00); | |
574 | clks[IMX8MM_CLK_USDHC3] = imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels, base + 0xbc80); | |
575 | clks[IMX8MM_CLK_CSI1_CORE] = imx8m_clk_composite("csi1_core", imx8mm_csi1_core_sels, base + 0xbd00); | |
576 | clks[IMX8MM_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mm_csi1_phy_sels, base + 0xbd80); | |
577 | clks[IMX8MM_CLK_CSI1_ESC] = imx8m_clk_composite("csi1_esc", imx8mm_csi1_esc_sels, base + 0xbe00); | |
578 | clks[IMX8MM_CLK_CSI2_CORE] = imx8m_clk_composite("csi2_core", imx8mm_csi2_core_sels, base + 0xbe80); | |
579 | clks[IMX8MM_CLK_CSI2_PHY_REF] = imx8m_clk_composite("csi2_phy_ref", imx8mm_csi2_phy_sels, base + 0xbf00); | |
580 | clks[IMX8MM_CLK_CSI2_ESC] = imx8m_clk_composite("csi2_esc", imx8mm_csi2_esc_sels, base + 0xbf80); | |
581 | clks[IMX8MM_CLK_PCIE2_CTRL] = imx8m_clk_composite("pcie2_ctrl", imx8mm_pcie2_ctrl_sels, base + 0xc000); | |
582 | clks[IMX8MM_CLK_PCIE2_PHY] = imx8m_clk_composite("pcie2_phy", imx8mm_pcie2_phy_sels, base + 0xc080); | |
583 | clks[IMX8MM_CLK_PCIE2_AUX] = imx8m_clk_composite("pcie2_aux", imx8mm_pcie2_aux_sels, base + 0xc100); | |
584 | clks[IMX8MM_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180); | |
585 | clks[IMX8MM_CLK_PDM] = imx8m_clk_composite("pdm", imx8mm_pdm_sels, base + 0xc200); | |
586 | clks[IMX8MM_CLK_VPU_H1] = imx8m_clk_composite("vpu_h1", imx8mm_vpu_h1_sels, base + 0xc280); | |
587 | ||
588 | /* CCGR */ | |
589 | clks[IMX8MM_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0); | |
590 | clks[IMX8MM_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0); | |
591 | clks[IMX8MM_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0); | |
592 | clks[IMX8MM_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0); | |
593 | clks[IMX8MM_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0); | |
594 | clks[IMX8MM_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0); | |
595 | clks[IMX8MM_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0); | |
596 | clks[IMX8MM_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0); | |
597 | clks[IMX8MM_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0); | |
598 | clks[IMX8MM_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0); | |
599 | clks[IMX8MM_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0); | |
600 | clks[IMX8MM_CLK_PCIE1_ROOT] = imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0); | |
601 | clks[IMX8MM_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0); | |
602 | clks[IMX8MM_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0); | |
603 | clks[IMX8MM_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0); | |
604 | clks[IMX8MM_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0); | |
605 | clks[IMX8MM_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0); | |
606 | clks[IMX8MM_CLK_NAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand); | |
607 | clks[IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand); | |
608 | clks[IMX8MM_CLK_SAI1_ROOT] = imx_clk_gate2_shared2("sai1_root_clk", "sai1", base + 0x4330, 0, &share_count_sai1); | |
609 | clks[IMX8MM_CLK_SAI1_IPG] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_audio_root", base + 0x4330, 0, &share_count_sai1); | |
610 | clks[IMX8MM_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2); | |
611 | clks[IMX8MM_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_audio_root", base + 0x4340, 0, &share_count_sai2); | |
612 | clks[IMX8MM_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3); | |
613 | clks[IMX8MM_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_audio_root", base + 0x4350, 0, &share_count_sai3); | |
614 | clks[IMX8MM_CLK_SAI4_ROOT] = imx_clk_gate2_shared2("sai4_root_clk", "sai4", base + 0x4360, 0, &share_count_sai4); | |
615 | clks[IMX8MM_CLK_SAI4_IPG] = imx_clk_gate2_shared2("sai4_ipg_clk", "ipg_audio_root", base + 0x4360, 0, &share_count_sai4); | |
616 | clks[IMX8MM_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5); | |
617 | clks[IMX8MM_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5); | |
618 | clks[IMX8MM_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6); | |
619 | clks[IMX8MM_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6); | |
620 | clks[IMX8MM_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); | |
621 | clks[IMX8MM_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); | |
622 | clks[IMX8MM_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); | |
623 | clks[IMX8MM_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0); | |
624 | clks[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0); | |
625 | clks[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_gate4("gpu3d_root_clk", "gpu3d_div", base + 0x44f0, 0); | |
626 | clks[IMX8MM_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0); | |
627 | clks[IMX8MM_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0); | |
628 | clks[IMX8MM_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0); | |
629 | clks[IMX8MM_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0); | |
630 | clks[IMX8MM_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0); | |
631 | clks[IMX8MM_CLK_VPU_G1_ROOT] = imx_clk_gate4("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0); | |
632 | clks[IMX8MM_CLK_GPU_BUS_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0); | |
633 | clks[IMX8MM_CLK_VPU_H1_ROOT] = imx_clk_gate4("vpu_h1_root_clk", "vpu_h1", base + 0x4590, 0); | |
634 | clks[IMX8MM_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0); | |
635 | clks[IMX8MM_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm); | |
636 | clks[IMX8MM_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm); | |
637 | clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_dcss); | |
638 | clks[IMX8MM_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss); | |
639 | clks[IMX8MM_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss); | |
640 | clks[IMX8MM_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss); | |
641 | clks[IMX8MM_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0); | |
642 | clks[IMX8MM_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0); | |
643 | clks[IMX8MM_CLK_VPU_DEC_ROOT] = imx_clk_gate4("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0); | |
644 | clks[IMX8MM_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0); | |
645 | clks[IMX8MM_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0); | |
646 | clks[IMX8MM_CLK_SDMA3_ROOT] = imx_clk_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0); | |
647 | clks[IMX8MM_CLK_GPU2D_ROOT] = imx_clk_gate4("gpu2d_root_clk", "gpu2d_div", base + 0x4660, 0); | |
648 | clks[IMX8MM_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0); | |
649 | ||
650 | clks[IMX8MM_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc_24m", 1, 8); | |
651 | ||
652 | clks[IMX8MM_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4); | |
653 | clks[IMX8MM_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mm_dram_core_sels, ARRAY_SIZE(imx8mm_dram_core_sels), CLK_IS_CRITICAL); | |
654 | ||
655 | clks[IMX8MM_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div", | |
656 | clks[IMX8MM_CLK_A53_DIV], | |
657 | clks[IMX8MM_CLK_A53_SRC], | |
658 | clks[IMX8MM_ARM_PLL_OUT], | |
659 | clks[IMX8MM_CLK_24M]); | |
660 | ||
661 | imx_check_clocks(clks, ARRAY_SIZE(clks)); | |
662 | ||
663 | clk_data.clks = clks; | |
664 | clk_data.clk_num = ARRAY_SIZE(clks); | |
665 | ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
666 | if (ret < 0) { | |
667 | pr_err("failed to register clks for i.MX8MM\n"); | |
668 | return -EINVAL; | |
669 | } | |
670 | ||
671 | imx_register_uart_clocks(uart_clks); | |
672 | ||
673 | return 0; | |
674 | } | |
675 | CLK_OF_DECLARE_DRIVER(imx8mm, "fsl,imx8mm-ccm", imx8mm_clocks_init); |